1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for NAND MLC Controller in LPC32xx
4 *
5 * Author: Roland Stigge <stigge@antcom.de>
6 *
7 * Copyright © 2011 WORK Microwave GmbH
8 * Copyright © 2011, 2012 Roland Stigge
9 *
10 * NAND Flash Controller Operation:
11 * - Read: Auto Decode
12 * - Write: Auto Encode
13 * - Tested Page Sizes: 2048, 4096
14 */
15
16 #include <linux/slab.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/delay.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/of.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/mtd/lpc32xx_mlc.h>
30 #include <linux/io.h>
31 #include <linux/mm.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34
35 #define DRV_NAME "lpc32xx_mlc"
36
37 /**********************************************************************
38 * MLC NAND controller register offsets
39 **********************************************************************/
40
41 #define MLC_BUFF(x) (x + 0x00000)
42 #define MLC_DATA(x) (x + 0x08000)
43 #define MLC_CMD(x) (x + 0x10000)
44 #define MLC_ADDR(x) (x + 0x10004)
45 #define MLC_ECC_ENC_REG(x) (x + 0x10008)
46 #define MLC_ECC_DEC_REG(x) (x + 0x1000C)
47 #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010)
48 #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014)
49 #define MLC_RPR(x) (x + 0x10018)
50 #define MLC_WPR(x) (x + 0x1001C)
51 #define MLC_RUBP(x) (x + 0x10020)
52 #define MLC_ROBP(x) (x + 0x10024)
53 #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028)
54 #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C)
55 #define MLC_ICR(x) (x + 0x10030)
56 #define MLC_TIME_REG(x) (x + 0x10034)
57 #define MLC_IRQ_MR(x) (x + 0x10038)
58 #define MLC_IRQ_SR(x) (x + 0x1003C)
59 #define MLC_LOCK_PR(x) (x + 0x10044)
60 #define MLC_ISR(x) (x + 0x10048)
61 #define MLC_CEH(x) (x + 0x1004C)
62
63 /**********************************************************************
64 * MLC_CMD bit definitions
65 **********************************************************************/
66 #define MLCCMD_RESET 0xFF
67
68 /**********************************************************************
69 * MLC_ICR bit definitions
70 **********************************************************************/
71 #define MLCICR_WPROT (1 << 3)
72 #define MLCICR_LARGEBLOCK (1 << 2)
73 #define MLCICR_LONGADDR (1 << 1)
74 #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */
75
76 /**********************************************************************
77 * MLC_TIME_REG bit definitions
78 **********************************************************************/
79 #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24)
80 #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19)
81 #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16)
82 #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12)
83 #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8)
84 #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4)
85 #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0)
86
87 /**********************************************************************
88 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
89 **********************************************************************/
90 #define MLCIRQ_NAND_READY (1 << 5)
91 #define MLCIRQ_CONTROLLER_READY (1 << 4)
92 #define MLCIRQ_DECODE_FAILURE (1 << 3)
93 #define MLCIRQ_DECODE_ERROR (1 << 2)
94 #define MLCIRQ_ECC_READY (1 << 1)
95 #define MLCIRQ_WRPROT_FAULT (1 << 0)
96
97 /**********************************************************************
98 * MLC_LOCK_PR bit definitions
99 **********************************************************************/
100 #define MLCLOCKPR_MAGIC 0xA25E
101
102 /**********************************************************************
103 * MLC_ISR bit definitions
104 **********************************************************************/
105 #define MLCISR_DECODER_FAILURE (1 << 6)
106 #define MLCISR_ERRORS ((1 << 4) | (1 << 5))
107 #define MLCISR_ERRORS_DETECTED (1 << 3)
108 #define MLCISR_ECC_READY (1 << 2)
109 #define MLCISR_CONTROLLER_READY (1 << 1)
110 #define MLCISR_NAND_READY (1 << 0)
111
112 /**********************************************************************
113 * MLC_CEH bit definitions
114 **********************************************************************/
115 #define MLCCEH_NORMAL (1 << 0)
116
117 struct lpc32xx_nand_cfg_mlc {
118 uint32_t tcea_delay;
119 uint32_t busy_delay;
120 uint32_t nand_ta;
121 uint32_t rd_high;
122 uint32_t rd_low;
123 uint32_t wr_high;
124 uint32_t wr_low;
125 struct mtd_partition *parts;
126 unsigned num_parts;
127 };
128
lpc32xx_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)129 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
130 struct mtd_oob_region *oobregion)
131 {
132 struct nand_chip *nand_chip = mtd_to_nand(mtd);
133
134 if (section >= nand_chip->ecc.steps)
135 return -ERANGE;
136
137 oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
138 oobregion->length = nand_chip->ecc.bytes;
139
140 return 0;
141 }
142
lpc32xx_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)143 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
144 struct mtd_oob_region *oobregion)
145 {
146 struct nand_chip *nand_chip = mtd_to_nand(mtd);
147
148 if (section >= nand_chip->ecc.steps)
149 return -ERANGE;
150
151 oobregion->offset = 16 * section;
152 oobregion->length = 16 - nand_chip->ecc.bytes;
153
154 return 0;
155 }
156
157 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
158 .ecc = lpc32xx_ooblayout_ecc,
159 .free = lpc32xx_ooblayout_free,
160 };
161
162 static struct nand_bbt_descr lpc32xx_nand_bbt = {
163 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
164 NAND_BBT_WRITE,
165 .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
166 };
167
168 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
169 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
170 NAND_BBT_WRITE,
171 .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
172 };
173
174 struct lpc32xx_nand_host {
175 struct platform_device *pdev;
176 struct nand_chip nand_chip;
177 struct lpc32xx_mlc_platform_data *pdata;
178 struct clk *clk;
179 struct gpio_desc *wp_gpio;
180 void __iomem *io_base;
181 int irq;
182 struct lpc32xx_nand_cfg_mlc *ncfg;
183 struct completion comp_nand;
184 struct completion comp_controller;
185 uint32_t llptr;
186 /*
187 * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
188 */
189 dma_addr_t oob_buf_phy;
190 /*
191 * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
192 */
193 uint8_t *oob_buf;
194 /* Physical address of DMA base address */
195 dma_addr_t io_base_phy;
196
197 struct completion comp_dma;
198 struct dma_chan *dma_chan;
199 struct dma_slave_config dma_slave_config;
200 struct scatterlist sgl;
201 uint8_t *dma_buf;
202 uint8_t *dummy_buf;
203 int mlcsubpages; /* number of 512bytes-subpages */
204 };
205
206 /*
207 * Activate/Deactivate DMA Operation:
208 *
209 * Using the PL080 DMA Controller for transferring the 512 byte subpages
210 * instead of doing readl() / writel() in a loop slows it down significantly.
211 * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
212 *
213 * - readl() of 128 x 32 bits in a loop: ~20us
214 * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
215 * - DMA read of 512 bytes (32 bit, no bursts): ~100us
216 *
217 * This applies to the transfer itself. In the DMA case: only the
218 * wait_for_completion() (DMA setup _not_ included).
219 *
220 * Note that the 512 bytes subpage transfer is done directly from/to a
221 * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
222 * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
223 * controller transferring data between its internal buffer to/from the NAND
224 * chip.)
225 *
226 * Therefore, using the PL080 DMA is disabled by default, for now.
227 *
228 */
229 static int use_dma;
230
lpc32xx_nand_setup(struct lpc32xx_nand_host * host)231 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
232 {
233 uint32_t clkrate, tmp;
234
235 /* Reset MLC controller */
236 writel(MLCCMD_RESET, MLC_CMD(host->io_base));
237 udelay(1000);
238
239 /* Get base clock for MLC block */
240 clkrate = clk_get_rate(host->clk);
241 if (clkrate == 0)
242 clkrate = 104000000;
243
244 /* Unlock MLC_ICR
245 * (among others, will be locked again automatically) */
246 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
247
248 /* Configure MLC Controller: Large Block, 5 Byte Address */
249 tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
250 writel(tmp, MLC_ICR(host->io_base));
251
252 /* Unlock MLC_TIME_REG
253 * (among others, will be locked again automatically) */
254 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
255
256 /* Compute clock setup values, see LPC and NAND manual */
257 tmp = 0;
258 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
259 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
260 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
261 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
262 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
263 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
264 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
265 writel(tmp, MLC_TIME_REG(host->io_base));
266
267 /* Enable IRQ for CONTROLLER_READY and NAND_READY */
268 writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
269 MLC_IRQ_MR(host->io_base));
270
271 /* Normal nCE operation: nCE controlled by controller */
272 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
273 }
274
275 /*
276 * Hardware specific access to control lines
277 */
lpc32xx_nand_cmd_ctrl(struct nand_chip * nand_chip,int cmd,unsigned int ctrl)278 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
279 unsigned int ctrl)
280 {
281 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
282
283 if (cmd != NAND_CMD_NONE) {
284 if (ctrl & NAND_CLE)
285 writel(cmd, MLC_CMD(host->io_base));
286 else
287 writel(cmd, MLC_ADDR(host->io_base));
288 }
289 }
290
291 /*
292 * Read Device Ready (NAND device _and_ controller ready)
293 */
lpc32xx_nand_device_ready(struct nand_chip * nand_chip)294 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
295 {
296 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
297
298 if ((readb(MLC_ISR(host->io_base)) &
299 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
300 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
301 return 1;
302
303 return 0;
304 }
305
lpc3xxx_nand_irq(int irq,void * data)306 static irqreturn_t lpc3xxx_nand_irq(int irq, void *data)
307 {
308 struct lpc32xx_nand_host *host = data;
309 uint8_t sr;
310
311 /* Clear interrupt flag by reading status */
312 sr = readb(MLC_IRQ_SR(host->io_base));
313 if (sr & MLCIRQ_NAND_READY)
314 complete(&host->comp_nand);
315 if (sr & MLCIRQ_CONTROLLER_READY)
316 complete(&host->comp_controller);
317
318 return IRQ_HANDLED;
319 }
320
lpc32xx_waitfunc_nand(struct nand_chip * chip)321 static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
322 {
323 struct mtd_info *mtd = nand_to_mtd(chip);
324 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
325
326 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
327 goto exit;
328
329 wait_for_completion(&host->comp_nand);
330
331 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
332 /* Seems to be delayed sometimes by controller */
333 dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
334 cpu_relax();
335 }
336
337 exit:
338 return NAND_STATUS_READY;
339 }
340
lpc32xx_waitfunc_controller(struct nand_chip * chip)341 static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
342 {
343 struct mtd_info *mtd = nand_to_mtd(chip);
344 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
345
346 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
347 goto exit;
348
349 wait_for_completion(&host->comp_controller);
350
351 while (!(readb(MLC_ISR(host->io_base)) &
352 MLCISR_CONTROLLER_READY)) {
353 dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
354 cpu_relax();
355 }
356
357 exit:
358 return NAND_STATUS_READY;
359 }
360
lpc32xx_waitfunc(struct nand_chip * chip)361 static int lpc32xx_waitfunc(struct nand_chip *chip)
362 {
363 lpc32xx_waitfunc_nand(chip);
364 lpc32xx_waitfunc_controller(chip);
365
366 return NAND_STATUS_READY;
367 }
368
369 /*
370 * Enable NAND write protect
371 */
lpc32xx_wp_enable(struct lpc32xx_nand_host * host)372 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
373 {
374 if (host->wp_gpio)
375 gpiod_set_value_cansleep(host->wp_gpio, 1);
376 }
377
378 /*
379 * Disable NAND write protect
380 */
lpc32xx_wp_disable(struct lpc32xx_nand_host * host)381 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
382 {
383 if (host->wp_gpio)
384 gpiod_set_value_cansleep(host->wp_gpio, 0);
385 }
386
lpc32xx_dma_complete_func(void * completion)387 static void lpc32xx_dma_complete_func(void *completion)
388 {
389 complete(completion);
390 }
391
lpc32xx_xmit_dma(struct mtd_info * mtd,void * mem,int len,enum dma_transfer_direction dir)392 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
393 enum dma_transfer_direction dir)
394 {
395 struct nand_chip *chip = mtd_to_nand(mtd);
396 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
397 struct dma_async_tx_descriptor *desc;
398 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
399 unsigned long time_left;
400 int res;
401
402 sg_init_one(&host->sgl, mem, len);
403
404 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
405 DMA_BIDIRECTIONAL);
406 if (res != 1) {
407 dev_err(mtd->dev.parent, "Failed to map sg list\n");
408 return -ENXIO;
409 }
410 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
411 flags);
412 if (!desc) {
413 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
414 res = -ENXIO;
415 goto out1;
416 }
417
418 init_completion(&host->comp_dma);
419 desc->callback = lpc32xx_dma_complete_func;
420 desc->callback_param = &host->comp_dma;
421
422 dmaengine_submit(desc);
423 dma_async_issue_pending(host->dma_chan);
424
425 time_left = wait_for_completion_timeout(&host->comp_dma,
426 msecs_to_jiffies(1000));
427 if (!time_left) {
428 dmaengine_terminate_sync(host->dma_chan);
429 res = -ETIMEDOUT;
430 goto out1;
431 }
432
433 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
434 DMA_BIDIRECTIONAL);
435 return 0;
436 out1:
437 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
438 DMA_BIDIRECTIONAL);
439 return res;
440 }
441
lpc32xx_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)442 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
443 int oob_required, int page)
444 {
445 struct mtd_info *mtd = nand_to_mtd(chip);
446 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
447 int i, j;
448 uint8_t *oobbuf = chip->oob_poi;
449 uint32_t mlc_isr;
450 int res;
451 uint8_t *dma_buf;
452 bool dma_mapped;
453
454 if ((void *)buf <= high_memory) {
455 dma_buf = buf;
456 dma_mapped = true;
457 } else {
458 dma_buf = host->dma_buf;
459 dma_mapped = false;
460 }
461
462 /* Writing Command and Address */
463 nand_read_page_op(chip, page, 0, NULL, 0);
464
465 /* For all sub-pages */
466 for (i = 0; i < host->mlcsubpages; i++) {
467 /* Start Auto Decode Command */
468 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
469
470 /* Wait for Controller Ready */
471 lpc32xx_waitfunc_controller(chip);
472
473 /* Check ECC Error status */
474 mlc_isr = readl(MLC_ISR(host->io_base));
475 if (mlc_isr & MLCISR_DECODER_FAILURE) {
476 mtd->ecc_stats.failed++;
477 dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
478 } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
479 mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
480 }
481
482 /* Read 512 + 16 Bytes */
483 if (use_dma) {
484 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
485 DMA_DEV_TO_MEM);
486 if (res)
487 return res;
488 } else {
489 for (j = 0; j < (512 >> 2); j++) {
490 *((uint32_t *)(buf)) =
491 readl(MLC_BUFF(host->io_base));
492 buf += 4;
493 }
494 }
495 for (j = 0; j < (16 >> 2); j++) {
496 *((uint32_t *)(oobbuf)) =
497 readl(MLC_BUFF(host->io_base));
498 oobbuf += 4;
499 }
500 }
501
502 if (use_dma && !dma_mapped)
503 memcpy(buf, dma_buf, mtd->writesize);
504
505 return 0;
506 }
507
lpc32xx_write_page_lowlevel(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)508 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
509 const uint8_t *buf, int oob_required,
510 int page)
511 {
512 struct mtd_info *mtd = nand_to_mtd(chip);
513 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
514 const uint8_t *oobbuf = chip->oob_poi;
515 uint8_t *dma_buf = (uint8_t *)buf;
516 int res;
517 int i, j;
518
519 if (use_dma && (void *)buf >= high_memory) {
520 dma_buf = host->dma_buf;
521 memcpy(dma_buf, buf, mtd->writesize);
522 }
523
524 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
525
526 for (i = 0; i < host->mlcsubpages; i++) {
527 /* Start Encode */
528 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
529
530 /* Write 512 + 6 Bytes to Buffer */
531 if (use_dma) {
532 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
533 DMA_MEM_TO_DEV);
534 if (res)
535 return res;
536 } else {
537 for (j = 0; j < (512 >> 2); j++) {
538 writel(*((uint32_t *)(buf)),
539 MLC_BUFF(host->io_base));
540 buf += 4;
541 }
542 }
543 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
544 oobbuf += 4;
545 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
546 oobbuf += 12;
547
548 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
549 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
550
551 /* Wait for Controller Ready */
552 lpc32xx_waitfunc_controller(chip);
553 }
554
555 return nand_prog_page_end_op(chip);
556 }
557
lpc32xx_read_oob(struct nand_chip * chip,int page)558 static int lpc32xx_read_oob(struct nand_chip *chip, int page)
559 {
560 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
561
562 /* Read whole page - necessary with MLC controller! */
563 lpc32xx_read_page(chip, host->dummy_buf, 1, page);
564
565 return 0;
566 }
567
lpc32xx_write_oob(struct nand_chip * chip,int page)568 static int lpc32xx_write_oob(struct nand_chip *chip, int page)
569 {
570 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
571 return 0;
572 }
573
574 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
lpc32xx_ecc_enable(struct nand_chip * chip,int mode)575 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
576 {
577 /* Always enabled! */
578 }
579
lpc32xx_dma_setup(struct lpc32xx_nand_host * host)580 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
581 {
582 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
583 dma_cap_mask_t mask;
584
585 host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx");
586 if (IS_ERR(host->dma_chan)) {
587 /* fallback to request using platform data */
588 if (!host->pdata || !host->pdata->dma_filter) {
589 dev_err(mtd->dev.parent, "no DMA platform data\n");
590 return -ENOENT;
591 }
592
593 dma_cap_zero(mask);
594 dma_cap_set(DMA_SLAVE, mask);
595 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-mlc");
596
597 if (!host->dma_chan) {
598 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
599 return -EBUSY;
600 }
601 }
602
603 /*
604 * Set direction to a sensible value even if the dmaengine driver
605 * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
606 * driver criticizes it as "alien transfer direction".
607 */
608 host->dma_slave_config.direction = DMA_DEV_TO_MEM;
609 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
610 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
611 host->dma_slave_config.src_maxburst = 128;
612 host->dma_slave_config.dst_maxburst = 128;
613 /* DMA controller does flow control: */
614 host->dma_slave_config.device_fc = false;
615 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
616 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
617 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
618 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
619 goto out1;
620 }
621
622 return 0;
623 out1:
624 dma_release_channel(host->dma_chan);
625 return -ENXIO;
626 }
627
lpc32xx_parse_dt(struct device * dev)628 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
629 {
630 struct lpc32xx_nand_cfg_mlc *ncfg;
631 struct device_node *np = dev->of_node;
632
633 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
634 if (!ncfg)
635 return NULL;
636
637 of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
638 of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
639 of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
640 of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
641 of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
642 of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
643 of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
644
645 if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
646 !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
647 !ncfg->wr_low) {
648 dev_err(dev, "chip parameters not specified correctly\n");
649 return NULL;
650 }
651
652 return ncfg;
653 }
654
lpc32xx_nand_attach_chip(struct nand_chip * chip)655 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
656 {
657 struct mtd_info *mtd = nand_to_mtd(chip);
658 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
659 struct device *dev = &host->pdev->dev;
660
661 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
662 return 0;
663
664 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
665 if (!host->dma_buf)
666 return -ENOMEM;
667
668 host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
669 if (!host->dummy_buf)
670 return -ENOMEM;
671
672 chip->ecc.size = 512;
673 chip->ecc.hwctl = lpc32xx_ecc_enable;
674 chip->ecc.read_page_raw = lpc32xx_read_page;
675 chip->ecc.read_page = lpc32xx_read_page;
676 chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
677 chip->ecc.write_page = lpc32xx_write_page_lowlevel;
678 chip->ecc.write_oob = lpc32xx_write_oob;
679 chip->ecc.read_oob = lpc32xx_read_oob;
680 chip->ecc.strength = 4;
681 chip->ecc.bytes = 10;
682
683 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
684 host->mlcsubpages = mtd->writesize / 512;
685
686 return 0;
687 }
688
689 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
690 .attach_chip = lpc32xx_nand_attach_chip,
691 };
692
693 /*
694 * Probe for NAND controller
695 */
lpc32xx_nand_probe(struct platform_device * pdev)696 static int lpc32xx_nand_probe(struct platform_device *pdev)
697 {
698 struct lpc32xx_nand_host *host;
699 struct mtd_info *mtd;
700 struct nand_chip *nand_chip;
701 struct resource *rc;
702 int res;
703
704 /* Allocate memory for the device structure (and zero it) */
705 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
706 if (!host)
707 return -ENOMEM;
708
709 host->pdev = pdev;
710
711 host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
712 if (IS_ERR(host->io_base))
713 return PTR_ERR(host->io_base);
714
715 host->io_base_phy = rc->start;
716
717 nand_chip = &host->nand_chip;
718 mtd = nand_to_mtd(nand_chip);
719 if (pdev->dev.of_node)
720 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
721 if (!host->ncfg) {
722 dev_err(&pdev->dev,
723 "Missing or bad NAND config from device tree\n");
724 return -ENOENT;
725 }
726
727 /* Start with WP disabled, if available */
728 host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
729 res = PTR_ERR_OR_ZERO(host->wp_gpio);
730 if (res) {
731 if (res != -EPROBE_DEFER)
732 dev_err(&pdev->dev, "WP GPIO is not available: %d\n",
733 res);
734 return res;
735 }
736
737 gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
738
739 host->pdata = dev_get_platdata(&pdev->dev);
740
741 /* link the private data structures */
742 nand_set_controller_data(nand_chip, host);
743 nand_set_flash_node(nand_chip, pdev->dev.of_node);
744 mtd->dev.parent = &pdev->dev;
745
746 /* Get NAND clock */
747 host->clk = clk_get(&pdev->dev, NULL);
748 if (IS_ERR(host->clk)) {
749 dev_err(&pdev->dev, "Clock initialization failure\n");
750 res = -ENOENT;
751 goto free_gpio;
752 }
753 res = clk_prepare_enable(host->clk);
754 if (res)
755 goto put_clk;
756
757 nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
758 nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
759 nand_chip->legacy.chip_delay = 25; /* us */
760 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
761 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
762
763 /* Init NAND controller */
764 lpc32xx_nand_setup(host);
765
766 platform_set_drvdata(pdev, host);
767
768 /* Initialize function pointers */
769 nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
770
771 nand_chip->options = NAND_NO_SUBPAGE_WRITE;
772 nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
773 nand_chip->bbt_td = &lpc32xx_nand_bbt;
774 nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
775
776 if (use_dma) {
777 res = lpc32xx_dma_setup(host);
778 if (res) {
779 res = -EIO;
780 goto unprepare_clk;
781 }
782 }
783
784 /* initially clear interrupt status */
785 readb(MLC_IRQ_SR(host->io_base));
786
787 init_completion(&host->comp_nand);
788 init_completion(&host->comp_controller);
789
790 host->irq = platform_get_irq(pdev, 0);
791 if (host->irq < 0) {
792 res = -EINVAL;
793 goto release_dma_chan;
794 }
795
796 if (request_irq(host->irq, &lpc3xxx_nand_irq,
797 IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
798 dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
799 res = -ENXIO;
800 goto release_dma_chan;
801 }
802
803 /*
804 * Scan to find existence of the device and get the type of NAND device:
805 * SMALL block or LARGE block.
806 */
807 nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
808 res = nand_scan(nand_chip, 1);
809 if (res)
810 goto free_irq;
811
812 mtd->name = DRV_NAME;
813
814 res = mtd_device_register(mtd, host->ncfg->parts,
815 host->ncfg->num_parts);
816 if (res)
817 goto cleanup_nand;
818
819 return 0;
820
821 cleanup_nand:
822 nand_cleanup(nand_chip);
823 free_irq:
824 free_irq(host->irq, host);
825 release_dma_chan:
826 if (use_dma)
827 dma_release_channel(host->dma_chan);
828 unprepare_clk:
829 clk_disable_unprepare(host->clk);
830 put_clk:
831 clk_put(host->clk);
832 free_gpio:
833 lpc32xx_wp_enable(host);
834 gpiod_put(host->wp_gpio);
835
836 return res;
837 }
838
839 /*
840 * Remove NAND device
841 */
lpc32xx_nand_remove(struct platform_device * pdev)842 static void lpc32xx_nand_remove(struct platform_device *pdev)
843 {
844 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
845 struct nand_chip *chip = &host->nand_chip;
846 int ret;
847
848 ret = mtd_device_unregister(nand_to_mtd(chip));
849 WARN_ON(ret);
850 nand_cleanup(chip);
851
852 free_irq(host->irq, host);
853 if (use_dma)
854 dma_release_channel(host->dma_chan);
855
856 clk_disable_unprepare(host->clk);
857 clk_put(host->clk);
858
859 lpc32xx_wp_enable(host);
860 gpiod_put(host->wp_gpio);
861 }
862
lpc32xx_nand_resume(struct platform_device * pdev)863 static int lpc32xx_nand_resume(struct platform_device *pdev)
864 {
865 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
866 int ret;
867
868 /* Re-enable NAND clock */
869 ret = clk_prepare_enable(host->clk);
870 if (ret)
871 return ret;
872
873 /* Fresh init of NAND controller */
874 lpc32xx_nand_setup(host);
875
876 /* Disable write protect */
877 lpc32xx_wp_disable(host);
878
879 return 0;
880 }
881
lpc32xx_nand_suspend(struct platform_device * pdev,pm_message_t pm)882 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
883 {
884 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
885
886 /* Enable write protect for safety */
887 lpc32xx_wp_enable(host);
888
889 /* Disable clock */
890 clk_disable_unprepare(host->clk);
891 return 0;
892 }
893
894 static const struct of_device_id lpc32xx_nand_match[] = {
895 { .compatible = "nxp,lpc3220-mlc" },
896 { /* sentinel */ },
897 };
898 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
899
900 static struct platform_driver lpc32xx_nand_driver = {
901 .probe = lpc32xx_nand_probe,
902 .remove = lpc32xx_nand_remove,
903 .resume = pm_ptr(lpc32xx_nand_resume),
904 .suspend = pm_ptr(lpc32xx_nand_suspend),
905 .driver = {
906 .name = DRV_NAME,
907 .of_match_table = lpc32xx_nand_match,
908 },
909 };
910
911 module_platform_driver(lpc32xx_nand_driver);
912
913 MODULE_LICENSE("GPL");
914 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
915 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
916