1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for NAND MLC Controller in LPC32xx 4 * 5 * Author: Roland Stigge <stigge@antcom.de> 6 * 7 * Copyright © 2011 WORK Microwave GmbH 8 * Copyright © 2011, 2012 Roland Stigge 9 * 10 * NAND Flash Controller Operation: 11 * - Read: Auto Decode 12 * - Write: Auto Encode 13 * - Tested Page Sizes: 2048, 4096 14 */ 15 16 #include <linux/slab.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/rawnand.h> 21 #include <linux/mtd/partitions.h> 22 #include <linux/clk.h> 23 #include <linux/err.h> 24 #include <linux/delay.h> 25 #include <linux/completion.h> 26 #include <linux/interrupt.h> 27 #include <linux/of.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/io.h> 30 #include <linux/mm.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/dmaengine.h> 33 34 #define DRV_NAME "lpc32xx_mlc" 35 36 /********************************************************************** 37 * MLC NAND controller register offsets 38 **********************************************************************/ 39 40 #define MLC_BUFF(x) (x + 0x00000) 41 #define MLC_DATA(x) (x + 0x08000) 42 #define MLC_CMD(x) (x + 0x10000) 43 #define MLC_ADDR(x) (x + 0x10004) 44 #define MLC_ECC_ENC_REG(x) (x + 0x10008) 45 #define MLC_ECC_DEC_REG(x) (x + 0x1000C) 46 #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010) 47 #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014) 48 #define MLC_RPR(x) (x + 0x10018) 49 #define MLC_WPR(x) (x + 0x1001C) 50 #define MLC_RUBP(x) (x + 0x10020) 51 #define MLC_ROBP(x) (x + 0x10024) 52 #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028) 53 #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C) 54 #define MLC_ICR(x) (x + 0x10030) 55 #define MLC_TIME_REG(x) (x + 0x10034) 56 #define MLC_IRQ_MR(x) (x + 0x10038) 57 #define MLC_IRQ_SR(x) (x + 0x1003C) 58 #define MLC_LOCK_PR(x) (x + 0x10044) 59 #define MLC_ISR(x) (x + 0x10048) 60 #define MLC_CEH(x) (x + 0x1004C) 61 62 /********************************************************************** 63 * MLC_CMD bit definitions 64 **********************************************************************/ 65 #define MLCCMD_RESET 0xFF 66 67 /********************************************************************** 68 * MLC_ICR bit definitions 69 **********************************************************************/ 70 #define MLCICR_WPROT (1 << 3) 71 #define MLCICR_LARGEBLOCK (1 << 2) 72 #define MLCICR_LONGADDR (1 << 1) 73 #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */ 74 75 /********************************************************************** 76 * MLC_TIME_REG bit definitions 77 **********************************************************************/ 78 #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24) 79 #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19) 80 #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16) 81 #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12) 82 #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8) 83 #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4) 84 #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0) 85 86 /********************************************************************** 87 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions 88 **********************************************************************/ 89 #define MLCIRQ_NAND_READY (1 << 5) 90 #define MLCIRQ_CONTROLLER_READY (1 << 4) 91 #define MLCIRQ_DECODE_FAILURE (1 << 3) 92 #define MLCIRQ_DECODE_ERROR (1 << 2) 93 #define MLCIRQ_ECC_READY (1 << 1) 94 #define MLCIRQ_WRPROT_FAULT (1 << 0) 95 96 /********************************************************************** 97 * MLC_LOCK_PR bit definitions 98 **********************************************************************/ 99 #define MLCLOCKPR_MAGIC 0xA25E 100 101 /********************************************************************** 102 * MLC_ISR bit definitions 103 **********************************************************************/ 104 #define MLCISR_DECODER_FAILURE (1 << 6) 105 #define MLCISR_ERRORS ((1 << 4) | (1 << 5)) 106 #define MLCISR_ERRORS_DETECTED (1 << 3) 107 #define MLCISR_ECC_READY (1 << 2) 108 #define MLCISR_CONTROLLER_READY (1 << 1) 109 #define MLCISR_NAND_READY (1 << 0) 110 111 /********************************************************************** 112 * MLC_CEH bit definitions 113 **********************************************************************/ 114 #define MLCCEH_NORMAL (1 << 0) 115 116 struct lpc32xx_nand_cfg_mlc { 117 uint32_t tcea_delay; 118 uint32_t busy_delay; 119 uint32_t nand_ta; 120 uint32_t rd_high; 121 uint32_t rd_low; 122 uint32_t wr_high; 123 uint32_t wr_low; 124 struct mtd_partition *parts; 125 unsigned num_parts; 126 }; 127 128 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, 129 struct mtd_oob_region *oobregion) 130 { 131 struct nand_chip *nand_chip = mtd_to_nand(mtd); 132 133 if (section >= nand_chip->ecc.steps) 134 return -ERANGE; 135 136 oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes; 137 oobregion->length = nand_chip->ecc.bytes; 138 139 return 0; 140 } 141 142 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, 143 struct mtd_oob_region *oobregion) 144 { 145 struct nand_chip *nand_chip = mtd_to_nand(mtd); 146 147 if (section >= nand_chip->ecc.steps) 148 return -ERANGE; 149 150 oobregion->offset = 16 * section; 151 oobregion->length = 16 - nand_chip->ecc.bytes; 152 153 return 0; 154 } 155 156 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = { 157 .ecc = lpc32xx_ooblayout_ecc, 158 .free = lpc32xx_ooblayout_free, 159 }; 160 161 static struct nand_bbt_descr lpc32xx_nand_bbt = { 162 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | 163 NAND_BBT_WRITE, 164 .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 }, 165 }; 166 167 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = { 168 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | 169 NAND_BBT_WRITE, 170 .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 }, 171 }; 172 173 struct lpc32xx_nand_host { 174 struct platform_device *pdev; 175 struct nand_chip nand_chip; 176 struct clk *clk; 177 struct gpio_desc *wp_gpio; 178 void __iomem *io_base; 179 int irq; 180 struct lpc32xx_nand_cfg_mlc *ncfg; 181 struct completion comp_nand; 182 struct completion comp_controller; 183 uint32_t llptr; 184 /* 185 * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer 186 */ 187 dma_addr_t oob_buf_phy; 188 /* 189 * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer 190 */ 191 uint8_t *oob_buf; 192 /* Physical address of DMA base address */ 193 dma_addr_t io_base_phy; 194 195 struct completion comp_dma; 196 struct dma_chan *dma_chan; 197 struct dma_slave_config dma_slave_config; 198 struct scatterlist sgl; 199 uint8_t *dma_buf; 200 uint8_t *dummy_buf; 201 int mlcsubpages; /* number of 512bytes-subpages */ 202 }; 203 204 /* 205 * Activate/Deactivate DMA Operation: 206 * 207 * Using the PL080 DMA Controller for transferring the 512 byte subpages 208 * instead of doing readl() / writel() in a loop slows it down significantly. 209 * Measurements via getnstimeofday() upon 512 byte subpage reads reveal: 210 * 211 * - readl() of 128 x 32 bits in a loop: ~20us 212 * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us 213 * - DMA read of 512 bytes (32 bit, no bursts): ~100us 214 * 215 * This applies to the transfer itself. In the DMA case: only the 216 * wait_for_completion() (DMA setup _not_ included). 217 * 218 * Note that the 512 bytes subpage transfer is done directly from/to a 219 * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a 220 * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND 221 * controller transferring data between its internal buffer to/from the NAND 222 * chip.) 223 * 224 * Therefore, using the PL080 DMA is disabled by default, for now. 225 * 226 */ 227 static int use_dma; 228 229 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) 230 { 231 uint32_t clkrate, tmp; 232 233 /* Reset MLC controller */ 234 writel(MLCCMD_RESET, MLC_CMD(host->io_base)); 235 udelay(1000); 236 237 /* Get base clock for MLC block */ 238 clkrate = clk_get_rate(host->clk); 239 if (clkrate == 0) 240 clkrate = 104000000; 241 242 /* Unlock MLC_ICR 243 * (among others, will be locked again automatically) */ 244 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); 245 246 /* Configure MLC Controller: Large Block, 5 Byte Address */ 247 tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR; 248 writel(tmp, MLC_ICR(host->io_base)); 249 250 /* Unlock MLC_TIME_REG 251 * (among others, will be locked again automatically) */ 252 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); 253 254 /* Compute clock setup values, see LPC and NAND manual */ 255 tmp = 0; 256 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); 257 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); 258 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); 259 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); 260 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); 261 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); 262 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low); 263 writel(tmp, MLC_TIME_REG(host->io_base)); 264 265 /* Enable IRQ for CONTROLLER_READY and NAND_READY */ 266 writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY, 267 MLC_IRQ_MR(host->io_base)); 268 269 /* Normal nCE operation: nCE controlled by controller */ 270 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); 271 } 272 273 /* 274 * Hardware specific access to control lines 275 */ 276 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, 277 unsigned int ctrl) 278 { 279 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip); 280 281 if (cmd != NAND_CMD_NONE) { 282 if (ctrl & NAND_CLE) 283 writel(cmd, MLC_CMD(host->io_base)); 284 else 285 writel(cmd, MLC_ADDR(host->io_base)); 286 } 287 } 288 289 /* 290 * Read Device Ready (NAND device _and_ controller ready) 291 */ 292 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip) 293 { 294 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip); 295 296 if ((readb(MLC_ISR(host->io_base)) & 297 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) == 298 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) 299 return 1; 300 301 return 0; 302 } 303 304 static irqreturn_t lpc3xxx_nand_irq(int irq, void *data) 305 { 306 struct lpc32xx_nand_host *host = data; 307 uint8_t sr; 308 309 /* Clear interrupt flag by reading status */ 310 sr = readb(MLC_IRQ_SR(host->io_base)); 311 if (sr & MLCIRQ_NAND_READY) 312 complete(&host->comp_nand); 313 if (sr & MLCIRQ_CONTROLLER_READY) 314 complete(&host->comp_controller); 315 316 return IRQ_HANDLED; 317 } 318 319 static int lpc32xx_waitfunc_nand(struct nand_chip *chip) 320 { 321 struct mtd_info *mtd = nand_to_mtd(chip); 322 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 323 324 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY) 325 goto exit; 326 327 wait_for_completion(&host->comp_nand); 328 329 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) { 330 /* Seems to be delayed sometimes by controller */ 331 dev_dbg(&mtd->dev, "Warning: NAND not ready.\n"); 332 cpu_relax(); 333 } 334 335 exit: 336 return NAND_STATUS_READY; 337 } 338 339 static int lpc32xx_waitfunc_controller(struct nand_chip *chip) 340 { 341 struct mtd_info *mtd = nand_to_mtd(chip); 342 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 343 344 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY) 345 goto exit; 346 347 wait_for_completion(&host->comp_controller); 348 349 while (!(readb(MLC_ISR(host->io_base)) & 350 MLCISR_CONTROLLER_READY)) { 351 dev_dbg(&mtd->dev, "Warning: Controller not ready.\n"); 352 cpu_relax(); 353 } 354 355 exit: 356 return NAND_STATUS_READY; 357 } 358 359 static int lpc32xx_waitfunc(struct nand_chip *chip) 360 { 361 lpc32xx_waitfunc_nand(chip); 362 lpc32xx_waitfunc_controller(chip); 363 364 return NAND_STATUS_READY; 365 } 366 367 /* 368 * Enable NAND write protect 369 */ 370 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) 371 { 372 if (host->wp_gpio) 373 gpiod_set_value_cansleep(host->wp_gpio, 1); 374 } 375 376 /* 377 * Disable NAND write protect 378 */ 379 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) 380 { 381 if (host->wp_gpio) 382 gpiod_set_value_cansleep(host->wp_gpio, 0); 383 } 384 385 static void lpc32xx_dma_complete_func(void *completion) 386 { 387 complete(completion); 388 } 389 390 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len, 391 enum dma_transfer_direction dir) 392 { 393 struct nand_chip *chip = mtd_to_nand(mtd); 394 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 395 struct device *dma_dev = dmaengine_get_dma_device(host->dma_chan); 396 struct dma_async_tx_descriptor *desc; 397 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 398 unsigned long time_left; 399 int res; 400 401 sg_init_one(&host->sgl, mem, len); 402 403 res = dma_map_sg(dma_dev, &host->sgl, 1, DMA_BIDIRECTIONAL); 404 if (res != 1) { 405 dev_err(mtd->dev.parent, "Failed to map sg list\n"); 406 return -ENXIO; 407 } 408 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, 409 flags); 410 if (!desc) { 411 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); 412 res = -ENXIO; 413 goto out1; 414 } 415 416 init_completion(&host->comp_dma); 417 desc->callback = lpc32xx_dma_complete_func; 418 desc->callback_param = &host->comp_dma; 419 420 dmaengine_submit(desc); 421 dma_async_issue_pending(host->dma_chan); 422 423 time_left = wait_for_completion_timeout(&host->comp_dma, 424 msecs_to_jiffies(1000)); 425 if (!time_left) { 426 dmaengine_terminate_sync(host->dma_chan); 427 res = -ETIMEDOUT; 428 goto out1; 429 } 430 431 dma_unmap_sg(dma_dev, &host->sgl, 1, DMA_BIDIRECTIONAL); 432 return 0; 433 out1: 434 dma_unmap_sg(dma_dev, &host->sgl, 1, DMA_BIDIRECTIONAL); 435 return res; 436 } 437 438 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf, 439 int oob_required, int page) 440 { 441 struct mtd_info *mtd = nand_to_mtd(chip); 442 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 443 int i, j; 444 uint8_t *oobbuf = chip->oob_poi; 445 uint32_t mlc_isr; 446 int res; 447 uint8_t *dma_buf; 448 bool dma_mapped; 449 450 if ((void *)buf <= high_memory) { 451 dma_buf = buf; 452 dma_mapped = true; 453 } else { 454 dma_buf = host->dma_buf; 455 dma_mapped = false; 456 } 457 458 /* Writing Command and Address */ 459 nand_read_page_op(chip, page, 0, NULL, 0); 460 461 /* For all sub-pages */ 462 for (i = 0; i < host->mlcsubpages; i++) { 463 /* Start Auto Decode Command */ 464 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base)); 465 466 /* Wait for Controller Ready */ 467 lpc32xx_waitfunc_controller(chip); 468 469 /* Check ECC Error status */ 470 mlc_isr = readl(MLC_ISR(host->io_base)); 471 if (mlc_isr & MLCISR_DECODER_FAILURE) { 472 mtd->ecc_stats.failed++; 473 dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__); 474 } else if (mlc_isr & MLCISR_ERRORS_DETECTED) { 475 mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1; 476 } 477 478 /* Read 512 + 16 Bytes */ 479 if (use_dma) { 480 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, 481 DMA_DEV_TO_MEM); 482 if (res) 483 return res; 484 } else { 485 for (j = 0; j < (512 >> 2); j++) { 486 *((uint32_t *)(buf)) = 487 readl(MLC_BUFF(host->io_base)); 488 buf += 4; 489 } 490 } 491 for (j = 0; j < (16 >> 2); j++) { 492 *((uint32_t *)(oobbuf)) = 493 readl(MLC_BUFF(host->io_base)); 494 oobbuf += 4; 495 } 496 } 497 498 if (use_dma && !dma_mapped) 499 memcpy(buf, dma_buf, mtd->writesize); 500 501 return 0; 502 } 503 504 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip, 505 const uint8_t *buf, int oob_required, 506 int page) 507 { 508 struct mtd_info *mtd = nand_to_mtd(chip); 509 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 510 const uint8_t *oobbuf = chip->oob_poi; 511 uint8_t *dma_buf = (uint8_t *)buf; 512 int res; 513 int i, j; 514 515 if (use_dma && (void *)buf >= high_memory) { 516 dma_buf = host->dma_buf; 517 memcpy(dma_buf, buf, mtd->writesize); 518 } 519 520 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 521 522 for (i = 0; i < host->mlcsubpages; i++) { 523 /* Start Encode */ 524 writeb(0x00, MLC_ECC_ENC_REG(host->io_base)); 525 526 /* Write 512 + 6 Bytes to Buffer */ 527 if (use_dma) { 528 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, 529 DMA_MEM_TO_DEV); 530 if (res) 531 return res; 532 } else { 533 for (j = 0; j < (512 >> 2); j++) { 534 writel(*((uint32_t *)(buf)), 535 MLC_BUFF(host->io_base)); 536 buf += 4; 537 } 538 } 539 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base)); 540 oobbuf += 4; 541 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base)); 542 oobbuf += 12; 543 544 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ 545 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base)); 546 547 /* Wait for Controller Ready */ 548 lpc32xx_waitfunc_controller(chip); 549 } 550 551 return nand_prog_page_end_op(chip); 552 } 553 554 static int lpc32xx_read_oob(struct nand_chip *chip, int page) 555 { 556 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 557 558 /* Read whole page - necessary with MLC controller! */ 559 lpc32xx_read_page(chip, host->dummy_buf, 1, page); 560 561 return 0; 562 } 563 564 static int lpc32xx_write_oob(struct nand_chip *chip, int page) 565 { 566 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ 567 return 0; 568 } 569 570 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */ 571 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode) 572 { 573 /* Always enabled! */ 574 } 575 576 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) 577 { 578 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); 579 580 host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx"); 581 if (IS_ERR(host->dma_chan)) { 582 dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); 583 return PTR_ERR(host->dma_chan); 584 } 585 586 /* 587 * Set direction to a sensible value even if the dmaengine driver 588 * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x 589 * driver criticizes it as "alien transfer direction". 590 */ 591 host->dma_slave_config.direction = DMA_DEV_TO_MEM; 592 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 593 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 594 host->dma_slave_config.src_maxburst = 128; 595 host->dma_slave_config.dst_maxburst = 128; 596 /* DMA controller does flow control: */ 597 host->dma_slave_config.device_fc = false; 598 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy); 599 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy); 600 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { 601 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); 602 goto out1; 603 } 604 605 return 0; 606 out1: 607 dma_release_channel(host->dma_chan); 608 return -ENXIO; 609 } 610 611 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) 612 { 613 struct lpc32xx_nand_cfg_mlc *ncfg; 614 struct device_node *np = dev->of_node; 615 616 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); 617 if (!ncfg) 618 return NULL; 619 620 of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay); 621 of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay); 622 of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta); 623 of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high); 624 of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low); 625 of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high); 626 of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low); 627 628 if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta || 629 !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high || 630 !ncfg->wr_low) { 631 dev_err(dev, "chip parameters not specified correctly\n"); 632 return NULL; 633 } 634 635 return ncfg; 636 } 637 638 static int lpc32xx_nand_attach_chip(struct nand_chip *chip) 639 { 640 struct mtd_info *mtd = nand_to_mtd(chip); 641 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 642 struct device *dev = &host->pdev->dev; 643 644 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 645 return 0; 646 647 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); 648 if (!host->dma_buf) 649 return -ENOMEM; 650 651 host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); 652 if (!host->dummy_buf) 653 return -ENOMEM; 654 655 chip->ecc.size = 512; 656 chip->ecc.hwctl = lpc32xx_ecc_enable; 657 chip->ecc.read_page_raw = lpc32xx_read_page; 658 chip->ecc.read_page = lpc32xx_read_page; 659 chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; 660 chip->ecc.write_page = lpc32xx_write_page_lowlevel; 661 chip->ecc.write_oob = lpc32xx_write_oob; 662 chip->ecc.read_oob = lpc32xx_read_oob; 663 chip->ecc.strength = 4; 664 chip->ecc.bytes = 10; 665 666 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 667 host->mlcsubpages = mtd->writesize / 512; 668 669 return 0; 670 } 671 672 static const struct nand_controller_ops lpc32xx_nand_controller_ops = { 673 .attach_chip = lpc32xx_nand_attach_chip, 674 }; 675 676 /* 677 * Probe for NAND controller 678 */ 679 static int lpc32xx_nand_probe(struct platform_device *pdev) 680 { 681 struct lpc32xx_nand_host *host; 682 struct mtd_info *mtd; 683 struct nand_chip *nand_chip; 684 struct resource *rc; 685 int res; 686 687 /* Allocate memory for the device structure (and zero it) */ 688 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 689 if (!host) 690 return -ENOMEM; 691 692 host->pdev = pdev; 693 694 host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc); 695 if (IS_ERR(host->io_base)) 696 return PTR_ERR(host->io_base); 697 698 host->io_base_phy = rc->start; 699 700 nand_chip = &host->nand_chip; 701 mtd = nand_to_mtd(nand_chip); 702 if (pdev->dev.of_node) 703 host->ncfg = lpc32xx_parse_dt(&pdev->dev); 704 if (!host->ncfg) { 705 dev_err(&pdev->dev, 706 "Missing or bad NAND config from device tree\n"); 707 return -ENOENT; 708 } 709 710 /* Start with WP disabled, if available */ 711 host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW); 712 res = PTR_ERR_OR_ZERO(host->wp_gpio); 713 if (res) { 714 if (res != -EPROBE_DEFER) 715 dev_err(&pdev->dev, "WP GPIO is not available: %d\n", 716 res); 717 return res; 718 } 719 720 gpiod_set_consumer_name(host->wp_gpio, "NAND WP"); 721 722 /* link the private data structures */ 723 nand_set_controller_data(nand_chip, host); 724 nand_set_flash_node(nand_chip, pdev->dev.of_node); 725 mtd->dev.parent = &pdev->dev; 726 727 /* Get NAND clock */ 728 host->clk = clk_get(&pdev->dev, NULL); 729 if (IS_ERR(host->clk)) { 730 dev_err(&pdev->dev, "Clock initialization failure\n"); 731 res = -ENOENT; 732 goto free_gpio; 733 } 734 res = clk_prepare_enable(host->clk); 735 if (res) 736 goto put_clk; 737 738 nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; 739 nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready; 740 nand_chip->legacy.chip_delay = 25; /* us */ 741 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base); 742 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base); 743 744 /* Init NAND controller */ 745 lpc32xx_nand_setup(host); 746 747 platform_set_drvdata(pdev, host); 748 749 /* Initialize function pointers */ 750 nand_chip->legacy.waitfunc = lpc32xx_waitfunc; 751 752 nand_chip->options = NAND_NO_SUBPAGE_WRITE; 753 nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 754 nand_chip->bbt_td = &lpc32xx_nand_bbt; 755 nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror; 756 757 if (use_dma) { 758 res = lpc32xx_dma_setup(host); 759 if (res) { 760 res = -EIO; 761 goto unprepare_clk; 762 } 763 } 764 765 /* initially clear interrupt status */ 766 readb(MLC_IRQ_SR(host->io_base)); 767 768 init_completion(&host->comp_nand); 769 init_completion(&host->comp_controller); 770 771 host->irq = platform_get_irq(pdev, 0); 772 if (host->irq < 0) { 773 res = -EINVAL; 774 goto release_dma_chan; 775 } 776 777 if (request_irq(host->irq, &lpc3xxx_nand_irq, 778 IRQF_TRIGGER_HIGH, DRV_NAME, host)) { 779 dev_err(&pdev->dev, "Error requesting NAND IRQ\n"); 780 res = -ENXIO; 781 goto release_dma_chan; 782 } 783 784 /* 785 * Scan to find existence of the device and get the type of NAND device: 786 * SMALL block or LARGE block. 787 */ 788 nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; 789 res = nand_scan(nand_chip, 1); 790 if (res) 791 goto free_irq; 792 793 mtd->name = DRV_NAME; 794 795 res = mtd_device_register(mtd, host->ncfg->parts, 796 host->ncfg->num_parts); 797 if (res) 798 goto cleanup_nand; 799 800 return 0; 801 802 cleanup_nand: 803 nand_cleanup(nand_chip); 804 free_irq: 805 free_irq(host->irq, host); 806 release_dma_chan: 807 if (use_dma) 808 dma_release_channel(host->dma_chan); 809 unprepare_clk: 810 clk_disable_unprepare(host->clk); 811 put_clk: 812 clk_put(host->clk); 813 free_gpio: 814 lpc32xx_wp_enable(host); 815 gpiod_put(host->wp_gpio); 816 817 return res; 818 } 819 820 /* 821 * Remove NAND device 822 */ 823 static void lpc32xx_nand_remove(struct platform_device *pdev) 824 { 825 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 826 struct nand_chip *chip = &host->nand_chip; 827 int ret; 828 829 ret = mtd_device_unregister(nand_to_mtd(chip)); 830 WARN_ON(ret); 831 nand_cleanup(chip); 832 833 free_irq(host->irq, host); 834 if (use_dma) 835 dma_release_channel(host->dma_chan); 836 837 clk_disable_unprepare(host->clk); 838 clk_put(host->clk); 839 840 lpc32xx_wp_enable(host); 841 gpiod_put(host->wp_gpio); 842 } 843 844 static int lpc32xx_nand_resume(struct platform_device *pdev) 845 { 846 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 847 int ret; 848 849 /* Re-enable NAND clock */ 850 ret = clk_prepare_enable(host->clk); 851 if (ret) 852 return ret; 853 854 /* Fresh init of NAND controller */ 855 lpc32xx_nand_setup(host); 856 857 /* Disable write protect */ 858 lpc32xx_wp_disable(host); 859 860 return 0; 861 } 862 863 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) 864 { 865 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 866 867 /* Enable write protect for safety */ 868 lpc32xx_wp_enable(host); 869 870 /* Disable clock */ 871 clk_disable_unprepare(host->clk); 872 return 0; 873 } 874 875 static const struct of_device_id lpc32xx_nand_match[] = { 876 { .compatible = "nxp,lpc3220-mlc" }, 877 { /* sentinel */ }, 878 }; 879 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); 880 881 static struct platform_driver lpc32xx_nand_driver = { 882 .probe = lpc32xx_nand_probe, 883 .remove = lpc32xx_nand_remove, 884 .resume = pm_ptr(lpc32xx_nand_resume), 885 .suspend = pm_ptr(lpc32xx_nand_suspend), 886 .driver = { 887 .name = DRV_NAME, 888 .of_match_table = lpc32xx_nand_match, 889 }, 890 }; 891 892 module_platform_driver(lpc32xx_nand_driver); 893 894 MODULE_LICENSE("GPL"); 895 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 896 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller"); 897