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Searched refs:MICROSECOND_TIME_BASE_DIV (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.h96 SR(MICROSECOND_TIME_BASE_DIV)
141 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
142 I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
186 uint8_t MICROSECOND_TIME_BASE_DIV; member
231 uint32_t MICROSECOND_TIME_BASE_DIV; member
268 uint32_t MICROSECOND_TIME_BASE_DIV; member
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c140 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); in dccg2_init()
161 return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; in dccg2_is_s0i3_golden_init_wa_done()
H A Ddcn20_dccg.h42 SR(MICROSECOND_TIME_BASE_DIV),\
478 uint32_t MICROSECOND_TIME_BASE_DIV; \
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.h40 SR(MICROSECOND_TIME_BASE_DIV),\
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.h72 SR(MICROSECOND_TIME_BASE_DIV)
H A Ddcn31_dccg.c801 dccg_reg_state->microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV); in dccg31_read_reg_state()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.h80 SR(MICROSECOND_TIME_BASE_DIV)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c524 SR(MICROSECOND_TIME_BASE_DIV), \