1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 // Copyright 2018 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26
27 #include "fsl_micfil.h"
28 #include "fsl_utils.h"
29
30 #define MICFIL_OSR_DEFAULT 16
31
32 #define MICFIL_NUM_RATES 7
33 #define MICFIL_CLK_SRC_NUM 3
34 /* clock source ids */
35 #define MICFIL_AUDIO_PLL1 0
36 #define MICFIL_AUDIO_PLL2 1
37 #define MICFIL_CLK_EXT3 2
38
39 static const unsigned int fsl_micfil_rates[] = {
40 8000, 11025, 16000, 22050, 32000, 44100, 48000,
41 };
42
43 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = {
44 .count = ARRAY_SIZE(fsl_micfil_rates),
45 .list = fsl_micfil_rates,
46 };
47
48 enum quality {
49 QUALITY_HIGH,
50 QUALITY_MEDIUM,
51 QUALITY_LOW,
52 QUALITY_VLOW0,
53 QUALITY_VLOW1,
54 QUALITY_VLOW2,
55 };
56
57 struct fsl_micfil {
58 struct platform_device *pdev;
59 struct regmap *regmap;
60 const struct fsl_micfil_soc_data *soc;
61 struct clk *busclk;
62 struct clk *mclk;
63 struct clk *pll8k_clk;
64 struct clk *pll11k_clk;
65 struct clk *clk_src[MICFIL_CLK_SRC_NUM];
66 struct snd_dmaengine_dai_dma_data dma_params_rx;
67 struct sdma_peripheral_config sdmacfg;
68 struct snd_soc_card *card;
69 struct snd_pcm_hw_constraint_list constraint_rates;
70 unsigned int constraint_rates_list[MICFIL_NUM_RATES];
71 unsigned int dataline;
72 char name[32];
73 int irq[MICFIL_IRQ_LINES];
74 enum quality quality;
75 int dc_remover;
76 int vad_init_mode;
77 int vad_enabled;
78 int vad_detected;
79 struct fsl_micfil_verid verid;
80 struct fsl_micfil_param param;
81 bool mclk_flag; /* mclk enable flag */
82 bool dec_bypass;
83 };
84
85 struct fsl_micfil_soc_data {
86 unsigned int fifos;
87 unsigned int fifo_depth;
88 unsigned int dataline;
89 bool imx;
90 bool use_edma;
91 bool use_verid;
92 bool volume_sx;
93 u64 formats;
94 int fifo_offset;
95 };
96
97 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
98 .imx = true,
99 .fifos = 8,
100 .fifo_depth = 8,
101 .dataline = 0xf,
102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
103 .volume_sx = true,
104 .fifo_offset = 0,
105 };
106
107 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
108 .imx = true,
109 .fifos = 8,
110 .fifo_depth = 32,
111 .dataline = 0xf,
112 .formats = SNDRV_PCM_FMTBIT_S32_LE,
113 .volume_sx = false,
114 .fifo_offset = 0,
115 };
116
117 static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
118 .imx = true,
119 .fifos = 8,
120 .fifo_depth = 32,
121 .dataline = 0xf,
122 .formats = SNDRV_PCM_FMTBIT_S32_LE,
123 .use_edma = true,
124 .use_verid = true,
125 .volume_sx = false,
126 .fifo_offset = 0,
127 };
128
129 static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
130 .imx = true,
131 .fifos = 8,
132 .fifo_depth = 32,
133 .dataline = 0xf,
134 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U32_BE,
135 .use_edma = true,
136 .use_verid = true,
137 .volume_sx = false,
138 .fifo_offset = -4,
139 };
140
141 static const struct of_device_id fsl_micfil_dt_ids[] = {
142 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
143 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
144 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
145 { .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
146 {}
147 };
148 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
149
150 static const char * const micfil_quality_select_texts[] = {
151 [QUALITY_HIGH] = "High",
152 [QUALITY_MEDIUM] = "Medium",
153 [QUALITY_LOW] = "Low",
154 [QUALITY_VLOW0] = "VLow0",
155 [QUALITY_VLOW1] = "Vlow1",
156 [QUALITY_VLOW2] = "Vlow2",
157 };
158
159 static const struct soc_enum fsl_micfil_quality_enum =
160 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
161 micfil_quality_select_texts);
162
163 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
164
micfil_set_quality(struct fsl_micfil * micfil)165 static int micfil_set_quality(struct fsl_micfil *micfil)
166 {
167 u32 qsel;
168
169 switch (micfil->quality) {
170 case QUALITY_HIGH:
171 qsel = MICFIL_QSEL_HIGH_QUALITY;
172 break;
173 case QUALITY_MEDIUM:
174 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
175 break;
176 case QUALITY_LOW:
177 qsel = MICFIL_QSEL_LOW_QUALITY;
178 break;
179 case QUALITY_VLOW0:
180 qsel = MICFIL_QSEL_VLOW0_QUALITY;
181 break;
182 case QUALITY_VLOW1:
183 qsel = MICFIL_QSEL_VLOW1_QUALITY;
184 break;
185 case QUALITY_VLOW2:
186 qsel = MICFIL_QSEL_VLOW2_QUALITY;
187 break;
188 default:
189 return -EINVAL;
190 }
191
192 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
193 MICFIL_CTRL2_QSEL,
194 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
195 }
196
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)197 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
198 struct snd_ctl_elem_value *ucontrol)
199 {
200 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
201 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
202
203 ucontrol->value.integer.value[0] = micfil->quality;
204
205 return 0;
206 }
207
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)208 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
209 struct snd_ctl_elem_value *ucontrol)
210 {
211 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
212 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
213
214 micfil->quality = ucontrol->value.integer.value[0];
215
216 return micfil_set_quality(micfil);
217 }
218
219 static const char * const micfil_hwvad_enable[] = {
220 "Disable (Record only)",
221 "Enable (Record with Vad)",
222 };
223
224 static const char * const micfil_hwvad_init_mode[] = {
225 "Envelope mode", "Energy mode",
226 };
227
228 static const char * const micfil_hwvad_hpf_texts[] = {
229 "Filter bypass",
230 "Cut-off @1750Hz",
231 "Cut-off @215Hz",
232 "Cut-off @102Hz",
233 };
234
235 /*
236 * DC Remover Control
237 * Filter Bypassed 1 1
238 * Cut-off @21Hz 0 0
239 * Cut-off @83Hz 0 1
240 * Cut-off @152HZ 1 0
241 */
242 static const char * const micfil_dc_remover_texts[] = {
243 "Cut-off @21Hz", "Cut-off @83Hz",
244 "Cut-off @152Hz", "Bypass",
245 };
246
247 static const struct soc_enum hwvad_enable_enum =
248 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
249 micfil_hwvad_enable);
250 static const struct soc_enum hwvad_init_mode_enum =
251 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
252 micfil_hwvad_init_mode);
253 static const struct soc_enum hwvad_hpf_enum =
254 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
255 ARRAY_SIZE(micfil_hwvad_hpf_texts),
256 micfil_hwvad_hpf_texts);
257 static const struct soc_enum fsl_micfil_dc_remover_enum =
258 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
259 micfil_dc_remover_texts);
260
micfil_put_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)261 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
262 struct snd_ctl_elem_value *ucontrol)
263 {
264 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
265 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
266 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
267 unsigned int *item = ucontrol->value.enumerated.item;
268 int val = snd_soc_enum_item_to_val(e, item[0]);
269 int i = 0, ret = 0;
270 u32 reg_val = 0;
271
272 if (val < 0 || val > 3)
273 return -EINVAL;
274
275 micfil->dc_remover = val;
276
277 /* Calculate total value for all channels */
278 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
279 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
280
281 /* Update DC Remover mode for all channels */
282 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
283 MICFIL_DC_CTRL_CONFIG, reg_val);
284 if (ret < 0)
285 return ret;
286
287 return 0;
288 }
289
micfil_get_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)290 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
292 {
293 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
294 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
295
296 ucontrol->value.enumerated.item[0] = micfil->dc_remover;
297
298 return 0;
299 }
300
hwvad_put_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)301 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
302 struct snd_ctl_elem_value *ucontrol)
303 {
304 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
305 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
306 unsigned int *item = ucontrol->value.enumerated.item;
307 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
308 int val = snd_soc_enum_item_to_val(e, item[0]);
309
310 micfil->vad_enabled = val;
311
312 return 0;
313 }
314
hwvad_get_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)315 static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
316 struct snd_ctl_elem_value *ucontrol)
317 {
318 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
319 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
320
321 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
322
323 return 0;
324 }
325
hwvad_put_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)326 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
327 struct snd_ctl_elem_value *ucontrol)
328 {
329 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
330 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
331 unsigned int *item = ucontrol->value.enumerated.item;
332 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
333 int val = snd_soc_enum_item_to_val(e, item[0]);
334
335 /* 0 - Envelope-based Mode
336 * 1 - Energy-based Mode
337 */
338 micfil->vad_init_mode = val;
339
340 return 0;
341 }
342
hwvad_get_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)343 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
344 struct snd_ctl_elem_value *ucontrol)
345 {
346 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
347 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
348
349 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
350
351 return 0;
352 }
353
hwvad_detected(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)354 static int hwvad_detected(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356 {
357 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
358 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
359
360 ucontrol->value.enumerated.item[0] = micfil->vad_detected;
361
362 return 0;
363 }
364
365 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = {
366 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
367 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv),
368 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
369 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv),
370 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
371 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv),
372 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
373 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv),
374 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
375 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv),
376 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
377 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv),
378 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
379 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv),
380 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
381 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv),
382 };
383
384 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
385 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
386 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
387 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
388 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
389 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
390 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
391 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
392 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
393 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
394 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
395 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
396 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
397 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
398 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
399 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
400 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
401 };
402
403 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
404 SOC_ENUM_EXT("MICFIL Quality Select",
405 fsl_micfil_quality_enum,
406 micfil_quality_get, micfil_quality_set),
407 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
408 hwvad_get_enable, hwvad_put_enable),
409 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
410 hwvad_get_init_mode, hwvad_put_init_mode),
411 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
412 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
413 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
414 REG_MICFIL_VAD0_ZCD, 2, 1, 0),
415 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
416 micfil_get_dc_remover_state, micfil_put_dc_remover_state),
417 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
418 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
419 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
420 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
421 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
422 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
423 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
424 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
425 SOC_SINGLE("HWVAD ZCD And Behavior Switch",
426 REG_MICFIL_VAD0_ZCD, 4, 1, 0),
427 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
428 };
429
fsl_micfil_use_verid(struct device * dev)430 static int fsl_micfil_use_verid(struct device *dev)
431 {
432 struct fsl_micfil *micfil = dev_get_drvdata(dev);
433 unsigned int val;
434 int ret;
435
436 if (!micfil->soc->use_verid)
437 return 0;
438
439 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
440 if (ret < 0)
441 return ret;
442
443 dev_dbg(dev, "VERID: 0x%016X\n", val);
444
445 micfil->verid.version = val &
446 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
447 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
448 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
449
450 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
451 if (ret < 0)
452 return ret;
453
454 dev_dbg(dev, "PARAM: 0x%016X\n", val);
455
456 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
457 MICFIL_PARAM_NUM_HWVAD_SHIFT;
458 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
459 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
460 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
461 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
462 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
463 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
464 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
465 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
466 MICFIL_PARAM_FIFO_PTRWID_SHIFT;
467 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
468 MICFIL_PARAM_NPAIR_SHIFT;
469
470 return 0;
471 }
472
473 /* The SRES is a self-negated bit which provides the CPU with the
474 * capability to initialize the PDM Interface module through the
475 * slave-bus interface. This bit always reads as zero, and this
476 * bit is only effective when MDIS is cleared
477 */
fsl_micfil_reset(struct device * dev)478 static int fsl_micfil_reset(struct device *dev)
479 {
480 struct fsl_micfil *micfil = dev_get_drvdata(dev);
481 int ret;
482
483 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
484 MICFIL_CTRL1_MDIS);
485 if (ret)
486 return ret;
487
488 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
489 MICFIL_CTRL1_SRES);
490 if (ret)
491 return ret;
492
493 /*
494 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
495 * as non-volatile register, so SRES still remain in regmap
496 * cache after set, that every update of REG_MICFIL_CTRL1,
497 * software reset happens. so clear it explicitly.
498 */
499 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
500 MICFIL_CTRL1_SRES);
501 if (ret)
502 return ret;
503
504 /*
505 * Set SRES should clear CHnF flags, But even add delay here
506 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
507 */
508 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
509 if (ret)
510 return ret;
511
512 return 0;
513 }
514
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)515 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
516 struct snd_soc_dai *dai)
517 {
518 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
519
520 if (!micfil) {
521 dev_err(dai->dev, "micfil dai priv_data not set\n");
522 return -EINVAL;
523 }
524
525 if (micfil->constraint_rates.count > 0)
526 snd_pcm_hw_constraint_list(substream->runtime, 0,
527 SNDRV_PCM_HW_PARAM_RATE,
528 &micfil->constraint_rates);
529
530 return 0;
531 }
532
533 /* Enable/disable hwvad interrupts */
fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil * micfil,int enable)534 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
535 {
536 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
537 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
538
539 /* Voice Activity Detector Error Interruption */
540 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
541 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
542
543 /* Voice Activity Detector Interruption */
544 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
545 MICFIL_VAD0_CTRL1_IE, vadie_reg);
546
547 return 0;
548 }
549
550 /* Configuration done only in energy-based initialization mode */
fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil * micfil)551 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
552 {
553 /* Keep the VADFRENDIS bitfield cleared. */
554 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
555 MICFIL_VAD0_CTRL2_FRENDIS);
556
557 /* Keep the VADPREFEN bitfield cleared. */
558 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
559 MICFIL_VAD0_CTRL2_PREFEN);
560
561 /* Keep the VADSFILEN bitfield cleared. */
562 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
563 MICFIL_VAD0_SCONFIG_SFILEN);
564
565 /* Keep the VADSMAXEN bitfield cleared. */
566 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
567 MICFIL_VAD0_SCONFIG_SMAXEN);
568
569 /* Keep the VADNFILAUTO bitfield asserted. */
570 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
571 MICFIL_VAD0_NCONFIG_NFILAUT);
572
573 /* Keep the VADNMINEN bitfield cleared. */
574 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
575 MICFIL_VAD0_NCONFIG_NMINEN);
576
577 /* Keep the VADNDECEN bitfield cleared. */
578 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
579 MICFIL_VAD0_NCONFIG_NDECEN);
580
581 /* Keep the VADNOREN bitfield cleared. */
582 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
583 MICFIL_VAD0_NCONFIG_NOREN);
584
585 return 0;
586 }
587
588 /* Configuration done only in envelope-based initialization mode */
fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil * micfil)589 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
590 {
591 /* Assert the VADFRENDIS bitfield */
592 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
593 MICFIL_VAD0_CTRL2_FRENDIS);
594
595 /* Assert the VADPREFEN bitfield. */
596 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
597 MICFIL_VAD0_CTRL2_PREFEN);
598
599 /* Assert the VADSFILEN bitfield. */
600 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
601 MICFIL_VAD0_SCONFIG_SFILEN);
602
603 /* Assert the VADSMAXEN bitfield. */
604 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
605 MICFIL_VAD0_SCONFIG_SMAXEN);
606
607 /* Clear the VADNFILAUTO bitfield */
608 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
609 MICFIL_VAD0_NCONFIG_NFILAUT);
610
611 /* Assert the VADNMINEN bitfield. */
612 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
613 MICFIL_VAD0_NCONFIG_NMINEN);
614
615 /* Assert the VADNDECEN bitfield. */
616 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
617 MICFIL_VAD0_NCONFIG_NDECEN);
618
619 /* Assert VADNOREN bitfield. */
620 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
621 MICFIL_VAD0_NCONFIG_NOREN);
622
623 return 0;
624 }
625
626 /*
627 * Hardware Voice Active Detection: The HWVAD takes data from the input
628 * of a selected PDM microphone to detect if there is any
629 * voice activity. When a voice activity is detected, an interrupt could
630 * be delivered to the system. Initialization in section 8.4:
631 * Can work in two modes:
632 * -> Eneveope-based mode (section 8.4.1)
633 * -> Energy-based mode (section 8.4.2)
634 *
635 * It is important to remark that the HWVAD detector could be enabled
636 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
637 * bit in STAT register is cleared
638 */
fsl_micfil_hwvad_enable(struct fsl_micfil * micfil)639 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
640 {
641 int ret;
642
643 micfil->vad_detected = 0;
644
645 /* envelope-based specific initialization */
646 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
647 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
648 else
649 ret = fsl_micfil_init_hwvad_energy_mode(micfil);
650 if (ret)
651 return ret;
652
653 /* Voice Activity Detector Internal Filters Initialization*/
654 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
655 MICFIL_VAD0_CTRL1_ST10);
656
657 /* Voice Activity Detector Internal Filter */
658 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
659 MICFIL_VAD0_CTRL1_ST10);
660
661 /* Enable Interrupts */
662 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
663 if (ret)
664 return ret;
665
666 /* Voice Activity Detector Reset */
667 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
668 MICFIL_VAD0_CTRL1_RST);
669
670 /* Voice Activity Detector Enabled */
671 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
672 MICFIL_VAD0_CTRL1_EN);
673
674 return 0;
675 }
676
fsl_micfil_hwvad_disable(struct fsl_micfil * micfil)677 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
678 {
679 struct device *dev = &micfil->pdev->dev;
680 int ret = 0;
681
682 /* Disable HWVAD */
683 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
684 MICFIL_VAD0_CTRL1_EN);
685
686 /* Disable hwvad interrupts */
687 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
688 if (ret)
689 dev_err(dev, "Failed to disable interrupts\n");
690
691 return ret;
692 }
693
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)694 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
695 struct snd_soc_dai *dai)
696 {
697 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
698 struct device *dev = &micfil->pdev->dev;
699 int ret;
700
701 switch (cmd) {
702 case SNDRV_PCM_TRIGGER_START:
703 case SNDRV_PCM_TRIGGER_RESUME:
704 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
705 ret = fsl_micfil_reset(dev);
706 if (ret) {
707 dev_err(dev, "failed to soft reset\n");
708 return ret;
709 }
710
711 /* DMA Interrupt Selection - DISEL bits
712 * 00 - DMA and IRQ disabled
713 * 01 - DMA req enabled
714 * 10 - IRQ enabled
715 * 11 - reserved
716 */
717 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
718 MICFIL_CTRL1_DISEL,
719 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
720 if (ret)
721 return ret;
722
723 /* Enable the module */
724 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
725 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
726 if (ret)
727 return ret;
728
729 if (micfil->vad_enabled && !micfil->dec_bypass)
730 fsl_micfil_hwvad_enable(micfil);
731
732 break;
733 case SNDRV_PCM_TRIGGER_STOP:
734 case SNDRV_PCM_TRIGGER_SUSPEND:
735 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
736 if (micfil->vad_enabled && !micfil->dec_bypass)
737 fsl_micfil_hwvad_disable(micfil);
738
739 /* Disable the module */
740 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
741 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
742 if (ret)
743 return ret;
744
745 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
746 MICFIL_CTRL1_DISEL,
747 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
748 if (ret)
749 return ret;
750 break;
751 default:
752 return -EINVAL;
753 }
754 return 0;
755 }
756
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)757 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
758 {
759 struct device *dev = &micfil->pdev->dev;
760 u64 ratio = sample_rate;
761 struct clk *clk;
762 int ret;
763
764 /* Get root clock */
765 clk = micfil->mclk;
766
767 /* Disable clock first, for it was enabled by pm_runtime */
768 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
769 micfil->pll11k_clk, ratio);
770 ret = clk_prepare_enable(clk);
771 if (ret)
772 return ret;
773
774 return 0;
775 }
776
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)777 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
778 struct snd_pcm_hw_params *params,
779 struct snd_soc_dai *dai)
780 {
781 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
782 unsigned int channels = params_channels(params);
783 snd_pcm_format_t format = params_format(params);
784 unsigned int rate = params_rate(params);
785 int clk_div = 8, mclk_rate, div_multiply_k;
786 int osr = MICFIL_OSR_DEFAULT;
787 int ret;
788
789 /* 1. Disable the module */
790 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
791 MICFIL_CTRL1_PDMIEN);
792 if (ret)
793 return ret;
794
795 /* enable channels */
796 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
797 0xFF, ((1 << channels) - 1));
798 if (ret)
799 return ret;
800
801 ret = fsl_micfil_reparent_rootclk(micfil, rate);
802 if (ret)
803 return ret;
804
805 micfil->mclk_flag = true;
806
807 /* floor(K * CLKDIV) */
808 switch (micfil->quality) {
809 case QUALITY_HIGH:
810 div_multiply_k = clk_div >> 1;
811 break;
812 case QUALITY_LOW:
813 case QUALITY_VLOW1:
814 div_multiply_k = clk_div << 1;
815 break;
816 case QUALITY_VLOW2:
817 div_multiply_k = clk_div << 2;
818 break;
819 case QUALITY_MEDIUM:
820 case QUALITY_VLOW0:
821 default:
822 div_multiply_k = clk_div;
823 break;
824 }
825
826 if (format == SNDRV_PCM_FORMAT_DSD_U32_BE) {
827 micfil->dec_bypass = true;
828 /*
829 * According to equation 29 in RM:
830 * MCLK_CLK_ROOT = PDM CLK rate * 2 * floor(K * CLKDIV)
831 * PDM CLK rate = rate * physical bit width (32)
832 */
833 mclk_rate = rate * div_multiply_k * 32 * 2;
834 } else {
835 micfil->dec_bypass = false;
836 mclk_rate = rate * clk_div * osr * 8;
837 }
838
839 ret = clk_set_rate(micfil->mclk, mclk_rate);
840 if (ret)
841 return ret;
842
843 ret = micfil_set_quality(micfil);
844 if (ret)
845 return ret;
846
847 regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
848 MICFIL_CTRL2_DEC_BYPASS,
849 micfil->dec_bypass ? MICFIL_CTRL2_DEC_BYPASS : 0);
850
851 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
852 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
853 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
854 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
855
856 /* Configure CIC OSR in VADCICOSR */
857 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
858 MICFIL_VAD0_CTRL1_CICOSR,
859 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
860
861 /* Configure source channel in VADCHSEL */
862 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
863 MICFIL_VAD0_CTRL1_CHSEL,
864 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
865
866 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
867 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
868 micfil->sdmacfg.n_fifos_src = channels;
869 micfil->sdmacfg.sw_done = true;
870 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
871 if (micfil->soc->use_edma)
872 micfil->dma_params_rx.maxburst = channels;
873
874 return 0;
875 }
876
fsl_micfil_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)877 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
878 struct snd_soc_dai *dai)
879 {
880 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
881
882 clk_disable_unprepare(micfil->mclk);
883 micfil->mclk_flag = false;
884
885 return 0;
886 }
887
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)888 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
889 {
890 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
891 struct device *dev = cpu_dai->dev;
892 unsigned int val = 0;
893 int ret, i;
894
895 micfil->quality = QUALITY_VLOW0;
896 micfil->card = cpu_dai->component->card;
897
898 /* set default gain to 2 */
899 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
900
901 /* set DC Remover in bypass mode*/
902 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
903 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
904 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
905 MICFIL_DC_CTRL_CONFIG, val);
906 if (ret) {
907 dev_err(dev, "failed to set DC Remover mode bits\n");
908 return ret;
909 }
910 micfil->dc_remover = MICFIL_DC_BYPASS;
911
912 snd_soc_dai_init_dma_data(cpu_dai, NULL,
913 &micfil->dma_params_rx);
914
915 /* FIFO Watermark Control - FIFOWMK*/
916 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
917 MICFIL_FIFO_CTRL_FIFOWMK,
918 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
919 if (ret)
920 return ret;
921
922 return 0;
923 }
924
fsl_micfil_component_probe(struct snd_soc_component * component)925 static int fsl_micfil_component_probe(struct snd_soc_component *component)
926 {
927 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
928
929 if (micfil->soc->volume_sx)
930 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
931 ARRAY_SIZE(fsl_micfil_volume_sx_controls));
932 else
933 snd_soc_add_component_controls(component, fsl_micfil_volume_controls,
934 ARRAY_SIZE(fsl_micfil_volume_controls));
935
936 return 0;
937 }
938
939 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
940 .probe = fsl_micfil_dai_probe,
941 .startup = fsl_micfil_startup,
942 .trigger = fsl_micfil_trigger,
943 .hw_params = fsl_micfil_hw_params,
944 .hw_free = fsl_micfil_hw_free,
945 };
946
947 static struct snd_soc_dai_driver fsl_micfil_dai = {
948 .capture = {
949 .stream_name = "CPU-Capture",
950 .channels_min = 1,
951 .channels_max = 8,
952 .rates = SNDRV_PCM_RATE_8000_48000,
953 .formats = SNDRV_PCM_FMTBIT_S16_LE,
954 },
955 .ops = &fsl_micfil_dai_ops,
956 };
957
958 static const struct snd_soc_component_driver fsl_micfil_component = {
959 .name = "fsl-micfil-dai",
960 .probe = fsl_micfil_component_probe,
961 .controls = fsl_micfil_snd_controls,
962 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
963 .legacy_dai_naming = 1,
964 };
965
966 /* REGMAP */
967 static const struct reg_default fsl_micfil_reg_defaults[] = {
968 {REG_MICFIL_CTRL1, 0x00000000},
969 {REG_MICFIL_CTRL2, 0x00000000},
970 {REG_MICFIL_STAT, 0x00000000},
971 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
972 {REG_MICFIL_FIFO_STAT, 0x00000000},
973 {REG_MICFIL_DATACH0, 0x00000000},
974 {REG_MICFIL_DATACH1, 0x00000000},
975 {REG_MICFIL_DATACH2, 0x00000000},
976 {REG_MICFIL_DATACH3, 0x00000000},
977 {REG_MICFIL_DATACH4, 0x00000000},
978 {REG_MICFIL_DATACH5, 0x00000000},
979 {REG_MICFIL_DATACH6, 0x00000000},
980 {REG_MICFIL_DATACH7, 0x00000000},
981 {REG_MICFIL_DC_CTRL, 0x00000000},
982 {REG_MICFIL_OUT_CTRL, 0x00000000},
983 {REG_MICFIL_OUT_STAT, 0x00000000},
984 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
985 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
986 {REG_MICFIL_VAD0_STAT, 0x00000000},
987 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
988 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
989 {REG_MICFIL_VAD0_NDATA, 0x00000000},
990 {REG_MICFIL_VAD0_ZCD, 0x00000004},
991 };
992
993 static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
994 {REG_MICFIL_CTRL1, 0x00000000},
995 {REG_MICFIL_CTRL2, 0x00000000},
996 {REG_MICFIL_STAT, 0x00000000},
997 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
998 {REG_MICFIL_FIFO_STAT, 0x00000000},
999 {REG_MICFIL_DATACH0 - 0x4, 0x00000000},
1000 {REG_MICFIL_DATACH1 - 0x4, 0x00000000},
1001 {REG_MICFIL_DATACH2 - 0x4, 0x00000000},
1002 {REG_MICFIL_DATACH3 - 0x4, 0x00000000},
1003 {REG_MICFIL_DATACH4 - 0x4, 0x00000000},
1004 {REG_MICFIL_DATACH5 - 0x4, 0x00000000},
1005 {REG_MICFIL_DATACH6 - 0x4, 0x00000000},
1006 {REG_MICFIL_DATACH7 - 0x4, 0x00000000},
1007 {REG_MICFIL_DC_CTRL, 0x00000000},
1008 {REG_MICFIL_OUT_CTRL, 0x00000000},
1009 {REG_MICFIL_OUT_STAT, 0x00000000},
1010 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
1011 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
1012 {REG_MICFIL_VAD0_STAT, 0x00000000},
1013 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
1014 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
1015 {REG_MICFIL_VAD0_NDATA, 0x00000000},
1016 {REG_MICFIL_VAD0_ZCD, 0x00000004},
1017 };
1018
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)1019 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
1020 {
1021 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1022 int ofs = micfil->soc->fifo_offset;
1023
1024 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1025 return true;
1026
1027 switch (reg) {
1028 case REG_MICFIL_CTRL1:
1029 case REG_MICFIL_CTRL2:
1030 case REG_MICFIL_STAT:
1031 case REG_MICFIL_FIFO_CTRL:
1032 case REG_MICFIL_FIFO_STAT:
1033 case REG_MICFIL_DC_CTRL:
1034 case REG_MICFIL_OUT_CTRL:
1035 case REG_MICFIL_OUT_STAT:
1036 case REG_MICFIL_VAD0_CTRL1:
1037 case REG_MICFIL_VAD0_CTRL2:
1038 case REG_MICFIL_VAD0_STAT:
1039 case REG_MICFIL_VAD0_SCONFIG:
1040 case REG_MICFIL_VAD0_NCONFIG:
1041 case REG_MICFIL_VAD0_NDATA:
1042 case REG_MICFIL_VAD0_ZCD:
1043 return true;
1044 case REG_MICFIL_FSYNC_CTRL:
1045 case REG_MICFIL_VERID:
1046 case REG_MICFIL_PARAM:
1047 if (micfil->soc->use_verid)
1048 return true;
1049 fallthrough;
1050 default:
1051 return false;
1052 }
1053 }
1054
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)1055 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
1056 {
1057 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1058
1059 switch (reg) {
1060 case REG_MICFIL_CTRL1:
1061 case REG_MICFIL_CTRL2:
1062 case REG_MICFIL_STAT: /* Write 1 to Clear */
1063 case REG_MICFIL_FIFO_CTRL:
1064 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
1065 case REG_MICFIL_DC_CTRL:
1066 case REG_MICFIL_OUT_CTRL:
1067 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
1068 case REG_MICFIL_VAD0_CTRL1:
1069 case REG_MICFIL_VAD0_CTRL2:
1070 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
1071 case REG_MICFIL_VAD0_SCONFIG:
1072 case REG_MICFIL_VAD0_NCONFIG:
1073 case REG_MICFIL_VAD0_ZCD:
1074 return true;
1075 case REG_MICFIL_FSYNC_CTRL:
1076 if (micfil->soc->use_verid)
1077 return true;
1078 fallthrough;
1079 default:
1080 return false;
1081 }
1082 }
1083
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)1084 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1085 {
1086 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1087 int ofs = micfil->soc->fifo_offset;
1088
1089 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1090 return true;
1091
1092 switch (reg) {
1093 case REG_MICFIL_STAT:
1094 case REG_MICFIL_FIFO_STAT:
1095 case REG_MICFIL_OUT_STAT:
1096 case REG_MICFIL_VERID:
1097 case REG_MICFIL_PARAM:
1098 case REG_MICFIL_VAD0_STAT:
1099 case REG_MICFIL_VAD0_NDATA:
1100 return true;
1101 default:
1102 return false;
1103 }
1104 }
1105
1106 static const struct regmap_config fsl_micfil_regmap_config = {
1107 .reg_bits = 32,
1108 .reg_stride = 4,
1109 .val_bits = 32,
1110
1111 .max_register = REG_MICFIL_VAD0_ZCD,
1112 .reg_defaults = fsl_micfil_reg_defaults,
1113 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1114 .readable_reg = fsl_micfil_readable_reg,
1115 .volatile_reg = fsl_micfil_volatile_reg,
1116 .writeable_reg = fsl_micfil_writeable_reg,
1117 .cache_type = REGCACHE_MAPLE,
1118 };
1119
1120 static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1121 .reg_bits = 32,
1122 .reg_stride = 4,
1123 .val_bits = 32,
1124
1125 .max_register = REG_MICFIL_VAD0_ZCD,
1126 .reg_defaults = fsl_micfil_reg_defaults_v2,
1127 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1128 .readable_reg = fsl_micfil_readable_reg,
1129 .volatile_reg = fsl_micfil_volatile_reg,
1130 .writeable_reg = fsl_micfil_writeable_reg,
1131 .cache_type = REGCACHE_MAPLE,
1132 };
1133
1134 /* END OF REGMAP */
1135
micfil_isr(int irq,void * devid)1136 static irqreturn_t micfil_isr(int irq, void *devid)
1137 {
1138 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1139 struct platform_device *pdev = micfil->pdev;
1140 u32 stat_reg;
1141 u32 fifo_stat_reg;
1142 u32 ctrl1_reg;
1143 bool dma_enabled;
1144 int i;
1145
1146 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1147 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1148 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1149
1150 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1151
1152 /* Channel 0-7 Output Data Flags */
1153 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1154 if (stat_reg & MICFIL_STAT_CHXF(i))
1155 dev_dbg(&pdev->dev,
1156 "Data available in Data Channel %d\n", i);
1157 /* if DMA is not enabled, field must be written with 1
1158 * to clear
1159 */
1160 if (!dma_enabled)
1161 regmap_write_bits(micfil->regmap,
1162 REG_MICFIL_STAT,
1163 MICFIL_STAT_CHXF(i),
1164 MICFIL_STAT_CHXF(i));
1165 }
1166
1167 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1168 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1169 dev_dbg(&pdev->dev,
1170 "FIFO Overflow Exception flag for channel %d\n",
1171 i);
1172
1173 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1174 dev_dbg(&pdev->dev,
1175 "FIFO Underflow Exception flag for channel %d\n",
1176 i);
1177 }
1178
1179 return IRQ_HANDLED;
1180 }
1181
micfil_err_isr(int irq,void * devid)1182 static irqreturn_t micfil_err_isr(int irq, void *devid)
1183 {
1184 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1185 struct platform_device *pdev = micfil->pdev;
1186 u32 fifo_stat_reg;
1187 u32 out_stat_reg;
1188 u32 stat_reg;
1189
1190 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1191
1192 if (stat_reg & MICFIL_STAT_BSY_FIL)
1193 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1194
1195 if (stat_reg & MICFIL_STAT_FIR_RDY)
1196 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1197
1198 if (stat_reg & MICFIL_STAT_LOWFREQF) {
1199 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1200 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1201 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1202 }
1203
1204 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1205 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
1206 fifo_stat_reg, fifo_stat_reg);
1207
1208 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
1209 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
1210 out_stat_reg, out_stat_reg);
1211
1212 return IRQ_HANDLED;
1213 }
1214
voice_detected_fn(int irq,void * devid)1215 static irqreturn_t voice_detected_fn(int irq, void *devid)
1216 {
1217 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1218 struct snd_kcontrol *kctl;
1219
1220 if (!micfil->card)
1221 return IRQ_HANDLED;
1222
1223 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1224 if (!kctl)
1225 return IRQ_HANDLED;
1226
1227 if (micfil->vad_detected)
1228 snd_ctl_notify(micfil->card->snd_card,
1229 SNDRV_CTL_EVENT_MASK_VALUE,
1230 &kctl->id);
1231
1232 return IRQ_HANDLED;
1233 }
1234
hwvad_isr(int irq,void * devid)1235 static irqreturn_t hwvad_isr(int irq, void *devid)
1236 {
1237 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1238 struct device *dev = &micfil->pdev->dev;
1239 u32 vad0_reg;
1240 int ret;
1241
1242 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1243
1244 /*
1245 * The only difference between MICFIL_VAD0_STAT_EF and
1246 * MICFIL_VAD0_STAT_IF is that the former requires Write
1247 * 1 to Clear. Since both flags are set, it is enough
1248 * to only read one of them
1249 */
1250 if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1251 /* Write 1 to clear */
1252 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1253 MICFIL_VAD0_STAT_IF,
1254 MICFIL_VAD0_STAT_IF);
1255
1256 micfil->vad_detected = 1;
1257 }
1258
1259 ret = fsl_micfil_hwvad_disable(micfil);
1260 if (ret)
1261 dev_err(dev, "Failed to disable hwvad\n");
1262
1263 return IRQ_WAKE_THREAD;
1264 }
1265
hwvad_err_isr(int irq,void * devid)1266 static irqreturn_t hwvad_err_isr(int irq, void *devid)
1267 {
1268 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1269 struct device *dev = &micfil->pdev->dev;
1270 u32 vad0_reg;
1271
1272 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1273
1274 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1275 dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1276
1277 return IRQ_HANDLED;
1278 }
1279
1280 static int fsl_micfil_runtime_suspend(struct device *dev);
1281 static int fsl_micfil_runtime_resume(struct device *dev);
1282
fsl_micfil_probe(struct platform_device * pdev)1283 static int fsl_micfil_probe(struct platform_device *pdev)
1284 {
1285 struct device_node *np = pdev->dev.of_node;
1286 struct fsl_micfil *micfil;
1287 struct resource *res;
1288 void __iomem *regs;
1289 int ret, i;
1290
1291 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1292 if (!micfil)
1293 return -ENOMEM;
1294
1295 micfil->pdev = pdev;
1296 strscpy(micfil->name, np->name, sizeof(micfil->name));
1297
1298 micfil->soc = of_device_get_match_data(&pdev->dev);
1299
1300 /* ipg_clk is used to control the registers
1301 * ipg_clk_app is used to operate the filter
1302 */
1303 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1304 if (IS_ERR(micfil->mclk)) {
1305 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1306 PTR_ERR(micfil->mclk));
1307 return PTR_ERR(micfil->mclk);
1308 }
1309
1310 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1311 if (IS_ERR(micfil->busclk)) {
1312 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1313 PTR_ERR(micfil->busclk));
1314 return PTR_ERR(micfil->busclk);
1315 }
1316
1317 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1318 &micfil->pll11k_clk);
1319
1320 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1321 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1322 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1323 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1324 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1325
1326 fsl_asoc_constrain_rates(&micfil->constraint_rates,
1327 &fsl_micfil_rate_constraints,
1328 micfil->clk_src[MICFIL_AUDIO_PLL1],
1329 micfil->clk_src[MICFIL_AUDIO_PLL2],
1330 micfil->clk_src[MICFIL_CLK_EXT3],
1331 micfil->constraint_rates_list);
1332
1333 /* init regmap */
1334 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1335 if (IS_ERR(regs))
1336 return PTR_ERR(regs);
1337
1338 if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1339 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1340 regs,
1341 &fsl_micfil_regmap_config_v2);
1342 else
1343 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1344 regs,
1345 &fsl_micfil_regmap_config);
1346 if (IS_ERR(micfil->regmap)) {
1347 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1348 PTR_ERR(micfil->regmap));
1349 return PTR_ERR(micfil->regmap);
1350 }
1351
1352 /* dataline mask for RX */
1353 ret = of_property_read_u32_index(np,
1354 "fsl,dataline",
1355 0,
1356 &micfil->dataline);
1357 if (ret)
1358 micfil->dataline = 1;
1359
1360 if (micfil->dataline & ~micfil->soc->dataline) {
1361 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1362 micfil->soc->dataline);
1363 return -EINVAL;
1364 }
1365
1366 /* get IRQs */
1367 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1368 micfil->irq[i] = platform_get_irq(pdev, i);
1369 if (micfil->irq[i] < 0)
1370 return micfil->irq[i];
1371 }
1372
1373 /* Digital Microphone interface interrupt */
1374 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1375 micfil_isr, IRQF_SHARED,
1376 micfil->name, micfil);
1377 if (ret) {
1378 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1379 micfil->irq[0]);
1380 return ret;
1381 }
1382
1383 /* Digital Microphone interface error interrupt */
1384 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1385 micfil_err_isr, IRQF_SHARED,
1386 micfil->name, micfil);
1387 if (ret) {
1388 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1389 micfil->irq[1]);
1390 return ret;
1391 }
1392
1393 /* Digital Microphone interface voice activity detector event */
1394 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1395 hwvad_isr, voice_detected_fn,
1396 IRQF_SHARED, micfil->name, micfil);
1397 if (ret) {
1398 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1399 micfil->irq[0]);
1400 return ret;
1401 }
1402
1403 /* Digital Microphone interface voice activity detector error */
1404 ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1405 hwvad_err_isr, IRQF_SHARED,
1406 micfil->name, micfil);
1407 if (ret) {
1408 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1409 micfil->irq[1]);
1410 return ret;
1411 }
1412
1413 micfil->dma_params_rx.chan_name = "rx";
1414 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
1415 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1416
1417 platform_set_drvdata(pdev, micfil);
1418
1419 pm_runtime_enable(&pdev->dev);
1420 if (!pm_runtime_enabled(&pdev->dev)) {
1421 ret = fsl_micfil_runtime_resume(&pdev->dev);
1422 if (ret)
1423 goto err_pm_disable;
1424 }
1425
1426 ret = pm_runtime_resume_and_get(&pdev->dev);
1427 if (ret < 0)
1428 goto err_pm_get_sync;
1429
1430 /* Get micfil version */
1431 ret = fsl_micfil_use_verid(&pdev->dev);
1432 if (ret < 0)
1433 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1434
1435 ret = pm_runtime_put_sync(&pdev->dev);
1436 if (ret < 0 && ret != -ENOSYS)
1437 goto err_pm_get_sync;
1438
1439 regcache_cache_only(micfil->regmap, true);
1440
1441 /*
1442 * Register platform component before registering cpu dai for there
1443 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1444 */
1445 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1446 if (ret) {
1447 dev_err(&pdev->dev, "failed to pcm register\n");
1448 goto err_pm_disable;
1449 }
1450
1451 fsl_micfil_dai.capture.formats = micfil->soc->formats;
1452
1453 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1454 &fsl_micfil_dai, 1);
1455 if (ret) {
1456 dev_err(&pdev->dev, "failed to register component %s\n",
1457 fsl_micfil_component.name);
1458 goto err_pm_disable;
1459 }
1460
1461 return ret;
1462
1463 err_pm_get_sync:
1464 if (!pm_runtime_status_suspended(&pdev->dev))
1465 fsl_micfil_runtime_suspend(&pdev->dev);
1466 err_pm_disable:
1467 pm_runtime_disable(&pdev->dev);
1468
1469 return ret;
1470 }
1471
fsl_micfil_remove(struct platform_device * pdev)1472 static void fsl_micfil_remove(struct platform_device *pdev)
1473 {
1474 pm_runtime_disable(&pdev->dev);
1475 }
1476
fsl_micfil_runtime_suspend(struct device * dev)1477 static int fsl_micfil_runtime_suspend(struct device *dev)
1478 {
1479 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1480
1481 regcache_cache_only(micfil->regmap, true);
1482
1483 if (micfil->mclk_flag)
1484 clk_disable_unprepare(micfil->mclk);
1485 clk_disable_unprepare(micfil->busclk);
1486
1487 return 0;
1488 }
1489
fsl_micfil_runtime_resume(struct device * dev)1490 static int fsl_micfil_runtime_resume(struct device *dev)
1491 {
1492 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1493 int ret;
1494
1495 ret = clk_prepare_enable(micfil->busclk);
1496 if (ret < 0)
1497 return ret;
1498
1499 if (micfil->mclk_flag) {
1500 ret = clk_prepare_enable(micfil->mclk);
1501 if (ret < 0) {
1502 clk_disable_unprepare(micfil->busclk);
1503 return ret;
1504 }
1505 }
1506
1507 regcache_cache_only(micfil->regmap, false);
1508 regcache_mark_dirty(micfil->regmap);
1509 regcache_sync(micfil->regmap);
1510
1511 return 0;
1512 }
1513
1514 static const struct dev_pm_ops fsl_micfil_pm_ops = {
1515 RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, fsl_micfil_runtime_resume, NULL)
1516 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1517 };
1518
1519 static struct platform_driver fsl_micfil_driver = {
1520 .probe = fsl_micfil_probe,
1521 .remove = fsl_micfil_remove,
1522 .driver = {
1523 .name = "fsl-micfil-dai",
1524 .pm = pm_ptr(&fsl_micfil_pm_ops),
1525 .of_match_table = fsl_micfil_dt_ids,
1526 },
1527 };
1528 module_platform_driver(fsl_micfil_driver);
1529
1530 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1531 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1532 MODULE_LICENSE("Dual BSD/GPL");
1533