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Searched refs:MHZ (Results 1 – 25 of 61) sorted by relevance

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/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c672 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
673 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
675 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
676 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
677 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
678 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
679 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
680 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
681 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
H A Dclk-exynos4.c1075 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1076 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1077 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1078 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1079 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1080 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1081 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1082 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1083 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1088 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
[all …]
H A Dclk-exynos5420.c1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1411 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1412 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
H A Dclk-exynos5250.c694 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
696 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
703 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
704 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
705 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
706 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
707 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
708 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
709 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
710 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
[all …]
H A Dclk-exynos5433.c735 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
736 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
737 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
738 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
740 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
741 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
743 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
744 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
H A Dclk-exynos850.c1164 PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1165 PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1166 PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1167 PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1168 PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1169 PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1170 PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1171 PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1172 PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
1173 PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux/drivers/net/can/softing/
H A Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux/arch/arm/mach-s3c/
H A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
H A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
323 unsigned long mbps = dphy_opts->hs_clk_rate / MHZ(1); in dphy_pll_get_hsfreqrange()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt2701.c28 108 * MHZ),
30 400 * MHZ),
34 340 * MHZ),
36 340 * MHZ),
38 340 * MHZ),
40 27 * MHZ),
42 416 * MHZ),
44 143 * MHZ),
46 27 * MHZ),
917 #define MT8590_PLL_FMAX (2000 * MHZ)
/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
H A Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
H A Dphy-exynos5250-usb2.c149 case 10 * MHZ: in exynos5250_rate_to_clk()
152 case 12 * MHZ: in exynos5250_rate_to_clk()
158 case 20 * MHZ: in exynos5250_rate_to_clk()
161 case 24 * MHZ: in exynos5250_rate_to_clk()
164 case 50 * MHZ: in exynos5250_rate_to_clk()
H A Dphy-exynos4210-usb2.c108 case 12 * MHZ: in exynos4210_rate_to_clk()
111 case 24 * MHZ: in exynos4210_rate_to_clk()
114 case 48 * MHZ: in exynos4210_rate_to_clk()
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c43 #ifndef MHZ
44 #define MHZ (1000UL * 1000UL) macro
340 if (int_pllclk < (50 * MHZ)) in fsl_samsung_hdmi_phy_configure_pll_lock_det()
361 fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
409 do_div(tmp, 24 * MHZ); in fsl_samsung_hdmi_phy_find_pms()
421 tmp = div64_ul((u64)_m * 24 * MHZ, _p); in fsl_samsung_hdmi_phy_find_pms()
422 if (tmp < 750 * MHZ || in fsl_samsung_hdmi_phy_find_pms()
423 tmp > 3000 * MHZ) in fsl_samsung_hdmi_phy_find_pms()
/linux/drivers/clk/hisilicon/
H A Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
76 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c61 #define MHZ (KHZ * KHZ) macro
68 #define PLL_FREF_SG2042 (25 * MHZ)
70 #define PLL_FOUTPOSTDIV_MIN (16 * MHZ)
71 #define PLL_FOUTPOSTDIV_MAX (3200 * MHZ)
73 #define PLL_FOUTVCO_MIN (800 * MHZ)
74 #define PLL_FOUTVCO_MAX (3200 * MHZ)
/linux/drivers/soc/samsung/
H A Dexynos-asv.c25 #define MHZ 1000000U macro
51 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
66 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
/linux/arch/powerpc/boot/
H A Dredboot-8xx.c19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
H A Dredboot-83xx.c20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
H A Ddevtree.c61 #define MHZ(x) ((x + 500000) / 1000000) macro
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
87 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()
/linux/drivers/clk/ingenic/
H A Djz4760-cgu.c20 #define MHZ (1000 * 1000) macro
64 n = parent_rate / (1 * MHZ); in jz4760_cgu_calc_m_n_od()
69 rate /= MHZ; in jz4760_cgu_calc_m_n_od()
70 parent_rate /= MHZ; in jz4760_cgu_calc_m_n_od()

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