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Searched refs:MHZ (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c32 #define MHZ(v) ((u32)((v) * 1000000U)) macro
104 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
105 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
106 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
107 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
108 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
109 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
110 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
111 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
112 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux/drivers/net/can/softing/
H A Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux/arch/arm/mach-s3c/
H A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
H A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
323 unsigned long mbps = dphy_opts->hs_clk_rate / MHZ(1); in dphy_pll_get_hsfreqrange()
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
H A Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
H A Dphy-exynos5250-usb2.c149 case 10 * MHZ: in exynos5250_rate_to_clk()
152 case 12 * MHZ: in exynos5250_rate_to_clk()
158 case 20 * MHZ: in exynos5250_rate_to_clk()
161 case 24 * MHZ: in exynos5250_rate_to_clk()
164 case 50 * MHZ: in exynos5250_rate_to_clk()
H A Dphy-exynos4210-usb2.c108 case 12 * MHZ: in exynos4210_rate_to_clk()
111 case 24 * MHZ: in exynos4210_rate_to_clk()
114 case 48 * MHZ: in exynos4210_rate_to_clk()
H A Dphy-samsung-usb2.h20 #define MHZ (KHZ * KHZ) macro
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp-common.dtsi220 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
222 * clock output from WiFi to the CMN PLL is 48 MHZ.
230 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
231 * from WiFi output clock 48 MHZ divided by 2.
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c61 #define MHZ (KHZ * KHZ) macro
68 #define PLL_FREF_SG2042 (25 * MHZ)
70 #define PLL_FOUTPOSTDIV_MIN (16 * MHZ)
71 #define PLL_FOUTPOSTDIV_MAX (3200 * MHZ)
73 #define PLL_FOUTVCO_MIN (800 * MHZ)
74 #define PLL_FOUTVCO_MAX (3200 * MHZ)
/linux/drivers/soc/samsung/
H A Dexynos-asv.c25 #define MHZ 1000000U macro
51 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
66 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
/linux/drivers/clk/hisilicon/
H A Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()
/linux/arch/powerpc/boot/
H A Dredboot-8xx.c19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
H A Dredboot-83xx.c20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
H A Ddevtree.c61 #define MHZ(x) ((x + 500000) / 1000000) macro
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
87 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()
/linux/drivers/clk/ingenic/
H A Djz4760-cgu.c20 #define MHZ (1000 * 1000) macro
64 n = parent_rate / (1 * MHZ); in jz4760_cgu_calc_m_n_od()
69 rate /= MHZ; in jz4760_cgu_calc_m_n_od()
70 parent_rate /= MHZ; in jz4760_cgu_calc_m_n_od()
/linux/drivers/mfd/
H A Dsm501.c86 #define MHZ (1000 * 1000) macro
121 pll2 = 288 * MHZ; in decode_div()
126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
1492 .mclk = 72 * MHZ,
[all …]
/linux/drivers/clk/samsung/
H A Dclk-artpec8.c170 PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
171 PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
172 PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
173 PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
174 PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184),
175 PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184),
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c351 FIXED_CLK(CLK_TOP_ADSYS_26M, "adsys_26m", "clk26m", 26 * MHZ),
353 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
/linux/arch/arc/boot/dts/
H A Dhaps_hs_idu.dts40 clock-frequency = <50000000>; /* 50 MHZ */
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c46 #define MHZ 1000000 macro
47 #define FVCO_MIN (1500U * MHZ)
48 #define FVCO_MAX (3000U * MHZ)

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