1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H 7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H 8 9 /* DISP_CC_0 and DISP_CC_1 clocks */ 10 #define MDSS_DISP_CC_ACMU_CLK 0 11 #define MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK 1 12 #define MDSS_DISP_CC_MDSS_AHB1_CLK 2 13 #define MDSS_DISP_CC_MDSS_AHB_CLK 3 14 #define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 4 15 #define MDSS_DISP_CC_MDSS_BYTE0_CLK 5 16 #define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 6 17 #define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7 18 #define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 8 19 #define MDSS_DISP_CC_MDSS_BYTE1_CLK 9 20 #define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 10 21 #define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 11 22 #define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 12 23 #define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 13 24 #define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 14 25 #define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 15 26 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 16 27 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 17 28 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 18 29 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 19 30 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 20 31 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 21 32 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 22 33 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 23 34 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 24 35 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 25 36 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 26 37 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 27 38 #define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28 39 #define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 29 40 #define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30 41 #define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 31 42 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32 43 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33 44 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34 45 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35 46 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36 47 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37 48 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38 49 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39 50 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK 40 51 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC 41 52 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK 42 53 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC 43 54 #define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 44 55 #define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK 45 56 #define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46 57 #define MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK 47 58 #define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK 48 59 #define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 49 60 #define MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 50 61 #define MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 51 62 #define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK 52 63 #define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 53 64 #define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK 54 65 #define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 55 66 #define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK 56 67 #define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57 68 #define MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK 58 69 #define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK 59 70 #define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 60 71 #define MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 61 72 #define MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62 73 #define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63 74 #define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64 75 #define MDSS_DISP_CC_MDSS_ESC0_CLK 65 76 #define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 66 77 #define MDSS_DISP_CC_MDSS_ESC1_CLK 67 78 #define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 68 79 #define MDSS_DISP_CC_MDSS_MDP1_CLK 69 80 #define MDSS_DISP_CC_MDSS_MDP_CLK 70 81 #define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 71 82 #define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 72 83 #define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 73 84 #define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 74 85 #define MDSS_DISP_CC_MDSS_PCLK0_CLK 75 86 #define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 76 87 #define MDSS_DISP_CC_MDSS_PCLK1_CLK 77 88 #define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 78 89 #define MDSS_DISP_CC_MDSS_PCLK2_CLK 79 90 #define MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC 80 91 #define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 81 92 #define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 82 93 #define MDSS_DISP_CC_MDSS_VSYNC1_CLK 83 94 #define MDSS_DISP_CC_MDSS_VSYNC_CLK 84 95 #define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 85 96 #define MDSS_DISP_CC_PLL0 86 97 #define MDSS_DISP_CC_PLL1 87 98 #define MDSS_DISP_CC_PLL2 88 99 #define MDSS_DISP_CC_PLL3 89 100 #define MDSS_DISP_CC_SLEEP_CLK 90 101 #define MDSS_DISP_CC_SLEEP_CLK_SRC 91 102 #define MDSS_DISP_CC_SM_DIV_CLK_SRC 92 103 #define MDSS_DISP_CC_XO_CLK 93 104 #define MDSS_DISP_CC_XO_CLK_SRC 94 105 106 /* DISP_CC_0 and DISP_CC_1 power domains */ 107 #define MDSS_DISP_CC_MDSS_CORE_GDSC 0 108 #define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1 109 110 /* DISP_CC_0 and DISP_CC_1 resets */ 111 #define MDSS_DISP_CC_MDSS_CORE_BCR 0 112 #define MDSS_DISP_CC_MDSS_CORE_INT2_BCR 1 113 #define MDSS_DISP_CC_MDSS_RSCC_BCR 2 114 115 #endif 116