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Searched refs:MDIO_MMD_VEND2 (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/net/phy/
H A Ddp83tg720.c217 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LINK_QUAL_3); in dp83tg720_update_stats()
235 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_1); in dp83tg720_update_stats()
241 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_2); in dp83tg720_update_stats()
248 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_3); in dp83tg720_update_stats()
254 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_4); in dp83tg720_update_stats()
260 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_5); in dp83tg720_update_stats()
267 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_6); in dp83tg720_update_stats()
336 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_start()
341 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
346 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
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H A Dmicrochip_t1s.c151 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb_indirect_read()
156 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb_indirect_read()
161 return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA); in lan865x_revb_indirect_read()
195 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in lan865x_read_cfg_params()
212 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], in lan865x_write_cfg_params()
276 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
311 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
317 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
353 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
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H A Dphy-c45.c1425 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1434 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1440 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1447 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1453 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1486 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1501 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1518 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1526 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1541 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
H A Dnxp-c45-tja11xx-macsec.c301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
H A Dphy_device.c918 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
960 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
/linux/drivers/net/pcs/
H A Dpcs-xpcs.c291 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
390 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, in xpcs_link_up_usxgmii()
774 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); in xpcs_config_aneg_c37_sgmii()
779 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
800 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); in xpcs_config_aneg_c37_sgmii()
815 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); in xpcs_config_aneg_c37_sgmii()
820 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
842 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); in xpcs_config_aneg_c37_1000basex()
847 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_1000basex()
862 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); in xpcs_config_aneg_c37_1000basex()
[all …]
H A Dpcs-lynx.c67 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
76 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
167 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c400 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_ADDR_REG, in rtl8261x_probe()
405 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_DATA_REG); in rtl8261x_probe()
458 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, in rtl8261x_read_status()
625 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); in rtl8261x_config_intr()
629 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, in rtl8261x_config_intr()
634 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 0); in rtl8261x_config_intr()
638 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); in rtl8261x_config_intr()
650 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); in rtl8261x_handle_interrupt()
685 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, in rtl8261x_config_aneg()
1736 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); in rtlgen_read_vend2()
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H A Drealtek_hwmon.c33 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSRR) & 0x3ff; in rtl822x_hwmon_read()
38 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSSR) >> 6; in rtl822x_hwmon_read()
68 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSALRM, 3); in rtl822x_hwmon_init()
/linux/drivers/net/phy/mediatek/
H A Dmtk-phy-lib.c127 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
133 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
255 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
263 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
300 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_on_set()
325 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_blink_set()
H A Dmtk-ge-soc.c431 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, in rext_fill_result()
1317 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mt7988_phy_fix_leds_polarities()
1471 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in an7581_phy_led_polarity_set()
1490 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED_BCR, in en7528_phy_config_init()
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c42 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
44 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
51 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
53 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
68 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
70 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
271 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL); in xgbe_an37_set()
276 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg); in xgbe_an37_set()
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H A Dxgbe-phy-v2.c1536 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); in xgbe_phy_an37_outcome()
1537 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); in xgbe_phy_an37_outcome()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
/linux/include/uapi/linux/
H A Dmdio.h33 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
190 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.c1055 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1071 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1076 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1081 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1114 mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR); in lan743x_serdes_clock_and_aneg_update()
1118 an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL); in lan743x_serdes_clock_and_aneg_update()
1122 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1138 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1149 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_serdes_clock_and_aneg_update()
1154 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
[all …]
/linux/rust/kernel/net/phy/
H A Dreg.rs175 pub const VEND2: Self = Mmd(uapi::MDIO_MMD_VEND2 as u8);
/linux/drivers/net/dsa/
H A Dmt7530.c73 MII_MMD_CTRL, MDIO_MMD_VEND2); in core_write()
85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); in core_write()
110 MII_MMD_CTRL, MDIO_MMD_VEND2); in core_rmw()
122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); in core_rmw()
2818 MDIO_MMD_VEND2, CORE_PLL_GROUP4); in mt7531_setup()
2827 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); in mt7531_setup()
/linux/drivers/net/dsa/microchip/
H A Dksz9477.c213 } else if (mmd == MDIO_MMD_VEND2) { in ksz9477_pcs_read()
269 if (mmd == MDIO_MMD_VEND2) { in ksz9477_pcs_write()
/linux/drivers/net/ethernet/
H A Doa_tc6.c486 case MDIO_MMD_VEND2: in oa_tc6_get_phy_c45_mms()