| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | mdio_10g.c | 39 ef4_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET); in ef4_mdio_reset_mmd()
43 ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1); in ef4_mdio_reset_mmd()
86 stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1); in ef4_mdio_wait_reset_mmds()
188 MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
191 MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
194 MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
207 ef4_mdio_set_flag(efx, mmd, MDIO_CTRL1, in ef4_mdio_set_mmd_lpower()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
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| H A D | qt202x_phy.c | 204 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, in qt2025c_bug17190_workaround()
207 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, in qt2025c_bug17190_workaround()
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| /linux/drivers/net/ethernet/chelsio/cxgb3/ |
| H A D | aq100x.c | 123 MDIO_MMD_PMAPMD, MDIO_CTRL1, in aq100x_power_down()
134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
197 MDIO_MMD_PMAPMD, MDIO_CTRL1, in aq100x_set_loopback()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
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| H A D | ael1002.c | 148 MDIO_MMD_PMAPMD, MDIO_CTRL1, in ael1002_power_down()
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| H A D | t3_hw.c | 358 err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER, in t3_phy_reset()
364 err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl); in t3_phy_reset()
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| /linux/drivers/net/phy/ |
| H A D | phy-c45.c | 58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
119 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
323 u16 reg = MDIO_CTRL1; in genphy_c45_an_disable_aneg()
343 u16 reg = MDIO_CTRL1; in genphy_c45_restart_aneg()
364 u16 reg = MDIO_CTRL1; in genphy_c45_check_and_restart_aneg()
397 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_soft_reset()
403 MDIO_CTRL1, val, in genphy_c45_pma_soft_reset()
540 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
[all …]
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| H A D | marvell-88q2xxx.c | 150 { MDIO_MMD_PMAPMD, MDIO_CTRL1,
154 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
155 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
181 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
187 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
605 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_suspend()
621 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_resume()
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| H A D | bcm7xxx.c | 606 case MDIO_CTRL1: in bcm7xxx_28nm_ephy_regnum_to_shd()
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| /linux/drivers/net/ethernet/amd/xgbe/ |
| H A D | xgbe-mdio.c | 259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
307 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
316 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
907 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an37_init()
909 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an37_init()
1483 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, in xgbe_dump_phy_registers()
1484 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); in xgbe_dump_phy_registers()
1496 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, in xgbe_dump_phy_registers()
1497 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); in xgbe_dump_phy_registers()
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| /linux/drivers/net/pcs/ |
| H A D | pcs-xpcs.c | 386 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); in xpcs_link_up_usxgmii()
395 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, in xpcs_link_up_usxgmii()
461 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, in xpcs_config_aneg_c73()
575 pcs_ctrl1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL1); in xpcs_c45_read_pcs_speed()
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| /linux/include/uapi/linux/ |
| H A D | mdio.h | 36 #define MDIO_CTRL1 MII_BMCR macro
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| /linux/drivers/net/phy/realtek/ |
| H A D | realtek_main.c | 2345 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in rtl822x_c45_soft_reset()
2351 MDIO_CTRL1, val, in rtl822x_c45_soft_reset()
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