1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __DRM_MCDE_DISPLAY_REGS 3 #define __DRM_MCDE_DISPLAY_REGS 4 5 /* PP (pixel processor) interrupts */ 6 #define MCDE_IMSCPP 0x00000104 7 #define MCDE_RISPP 0x00000114 8 #define MCDE_MISPP 0x00000124 9 #define MCDE_SISPP 0x00000134 10 11 #define MCDE_PP_VCMPA BIT(0) 12 #define MCDE_PP_VCMPB BIT(1) 13 #define MCDE_PP_VSCC0 BIT(2) 14 #define MCDE_PP_VSCC1 BIT(3) 15 #define MCDE_PP_VCMPC0 BIT(4) 16 #define MCDE_PP_VCMPC1 BIT(5) 17 #define MCDE_PP_ROTFD_A BIT(6) 18 #define MCDE_PP_ROTFD_B BIT(7) 19 20 /* Overlay interrupts */ 21 #define MCDE_IMSCOVL 0x00000108 22 #define MCDE_RISOVL 0x00000118 23 #define MCDE_MISOVL 0x00000128 24 #define MCDE_SISOVL 0x00000138 25 26 /* Channel interrupts */ 27 #define MCDE_IMSCCHNL 0x0000010C 28 #define MCDE_RISCHNL 0x0000011C 29 #define MCDE_MISCHNL 0x0000012C 30 #define MCDE_SISCHNL 0x0000013C 31 32 /* X = 0..9 */ 33 #define MCDE_EXTSRCXA0 0x00000200 34 #define MCDE_EXTSRCXA0_GROUPOFFSET 0x20 35 #define MCDE_EXTSRCXA0_BASEADDRESS0_SHIFT 3 36 #define MCDE_EXTSRCXA0_BASEADDRESS0_MASK 0xFFFFFFF8 37 38 #define MCDE_EXTSRCXA1 0x00000204 39 #define MCDE_EXTSRCXA1_GROUPOFFSET 0x20 40 #define MCDE_EXTSRCXA1_BASEADDRESS1_SHIFT 3 41 #define MCDE_EXTSRCXA1_BASEADDRESS1_MASK 0xFFFFFFF8 42 43 /* External sources 0..9 */ 44 #define MCDE_EXTSRC0CONF 0x0000020C 45 #define MCDE_EXTSRC1CONF 0x0000022C 46 #define MCDE_EXTSRC2CONF 0x0000024C 47 #define MCDE_EXTSRC3CONF 0x0000026C 48 #define MCDE_EXTSRC4CONF 0x0000028C 49 #define MCDE_EXTSRC5CONF 0x000002AC 50 #define MCDE_EXTSRC6CONF 0x000002CC 51 #define MCDE_EXTSRC7CONF 0x000002EC 52 #define MCDE_EXTSRC8CONF 0x0000030C 53 #define MCDE_EXTSRC9CONF 0x0000032C 54 #define MCDE_EXTSRCXCONF_GROUPOFFSET 0x20 55 #define MCDE_EXTSRCXCONF_BUF_ID_SHIFT 0 56 #define MCDE_EXTSRCXCONF_BUF_ID_MASK 0x00000003 57 #define MCDE_EXTSRCXCONF_BUF_NB_SHIFT 2 58 #define MCDE_EXTSRCXCONF_BUF_NB_MASK 0x0000000C 59 #define MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT 4 60 #define MCDE_EXTSRCXCONF_PRI_OVLID_MASK 0x000000F0 61 #define MCDE_EXTSRCXCONF_BPP_SHIFT 8 62 #define MCDE_EXTSRCXCONF_BPP_MASK 0x00000F00 63 #define MCDE_EXTSRCXCONF_BPP_1BPP_PAL 0 64 #define MCDE_EXTSRCXCONF_BPP_2BPP_PAL 1 65 #define MCDE_EXTSRCXCONF_BPP_4BPP_PAL 2 66 #define MCDE_EXTSRCXCONF_BPP_8BPP_PAL 3 67 #define MCDE_EXTSRCXCONF_BPP_RGB444 4 68 #define MCDE_EXTSRCXCONF_BPP_ARGB4444 5 69 #define MCDE_EXTSRCXCONF_BPP_IRGB1555 6 70 #define MCDE_EXTSRCXCONF_BPP_RGB565 7 71 #define MCDE_EXTSRCXCONF_BPP_RGB888 8 72 #define MCDE_EXTSRCXCONF_BPP_XRGB8888 9 73 #define MCDE_EXTSRCXCONF_BPP_ARGB8888 10 74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11 75 #define MCDE_EXTSRCXCONF_BGR BIT(12) 76 #define MCDE_EXTSRCXCONF_BEBO BIT(13) 77 #define MCDE_EXTSRCXCONF_BEPO BIT(14) 78 #define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_SHIFT 16 79 #define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_MASK 0x0FFF0000 80 81 /* External sources 0..9 */ 82 #define MCDE_EXTSRC0CR 0x00000210 83 #define MCDE_EXTSRC1CR 0x00000230 84 #define MCDE_EXTSRC2CR 0x00000250 85 #define MCDE_EXTSRC3CR 0x00000270 86 #define MCDE_EXTSRC4CR 0x00000290 87 #define MCDE_EXTSRC5CR 0x000002B0 88 #define MCDE_EXTSRC6CR 0x000002D0 89 #define MCDE_EXTSRC7CR 0x000002F0 90 #define MCDE_EXTSRC8CR 0x00000310 91 #define MCDE_EXTSRC9CR 0x00000330 92 #define MCDE_EXTSRCXCR_SEL_MOD_SHIFT 0 93 #define MCDE_EXTSRCXCR_SEL_MOD_MASK 0x00000003 94 #define MCDE_EXTSRCXCR_SEL_MOD_EXTERNAL_SEL 0 95 #define MCDE_EXTSRCXCR_SEL_MOD_AUTO_TOGGLE 1 96 #define MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL 2 97 #define MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY BIT(2) /* 0 = all */ 98 #define MCDE_EXTSRCXCR_FS_DIV_DISABLE BIT(3) 99 #define MCDE_EXTSRCXCR_FORCE_FS_DIV BIT(4) 100 101 /* Only external source 6 has a second address register */ 102 #define MCDE_EXTSRC6A2 0x000002C8 103 104 /* 6 overlays */ 105 #define MCDE_OVL0CR 0x00000400 106 #define MCDE_OVL1CR 0x00000420 107 #define MCDE_OVL2CR 0x00000440 108 #define MCDE_OVL3CR 0x00000460 109 #define MCDE_OVL4CR 0x00000480 110 #define MCDE_OVL5CR 0x000004A0 111 #define MCDE_OVLXCR_OVLEN BIT(0) 112 #define MCDE_OVLXCR_COLCCTRL_DISABLED 0 113 #define MCDE_OVLXCR_COLCCTRL_ENABLED_NO_SAT (1 << 1) 114 #define MCDE_OVLXCR_COLCCTRL_ENABLED_SAT (2 << 1) 115 #define MCDE_OVLXCR_CKEYGEN BIT(3) 116 #define MCDE_OVLXCR_ALPHAPMEN BIT(4) 117 #define MCDE_OVLXCR_OVLF BIT(5) 118 #define MCDE_OVLXCR_OVLR BIT(6) 119 #define MCDE_OVLXCR_OVLB BIT(7) 120 #define MCDE_OVLXCR_FETCH_ROPC_SHIFT 8 121 #define MCDE_OVLXCR_FETCH_ROPC_MASK 0x0000FF00 122 #define MCDE_OVLXCR_STBPRIO_SHIFT 16 123 #define MCDE_OVLXCR_STBPRIO_MASK 0x000F0000 124 #define MCDE_OVLXCR_BURSTSIZE_SHIFT 20 125 #define MCDE_OVLXCR_BURSTSIZE_MASK 0x00F00000 126 #define MCDE_OVLXCR_BURSTSIZE_1W 0 127 #define MCDE_OVLXCR_BURSTSIZE_2W 1 128 #define MCDE_OVLXCR_BURSTSIZE_4W 2 129 #define MCDE_OVLXCR_BURSTSIZE_8W 3 130 #define MCDE_OVLXCR_BURSTSIZE_16W 4 131 #define MCDE_OVLXCR_BURSTSIZE_HW_1W 8 132 #define MCDE_OVLXCR_BURSTSIZE_HW_2W 9 133 #define MCDE_OVLXCR_BURSTSIZE_HW_4W 10 134 #define MCDE_OVLXCR_BURSTSIZE_HW_8W 11 135 #define MCDE_OVLXCR_BURSTSIZE_HW_16W 12 136 #define MCDE_OVLXCR_MAXOUTSTANDING_SHIFT 24 137 #define MCDE_OVLXCR_MAXOUTSTANDING_MASK 0x0F000000 138 #define MCDE_OVLXCR_MAXOUTSTANDING_1_REQ 0 139 #define MCDE_OVLXCR_MAXOUTSTANDING_2_REQ 1 140 #define MCDE_OVLXCR_MAXOUTSTANDING_4_REQ 2 141 #define MCDE_OVLXCR_MAXOUTSTANDING_8_REQ 3 142 #define MCDE_OVLXCR_MAXOUTSTANDING_16_REQ 4 143 #define MCDE_OVLXCR_ROTBURSTSIZE_SHIFT 28 144 #define MCDE_OVLXCR_ROTBURSTSIZE_MASK 0xF0000000 145 #define MCDE_OVLXCR_ROTBURSTSIZE_1W 0 146 #define MCDE_OVLXCR_ROTBURSTSIZE_2W 1 147 #define MCDE_OVLXCR_ROTBURSTSIZE_4W 2 148 #define MCDE_OVLXCR_ROTBURSTSIZE_8W 3 149 #define MCDE_OVLXCR_ROTBURSTSIZE_16W 4 150 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_1W 8 151 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_2W 9 152 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_4W 10 153 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11 154 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_16W 12 155 156 #define MCDE_OVL0CONF 0x00000404 157 #define MCDE_OVL1CONF 0x00000424 158 #define MCDE_OVL2CONF 0x00000444 159 #define MCDE_OVL3CONF 0x00000464 160 #define MCDE_OVL4CONF 0x00000484 161 #define MCDE_OVL5CONF 0x000004A4 162 #define MCDE_OVLXCONF_PPL_SHIFT 0 163 #define MCDE_OVLXCONF_PPL_MASK 0x000007FF 164 #define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11 165 #define MCDE_OVLXCONF_EXTSRC_ID_MASK 0x00007800 166 #define MCDE_OVLXCONF_LPF_SHIFT 16 167 #define MCDE_OVLXCONF_LPF_MASK 0x07FF0000 168 169 #define MCDE_OVL0CONF2 0x00000408 170 #define MCDE_OVL1CONF2 0x00000428 171 #define MCDE_OVL2CONF2 0x00000448 172 #define MCDE_OVL3CONF2 0x00000468 173 #define MCDE_OVL4CONF2 0x00000488 174 #define MCDE_OVL5CONF2 0x000004A8 175 #define MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA 0 176 #define MCDE_OVLXCONF2_BP_CONSTANT_ALPHA BIT(0) 177 #define MCDE_OVLXCONF2_ALPHAVALUE_SHIFT 1 178 #define MCDE_OVLXCONF2_ALPHAVALUE_MASK 0x000001FE 179 #define MCDE_OVLXCONF2_OPQ BIT(9) 180 #define MCDE_OVLXCONF2_PIXOFF_SHIFT 10 181 #define MCDE_OVLXCONF2_PIXOFF_MASK 0x0000FC00 182 #define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 183 #define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 184 185 #define MCDE_OVL0LJINC 0x0000040C 186 #define MCDE_OVL1LJINC 0x0000042C 187 #define MCDE_OVL2LJINC 0x0000044C 188 #define MCDE_OVL3LJINC 0x0000046C 189 #define MCDE_OVL4LJINC 0x0000048C 190 #define MCDE_OVL5LJINC 0x000004AC 191 192 #define MCDE_OVL0CROP 0x00000410 193 #define MCDE_OVL1CROP 0x00000430 194 #define MCDE_OVL2CROP 0x00000450 195 #define MCDE_OVL3CROP 0x00000470 196 #define MCDE_OVL4CROP 0x00000490 197 #define MCDE_OVL5CROP 0x000004B0 198 #define MCDE_OVLXCROP_TMRGN_SHIFT 0 199 #define MCDE_OVLXCROP_TMRGN_MASK 0x003FFFFF 200 #define MCDE_OVLXCROP_LMRGN_SHIFT 22 201 #define MCDE_OVLXCROP_LMRGN_MASK 0xFFC00000 202 203 #define MCDE_OVL0COMP 0x00000414 204 #define MCDE_OVL1COMP 0x00000434 205 #define MCDE_OVL2COMP 0x00000454 206 #define MCDE_OVL3COMP 0x00000474 207 #define MCDE_OVL4COMP 0x00000494 208 #define MCDE_OVL5COMP 0x000004B4 209 #define MCDE_OVLXCOMP_XPOS_SHIFT 0 210 #define MCDE_OVLXCOMP_XPOS_MASK 0x000007FF 211 #define MCDE_OVLXCOMP_CH_ID_SHIFT 11 212 #define MCDE_OVLXCOMP_CH_ID_MASK 0x00007800 213 #define MCDE_OVLXCOMP_YPOS_SHIFT 16 214 #define MCDE_OVLXCOMP_YPOS_MASK 0x07FF0000 215 #define MCDE_OVLXCOMP_Z_SHIFT 27 216 #define MCDE_OVLXCOMP_Z_MASK 0x78000000 217 218 /* DPI/TV configuration registers, channel A and B */ 219 #define MCDE_TVCRA 0x00000838 220 #define MCDE_TVCRB 0x00000A38 221 #define MCDE_TVCR_MOD_TV BIT(0) /* 0 = LCD mode */ 222 #define MCDE_TVCR_INTEREN BIT(1) 223 #define MCDE_TVCR_IFIELD BIT(2) 224 #define MCDE_TVCR_TVMODE_SDTV_656P (0 << 3) 225 #define MCDE_TVCR_TVMODE_SDTV_656P_LE (3 << 3) 226 #define MCDE_TVCR_TVMODE_SDTV_656P_BE (4 << 3) 227 #define MCDE_TVCR_SDTVMODE_Y0CBY1CR (0 << 6) 228 #define MCDE_TVCR_SDTVMODE_CBY0CRY1 (1 << 6) 229 #define MCDE_TVCR_AVRGEN BIT(8) 230 #define MCDE_TVCR_CKINV BIT(9) 231 232 /* TV blanking control register 1, channel A and B */ 233 #define MCDE_TVBL1A 0x0000083C 234 #define MCDE_TVBL1B 0x00000A3C 235 #define MCDE_TVBL1_BEL1_SHIFT 0 /* VFP vertical front porch 11 bits */ 236 #define MCDE_TVBL1_BSL1_SHIFT 16 /* VSW vertical sync pulse width 11 bits */ 237 238 /* Pixel processing TV start line, channel A and B */ 239 #define MCDE_TVISLA 0x00000840 240 #define MCDE_TVISLB 0x00000A40 241 #define MCDE_TVISL_FSL1_SHIFT 0 /* Field 1 identification start line 11 bits */ 242 #define MCDE_TVISL_FSL2_SHIFT 16 /* Field 2 identification start line 11 bits */ 243 244 /* Pixel processing TV DVO offset */ 245 #define MCDE_TVDVOA 0x00000844 246 #define MCDE_TVDVOB 0x00000A44 247 #define MCDE_TVDVO_DVO1_SHIFT 0 /* VBP vertical back porch 0 = 0 */ 248 #define MCDE_TVDVO_DVO2_SHIFT 16 249 250 /* 251 * Pixel processing TV Timing 1 252 * HBP horizontal back porch 11 bits horizontal offset 253 * 0 = 1 pixel HBP, 255 = 256 pixels, so actual value - 1 254 */ 255 #define MCDE_TVTIM1A 0x0000084C 256 #define MCDE_TVTIM1B 0x00000A4C 257 258 /* Pixel processing TV LBALW */ 259 /* 0 = 1 clock cycle, 255 = 256 clock cycles */ 260 #define MCDE_TVLBALWA 0x00000850 261 #define MCDE_TVLBALWB 0x00000A50 262 #define MCDE_TVLBALW_LBW_SHIFT 0 /* HSW horizonal sync width, line blanking width 11 bits */ 263 #define MCDE_TVLBALW_ALW_SHIFT 16 /* HFP horizontal front porch, active line width 11 bits */ 264 265 /* TV blanking control register 1, channel A and B */ 266 #define MCDE_TVBL2A 0x00000854 267 #define MCDE_TVBL2B 0x00000A54 268 #define MCDE_TVBL2_BEL2_SHIFT 0 /* Field 2 blanking end line 11 bits */ 269 #define MCDE_TVBL2_BSL2_SHIFT 16 /* Field 2 blanking start line 11 bits */ 270 271 /* Pixel processing TV background */ 272 #define MCDE_TVBLUA 0x00000858 273 #define MCDE_TVBLUB 0x00000A58 274 #define MCDE_TVBLU_TVBLU_SHIFT 0 /* 8 bits luminance */ 275 #define MCDE_TVBLU_TVBCB_SHIFT 8 /* 8 bits Cb chrominance */ 276 #define MCDE_TVBLU_TVBCR_SHIFT 16 /* 8 bits Cr chrominance */ 277 278 /* Pixel processing LCD timing 1 */ 279 #define MCDE_LCDTIM1A 0x00000860 280 #define MCDE_LCDTIM1B 0x00000A60 281 /* inverted vertical sync pulse for HRTFT 0 = active low, 1 active high */ 282 #define MCDE_LCDTIM1B_IVP BIT(19) 283 /* inverted vertical sync, 0 = active high (the normal), 1 = active low */ 284 #define MCDE_LCDTIM1B_IVS BIT(20) 285 /* inverted horizontal sync, 0 = active high (the normal), 1 = active low */ 286 #define MCDE_LCDTIM1B_IHS BIT(21) 287 /* inverted panel clock 0 = rising edge data out, 1 = falling edge data out */ 288 #define MCDE_LCDTIM1B_IPC BIT(22) 289 /* invert output enable 0 = active high, 1 = active low */ 290 #define MCDE_LCDTIM1B_IOE BIT(23) 291 292 #define MCDE_CRC 0x00000C00 293 #define MCDE_CRC_C1EN BIT(2) 294 #define MCDE_CRC_C2EN BIT(3) 295 #define MCDE_CRC_SYCEN0 BIT(7) 296 #define MCDE_CRC_SYCEN1 BIT(8) 297 #define MCDE_CRC_SIZE1 BIT(9) 298 #define MCDE_CRC_SIZE2 BIT(10) 299 #define MCDE_CRC_YUVCONVC1EN BIT(15) 300 #define MCDE_CRC_CS1EN BIT(16) 301 #define MCDE_CRC_CS2EN BIT(17) 302 #define MCDE_CRC_CS1POL BIT(19) 303 #define MCDE_CRC_CS2POL BIT(20) 304 #define MCDE_CRC_CD1POL BIT(21) 305 #define MCDE_CRC_CD2POL BIT(22) 306 #define MCDE_CRC_WR1POL BIT(23) 307 #define MCDE_CRC_WR2POL BIT(24) 308 #define MCDE_CRC_RD1POL BIT(25) 309 #define MCDE_CRC_RD2POL BIT(26) 310 #define MCDE_CRC_SYNCCTRL_SHIFT 29 311 #define MCDE_CRC_SYNCCTRL_MASK 0x60000000 312 #define MCDE_CRC_SYNCCTRL_NO_SYNC 0 313 #define MCDE_CRC_SYNCCTRL_DBI0 1 314 #define MCDE_CRC_SYNCCTRL_DBI1 2 315 #define MCDE_CRC_SYNCCTRL_PING_PONG 3 316 #define MCDE_CRC_CLAMPC1EN BIT(31) 317 318 #define MCDE_VSCRC0 0x00000C5C 319 #define MCDE_VSCRC1 0x00000C60 320 #define MCDE_VSCRC_VSPMIN_MASK 0x00000FFF 321 #define MCDE_VSCRC_VSPMAX_SHIFT 12 322 #define MCDE_VSCRC_VSPMAX_MASK 0x00FFF000 323 #define MCDE_VSCRC_VSPDIV_SHIFT 24 324 #define MCDE_VSCRC_VSPDIV_MASK 0x07000000 325 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_1 0 326 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_2 1 327 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_4 2 328 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_8 3 329 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_16 4 330 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_32 5 331 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_64 6 332 #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_128 7 333 #define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */ 334 #define MCDE_VSCRC_VSSEL BIT(28) /* 0 VSYNC0, 1 VSYNC1 */ 335 #define MCDE_VSCRC_VSDBL BIT(29) 336 337 /* Channel config 0..3 */ 338 #define MCDE_CHNL0CONF 0x00000600 339 #define MCDE_CHNL1CONF 0x00000620 340 #define MCDE_CHNL2CONF 0x00000640 341 #define MCDE_CHNL3CONF 0x00000660 342 #define MCDE_CHNLXCONF_PPL_SHIFT 0 343 #define MCDE_CHNLXCONF_PPL_MASK 0x000007FF 344 #define MCDE_CHNLXCONF_LPF_SHIFT 16 345 #define MCDE_CHNLXCONF_LPF_MASK 0x07FF0000 346 #define MCDE_MAX_WIDTH 2048 347 348 /* Channel status 0..3 */ 349 #define MCDE_CHNL0STAT 0x00000604 350 #define MCDE_CHNL1STAT 0x00000624 351 #define MCDE_CHNL2STAT 0x00000644 352 #define MCDE_CHNL3STAT 0x00000664 353 #define MCDE_CHNLXSTAT_CHNLRD BIT(0) 354 #define MCDE_CHNLXSTAT_CHNLA BIT(1) 355 #define MCDE_CHNLXSTAT_CHNLBLBCKGND_EN BIT(16) 356 #define MCDE_CHNLXSTAT_PPLX2_V422 BIT(17) 357 #define MCDE_CHNLXSTAT_LPFX2_V422 BIT(18) 358 359 /* Sync settings for channel 0..3 */ 360 #define MCDE_CHNL0SYNCHMOD 0x00000608 361 #define MCDE_CHNL1SYNCHMOD 0x00000628 362 #define MCDE_CHNL2SYNCHMOD 0x00000648 363 #define MCDE_CHNL3SYNCHMOD 0x00000668 364 365 #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT 0 366 #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_MASK 0x00000003 367 #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 0 368 #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_NO_SYNCH 1 369 #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE 2 370 #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 371 #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C 372 #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 373 #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 1 374 #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE1 2 375 376 /* Software sync triggers for channel 0..3 */ 377 #define MCDE_CHNL0SYNCHSW 0x0000060C 378 #define MCDE_CHNL1SYNCHSW 0x0000062C 379 #define MCDE_CHNL2SYNCHSW 0x0000064C 380 #define MCDE_CHNL3SYNCHSW 0x0000066C 381 #define MCDE_CHNLXSYNCHSW_SW_TRIG BIT(0) 382 383 #define MCDE_CHNL0BCKGNDCOL 0x00000610 384 #define MCDE_CHNL1BCKGNDCOL 0x00000630 385 #define MCDE_CHNL2BCKGNDCOL 0x00000650 386 #define MCDE_CHNL3BCKGNDCOL 0x00000670 387 #define MCDE_CHNLXBCKGNDCOL_B_SHIFT 0 388 #define MCDE_CHNLXBCKGNDCOL_B_MASK 0x000000FF 389 #define MCDE_CHNLXBCKGNDCOL_G_SHIFT 8 390 #define MCDE_CHNLXBCKGNDCOL_G_MASK 0x0000FF00 391 #define MCDE_CHNLXBCKGNDCOL_R_SHIFT 16 392 #define MCDE_CHNLXBCKGNDCOL_R_MASK 0x00FF0000 393 394 #define MCDE_CHNL0MUXING 0x00000614 395 #define MCDE_CHNL1MUXING 0x00000634 396 #define MCDE_CHNL2MUXING 0x00000654 397 #define MCDE_CHNL3MUXING 0x00000674 398 #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_A 0 399 #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_B 1 400 #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C0 2 401 #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C1 3 402 403 /* Pixel processing control registers for channel A B, */ 404 #define MCDE_CRA0 0x00000800 405 #define MCDE_CRB0 0x00000A00 406 #define MCDE_CRX0_FLOEN BIT(0) 407 #define MCDE_CRX0_POWEREN BIT(1) 408 #define MCDE_CRX0_BLENDEN BIT(2) 409 #define MCDE_CRX0_AFLICKEN BIT(3) 410 #define MCDE_CRX0_PALEN BIT(4) 411 #define MCDE_CRX0_DITHEN BIT(5) 412 #define MCDE_CRX0_GAMEN BIT(6) 413 #define MCDE_CRX0_KEYCTRL_SHIFT 7 414 #define MCDE_CRX0_KEYCTRL_MASK 0x00000380 415 #define MCDE_CRX0_KEYCTRL_OFF 0 416 #define MCDE_CRX0_KEYCTRL_ALPHA_RGB 1 417 #define MCDE_CRX0_KEYCTRL_RGB 2 418 #define MCDE_CRX0_KEYCTRL_FALPHA_FRGB 4 419 #define MCDE_CRX0_KEYCTRL_FRGB 5 420 #define MCDE_CRX0_BLENDCTRL BIT(10) 421 #define MCDE_CRX0_FLICKMODE_SHIFT 11 422 #define MCDE_CRX0_FLICKMODE_MASK 0x00001800 423 #define MCDE_CRX0_FLICKMODE_FORCE_FILTER_0 0 424 #define MCDE_CRX0_FLICKMODE_ADAPTIVE 1 425 #define MCDE_CRX0_FLICKMODE_TEST_MODE 2 426 #define MCDE_CRX0_FLOCKFORMAT_RGB BIT(13) /* 0 = YCVCR */ 427 #define MCDE_CRX0_PALMODE_GAMMA BIT(14) /* 0 = palette */ 428 #define MCDE_CRX0_OLEDEN BIT(15) 429 #define MCDE_CRX0_ALPHABLEND_SHIFT 16 430 #define MCDE_CRX0_ALPHABLEND_MASK 0x00FF0000 431 #define MCDE_CRX0_ROTEN BIT(24) 432 433 #define MCDE_CRA1 0x00000804 434 #define MCDE_CRB1 0x00000A04 435 #define MCDE_CRX1_PCD_SHIFT 0 436 #define MCDE_CRX1_PCD_MASK 0x000003FF 437 #define MCDE_CRX1_PCD_BITS 10 438 #define MCDE_CRX1_CLKSEL_SHIFT 10 439 #define MCDE_CRX1_CLKSEL_MASK 0x00001C00 440 #define MCDE_CRX1_CLKSEL_CLKPLL72 0 441 #define MCDE_CRX1_CLKSEL_CLKPLL27 2 442 #define MCDE_CRX1_CLKSEL_TV1CLK 3 443 #define MCDE_CRX1_CLKSEL_TV2CLK 4 444 #define MCDE_CRX1_CLKSEL_MCDECLK 5 445 #define MCDE_CRX1_CDWIN_SHIFT 13 446 #define MCDE_CRX1_CDWIN_MASK 0x0001E000 447 #define MCDE_CRX1_CDWIN_8BPP_C1 0 448 #define MCDE_CRX1_CDWIN_12BPP_C1 1 449 #define MCDE_CRX1_CDWIN_12BPP_C2 2 450 #define MCDE_CRX1_CDWIN_16BPP_C1 3 451 #define MCDE_CRX1_CDWIN_16BPP_C2 4 452 #define MCDE_CRX1_CDWIN_16BPP_C3 5 453 #define MCDE_CRX1_CDWIN_18BPP_C1 6 454 #define MCDE_CRX1_CDWIN_18BPP_C2 7 455 #define MCDE_CRX1_CDWIN_24BPP 8 456 #define MCDE_CRX1_OUTBPP_SHIFT 25 457 #define MCDE_CRX1_OUTBPP_MASK 0x1E000000 458 #define MCDE_CRX1_OUTBPP_MONO1 0 459 #define MCDE_CRX1_OUTBPP_MONO2 1 460 #define MCDE_CRX1_OUTBPP_MONO4 2 461 #define MCDE_CRX1_OUTBPP_MONO8 3 462 #define MCDE_CRX1_OUTBPP_8BPP 4 463 #define MCDE_CRX1_OUTBPP_12BPP 5 464 #define MCDE_CRX1_OUTBPP_15BPP 6 465 #define MCDE_CRX1_OUTBPP_16BPP 7 466 #define MCDE_CRX1_OUTBPP_18BPP 8 467 #define MCDE_CRX1_OUTBPP_24BPP 9 468 #define MCDE_CRX1_BCD BIT(29) 469 #define MCDE_CRA1_CLKTYPE_TVXCLKSEL1 BIT(30) /* 0 = TVXCLKSEL1 */ 470 471 #define MCDE_COLKEYA 0x00000808 472 #define MCDE_COLKEYB 0x00000A08 473 474 #define MCDE_FCOLKEYA 0x0000080C 475 #define MCDE_FCOLKEYB 0x00000A0C 476 477 #define MCDE_RGBCONV1A 0x00000810 478 #define MCDE_RGBCONV1B 0x00000A10 479 480 #define MCDE_RGBCONV2A 0x00000814 481 #define MCDE_RGBCONV2B 0x00000A14 482 483 #define MCDE_RGBCONV3A 0x00000818 484 #define MCDE_RGBCONV3B 0x00000A18 485 486 #define MCDE_RGBCONV4A 0x0000081C 487 #define MCDE_RGBCONV4B 0x00000A1C 488 489 #define MCDE_RGBCONV5A 0x00000820 490 #define MCDE_RGBCONV5B 0x00000A20 491 492 #define MCDE_RGBCONV6A 0x00000824 493 #define MCDE_RGBCONV6B 0x00000A24 494 495 /* Rotation */ 496 #define MCDE_ROTACONF 0x0000087C 497 #define MCDE_ROTBCONF 0x00000A7C 498 499 /* Synchronization event configuration */ 500 #define MCDE_SYNCHCONFA 0x00000880 501 #define MCDE_SYNCHCONFB 0x00000A80 502 #define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0 503 #define MCDE_SYNCHCONF_HWREQVEVENT_VSYNC (0 << 0) 504 #define MCDE_SYNCHCONF_HWREQVEVENT_BACK_PORCH (1 << 0) 505 #define MCDE_SYNCHCONF_HWREQVEVENT_ACTIVE_VIDEO (2 << 0) 506 #define MCDE_SYNCHCONF_HWREQVEVENT_FRONT_PORCH (3 << 0) 507 #define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2 /* 14 bits */ 508 #define MCDE_SYNCHCONF_SWINTVEVENT_VSYNC (0 << 16) 509 #define MCDE_SYNCHCONF_SWINTVEVENT_BACK_PORCH (1 << 16) 510 #define MCDE_SYNCHCONF_SWINTVEVENT_ACTIVE_VIDEO (2 << 16) 511 #define MCDE_SYNCHCONF_SWINTVEVENT_FRONT_PORCH (3 << 16) 512 #define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18 /* 14 bits */ 513 514 /* Channel A+B control registers */ 515 #define MCDE_CTRLA 0x00000884 516 #define MCDE_CTRLB 0x00000A84 517 #define MCDE_CTRLX_FIFOWTRMRK_SHIFT 0 518 #define MCDE_CTRLX_FIFOWTRMRK_MASK 0x000003FF 519 #define MCDE_CTRLX_FIFOEMPTY BIT(12) 520 #define MCDE_CTRLX_FIFOFULL BIT(13) 521 #define MCDE_CTRLX_FORMID_SHIFT 16 522 #define MCDE_CTRLX_FORMID_MASK 0x00070000 523 #define MCDE_CTRLX_FORMID_DSI0VID 0 524 #define MCDE_CTRLX_FORMID_DSI0CMD 1 525 #define MCDE_CTRLX_FORMID_DSI1VID 2 526 #define MCDE_CTRLX_FORMID_DSI1CMD 3 527 #define MCDE_CTRLX_FORMID_DSI2VID 4 528 #define MCDE_CTRLX_FORMID_DSI2CMD 5 529 #define MCDE_CTRLX_FORMID_DPIA 0 530 #define MCDE_CTRLX_FORMID_DPIB 1 531 #define MCDE_CTRLX_FORMTYPE_SHIFT 20 532 #define MCDE_CTRLX_FORMTYPE_MASK 0x00700000 533 #define MCDE_CTRLX_FORMTYPE_DPITV 0 534 #define MCDE_CTRLX_FORMTYPE_DBI 1 535 #define MCDE_CTRLX_FORMTYPE_DSI 2 536 537 #define MCDE_DSIVID0CONF0 0x00000E00 538 #define MCDE_DSICMD0CONF0 0x00000E20 539 #define MCDE_DSIVID1CONF0 0x00000E40 540 #define MCDE_DSICMD1CONF0 0x00000E60 541 #define MCDE_DSIVID2CONF0 0x00000E80 542 #define MCDE_DSICMD2CONF0 0x00000EA0 543 #define MCDE_DSICONF0_BLANKING_SHIFT 0 544 #define MCDE_DSICONF0_BLANKING_MASK 0x000000FF 545 #define MCDE_DSICONF0_VID_MODE_CMD 0 546 #define MCDE_DSICONF0_VID_MODE_VID BIT(12) 547 #define MCDE_DSICONF0_CMD8 BIT(13) 548 #define MCDE_DSICONF0_BIT_SWAP BIT(16) 549 #define MCDE_DSICONF0_BYTE_SWAP BIT(17) 550 #define MCDE_DSICONF0_DCSVID_NOTGEN BIT(18) 551 #define MCDE_DSICONF0_PACKING_SHIFT 20 552 #define MCDE_DSICONF0_PACKING_MASK 0x00700000 553 #define MCDE_DSICONF0_PACKING_RGB565 0 554 #define MCDE_DSICONF0_PACKING_RGB666 1 555 #define MCDE_DSICONF0_PACKING_RGB888 2 556 #define MCDE_DSICONF0_PACKING_BGR888 3 557 #define MCDE_DSICONF0_PACKING_HDTV 4 558 559 #define MCDE_DSIVID0FRAME 0x00000E04 560 #define MCDE_DSICMD0FRAME 0x00000E24 561 #define MCDE_DSIVID1FRAME 0x00000E44 562 #define MCDE_DSICMD1FRAME 0x00000E64 563 #define MCDE_DSIVID2FRAME 0x00000E84 564 #define MCDE_DSICMD2FRAME 0x00000EA4 565 566 #define MCDE_DSIVID0PKT 0x00000E08 567 #define MCDE_DSICMD0PKT 0x00000E28 568 #define MCDE_DSIVID1PKT 0x00000E48 569 #define MCDE_DSICMD1PKT 0x00000E68 570 #define MCDE_DSIVID2PKT 0x00000E88 571 #define MCDE_DSICMD2PKT 0x00000EA8 572 573 #define MCDE_DSIVID0SYNC 0x00000E0C 574 #define MCDE_DSICMD0SYNC 0x00000E2C 575 #define MCDE_DSIVID1SYNC 0x00000E4C 576 #define MCDE_DSICMD1SYNC 0x00000E6C 577 #define MCDE_DSIVID2SYNC 0x00000E8C 578 #define MCDE_DSICMD2SYNC 0x00000EAC 579 580 #define MCDE_DSIVID0CMDW 0x00000E10 581 #define MCDE_DSICMD0CMDW 0x00000E30 582 #define MCDE_DSIVID1CMDW 0x00000E50 583 #define MCDE_DSICMD1CMDW 0x00000E70 584 #define MCDE_DSIVID2CMDW 0x00000E90 585 #define MCDE_DSICMD2CMDW 0x00000EB0 586 #define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT 0 587 #define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_MASK 0x0000FFFF 588 #define MCDE_DSIVIDXCMDW_CMDW_START_SHIFT 16 589 #define MCDE_DSIVIDXCMDW_CMDW_START_MASK 0xFFFF0000 590 591 #define MCDE_DSIVID0DELAY0 0x00000E14 592 #define MCDE_DSICMD0DELAY0 0x00000E34 593 #define MCDE_DSIVID1DELAY0 0x00000E54 594 #define MCDE_DSICMD1DELAY0 0x00000E74 595 #define MCDE_DSIVID2DELAY0 0x00000E94 596 #define MCDE_DSICMD2DELAY0 0x00000EB4 597 598 #define MCDE_DSIVID0DELAY1 0x00000E18 599 #define MCDE_DSICMD0DELAY1 0x00000E38 600 #define MCDE_DSIVID1DELAY1 0x00000E58 601 #define MCDE_DSICMD1DELAY1 0x00000E78 602 #define MCDE_DSIVID2DELAY1 0x00000E98 603 #define MCDE_DSICMD2DELAY1 0x00000EB8 604 605 #endif /* __DRM_MCDE_DISPLAY_REGS */ 606