1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/iopoll.h>
10 #include <linux/irq.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/phy/phy.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16 #include <linux/units.h>
17
18 #include <video/mipi_display.h>
19 #include <video/videomode.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_bridge_connector.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_print.h>
28 #include <drm/drm_probe_helper.h>
29 #include <drm/drm_simple_kms_helper.h>
30
31 #include "mtk_ddp_comp.h"
32 #include "mtk_disp_drv.h"
33 #include "mtk_drm_drv.h"
34
35 #define DSI_START 0x00
36
37 #define DSI_INTEN 0x08
38
39 #define DSI_INTSTA 0x0c
40 #define LPRX_RD_RDY_INT_FLAG BIT(0)
41 #define CMD_DONE_INT_FLAG BIT(1)
42 #define TE_RDY_INT_FLAG BIT(2)
43 #define VM_DONE_INT_FLAG BIT(3)
44 #define EXT_TE_RDY_INT_FLAG BIT(4)
45 #define DSI_BUSY BIT(31)
46
47 #define DSI_CON_CTRL 0x10
48 #define DSI_RESET BIT(0)
49 #define DSI_EN BIT(1)
50 #define DPHY_RESET BIT(2)
51
52 #define DSI_MODE_CTRL 0x14
53 #define MODE (3)
54 #define CMD_MODE 0
55 #define SYNC_PULSE_MODE 1
56 #define SYNC_EVENT_MODE 2
57 #define BURST_MODE 3
58 #define FRM_MODE BIT(16)
59 #define MIX_MODE BIT(17)
60
61 #define DSI_TXRX_CTRL 0x18
62 #define VC_NUM BIT(1)
63 #define LANE_NUM GENMASK(5, 2)
64 #define DIS_EOT BIT(6)
65 #define NULL_EN BIT(7)
66 #define TE_FREERUN BIT(8)
67 #define EXT_TE_EN BIT(9)
68 #define EXT_TE_EDGE BIT(10)
69 #define MAX_RTN_SIZE GENMASK(15, 12)
70 #define HSTX_CKLP_EN BIT(16)
71
72 #define DSI_PSCTRL 0x1c
73 #define DSI_PS_WC GENMASK(13, 0)
74 #define DSI_PS_SEL GENMASK(17, 16)
75 #define PACKED_PS_16BIT_RGB565 0
76 #define PACKED_PS_18BIT_RGB666 1
77 #define LOOSELY_PS_24BIT_RGB666 2
78 #define PACKED_PS_24BIT_RGB888 3
79
80 #define DSI_VSA_NL 0x20
81 #define DSI_VBP_NL 0x24
82 #define DSI_VFP_NL 0x28
83 #define DSI_VACT_NL 0x2C
84 #define VACT_NL GENMASK(14, 0)
85 #define DSI_SIZE_CON 0x38
86 #define DSI_HEIGHT GENMASK(30, 16)
87 #define DSI_WIDTH GENMASK(14, 0)
88 #define DSI_HSA_WC 0x50
89 #define DSI_HBP_WC 0x54
90 #define DSI_HFP_WC 0x58
91 #define HFP_HS_VB_PS_WC GENMASK(30, 16)
92 #define HFP_HS_EN BIT(31)
93
94 #define DSI_CMDQ_SIZE 0x60
95 #define CMDQ_SIZE 0x3f
96 #define CMDQ_SIZE_SEL BIT(15)
97
98 #define DSI_HSTX_CKL_WC 0x64
99 #define HSTX_CKL_WC GENMASK(15, 2)
100
101 #define DSI_RX_DATA0 0x74
102 #define DSI_RX_DATA1 0x78
103 #define DSI_RX_DATA2 0x7c
104 #define DSI_RX_DATA3 0x80
105
106 #define DSI_RACK 0x84
107 #define RACK BIT(0)
108
109 #define DSI_PHY_LCCON 0x104
110 #define LC_HS_TX_EN BIT(0)
111 #define LC_ULPM_EN BIT(1)
112 #define LC_WAKEUP_EN BIT(2)
113
114 #define DSI_PHY_LD0CON 0x108
115 #define LD0_HS_TX_EN BIT(0)
116 #define LD0_ULPM_EN BIT(1)
117 #define LD0_WAKEUP_EN BIT(2)
118
119 #define DSI_PHY_TIMECON0 0x110
120 #define LPX GENMASK(7, 0)
121 #define HS_PREP GENMASK(15, 8)
122 #define HS_ZERO GENMASK(23, 16)
123 #define HS_TRAIL GENMASK(31, 24)
124
125 #define DSI_PHY_TIMECON1 0x114
126 #define TA_GO GENMASK(7, 0)
127 #define TA_SURE GENMASK(15, 8)
128 #define TA_GET GENMASK(23, 16)
129 #define DA_HS_EXIT GENMASK(31, 24)
130
131 #define DSI_PHY_TIMECON2 0x118
132 #define CONT_DET GENMASK(7, 0)
133 #define DA_HS_SYNC GENMASK(15, 8)
134 #define CLK_ZERO GENMASK(23, 16)
135 #define CLK_TRAIL GENMASK(31, 24)
136
137 #define DSI_PHY_TIMECON3 0x11c
138 #define CLK_HS_PREP GENMASK(7, 0)
139 #define CLK_HS_POST GENMASK(15, 8)
140 #define CLK_HS_EXIT GENMASK(23, 16)
141
142 #define DSI_VM_CMD_CON 0x130
143 #define VM_CMD_EN BIT(0)
144 #define TS_VFP_EN BIT(5)
145
146 #define DSI_SHADOW_DEBUG 0x190U
147 #define FORCE_COMMIT BIT(0)
148 #define BYPASS_SHADOW BIT(1)
149
150 /* CMDQ related bits */
151 #define CONFIG GENMASK(7, 0)
152 #define SHORT_PACKET 0
153 #define LONG_PACKET 2
154 #define BTA BIT(2)
155 #define DATA_ID GENMASK(15, 8)
156 #define DATA_0 GENMASK(23, 16)
157 #define DATA_1 GENMASK(31, 24)
158
159 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
160
161 #define MTK_DSI_HOST_IS_READ(type) \
162 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
163 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
164 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
165 (type == MIPI_DSI_DCS_READ))
166
167 struct mtk_phy_timing {
168 u32 lpx;
169 u32 da_hs_prepare;
170 u32 da_hs_zero;
171 u32 da_hs_trail;
172
173 u32 ta_go;
174 u32 ta_sure;
175 u32 ta_get;
176 u32 da_hs_exit;
177
178 u32 clk_hs_zero;
179 u32 clk_hs_trail;
180
181 u32 clk_hs_prepare;
182 u32 clk_hs_post;
183 u32 clk_hs_exit;
184 };
185
186 struct phy;
187
188 struct mtk_dsi_driver_data {
189 const u32 reg_cmdq_off;
190 bool has_shadow_ctl;
191 bool has_size_ctl;
192 bool cmdq_long_packet_ctl;
193 bool support_per_frame_lp;
194 };
195
196 struct mtk_dsi {
197 struct device *dev;
198 struct mipi_dsi_host host;
199 struct drm_encoder encoder;
200 struct drm_bridge bridge;
201 struct drm_bridge *next_bridge;
202 struct drm_connector *connector;
203 struct phy *phy;
204
205 void __iomem *regs;
206
207 struct clk *engine_clk;
208 struct clk *digital_clk;
209 struct clk *hs_clk;
210
211 u32 data_rate;
212
213 unsigned long mode_flags;
214 enum mipi_dsi_pixel_format format;
215 unsigned int lanes;
216 struct videomode vm;
217 struct mtk_phy_timing phy_timing;
218 int refcount;
219 bool enabled;
220 bool lanes_ready;
221 u32 irq_data;
222 wait_queue_head_t irq_wait_queue;
223 const struct mtk_dsi_driver_data *driver_data;
224 };
225
bridge_to_dsi(struct drm_bridge * b)226 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
227 {
228 return container_of(b, struct mtk_dsi, bridge);
229 }
230
host_to_dsi(struct mipi_dsi_host * h)231 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
232 {
233 return container_of(h, struct mtk_dsi, host);
234 }
235
mtk_dsi_mask(struct mtk_dsi * dsi,u32 offset,u32 mask,u32 data)236 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
237 {
238 u32 temp = readl(dsi->regs + offset);
239
240 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
241 }
242
mtk_dsi_phy_timconfig(struct mtk_dsi * dsi)243 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
244 {
245 u32 timcon0, timcon1, timcon2, timcon3;
246 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
247 struct mtk_phy_timing *timing = &dsi->phy_timing;
248
249 timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;
250 timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1;
251 timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 -
252 timing->da_hs_prepare;
253 timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
254
255 timing->ta_go = 4 * timing->lpx;
256 timing->ta_sure = 3 * timing->lpx / 2;
257 timing->ta_get = 5 * timing->lpx;
258 timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
259
260 timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1;
261 timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1;
262 timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
263 timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 -
264 timing->clk_hs_prepare;
265 timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
266
267 timcon0 = FIELD_PREP(LPX, timing->lpx) |
268 FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
269 FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
270 FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
271
272 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
273 FIELD_PREP(TA_SURE, timing->ta_sure) |
274 FIELD_PREP(TA_GET, timing->ta_get) |
275 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
276
277 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
278 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
279 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
280
281 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
282 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
283 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
284
285 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
286 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
287 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
288 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
289 }
290
mtk_dsi_enable(struct mtk_dsi * dsi)291 static void mtk_dsi_enable(struct mtk_dsi *dsi)
292 {
293 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
294 }
295
mtk_dsi_disable(struct mtk_dsi * dsi)296 static void mtk_dsi_disable(struct mtk_dsi *dsi)
297 {
298 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
299 }
300
mtk_dsi_reset_engine(struct mtk_dsi * dsi)301 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
302 {
303 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
304 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
305 }
306
mtk_dsi_reset_dphy(struct mtk_dsi * dsi)307 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
308 {
309 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
310 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
311 }
312
mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi * dsi)313 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
314 {
315 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
316 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
317 }
318
mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi * dsi)319 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
320 {
321 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
322 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
324 }
325
mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi * dsi)326 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
327 {
328 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
329 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
330 }
331
mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi * dsi)332 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
333 {
334 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
335 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
336 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
337 }
338
mtk_dsi_clk_hs_state(struct mtk_dsi * dsi)339 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
340 {
341 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
342 }
343
mtk_dsi_clk_hs_mode(struct mtk_dsi * dsi,bool enter)344 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
345 {
346 if (enter && !mtk_dsi_clk_hs_state(dsi))
347 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
348 else if (!enter && mtk_dsi_clk_hs_state(dsi))
349 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
350 }
351
mtk_dsi_set_mode(struct mtk_dsi * dsi)352 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
353 {
354 u32 vid_mode = CMD_MODE;
355
356 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
357 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
358 vid_mode = BURST_MODE;
359 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
360 vid_mode = SYNC_PULSE_MODE;
361 else
362 vid_mode = SYNC_EVENT_MODE;
363 }
364
365 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
366 }
367
mtk_dsi_set_vm_cmd(struct mtk_dsi * dsi)368 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
369 {
370 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
371 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
372 }
373
mtk_dsi_rxtx_control(struct mtk_dsi * dsi)374 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
375 {
376 u32 regval, tmp_reg = 0;
377 u8 i;
378
379 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
380 for (i = 0; i < dsi->lanes; i++)
381 tmp_reg |= BIT(i);
382
383 regval = FIELD_PREP(LANE_NUM, tmp_reg);
384
385 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
386 regval |= HSTX_CKLP_EN;
387
388 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
389 regval |= DIS_EOT;
390
391 writel(regval, dsi->regs + DSI_TXRX_CTRL);
392 }
393
mtk_dsi_ps_control(struct mtk_dsi * dsi,bool config_vact)394 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
395 {
396 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
397
398 if (dsi->format == MIPI_DSI_FMT_RGB565)
399 dsi_buf_bpp = 2;
400 else
401 dsi_buf_bpp = 3;
402
403 /* Word count */
404 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
405 ps_val = ps_wc;
406
407 /* Pixel Stream type */
408 switch (dsi->format) {
409 default:
410 fallthrough;
411 case MIPI_DSI_FMT_RGB888:
412 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
413 break;
414 case MIPI_DSI_FMT_RGB666:
415 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
416 break;
417 case MIPI_DSI_FMT_RGB666_PACKED:
418 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
419 break;
420 case MIPI_DSI_FMT_RGB565:
421 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
422 break;
423 }
424
425 if (config_vact) {
426 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
427 writel(vact_nl, dsi->regs + DSI_VACT_NL);
428 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
429 }
430 writel(ps_val, dsi->regs + DSI_PSCTRL);
431 }
432
mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi * dsi)433 static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi)
434 {
435 u32 horizontal_sync_active_byte;
436 u32 horizontal_backporch_byte;
437 u32 horizontal_frontporch_byte;
438 u32 hfp_byte_adjust, v_active_adjust;
439 u32 cklp_wc_min_adjust, cklp_wc_max_adjust;
440 u32 dsi_tmp_buf_bpp;
441 unsigned int da_hs_trail;
442 unsigned int ps_wc, hs_vb_ps_wc;
443 u32 v_active_roundup, hstx_cklp_wc;
444 u32 hstx_cklp_wc_max, hstx_cklp_wc_min;
445 struct videomode *vm = &dsi->vm;
446
447 if (dsi->format == MIPI_DSI_FMT_RGB565)
448 dsi_tmp_buf_bpp = 2;
449 else
450 dsi_tmp_buf_bpp = 3;
451
452 da_hs_trail = dsi->phy_timing.da_hs_trail;
453 ps_wc = vm->hactive * dsi_tmp_buf_bpp;
454
455 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
456 horizontal_sync_active_byte =
457 vm->hsync_len * dsi_tmp_buf_bpp - 10;
458 horizontal_backporch_byte =
459 vm->hback_porch * dsi_tmp_buf_bpp - 10;
460 hfp_byte_adjust = 12;
461 v_active_adjust = 32 + horizontal_sync_active_byte;
462 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte;
463 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte;
464 } else {
465 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4;
466 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
467 dsi_tmp_buf_bpp - 10;
468 cklp_wc_min_adjust = 4;
469 cklp_wc_max_adjust = 12 + 4 + 4;
470 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
471 hfp_byte_adjust = 18;
472 v_active_adjust = 28;
473 } else {
474 hfp_byte_adjust = 12;
475 v_active_adjust = 22;
476 }
477 }
478 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust;
479 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc +
480 horizontal_frontporch_byte) % dsi->lanes;
481 if (v_active_roundup)
482 horizontal_backporch_byte += dsi->lanes - v_active_roundup;
483 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1)
484 * dsi->lanes / 6 - 1;
485 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte +
486 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1;
487
488 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2);
489 writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC);
490
491 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit +
492 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes;
493 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) |
494 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc);
495
496 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
497 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
498 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
499 }
500
mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi * dsi)501 static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi)
502 {
503 u32 horizontal_sync_active_byte;
504 u32 horizontal_backporch_byte;
505 u32 horizontal_frontporch_byte;
506 u32 horizontal_front_back_byte;
507 u32 data_phy_cycles_byte;
508 u32 dsi_tmp_buf_bpp, data_phy_cycles;
509 u32 delta;
510 struct mtk_phy_timing *timing = &dsi->phy_timing;
511 struct videomode *vm = &dsi->vm;
512
513 if (dsi->format == MIPI_DSI_FMT_RGB565)
514 dsi_tmp_buf_bpp = 2;
515 else
516 dsi_tmp_buf_bpp = 3;
517
518 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
519
520 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
521 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
522 else
523 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
524 dsi_tmp_buf_bpp - 10;
525
526 data_phy_cycles = timing->lpx + timing->da_hs_prepare +
527 timing->da_hs_zero + timing->da_hs_exit + 3;
528
529 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
530 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
531
532 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
533 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
534 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
535
536 if (horizontal_front_back_byte > data_phy_cycles_byte) {
537 horizontal_frontporch_byte -= data_phy_cycles_byte *
538 horizontal_frontporch_byte /
539 horizontal_front_back_byte;
540
541 horizontal_backporch_byte -= data_phy_cycles_byte *
542 horizontal_backporch_byte /
543 horizontal_front_back_byte;
544 } else {
545 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
546 }
547
548 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
549 (dsi->lanes == 4)) {
550 horizontal_sync_active_byte =
551 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
552 horizontal_frontporch_byte =
553 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
554 horizontal_backporch_byte =
555 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
556 horizontal_backporch_byte -=
557 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
558 }
559
560 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
561 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
562 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
563 }
564
mtk_dsi_config_vdo_timing(struct mtk_dsi * dsi)565 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
566 {
567 struct videomode *vm = &dsi->vm;
568
569 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
570 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
571 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
572 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
573
574 if (dsi->driver_data->has_size_ctl)
575 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
576 FIELD_PREP(DSI_WIDTH, vm->hactive),
577 dsi->regs + DSI_SIZE_CON);
578
579 if (dsi->driver_data->support_per_frame_lp)
580 mtk_dsi_config_vdo_timing_per_frame_lp(dsi);
581 else
582 mtk_dsi_config_vdo_timing_per_line_lp(dsi);
583
584 mtk_dsi_ps_control(dsi, false);
585 }
586
mtk_dsi_start(struct mtk_dsi * dsi)587 static void mtk_dsi_start(struct mtk_dsi *dsi)
588 {
589 writel(0, dsi->regs + DSI_START);
590 writel(1, dsi->regs + DSI_START);
591 }
592
mtk_dsi_stop(struct mtk_dsi * dsi)593 static void mtk_dsi_stop(struct mtk_dsi *dsi)
594 {
595 writel(0, dsi->regs + DSI_START);
596 }
597
mtk_dsi_set_cmd_mode(struct mtk_dsi * dsi)598 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
599 {
600 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
601 }
602
mtk_dsi_set_interrupt_enable(struct mtk_dsi * dsi)603 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
604 {
605 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
606
607 writel(inten, dsi->regs + DSI_INTEN);
608 }
609
mtk_dsi_irq_data_set(struct mtk_dsi * dsi,u32 irq_bit)610 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
611 {
612 dsi->irq_data |= irq_bit;
613 }
614
mtk_dsi_irq_data_clear(struct mtk_dsi * dsi,u32 irq_bit)615 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
616 {
617 dsi->irq_data &= ~irq_bit;
618 }
619
mtk_dsi_wait_for_irq_done(struct mtk_dsi * dsi,u32 irq_flag,unsigned int timeout)620 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
621 unsigned int timeout)
622 {
623 s32 ret = 0;
624 unsigned long jiffies = msecs_to_jiffies(timeout);
625
626 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
627 dsi->irq_data & irq_flag,
628 jiffies);
629 if (ret == 0) {
630 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
631
632 mtk_dsi_enable(dsi);
633 mtk_dsi_reset_engine(dsi);
634 }
635
636 return ret;
637 }
638
mtk_dsi_irq(int irq,void * dev_id)639 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
640 {
641 struct mtk_dsi *dsi = dev_id;
642 u32 status, tmp;
643 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
644
645 status = readl(dsi->regs + DSI_INTSTA) & flag;
646
647 if (status) {
648 do {
649 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
650 tmp = readl(dsi->regs + DSI_INTSTA);
651 } while (tmp & DSI_BUSY);
652
653 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
654 mtk_dsi_irq_data_set(dsi, status);
655 wake_up_interruptible(&dsi->irq_wait_queue);
656 }
657
658 return IRQ_HANDLED;
659 }
660
mtk_dsi_switch_to_cmd_mode(struct mtk_dsi * dsi,u8 irq_flag,u32 t)661 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
662 {
663 mtk_dsi_irq_data_clear(dsi, irq_flag);
664 mtk_dsi_set_cmd_mode(dsi);
665
666 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
667 DRM_ERROR("failed to switch cmd mode\n");
668 return -ETIME;
669 } else {
670 return 0;
671 }
672 }
673
mtk_dsi_poweron(struct mtk_dsi * dsi)674 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
675 {
676 struct device *dev = dsi->host.dev;
677 int ret;
678 u32 bit_per_pixel;
679
680 if (++dsi->refcount != 1)
681 return 0;
682
683 ret = mipi_dsi_pixel_format_to_bpp(dsi->format);
684 if (ret < 0) {
685 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
686 return ret;
687 }
688 bit_per_pixel = ret;
689
690 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
691 dsi->lanes);
692
693 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
694 if (ret < 0) {
695 dev_err(dev, "Failed to set data rate: %d\n", ret);
696 goto err_refcount;
697 }
698
699 phy_power_on(dsi->phy);
700
701 ret = clk_prepare_enable(dsi->engine_clk);
702 if (ret < 0) {
703 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
704 goto err_phy_power_off;
705 }
706
707 ret = clk_prepare_enable(dsi->digital_clk);
708 if (ret < 0) {
709 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
710 goto err_disable_engine_clk;
711 }
712
713 mtk_dsi_enable(dsi);
714
715 if (dsi->driver_data->has_shadow_ctl)
716 writel(FORCE_COMMIT | BYPASS_SHADOW,
717 dsi->regs + DSI_SHADOW_DEBUG);
718
719 mtk_dsi_reset_engine(dsi);
720 mtk_dsi_phy_timconfig(dsi);
721
722 mtk_dsi_ps_control(dsi, true);
723 mtk_dsi_set_vm_cmd(dsi);
724 mtk_dsi_config_vdo_timing(dsi);
725 mtk_dsi_set_interrupt_enable(dsi);
726
727 return 0;
728 err_disable_engine_clk:
729 clk_disable_unprepare(dsi->engine_clk);
730 err_phy_power_off:
731 phy_power_off(dsi->phy);
732 err_refcount:
733 dsi->refcount--;
734 return ret;
735 }
736
mtk_dsi_poweroff(struct mtk_dsi * dsi)737 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
738 {
739 if (WARN_ON(dsi->refcount == 0))
740 return;
741
742 if (--dsi->refcount != 0)
743 return;
744
745 /*
746 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
747 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(),
748 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
749 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
750 * after dsi is fully set.
751 */
752 mtk_dsi_stop(dsi);
753
754 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
755 mtk_dsi_reset_engine(dsi);
756 mtk_dsi_lane0_ulp_mode_enter(dsi);
757 mtk_dsi_clk_ulp_mode_enter(dsi);
758 /* set the lane number as 0 to pull down mipi */
759 writel(0, dsi->regs + DSI_TXRX_CTRL);
760
761 mtk_dsi_disable(dsi);
762
763 clk_disable_unprepare(dsi->engine_clk);
764 clk_disable_unprepare(dsi->digital_clk);
765
766 phy_power_off(dsi->phy);
767
768 dsi->lanes_ready = false;
769 }
770
mtk_dsi_lane_ready(struct mtk_dsi * dsi)771 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
772 {
773 if (!dsi->lanes_ready) {
774 dsi->lanes_ready = true;
775 mtk_dsi_rxtx_control(dsi);
776 usleep_range(30, 100);
777 mtk_dsi_reset_dphy(dsi);
778 mtk_dsi_clk_ulp_mode_leave(dsi);
779 mtk_dsi_lane0_ulp_mode_leave(dsi);
780 mtk_dsi_clk_hs_mode(dsi, 0);
781 usleep_range(1000, 3000);
782 /* The reaction time after pulling up the mipi signal for dsi_rx */
783 }
784 }
785
mtk_output_dsi_enable(struct mtk_dsi * dsi)786 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
787 {
788 if (dsi->enabled)
789 return;
790
791 mtk_dsi_lane_ready(dsi);
792 mtk_dsi_set_mode(dsi);
793 mtk_dsi_clk_hs_mode(dsi, 1);
794
795 mtk_dsi_start(dsi);
796
797 dsi->enabled = true;
798 }
799
mtk_output_dsi_disable(struct mtk_dsi * dsi)800 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
801 {
802 if (!dsi->enabled)
803 return;
804
805 dsi->enabled = false;
806 }
807
mtk_dsi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)808 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
809 enum drm_bridge_attach_flags flags)
810 {
811 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
812
813 /* Attach the panel or bridge to the dsi bridge */
814 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
815 &dsi->bridge, flags);
816 }
817
mtk_dsi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted)818 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
819 const struct drm_display_mode *mode,
820 const struct drm_display_mode *adjusted)
821 {
822 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
823
824 drm_display_mode_to_videomode(adjusted, &dsi->vm);
825 }
826
mtk_dsi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)827 static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
828 struct drm_bridge_state *old_bridge_state)
829 {
830 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
831
832 mtk_output_dsi_disable(dsi);
833 }
834
mtk_dsi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)835 static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
836 struct drm_bridge_state *old_bridge_state)
837 {
838 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
839
840 if (dsi->refcount == 0)
841 return;
842
843 mtk_output_dsi_enable(dsi);
844 }
845
mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)846 static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
847 struct drm_bridge_state *old_bridge_state)
848 {
849 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
850 int ret;
851
852 ret = mtk_dsi_poweron(dsi);
853 if (ret < 0)
854 DRM_ERROR("failed to power on dsi\n");
855 }
856
mtk_dsi_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)857 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
858 struct drm_bridge_state *old_bridge_state)
859 {
860 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
861
862 mtk_dsi_poweroff(dsi);
863 }
864
865 static enum drm_mode_status
mtk_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)866 mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
867 const struct drm_display_info *info,
868 const struct drm_display_mode *mode)
869 {
870 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
871 int bpp;
872
873 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
874 if (bpp < 0)
875 return MODE_ERROR;
876
877 if (mode->clock * bpp / dsi->lanes > 1500000)
878 return MODE_CLOCK_HIGH;
879
880 return MODE_OK;
881 }
882
883 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
884 .attach = mtk_dsi_bridge_attach,
885 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
886 .atomic_disable = mtk_dsi_bridge_atomic_disable,
887 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
888 .atomic_enable = mtk_dsi_bridge_atomic_enable,
889 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
890 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
891 .atomic_reset = drm_atomic_helper_bridge_reset,
892 .mode_valid = mtk_dsi_bridge_mode_valid,
893 .mode_set = mtk_dsi_bridge_mode_set,
894 };
895
mtk_dsi_ddp_start(struct device * dev)896 void mtk_dsi_ddp_start(struct device *dev)
897 {
898 struct mtk_dsi *dsi = dev_get_drvdata(dev);
899
900 mtk_dsi_poweron(dsi);
901 }
902
mtk_dsi_ddp_stop(struct device * dev)903 void mtk_dsi_ddp_stop(struct device *dev)
904 {
905 struct mtk_dsi *dsi = dev_get_drvdata(dev);
906
907 mtk_dsi_poweroff(dsi);
908 }
909
mtk_dsi_encoder_init(struct drm_device * drm,struct mtk_dsi * dsi)910 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
911 {
912 int ret;
913
914 ret = drm_simple_encoder_init(drm, &dsi->encoder,
915 DRM_MODE_ENCODER_DSI);
916 if (ret) {
917 DRM_ERROR("Failed to encoder init to drm\n");
918 return ret;
919 }
920
921 ret = mtk_find_possible_crtcs(drm, dsi->host.dev);
922 if (ret < 0)
923 goto err_cleanup_encoder;
924 dsi->encoder.possible_crtcs = ret;
925
926 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
927 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
928 if (ret)
929 goto err_cleanup_encoder;
930
931 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
932 if (IS_ERR(dsi->connector)) {
933 DRM_ERROR("Unable to create bridge connector\n");
934 ret = PTR_ERR(dsi->connector);
935 goto err_cleanup_encoder;
936 }
937 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
938
939 return 0;
940
941 err_cleanup_encoder:
942 drm_encoder_cleanup(&dsi->encoder);
943 return ret;
944 }
945
mtk_dsi_encoder_index(struct device * dev)946 unsigned int mtk_dsi_encoder_index(struct device *dev)
947 {
948 struct mtk_dsi *dsi = dev_get_drvdata(dev);
949 unsigned int encoder_index = drm_encoder_index(&dsi->encoder);
950
951 dev_dbg(dev, "encoder index:%d\n", encoder_index);
952 return encoder_index;
953 }
954
mtk_dsi_bind(struct device * dev,struct device * master,void * data)955 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
956 {
957 int ret;
958 struct drm_device *drm = data;
959 struct mtk_dsi *dsi = dev_get_drvdata(dev);
960
961 ret = mtk_dsi_encoder_init(drm, dsi);
962 if (ret)
963 return ret;
964
965 return device_reset_optional(dev);
966 }
967
mtk_dsi_unbind(struct device * dev,struct device * master,void * data)968 static void mtk_dsi_unbind(struct device *dev, struct device *master,
969 void *data)
970 {
971 struct mtk_dsi *dsi = dev_get_drvdata(dev);
972
973 drm_encoder_cleanup(&dsi->encoder);
974 }
975
976 static const struct component_ops mtk_dsi_component_ops = {
977 .bind = mtk_dsi_bind,
978 .unbind = mtk_dsi_unbind,
979 };
980
mtk_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)981 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
982 struct mipi_dsi_device *device)
983 {
984 struct mtk_dsi *dsi = host_to_dsi(host);
985 struct device *dev = host->dev;
986 int ret;
987
988 dsi->lanes = device->lanes;
989 dsi->format = device->format;
990 dsi->mode_flags = device->mode_flags;
991 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
992 if (IS_ERR(dsi->next_bridge)) {
993 ret = PTR_ERR(dsi->next_bridge);
994 if (ret == -EPROBE_DEFER)
995 return ret;
996
997 /* Old devicetree has only one endpoint */
998 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
999 if (IS_ERR(dsi->next_bridge))
1000 return PTR_ERR(dsi->next_bridge);
1001 }
1002
1003 drm_bridge_add(&dsi->bridge);
1004
1005 ret = component_add(host->dev, &mtk_dsi_component_ops);
1006 if (ret) {
1007 DRM_ERROR("failed to add dsi_host component: %d\n", ret);
1008 drm_bridge_remove(&dsi->bridge);
1009 return ret;
1010 }
1011
1012 return 0;
1013 }
1014
mtk_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1015 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
1016 struct mipi_dsi_device *device)
1017 {
1018 struct mtk_dsi *dsi = host_to_dsi(host);
1019
1020 component_del(host->dev, &mtk_dsi_component_ops);
1021 drm_bridge_remove(&dsi->bridge);
1022 return 0;
1023 }
1024
mtk_dsi_wait_for_idle(struct mtk_dsi * dsi)1025 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
1026 {
1027 int ret;
1028 u32 val;
1029
1030 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
1031 4, 2000000);
1032 if (ret) {
1033 DRM_WARN("polling dsi wait not busy timeout!\n");
1034
1035 mtk_dsi_enable(dsi);
1036 mtk_dsi_reset_engine(dsi);
1037 }
1038 }
1039
mtk_dsi_recv_cnt(u8 type,u8 * read_data)1040 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
1041 {
1042 switch (type) {
1043 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1044 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1045 return 1;
1046 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1047 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1048 return 2;
1049 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1050 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1051 return read_data[1] + read_data[2] * 16;
1052 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1053 DRM_INFO("type is 0x02, try again\n");
1054 break;
1055 default:
1056 DRM_INFO("type(0x%x) not recognized\n", type);
1057 break;
1058 }
1059
1060 return 0;
1061 }
1062
mtk_dsi_cmdq(struct mtk_dsi * dsi,const struct mipi_dsi_msg * msg)1063 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1064 {
1065 const char *tx_buf = msg->tx_buf;
1066 u8 config, cmdq_size, cmdq_off, type = msg->type;
1067 u32 reg_val, cmdq_mask, i;
1068 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1069
1070 if (MTK_DSI_HOST_IS_READ(type))
1071 config = BTA;
1072 else
1073 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1074
1075 if (msg->tx_len > 2) {
1076 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1077 cmdq_off = 4;
1078 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1079 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1080 } else {
1081 cmdq_size = 1;
1082 cmdq_off = 2;
1083 cmdq_mask = CONFIG | DATA_ID;
1084 reg_val = (type << 8) | config;
1085 }
1086
1087 for (i = 0; i < msg->tx_len; i++)
1088 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1089 (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1090 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1091
1092 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1093 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1094 if (dsi->driver_data->cmdq_long_packet_ctl) {
1095 /* Disable setting cmdq_size automatically for long packets */
1096 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
1097 }
1098 }
1099
mtk_dsi_host_send_cmd(struct mtk_dsi * dsi,const struct mipi_dsi_msg * msg,u8 flag)1100 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1101 const struct mipi_dsi_msg *msg, u8 flag)
1102 {
1103 mtk_dsi_wait_for_idle(dsi);
1104 mtk_dsi_irq_data_clear(dsi, flag);
1105 mtk_dsi_cmdq(dsi, msg);
1106 mtk_dsi_start(dsi);
1107
1108 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1109 return -ETIME;
1110 else
1111 return 0;
1112 }
1113
mtk_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1114 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1115 const struct mipi_dsi_msg *msg)
1116 {
1117 struct mtk_dsi *dsi = host_to_dsi(host);
1118 u32 recv_cnt, i;
1119 u8 read_data[16];
1120 void *src_addr;
1121 u8 irq_flag = CMD_DONE_INT_FLAG;
1122 u32 dsi_mode;
1123 int ret;
1124
1125 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
1126 if (dsi_mode & MODE) {
1127 mtk_dsi_stop(dsi);
1128 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
1129 if (ret)
1130 goto restore_dsi_mode;
1131 }
1132
1133 if (MTK_DSI_HOST_IS_READ(msg->type))
1134 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1135
1136 mtk_dsi_lane_ready(dsi);
1137
1138 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1139 if (ret)
1140 goto restore_dsi_mode;
1141
1142 if (!MTK_DSI_HOST_IS_READ(msg->type)) {
1143 recv_cnt = 0;
1144 goto restore_dsi_mode;
1145 }
1146
1147 if (!msg->rx_buf) {
1148 DRM_ERROR("dsi receive buffer size may be NULL\n");
1149 ret = -EINVAL;
1150 goto restore_dsi_mode;
1151 }
1152
1153 for (i = 0; i < 16; i++)
1154 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1155
1156 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1157
1158 if (recv_cnt > 2)
1159 src_addr = &read_data[4];
1160 else
1161 src_addr = &read_data[1];
1162
1163 if (recv_cnt > 10)
1164 recv_cnt = 10;
1165
1166 if (recv_cnt > msg->rx_len)
1167 recv_cnt = msg->rx_len;
1168
1169 if (recv_cnt)
1170 memcpy(msg->rx_buf, src_addr, recv_cnt);
1171
1172 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1173 recv_cnt, *((u8 *)(msg->tx_buf)));
1174
1175 restore_dsi_mode:
1176 if (dsi_mode & MODE) {
1177 mtk_dsi_set_mode(dsi);
1178 mtk_dsi_start(dsi);
1179 }
1180
1181 return ret < 0 ? ret : recv_cnt;
1182 }
1183
1184 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1185 .attach = mtk_dsi_host_attach,
1186 .detach = mtk_dsi_host_detach,
1187 .transfer = mtk_dsi_host_transfer,
1188 };
1189
mtk_dsi_probe(struct platform_device * pdev)1190 static int mtk_dsi_probe(struct platform_device *pdev)
1191 {
1192 struct mtk_dsi *dsi;
1193 struct device *dev = &pdev->dev;
1194 struct resource *regs;
1195 int irq_num;
1196 int ret;
1197
1198 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1199 if (!dsi)
1200 return -ENOMEM;
1201
1202 dsi->driver_data = of_device_get_match_data(dev);
1203
1204 dsi->engine_clk = devm_clk_get(dev, "engine");
1205 if (IS_ERR(dsi->engine_clk))
1206 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),
1207 "Failed to get engine clock\n");
1208
1209
1210 dsi->digital_clk = devm_clk_get(dev, "digital");
1211 if (IS_ERR(dsi->digital_clk))
1212 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),
1213 "Failed to get digital clock\n");
1214
1215 dsi->hs_clk = devm_clk_get(dev, "hs");
1216 if (IS_ERR(dsi->hs_clk))
1217 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
1218
1219 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 dsi->regs = devm_ioremap_resource(dev, regs);
1221 if (IS_ERR(dsi->regs))
1222 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");
1223
1224 dsi->phy = devm_phy_get(dev, "dphy");
1225 if (IS_ERR(dsi->phy))
1226 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");
1227
1228 irq_num = platform_get_irq(pdev, 0);
1229 if (irq_num < 0)
1230 return irq_num;
1231
1232 dsi->host.ops = &mtk_dsi_ops;
1233 dsi->host.dev = dev;
1234 ret = mipi_dsi_host_register(&dsi->host);
1235 if (ret < 0)
1236 return dev_err_probe(dev, ret, "Failed to register DSI host\n");
1237
1238 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1239 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1240 if (ret) {
1241 mipi_dsi_host_unregister(&dsi->host);
1242 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");
1243 }
1244
1245 init_waitqueue_head(&dsi->irq_wait_queue);
1246
1247 platform_set_drvdata(pdev, dsi);
1248
1249 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1250 dsi->bridge.of_node = dev->of_node;
1251 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1252
1253 return 0;
1254 }
1255
mtk_dsi_remove(struct platform_device * pdev)1256 static void mtk_dsi_remove(struct platform_device *pdev)
1257 {
1258 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1259
1260 mtk_output_dsi_disable(dsi);
1261 mipi_dsi_host_unregister(&dsi->host);
1262 }
1263
1264 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1265 .reg_cmdq_off = 0x200,
1266 };
1267
1268 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1269 .reg_cmdq_off = 0x180,
1270 };
1271
1272 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1273 .reg_cmdq_off = 0x200,
1274 .has_shadow_ctl = true,
1275 .has_size_ctl = true,
1276 };
1277
1278 static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
1279 .reg_cmdq_off = 0xd00,
1280 .has_shadow_ctl = true,
1281 .has_size_ctl = true,
1282 };
1283
1284 static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
1285 .reg_cmdq_off = 0xd00,
1286 .has_shadow_ctl = true,
1287 .has_size_ctl = true,
1288 .cmdq_long_packet_ctl = true,
1289 .support_per_frame_lp = true,
1290 };
1291
1292 static const struct of_device_id mtk_dsi_of_match[] = {
1293 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
1294 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
1295 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
1296 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
1297 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
1298 { /* sentinel */ }
1299 };
1300 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
1301
1302 struct platform_driver mtk_dsi_driver = {
1303 .probe = mtk_dsi_probe,
1304 .remove = mtk_dsi_remove,
1305 .driver = {
1306 .name = "mtk-dsi",
1307 .of_match_table = mtk_dsi_of_match,
1308 },
1309 };
1310