| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 864 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
1165 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1182 uint32_t acpi_transition_bitmasks[MAX_PIPES];
1798 …bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first…
1859 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
1860 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
1861 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
1862 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
1863 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
1864 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | hw_shared.h | 45 #define MAX_PIPES 6 macro
46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
96 struct pipe_topology_line pipe_log_lines[MAX_PIPES];
|
| H A D | pg_cntl.h | 35 bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
|
| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 141 if (dsc_inst < MAX_PIPES) in pg_cntl35_dsc_pg_control()
232 if (hubp_dpp_inst < MAX_PIPES) { in pg_cntl35_hubp_dpp_pg_control()
353 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
363 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
373 if (optc_inst < MAX_PIPES) in pg_cntl35_optc_pg_control()
561 memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); in pg_cntl35_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 249 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
396 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
683 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
713 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
751 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
778 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
784 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
808 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
814 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
850 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
|
| H A D | dc.c | 431 for (i = 0; i < MAX_PIPES; i++) { in set_long_vtotal()
495 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
537 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
603 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_crc_window()
610 if (i == MAX_PIPES) in dc_stream_forward_crc_window()
669 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_multiple_crc_window()
676 if (i == MAX_PIPES) in dc_stream_forward_multiple_crc_window()
792 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
798 if (i == MAX_PIPES) in dc_stream_get_crc()
818 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dyn_expansion()
[all …]
|
| H A D | dc_resource.c | 107 if (current_snapshot->line_count >= MAX_PIPES) in capture_pipe_topology_data()
737 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1454 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_build_test_pattern_params()
1746 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
2000 for (i = 0; i < MAX_PIPES; i++) { in resource_get_otg_master_for_stream()
2010 struct pipe_ctx *opp_heads[MAX_PIPES]) in resource_get_opp_heads_for_otg_master() argument
2026 ASSERT(i < MAX_PIPES); in resource_get_opp_heads_for_otg_master()
2035 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_opp_head() argument
2045 ASSERT(i < MAX_PIPES); in resource_get_dpp_pipes_for_opp_head()
2054 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_plane() argument
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 69 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test()
78 struct audio_output audio_output[MAX_PIPES]; in dp_retrain_link_dp_test()
79 struct dc_stream_state *streams_on_link[MAX_PIPES]; in dp_retrain_link_dp_test()
145 for (i = 0; i < MAX_PIPES; i++) { in dp_retrain_link_dp_test()
665 for (i = 0; i < MAX_PIPES; i++) { in dp_set_test_pattern()
972 for (i = 0; i < MAX_PIPES; i++) { in dp_set_preferred_link_settings()
983 if (i == MAX_PIPES) in dp_set_preferred_link_settings()
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 998 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
999 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1101 bool tried[MAX_PIPES]; in try_disable_dsc()
1102 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1194 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1357 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1373 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1488 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1558 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_resource.c | 40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_edp_panel_control.c | 537 for (i = 0; i < MAX_PIPES; i++) { in get_pipe_from_link()
799 for (i = 0; i < MAX_PIPES; i++) { in edp_setup_psr()
1034 for (i = 0; i < MAX_PIPES; i++) { in edp_setup_panel_replay()
1140 for (i = 0; i < MAX_PIPES; i++) { in edp_setup_freesync_replay()
1314 for (i = 0; i < MAX_PIPES; i++) { in get_abm_from_stream_res()
|
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 14 #define MAX_PIPES 6 macro
128 for (i = 0; i < MAX_PIPES; i++) { in dmub_replay_copy_settings()
|
| H A D | dce_clk_mgr.c | 189 for (i = 0; i < MAX_PIPES; i++) { in get_max_pixel_clock_for_all_paths()
510 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 719 struct pipe_ctx *opp_heads[MAX_PIPES], in enable_stream_timing_calc() argument
762 int opp_inst[MAX_PIPES] = {0}; in dcn401_enable_stream_timing()
763 struct pipe_ctx *opp_heads[MAX_PIPES] = {0}; in dcn401_enable_stream_timing()
1022 for (i = 0; i < MAX_PIPES; i++) { in disable_link_output_symclk_on_tx_off()
1527 struct pipe_ctx *old_opp_heads[MAX_PIPES]; in update_dsc_for_odm_change()
1563 struct pipe_ctx *opp_heads[MAX_PIPES]; in dcn401_update_odm()
1564 int opp_inst[MAX_PIPES] = {0}; in dcn401_update_odm()
1610 struct pipe_ctx *old_opp_heads[MAX_PIPES]; in dcn401_add_dsc_sequence_for_odm_change()
1700 struct pipe_ctx *opp_heads[MAX_PIPES]; in dcn401_update_odm_sequence()
1701 int opp_inst[MAX_PIPES] = {0}; in dcn401_update_odm_sequence()
[all …]
|
| /linux/drivers/net/ipa/ |
| H A D | ipa_reg.h | 264 MAX_PIPES, enumerator
|
| /linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| H A D | irq_service_dce110.c | 216 if (pipe_offset >= MAX_PIPES) in dce110_vblank_set()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 316 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0}; in dcn32_determine_det_override()
317 uint8_t pipe_counted[MAX_PIPES] = {0}; in dcn32_determine_det_override()
|
| /linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v3.5.1.c | 133 [MAX_PIPES] = GENMASK(3, 0),
|
| H A D | ipa_reg-v4.2.c | 177 [MAX_PIPES] = GENMASK(3, 0),
|
| H A D | ipa_reg-v4.7.c | 155 [MAX_PIPES] = GENMASK(3, 0),
|
| H A D | ipa_reg-v4.9.c | 160 [MAX_PIPES] = GENMASK(3, 0),
|
| H A D | ipa_reg-v4.11.c | 161 [MAX_PIPES] = GENMASK(4, 0),
|
| H A D | ipa_reg-v5.0.c | 13 [MAX_PIPES] = GENMASK(7, 0),
|
| H A D | ipa_reg-v5.5.c | 13 [MAX_PIPES] = GENMASK(7, 0),
|
| H A D | ipa_reg-v4.5.c | 154 [MAX_PIPES] = GENMASK(3, 0),
|