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Searched refs:MAX_PIPES (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h873 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
1188 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1205 uint32_t acpi_transition_bitmasks[MAX_PIPES];
1869 …bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first…
1935 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
1936 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
1937 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
1938 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
1939 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
1940 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.h138 type OTG_ADD_PIXEL[MAX_PIPES];\
139 type OTG_DROP_PIXEL[MAX_PIPES];\
175 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
176 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
177 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
178 type DTBCLK_DTO_DIV[MAX_PIPES];\
367 type DP_DTO_ENABLE[MAX_PIPES];
407 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
414 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
415 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_dc_resource_mgmt.c47 unsigned int odm_slice_end_x[MAX_PIPES];
48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
354 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
355 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
423 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
424 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
626 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_stream()
664 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_plane()
926 struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0}; in get_source_mpc_factor()
942 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) in populate_mpc_factors_for_stream() argument
[all …]
H A Ddml2_translation_helper.c993 for (i = 0; i < MAX_PIPES; i++) { in get_scaler_data_for_plane()
1006 ASSERT(i < MAX_PIPES); in get_scaler_data_for_plane()
1287 for (i = 0; i < MAX_PIPES; i++) { in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
1326 for (k = 0; k < MAX_PIPES; k++) { in map_dc_state_into_dml_display_cfg()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c141 if (dsc_inst < MAX_PIPES) in pg_cntl35_dsc_pg_control()
232 if (hubp_dpp_inst < MAX_PIPES) { in pg_cntl35_hubp_dpp_pg_control()
353 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
363 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
373 if (optc_inst < MAX_PIPES) in pg_cntl35_optc_pg_control()
561 memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); in pg_cntl35_create()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c276 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
423 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
727 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
757 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
795 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
822 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
828 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
852 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
858 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
894 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
H A Ddc_resource.c108 if (current_snapshot->line_count >= MAX_PIPES) in capture_pipe_topology_data()
744 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1461 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_build_test_pattern_params()
1754 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
2010 for (i = 0; i < MAX_PIPES; i++) { in resource_get_otg_master_for_stream()
2020 struct pipe_ctx *opp_heads[MAX_PIPES]) in resource_get_opp_heads_for_otg_master() argument
2036 ASSERT(i < MAX_PIPES); in resource_get_opp_heads_for_otg_master()
2045 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_opp_head() argument
2055 ASSERT(i < MAX_PIPES); in resource_get_dpp_pipes_for_opp_head()
2064 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_plane() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dpg_cntl.h35 bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
H A Ddccg.h196 int pipe_dppclk_khz[MAX_PIPES];
198 bool dpp_clock_gated[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c998 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
999 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1101 bool tried[MAX_PIPES]; in try_disable_dsc()
1102 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1194 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1357 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1373 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1488 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1558 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_resource.c40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
H A Dlink_dpms.c152 struct pipe_ctx *pipes[MAX_PIPES]; in link_set_all_streams_dpms_off_for_link()
153 struct dc_stream_state *streams[MAX_PIPES]; in link_set_all_streams_dpms_off_for_link()
211 struct pipe_ctx *pipes[MAX_PIPES]) in link_get_master_pipes_with_dpms_on() argument
217 for (i = 0; i < MAX_PIPES; i++) { in link_get_master_pipes_with_dpms_on()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c34 #define MAX_PIPES 6 macro
305 for (i = 0; i < MAX_PIPES; i++) { in dmub_psr_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c617 struct pipe_ctx *opp_heads[MAX_PIPES], in enable_stream_timing_calc() argument
661 int opp_inst[MAX_PIPES] = {0}; in dcn401_enable_stream_timing()
662 struct pipe_ctx *opp_heads[MAX_PIPES] = {0}; in dcn401_enable_stream_timing()
923 for (i = 0; i < MAX_PIPES; i++) { in disable_link_output_symclk_on_tx_off()
1452 struct pipe_ctx *old_opp_heads[MAX_PIPES]; in update_dsc_for_odm_change()
1488 struct pipe_ctx *opp_heads[MAX_PIPES]; in dcn401_update_odm()
1489 int opp_inst[MAX_PIPES] = {0}; in dcn401_update_odm()
1535 struct pipe_ctx *old_opp_heads[MAX_PIPES]; in dcn401_add_dsc_sequence_for_odm_change()
1625 struct pipe_ctx *opp_heads[MAX_PIPES]; in dcn401_update_odm_sequence()
1626 int opp_inst[MAX_PIPES] = {0}; in dcn401_update_odm_sequence()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1173 struct pipe_ctx *dpp_pipes[MAX_PIPES]; in init_pipe_slice_table_from_context()
1203 int split[MAX_PIPES], in update_pipe_slice_table_with_split_flags() argument
1204 bool merge[MAX_PIPES]) in update_pipe_slice_table_with_split_flags() argument
1286 struct vba_vars_st *vba, int split[MAX_PIPES], in update_pipes_with_split_flags() argument
1287 bool merge[MAX_PIPES]) in update_pipes_with_split_flags() argument
1404 unsigned int cur_policy[MAX_PIPES]; in try_odm_power_optimization_and_revalidate()
1414 memset(split, 0, MAX_PIPES * sizeof(int)); in try_odm_power_optimization_and_revalidate()
1415 memset(merge, 0, MAX_PIPES * sizeof(bool)); in try_odm_power_optimization_and_revalidate()
1477 memset(split, 0, MAX_PIPES * sizeof(int)); in dcn32_full_validate_bw_helper()
1478 memset(merge, 0, MAX_PIPES * sizeof(bool)); in dcn32_full_validate_bw_helper()
[all …]
/linux/drivers/net/ipa/
H A Dipa_reg.h264 MAX_PIPES, enumerator
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.5.1.c133 [MAX_PIPES] = GENMASK(3, 0),
H A Dipa_reg-v4.2.c177 [MAX_PIPES] = GENMASK(3, 0),
H A Dipa_reg-v4.7.c155 [MAX_PIPES] = GENMASK(3, 0),
H A Dipa_reg-v4.9.c160 [MAX_PIPES] = GENMASK(3, 0),
H A Dipa_reg-v4.11.c161 [MAX_PIPES] = GENMASK(4, 0),
H A Dipa_reg-v5.0.c13 [MAX_PIPES] = GENMASK(7, 0),
H A Dipa_reg-v5.5.c13 [MAX_PIPES] = GENMASK(7, 0),
H A Dipa_reg-v4.5.c154 [MAX_PIPES] = GENMASK(3, 0),
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c805 int split[MAX_PIPES] = { 0 }; in dcn21_fast_validate_bw()
806 bool merge[MAX_PIPES] = { false }; in dcn21_fast_validate_bw()
875 for (i = 0; i < MAX_PIPES; i++) in dcn21_fast_validate_bw()

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