1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * iio/adc/max1363.c
4 * Copyright (C) 2008-2010 Jonathan Cameron
5 *
6 * based on linux/drivers/i2c/chips/max123x
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
8 *
9 * based on linux/drivers/acron/char/pcf8583.c
10 * Copyright (C) 2000 Russell King
11 *
12 * Driver for max1363 and similar chips.
13 */
14
15 #include <linux/interrupt.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/kernel.h>
19 #include <linux/sysfs.h>
20 #include <linux/list.h>
21 #include <linux/i2c.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/err.h>
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/property.h>
28
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/events.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/kfifo_buf.h>
34 #include <linux/iio/trigger_consumer.h>
35 #include <linux/iio/triggered_buffer.h>
36
37 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
38
39 /* There is a fair bit more defined here than currently
40 * used, but the intention is to support everything these
41 * chips do in the long run */
42
43 /* see data sheets */
44 /* max1363 and max1236, max1237, max1238, max1239 */
45 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
46 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
47 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
48 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
49 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
50 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
51
52 /* think about including max11600 etc - more settings */
53 #define MAX1363_SETUP_EXT_CLOCK 0x08
54 #define MAX1363_SETUP_INT_CLOCK 0x00
55 #define MAX1363_SETUP_UNIPOLAR 0x00
56 #define MAX1363_SETUP_BIPOLAR 0x04
57 #define MAX1363_SETUP_RESET 0x00
58 #define MAX1363_SETUP_NORESET 0x02
59 /* max1363 only - though don't care on others.
60 * For now monitor modes are not implemented as the relevant
61 * line is not connected on my test board.
62 * The definitions are here as I intend to add this soon.
63 */
64 #define MAX1363_SETUP_MONITOR_SETUP 0x01
65
66 /* Specific to the max1363 */
67 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
68 #define MAX1363_MON_INT_ENABLE 0x01
69
70 /* defined for readability reasons */
71 /* All chips */
72 #define MAX1363_CONFIG_BYTE(a) ((a))
73
74 #define MAX1363_CONFIG_SE 0x01
75 #define MAX1363_CONFIG_DE 0x00
76 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
77 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
78 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
79 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
80 /* max123{6-9} only */
81 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
82
83 /* max1363 only - merely part of channel selects or don't care for others */
84 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
85
86 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
87
88 /* max1363 strictly 0x06 - but doesn't matter */
89 #define MAX1363_CHANNEL_SEL_MASK 0x1E
90 #define MAX1363_SCAN_MASK 0x60
91 #define MAX1363_SE_DE_MASK 0x01
92
93 #define MAX1363_MAX_CHANNELS 25
94 /**
95 * struct max1363_mode - scan mode information
96 * @conf: The corresponding value of the configuration register
97 * @modemask: Bit mask corresponding to channels enabled in this mode
98 */
99 struct max1363_mode {
100 int8_t conf;
101 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
102 };
103
104 /* This must be maintained along side the max1363_mode_table in max1363_core */
105 enum max1363_modes {
106 /* Single read of a single channel */
107 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
108 /* Differential single read */
109 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
110 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
111 /* Scan to channel and mid to channel where overlapping */
112 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
113 s6to7, s0to7, s6to8, s0to8, s6to9,
114 s0to9, s6to10, s0to10, s6to11, s0to11,
115 /* Differential scan to channel and mid to channel where overlapping */
116 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
117 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
118 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
119 d7m6to11m10, d1m0to11m10,
120 };
121
122 /**
123 * struct max1363_chip_info - chip specifc information
124 * @info: iio core function callbacks structure
125 * @channels: channel specification
126 * @num_channels: number of channels
127 * @mode_list: array of available scan modes
128 * @default_mode: the scan mode in which the chip starts up
129 * @int_vref_mv: the internal reference voltage
130 * @num_modes: number of modes
131 * @bits: accuracy of the adc in bits
132 */
133 struct max1363_chip_info {
134 const struct iio_info *info;
135 const struct iio_chan_spec *channels;
136 int num_channels;
137 const enum max1363_modes *mode_list;
138 enum max1363_modes default_mode;
139 u16 int_vref_mv;
140 u8 num_modes;
141 u8 bits;
142 };
143
144 /**
145 * struct max1363_state - driver instance specific data
146 * @client: i2c_client
147 * @setupbyte: cache of current device setup byte
148 * @configbyte: cache of current device config byte
149 * @chip_info: chip model specific constants, available modes, etc.
150 * @current_mode: the scan mode of this chip
151 * @requestedmask: a valid requested set of channels
152 * @lock: lock to ensure state is consistent
153 * @monitor_on: whether monitor mode is enabled
154 * @monitor_speed: parameter corresponding to device monitor speed setting
155 * @mask_high: bitmask for enabled high thresholds
156 * @mask_low: bitmask for enabled low thresholds
157 * @thresh_high: high threshold values
158 * @thresh_low: low threshold values
159 * @vref: Reference voltage regulator
160 * @vref_uv: Actual (external or internal) reference voltage
161 * @send: function used to send data to the chip
162 * @recv: function used to receive data from the chip
163 */
164 struct max1363_state {
165 struct i2c_client *client;
166 u8 setupbyte;
167 u8 configbyte;
168 const struct max1363_chip_info *chip_info;
169 const struct max1363_mode *current_mode;
170 u32 requestedmask;
171 struct mutex lock;
172
173 /* Using monitor modes and buffer at the same time is
174 currently not supported */
175 bool monitor_on;
176 unsigned int monitor_speed:3;
177 u8 mask_high;
178 u8 mask_low;
179 /* 4x unipolar first then the fours bipolar ones */
180 s16 thresh_high[8];
181 s16 thresh_low[8];
182 struct regulator *vref;
183 u32 vref_uv;
184 int (*send)(const struct i2c_client *client,
185 const char *buf, int count);
186 int (*recv)(const struct i2c_client *client,
187 char *buf, int count);
188 };
189
190 #define MAX1363_MODE_SINGLE(_num, _mask) { \
191 .conf = MAX1363_CHANNEL_SEL(_num) \
192 | MAX1363_CONFIG_SCAN_SINGLE_1 \
193 | MAX1363_CONFIG_SE, \
194 .modemask[0] = _mask, \
195 }
196
197 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
198 .conf = MAX1363_CHANNEL_SEL(_num) \
199 | MAX1363_CONFIG_SCAN_TO_CS \
200 | MAX1363_CONFIG_SE, \
201 .modemask[0] = _mask, \
202 }
203
204 /* note not available for max1363 hence naming */
205 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
206 .conf = MAX1363_CHANNEL_SEL(_num) \
207 | MAX1236_SCAN_MID_TO_CHANNEL \
208 | MAX1363_CONFIG_SE, \
209 .modemask[0] = _mask \
210 }
211
212 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
213 .conf = MAX1363_CHANNEL_SEL(_nump) \
214 | MAX1363_CONFIG_SCAN_SINGLE_1 \
215 | MAX1363_CONFIG_DE, \
216 .modemask[0] = _mask \
217 }
218
219 /* Can't think how to automate naming so specify for now */
220 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
221 .conf = MAX1363_CHANNEL_SEL(_num) \
222 | MAX1363_CONFIG_SCAN_TO_CS \
223 | MAX1363_CONFIG_DE, \
224 .modemask[0] = _mask \
225 }
226
227 /* note only available for max1363 hence naming */
228 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
229 .conf = MAX1363_CHANNEL_SEL(_num) \
230 | MAX1236_SCAN_MID_TO_CHANNEL \
231 | MAX1363_CONFIG_SE, \
232 .modemask[0] = _mask \
233 }
234
235 static const struct max1363_mode max1363_mode_table[] = {
236 /* All of the single channel options first */
237 MAX1363_MODE_SINGLE(0, 1 << 0),
238 MAX1363_MODE_SINGLE(1, 1 << 1),
239 MAX1363_MODE_SINGLE(2, 1 << 2),
240 MAX1363_MODE_SINGLE(3, 1 << 3),
241 MAX1363_MODE_SINGLE(4, 1 << 4),
242 MAX1363_MODE_SINGLE(5, 1 << 5),
243 MAX1363_MODE_SINGLE(6, 1 << 6),
244 MAX1363_MODE_SINGLE(7, 1 << 7),
245 MAX1363_MODE_SINGLE(8, 1 << 8),
246 MAX1363_MODE_SINGLE(9, 1 << 9),
247 MAX1363_MODE_SINGLE(10, 1 << 10),
248 MAX1363_MODE_SINGLE(11, 1 << 11),
249
250 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
251 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
252 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
253 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
254 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
255 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
256 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
257 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
258 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
259 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
260 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
261 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
262
263 /* The multichannel scans next */
264 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
265 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
266 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
267 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
268 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
270 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
271 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
272 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
273 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
274 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
275 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
276 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
277 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
278 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
279 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
280 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
281
282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
284 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
285 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
287 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
292 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
294 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
295 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
296 };
297
298 static const struct max1363_mode
max1363_match_mode(const unsigned long * mask,const struct max1363_chip_info * ci)299 *max1363_match_mode(const unsigned long *mask,
300 const struct max1363_chip_info *ci)
301 {
302 int i;
303 if (mask)
304 for (i = 0; i < ci->num_modes; i++)
305 if (bitmap_subset(mask,
306 max1363_mode_table[ci->mode_list[i]].
307 modemask,
308 MAX1363_MAX_CHANNELS))
309 return &max1363_mode_table[ci->mode_list[i]];
310 return NULL;
311 }
312
max1363_smbus_send(const struct i2c_client * client,const char * buf,int count)313 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
314 int count)
315 {
316 int i, err;
317
318 for (i = err = 0; err == 0 && i < count; ++i)
319 err = i2c_smbus_write_byte(client, buf[i]);
320
321 return err ? err : count;
322 }
323
max1363_smbus_recv(const struct i2c_client * client,char * buf,int count)324 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
325 int count)
326 {
327 int i, ret;
328
329 for (i = 0; i < count; ++i) {
330 ret = i2c_smbus_read_byte(client);
331 if (ret < 0)
332 return ret;
333 buf[i] = ret;
334 }
335
336 return count;
337 }
338
max1363_write_basic_config(struct max1363_state * st)339 static int max1363_write_basic_config(struct max1363_state *st)
340 {
341 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
342
343 return st->send(st->client, tx_buf, 2);
344 }
345
max1363_set_scan_mode(struct max1363_state * st)346 static int max1363_set_scan_mode(struct max1363_state *st)
347 {
348 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
349 | MAX1363_SCAN_MASK
350 | MAX1363_SE_DE_MASK);
351 st->configbyte |= st->current_mode->conf;
352
353 return max1363_write_basic_config(st);
354 }
355
max1363_read_single_chan(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,long m)356 static int max1363_read_single_chan(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
358 int *val,
359 long m)
360 {
361 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
362 s32 data;
363 u8 rxbuf[2];
364 struct max1363_state *st = iio_priv(indio_dev);
365 struct i2c_client *client = st->client;
366
367 guard(mutex)(&st->lock);
368
369 /*
370 * If monitor mode is enabled, the method for reading a single
371 * channel will have to be rather different and has not yet
372 * been implemented.
373 *
374 * Also, cannot read directly if buffered capture enabled.
375 */
376 if (st->monitor_on)
377 return -EBUSY;
378
379 /* Check to see if current scan mode is correct */
380 if (st->current_mode != &max1363_mode_table[chan->address]) {
381 int ret;
382
383 /* Update scan mode if needed */
384 st->current_mode = &max1363_mode_table[chan->address];
385 ret = max1363_set_scan_mode(st);
386 if (ret < 0)
387 return ret;
388 }
389 if (st->chip_info->bits != 8) {
390 /* Get reading */
391 data = st->recv(client, rxbuf, 2);
392 if (data < 0)
393 return data;
394
395 data = (rxbuf[1] | rxbuf[0] << 8) &
396 ((1 << st->chip_info->bits) - 1);
397 } else {
398 /* Get reading */
399 data = st->recv(client, rxbuf, 1);
400 if (data < 0)
401 return data;
402
403 data = rxbuf[0];
404 }
405 *val = data;
406
407 return 0;
408 }
409 unreachable();
410 }
411
max1363_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)412 static int max1363_read_raw(struct iio_dev *indio_dev,
413 struct iio_chan_spec const *chan,
414 int *val,
415 int *val2,
416 long m)
417 {
418 struct max1363_state *st = iio_priv(indio_dev);
419 int ret;
420
421 switch (m) {
422 case IIO_CHAN_INFO_RAW:
423 ret = max1363_read_single_chan(indio_dev, chan, val, m);
424 if (ret < 0)
425 return ret;
426 return IIO_VAL_INT;
427 case IIO_CHAN_INFO_SCALE:
428 *val = st->vref_uv / 1000;
429 *val2 = st->chip_info->bits;
430 return IIO_VAL_FRACTIONAL_LOG2;
431 default:
432 return -EINVAL;
433 }
434 return 0;
435 }
436
437 /* Applies to max1363 */
438 static const enum max1363_modes max1363_mode_list[] = {
439 _s0, _s1, _s2, _s3,
440 s0to1, s0to2, s0to3,
441 d0m1, d2m3, d1m0, d3m2,
442 d0m1to2m3, d1m0to3m2,
443 };
444
445 static const struct iio_event_spec max1363_events[] = {
446 {
447 .type = IIO_EV_TYPE_THRESH,
448 .dir = IIO_EV_DIR_RISING,
449 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
450 BIT(IIO_EV_INFO_ENABLE),
451 }, {
452 .type = IIO_EV_TYPE_THRESH,
453 .dir = IIO_EV_DIR_FALLING,
454 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
455 BIT(IIO_EV_INFO_ENABLE),
456 },
457 };
458
459 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
460 { \
461 .type = IIO_VOLTAGE, \
462 .indexed = 1, \
463 .channel = num, \
464 .address = addr, \
465 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
466 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
467 .datasheet_name = "AIN"#num, \
468 .scan_type = { \
469 .sign = 'u', \
470 .realbits = bits, \
471 .storagebits = (bits > 8) ? 16 : 8, \
472 .endianness = IIO_BE, \
473 }, \
474 .scan_index = si, \
475 .event_spec = ev_spec, \
476 .num_event_specs = num_ev_spec, \
477 }
478
479 /* bipolar channel */
480 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
481 { \
482 .type = IIO_VOLTAGE, \
483 .differential = 1, \
484 .indexed = 1, \
485 .channel = num, \
486 .channel2 = num2, \
487 .address = addr, \
488 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
489 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
490 .datasheet_name = "AIN"#num"-AIN"#num2, \
491 .scan_type = { \
492 .sign = 's', \
493 .realbits = bits, \
494 .storagebits = (bits > 8) ? 16 : 8, \
495 .endianness = IIO_BE, \
496 }, \
497 .scan_index = si, \
498 .event_spec = ev_spec, \
499 .num_event_specs = num_ev_spec, \
500 }
501
502 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
503 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
504 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
505 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
511 IIO_CHAN_SOFT_TIMESTAMP(8) \
512 }
513
514 static const struct iio_chan_spec max1036_channels[] =
515 MAX1363_4X_CHANS(8, NULL, 0);
516 static const struct iio_chan_spec max1136_channels[] =
517 MAX1363_4X_CHANS(10, NULL, 0);
518 static const struct iio_chan_spec max1236_channels[] =
519 MAX1363_4X_CHANS(12, NULL, 0);
520 static const struct iio_chan_spec max1361_channels[] =
521 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
522 static const struct iio_chan_spec max1363_channels[] =
523 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
524
525 /* Applies to max1236, max1237 */
526 static const enum max1363_modes max1236_mode_list[] = {
527 _s0, _s1, _s2, _s3,
528 s0to1, s0to2, s0to3,
529 d0m1, d2m3, d1m0, d3m2,
530 d0m1to2m3, d1m0to3m2,
531 s2to3,
532 };
533
534 /* Applies to max1238, max1239 */
535 static const enum max1363_modes max1238_mode_list[] = {
536 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
537 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
538 s0to7, s0to8, s0to9, s0to10, s0to11,
539 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
540 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
541 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
542 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
543 s6to7, s6to8, s6to9, s6to10, s6to11,
544 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
545 };
546
547 #define MAX1363_12X_CHANS(bits) { \
548 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
549 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
550 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
551 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
552 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
553 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
554 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
555 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
556 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
557 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
558 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
559 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
560 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
561 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
562 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
563 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
564 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
565 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
566 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
567 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
568 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
569 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
570 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
571 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
572 IIO_CHAN_SOFT_TIMESTAMP(24) \
573 }
574 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
575 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
576 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
577
578 static const enum max1363_modes max11607_mode_list[] = {
579 _s0, _s1, _s2, _s3,
580 s0to1, s0to2, s0to3,
581 s2to3,
582 d0m1, d2m3, d1m0, d3m2,
583 d0m1to2m3, d1m0to3m2,
584 };
585
586 static const enum max1363_modes max11608_mode_list[] = {
587 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
588 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
589 s6to7,
590 d0m1, d2m3, d4m5, d6m7,
591 d1m0, d3m2, d5m4, d7m6,
592 d0m1to2m3, d0m1to4m5, d0m1to6m7,
593 d1m0to3m2, d1m0to5m4, d1m0to7m6,
594 };
595
596 #define MAX1363_8X_CHANS(bits) { \
597 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
598 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
599 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
600 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
601 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
602 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
603 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
604 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
605 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
606 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
607 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
608 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
609 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
610 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
611 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
612 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
613 IIO_CHAN_SOFT_TIMESTAMP(16) \
614 }
615 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
616 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
617 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
618
619 static const enum max1363_modes max11644_mode_list[] = {
620 _s0, _s1, s0to1, d0m1, d1m0,
621 };
622
623 #define MAX1363_2X_CHANS(bits) { \
624 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
625 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
626 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
627 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
628 IIO_CHAN_SOFT_TIMESTAMP(4) \
629 }
630
631 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
632 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
633
634 enum { max1361,
635 max1362,
636 max1363,
637 max1364,
638 max1036,
639 max1037,
640 max1038,
641 max1039,
642 max1136,
643 max1137,
644 max1138,
645 max1139,
646 max1236,
647 max1237,
648 max1238,
649 max1239,
650 max11600,
651 max11601,
652 max11602,
653 max11603,
654 max11604,
655 max11605,
656 max11606,
657 max11607,
658 max11608,
659 max11609,
660 max11610,
661 max11611,
662 max11612,
663 max11613,
664 max11614,
665 max11615,
666 max11616,
667 max11617,
668 max11644,
669 max11645,
670 max11646,
671 max11647
672 };
673
674 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
675 8300, 4200, 2000, 1000 };
676
max1363_monitor_show_freq(struct device * dev,struct device_attribute * attr,char * buf)677 static ssize_t max1363_monitor_show_freq(struct device *dev,
678 struct device_attribute *attr,
679 char *buf)
680 {
681 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
682 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
683 }
684
max1363_monitor_store_freq(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)685 static ssize_t max1363_monitor_store_freq(struct device *dev,
686 struct device_attribute *attr,
687 const char *buf,
688 size_t len)
689 {
690 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
691 struct max1363_state *st = iio_priv(indio_dev);
692 int i, ret;
693 unsigned long val;
694 bool found = false;
695
696 ret = kstrtoul(buf, 10, &val);
697 if (ret)
698 return -EINVAL;
699 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
700 if (val == max1363_monitor_speeds[i]) {
701 found = true;
702 break;
703 }
704 if (!found)
705 return -EINVAL;
706
707 scoped_guard(mutex, &st->lock)
708 st->monitor_speed = i;
709
710 return 0;
711 }
712
713 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
714 max1363_monitor_show_freq,
715 max1363_monitor_store_freq);
716
717 static IIO_CONST_ATTR(sampling_frequency_available,
718 "133000 665000 33300 16600 8300 4200 2000 1000");
719
max1363_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)720 static int max1363_read_thresh(struct iio_dev *indio_dev,
721 const struct iio_chan_spec *chan, enum iio_event_type type,
722 enum iio_event_direction dir, enum iio_event_info info, int *val,
723 int *val2)
724 {
725 struct max1363_state *st = iio_priv(indio_dev);
726 if (dir == IIO_EV_DIR_FALLING)
727 *val = st->thresh_low[chan->channel];
728 else
729 *val = st->thresh_high[chan->channel];
730 return IIO_VAL_INT;
731 }
732
max1363_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)733 static int max1363_write_thresh(struct iio_dev *indio_dev,
734 const struct iio_chan_spec *chan, enum iio_event_type type,
735 enum iio_event_direction dir, enum iio_event_info info, int val,
736 int val2)
737 {
738 struct max1363_state *st = iio_priv(indio_dev);
739 /* make it handle signed correctly as well */
740 switch (st->chip_info->bits) {
741 case 10:
742 if (val > 0x3FF)
743 return -EINVAL;
744 break;
745 case 12:
746 if (val > 0xFFF)
747 return -EINVAL;
748 break;
749 }
750
751 switch (dir) {
752 case IIO_EV_DIR_FALLING:
753 st->thresh_low[chan->channel] = val;
754 break;
755 case IIO_EV_DIR_RISING:
756 st->thresh_high[chan->channel] = val;
757 break;
758 default:
759 return -EINVAL;
760 }
761
762 return 0;
763 }
764
765 static const u64 max1363_event_codes[] = {
766 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
767 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
768 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
769 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
770 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
771 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
772 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
773 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
774 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
775 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
776 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
777 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
778 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
779 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
780 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
781 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
782 };
783
max1363_event_handler(int irq,void * private)784 static irqreturn_t max1363_event_handler(int irq, void *private)
785 {
786 struct iio_dev *indio_dev = private;
787 struct max1363_state *st = iio_priv(indio_dev);
788 s64 timestamp = iio_get_time_ns(indio_dev);
789 unsigned long mask, loc;
790 u8 rx;
791 u8 tx[2] = { st->setupbyte,
792 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
793
794 st->recv(st->client, &rx, 1);
795 mask = rx;
796 for_each_set_bit(loc, &mask, 8)
797 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
798 st->send(st->client, tx, 2);
799
800 return IRQ_HANDLED;
801 }
802
max1363_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)803 static int max1363_read_event_config(struct iio_dev *indio_dev,
804 const struct iio_chan_spec *chan, enum iio_event_type type,
805 enum iio_event_direction dir)
806 {
807 struct max1363_state *st = iio_priv(indio_dev);
808 int val;
809 int number = chan->channel;
810
811 guard(mutex)(&st->lock);
812 if (dir == IIO_EV_DIR_FALLING)
813 val = (1 << number) & st->mask_low;
814 else
815 val = (1 << number) & st->mask_high;
816
817 return val;
818 }
819
max1363_monitor_mode_update(struct max1363_state * st,int enabled)820 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
821 {
822 int ret, i = 3, j;
823 unsigned long numelements;
824 int len;
825 const long *modemask;
826
827 if (!enabled) {
828 /* transition to buffered capture is not currently supported */
829 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
830 st->configbyte &= ~MAX1363_SCAN_MASK;
831 st->monitor_on = false;
832 return max1363_write_basic_config(st);
833 }
834
835 /* Ensure we are in the relevant mode */
836 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
837 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
838 | MAX1363_SCAN_MASK
839 | MAX1363_SE_DE_MASK);
840 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
841 if ((st->mask_low | st->mask_high) & 0x0F) {
842 st->configbyte |= max1363_mode_table[s0to3].conf;
843 modemask = max1363_mode_table[s0to3].modemask;
844 } else if ((st->mask_low | st->mask_high) & 0x30) {
845 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
846 modemask = max1363_mode_table[d0m1to2m3].modemask;
847 } else {
848 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
849 modemask = max1363_mode_table[d1m0to3m2].modemask;
850 }
851 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
852 len = 3 * numelements + 3;
853 u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL);
854 if (!tx_buf)
855 return -ENOMEM;
856
857 tx_buf[0] = st->configbyte;
858 tx_buf[1] = st->setupbyte;
859 tx_buf[2] = (st->monitor_speed << 1);
860
861 /*
862 * So we need to do yet another bit of nefarious scan mode
863 * setup to match what we need.
864 */
865 for (j = 0; j < 8; j++)
866 if (test_bit(j, modemask)) {
867 /* Establish the mode is in the scan */
868 if (st->mask_low & (1 << j)) {
869 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
870 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
871 } else if (j < 4) {
872 tx_buf[i] = 0;
873 tx_buf[i + 1] = 0;
874 } else {
875 tx_buf[i] = 0x80;
876 tx_buf[i + 1] = 0;
877 }
878 if (st->mask_high & (1 << j)) {
879 tx_buf[i + 1] |=
880 (st->thresh_high[j] >> 8) & 0x0F;
881 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
882 } else if (j < 4) {
883 tx_buf[i + 1] |= 0x0F;
884 tx_buf[i + 2] = 0xFF;
885 } else {
886 tx_buf[i + 1] |= 0x07;
887 tx_buf[i + 2] = 0xFF;
888 }
889 i += 3;
890 }
891
892
893 ret = st->send(st->client, tx_buf, len);
894 if (ret < 0)
895 return ret;
896 if (ret != len)
897 return -EIO;
898
899 /*
900 * Now that we hopefully have sensible thresholds in place it is
901 * time to turn the interrupts on.
902 * It is unclear from the data sheet if this should be necessary
903 * (i.e. whether monitor mode setup is atomic) but it appears to
904 * be in practice.
905 */
906 tx_buf[0] = st->setupbyte;
907 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
908 ret = st->send(st->client, tx_buf, 2);
909 if (ret < 0)
910 return ret;
911 if (ret != 2)
912 return -EIO;
913
914 st->monitor_on = true;
915
916 return 0;
917 }
918
919 /*
920 * To keep this manageable we always use one of 3 scan modes.
921 * Scan 0...3, 0-1,2-3 and 1-0,3-2
922 */
923
__max1363_check_event_mask(int thismask,int checkmask)924 static inline int __max1363_check_event_mask(int thismask, int checkmask)
925 {
926 int ret = 0;
927 /* Is it unipolar */
928 if (thismask < 4) {
929 if (checkmask & ~0x0F) {
930 ret = -EBUSY;
931 goto error_ret;
932 }
933 } else if (thismask < 6) {
934 if (checkmask & ~0x30) {
935 ret = -EBUSY;
936 goto error_ret;
937 }
938 } else if (checkmask & ~0xC0)
939 ret = -EBUSY;
940 error_ret:
941 return ret;
942 }
943
max1363_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)944 static int max1363_write_event_config(struct iio_dev *indio_dev,
945 const struct iio_chan_spec *chan, enum iio_event_type type,
946 enum iio_event_direction dir, int state)
947 {
948 struct max1363_state *st = iio_priv(indio_dev);
949
950 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
951 int number = chan->channel;
952 u16 unifiedmask;
953 int ret;
954
955 guard(mutex)(&st->lock);
956
957 unifiedmask = st->mask_low | st->mask_high;
958 if (dir == IIO_EV_DIR_FALLING) {
959
960 if (state == 0)
961 st->mask_low &= ~(1 << number);
962 else {
963 ret = __max1363_check_event_mask((1 << number),
964 unifiedmask);
965 if (ret)
966 return ret;
967 st->mask_low |= (1 << number);
968 }
969 } else {
970 if (state == 0)
971 st->mask_high &= ~(1 << number);
972 else {
973 ret = __max1363_check_event_mask((1 << number),
974 unifiedmask);
975 if (ret)
976 return ret;
977 st->mask_high |= (1 << number);
978 }
979 }
980 }
981 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
982
983 return 0;
984 }
985
986 /*
987 * As with scan_elements, only certain sets of these can
988 * be combined.
989 */
990 static struct attribute *max1363_event_attributes[] = {
991 &iio_dev_attr_sampling_frequency.dev_attr.attr,
992 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
993 NULL,
994 };
995
996 static const struct attribute_group max1363_event_attribute_group = {
997 .attrs = max1363_event_attributes,
998 };
999
max1363_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1000 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1001 const unsigned long *scan_mask)
1002 {
1003 struct max1363_state *st = iio_priv(indio_dev);
1004
1005 /*
1006 * Need to figure out the current mode based upon the requested
1007 * scan mask in iio_dev
1008 */
1009 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1010 if (!st->current_mode)
1011 return -EINVAL;
1012 max1363_set_scan_mode(st);
1013 return 0;
1014 }
1015
1016 static const struct iio_info max1238_info = {
1017 .read_raw = &max1363_read_raw,
1018 .update_scan_mode = &max1363_update_scan_mode,
1019 };
1020
1021 static const struct iio_info max1363_info = {
1022 .read_event_value = &max1363_read_thresh,
1023 .write_event_value = &max1363_write_thresh,
1024 .read_event_config = &max1363_read_event_config,
1025 .write_event_config = &max1363_write_event_config,
1026 .read_raw = &max1363_read_raw,
1027 .update_scan_mode = &max1363_update_scan_mode,
1028 .event_attrs = &max1363_event_attribute_group,
1029 };
1030
1031 /* max1363 and max1368 tested - rest from data sheet */
1032 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1033 [max1361] = {
1034 .bits = 10,
1035 .int_vref_mv = 2048,
1036 .mode_list = max1363_mode_list,
1037 .num_modes = ARRAY_SIZE(max1363_mode_list),
1038 .default_mode = s0to3,
1039 .channels = max1361_channels,
1040 .num_channels = ARRAY_SIZE(max1361_channels),
1041 .info = &max1363_info,
1042 },
1043 [max1362] = {
1044 .bits = 10,
1045 .int_vref_mv = 4096,
1046 .mode_list = max1363_mode_list,
1047 .num_modes = ARRAY_SIZE(max1363_mode_list),
1048 .default_mode = s0to3,
1049 .channels = max1361_channels,
1050 .num_channels = ARRAY_SIZE(max1361_channels),
1051 .info = &max1363_info,
1052 },
1053 [max1363] = {
1054 .bits = 12,
1055 .int_vref_mv = 2048,
1056 .mode_list = max1363_mode_list,
1057 .num_modes = ARRAY_SIZE(max1363_mode_list),
1058 .default_mode = s0to3,
1059 .channels = max1363_channels,
1060 .num_channels = ARRAY_SIZE(max1363_channels),
1061 .info = &max1363_info,
1062 },
1063 [max1364] = {
1064 .bits = 12,
1065 .int_vref_mv = 4096,
1066 .mode_list = max1363_mode_list,
1067 .num_modes = ARRAY_SIZE(max1363_mode_list),
1068 .default_mode = s0to3,
1069 .channels = max1363_channels,
1070 .num_channels = ARRAY_SIZE(max1363_channels),
1071 .info = &max1363_info,
1072 },
1073 [max1036] = {
1074 .bits = 8,
1075 .int_vref_mv = 4096,
1076 .mode_list = max1236_mode_list,
1077 .num_modes = ARRAY_SIZE(max1236_mode_list),
1078 .default_mode = s0to3,
1079 .info = &max1238_info,
1080 .channels = max1036_channels,
1081 .num_channels = ARRAY_SIZE(max1036_channels),
1082 },
1083 [max1037] = {
1084 .bits = 8,
1085 .int_vref_mv = 2048,
1086 .mode_list = max1236_mode_list,
1087 .num_modes = ARRAY_SIZE(max1236_mode_list),
1088 .default_mode = s0to3,
1089 .info = &max1238_info,
1090 .channels = max1036_channels,
1091 .num_channels = ARRAY_SIZE(max1036_channels),
1092 },
1093 [max1038] = {
1094 .bits = 8,
1095 .int_vref_mv = 4096,
1096 .mode_list = max1238_mode_list,
1097 .num_modes = ARRAY_SIZE(max1238_mode_list),
1098 .default_mode = s0to11,
1099 .info = &max1238_info,
1100 .channels = max1038_channels,
1101 .num_channels = ARRAY_SIZE(max1038_channels),
1102 },
1103 [max1039] = {
1104 .bits = 8,
1105 .int_vref_mv = 2048,
1106 .mode_list = max1238_mode_list,
1107 .num_modes = ARRAY_SIZE(max1238_mode_list),
1108 .default_mode = s0to11,
1109 .info = &max1238_info,
1110 .channels = max1038_channels,
1111 .num_channels = ARRAY_SIZE(max1038_channels),
1112 },
1113 [max1136] = {
1114 .bits = 10,
1115 .int_vref_mv = 4096,
1116 .mode_list = max1236_mode_list,
1117 .num_modes = ARRAY_SIZE(max1236_mode_list),
1118 .default_mode = s0to3,
1119 .info = &max1238_info,
1120 .channels = max1136_channels,
1121 .num_channels = ARRAY_SIZE(max1136_channels),
1122 },
1123 [max1137] = {
1124 .bits = 10,
1125 .int_vref_mv = 2048,
1126 .mode_list = max1236_mode_list,
1127 .num_modes = ARRAY_SIZE(max1236_mode_list),
1128 .default_mode = s0to3,
1129 .info = &max1238_info,
1130 .channels = max1136_channels,
1131 .num_channels = ARRAY_SIZE(max1136_channels),
1132 },
1133 [max1138] = {
1134 .bits = 10,
1135 .int_vref_mv = 4096,
1136 .mode_list = max1238_mode_list,
1137 .num_modes = ARRAY_SIZE(max1238_mode_list),
1138 .default_mode = s0to11,
1139 .info = &max1238_info,
1140 .channels = max1138_channels,
1141 .num_channels = ARRAY_SIZE(max1138_channels),
1142 },
1143 [max1139] = {
1144 .bits = 10,
1145 .int_vref_mv = 2048,
1146 .mode_list = max1238_mode_list,
1147 .num_modes = ARRAY_SIZE(max1238_mode_list),
1148 .default_mode = s0to11,
1149 .info = &max1238_info,
1150 .channels = max1138_channels,
1151 .num_channels = ARRAY_SIZE(max1138_channels),
1152 },
1153 [max1236] = {
1154 .bits = 12,
1155 .int_vref_mv = 4096,
1156 .mode_list = max1236_mode_list,
1157 .num_modes = ARRAY_SIZE(max1236_mode_list),
1158 .default_mode = s0to3,
1159 .info = &max1238_info,
1160 .channels = max1236_channels,
1161 .num_channels = ARRAY_SIZE(max1236_channels),
1162 },
1163 [max1237] = {
1164 .bits = 12,
1165 .int_vref_mv = 2048,
1166 .mode_list = max1236_mode_list,
1167 .num_modes = ARRAY_SIZE(max1236_mode_list),
1168 .default_mode = s0to3,
1169 .info = &max1238_info,
1170 .channels = max1236_channels,
1171 .num_channels = ARRAY_SIZE(max1236_channels),
1172 },
1173 [max1238] = {
1174 .bits = 12,
1175 .int_vref_mv = 4096,
1176 .mode_list = max1238_mode_list,
1177 .num_modes = ARRAY_SIZE(max1238_mode_list),
1178 .default_mode = s0to11,
1179 .info = &max1238_info,
1180 .channels = max1238_channels,
1181 .num_channels = ARRAY_SIZE(max1238_channels),
1182 },
1183 [max1239] = {
1184 .bits = 12,
1185 .int_vref_mv = 2048,
1186 .mode_list = max1238_mode_list,
1187 .num_modes = ARRAY_SIZE(max1238_mode_list),
1188 .default_mode = s0to11,
1189 .info = &max1238_info,
1190 .channels = max1238_channels,
1191 .num_channels = ARRAY_SIZE(max1238_channels),
1192 },
1193 [max11600] = {
1194 .bits = 8,
1195 .int_vref_mv = 4096,
1196 .mode_list = max11607_mode_list,
1197 .num_modes = ARRAY_SIZE(max11607_mode_list),
1198 .default_mode = s0to3,
1199 .info = &max1238_info,
1200 .channels = max1036_channels,
1201 .num_channels = ARRAY_SIZE(max1036_channels),
1202 },
1203 [max11601] = {
1204 .bits = 8,
1205 .int_vref_mv = 2048,
1206 .mode_list = max11607_mode_list,
1207 .num_modes = ARRAY_SIZE(max11607_mode_list),
1208 .default_mode = s0to3,
1209 .info = &max1238_info,
1210 .channels = max1036_channels,
1211 .num_channels = ARRAY_SIZE(max1036_channels),
1212 },
1213 [max11602] = {
1214 .bits = 8,
1215 .int_vref_mv = 4096,
1216 .mode_list = max11608_mode_list,
1217 .num_modes = ARRAY_SIZE(max11608_mode_list),
1218 .default_mode = s0to7,
1219 .info = &max1238_info,
1220 .channels = max11602_channels,
1221 .num_channels = ARRAY_SIZE(max11602_channels),
1222 },
1223 [max11603] = {
1224 .bits = 8,
1225 .int_vref_mv = 2048,
1226 .mode_list = max11608_mode_list,
1227 .num_modes = ARRAY_SIZE(max11608_mode_list),
1228 .default_mode = s0to7,
1229 .info = &max1238_info,
1230 .channels = max11602_channels,
1231 .num_channels = ARRAY_SIZE(max11602_channels),
1232 },
1233 [max11604] = {
1234 .bits = 8,
1235 .int_vref_mv = 4096,
1236 .mode_list = max1238_mode_list,
1237 .num_modes = ARRAY_SIZE(max1238_mode_list),
1238 .default_mode = s0to11,
1239 .info = &max1238_info,
1240 .channels = max1038_channels,
1241 .num_channels = ARRAY_SIZE(max1038_channels),
1242 },
1243 [max11605] = {
1244 .bits = 8,
1245 .int_vref_mv = 2048,
1246 .mode_list = max1238_mode_list,
1247 .num_modes = ARRAY_SIZE(max1238_mode_list),
1248 .default_mode = s0to11,
1249 .info = &max1238_info,
1250 .channels = max1038_channels,
1251 .num_channels = ARRAY_SIZE(max1038_channels),
1252 },
1253 [max11606] = {
1254 .bits = 10,
1255 .int_vref_mv = 4096,
1256 .mode_list = max11607_mode_list,
1257 .num_modes = ARRAY_SIZE(max11607_mode_list),
1258 .default_mode = s0to3,
1259 .info = &max1238_info,
1260 .channels = max1136_channels,
1261 .num_channels = ARRAY_SIZE(max1136_channels),
1262 },
1263 [max11607] = {
1264 .bits = 10,
1265 .int_vref_mv = 2048,
1266 .mode_list = max11607_mode_list,
1267 .num_modes = ARRAY_SIZE(max11607_mode_list),
1268 .default_mode = s0to3,
1269 .info = &max1238_info,
1270 .channels = max1136_channels,
1271 .num_channels = ARRAY_SIZE(max1136_channels),
1272 },
1273 [max11608] = {
1274 .bits = 10,
1275 .int_vref_mv = 4096,
1276 .mode_list = max11608_mode_list,
1277 .num_modes = ARRAY_SIZE(max11608_mode_list),
1278 .default_mode = s0to7,
1279 .info = &max1238_info,
1280 .channels = max11608_channels,
1281 .num_channels = ARRAY_SIZE(max11608_channels),
1282 },
1283 [max11609] = {
1284 .bits = 10,
1285 .int_vref_mv = 2048,
1286 .mode_list = max11608_mode_list,
1287 .num_modes = ARRAY_SIZE(max11608_mode_list),
1288 .default_mode = s0to7,
1289 .info = &max1238_info,
1290 .channels = max11608_channels,
1291 .num_channels = ARRAY_SIZE(max11608_channels),
1292 },
1293 [max11610] = {
1294 .bits = 10,
1295 .int_vref_mv = 4096,
1296 .mode_list = max1238_mode_list,
1297 .num_modes = ARRAY_SIZE(max1238_mode_list),
1298 .default_mode = s0to11,
1299 .info = &max1238_info,
1300 .channels = max1138_channels,
1301 .num_channels = ARRAY_SIZE(max1138_channels),
1302 },
1303 [max11611] = {
1304 .bits = 10,
1305 .int_vref_mv = 2048,
1306 .mode_list = max1238_mode_list,
1307 .num_modes = ARRAY_SIZE(max1238_mode_list),
1308 .default_mode = s0to11,
1309 .info = &max1238_info,
1310 .channels = max1138_channels,
1311 .num_channels = ARRAY_SIZE(max1138_channels),
1312 },
1313 [max11612] = {
1314 .bits = 12,
1315 .int_vref_mv = 4096,
1316 .mode_list = max11607_mode_list,
1317 .num_modes = ARRAY_SIZE(max11607_mode_list),
1318 .default_mode = s0to3,
1319 .info = &max1238_info,
1320 .channels = max1363_channels,
1321 .num_channels = ARRAY_SIZE(max1363_channels),
1322 },
1323 [max11613] = {
1324 .bits = 12,
1325 .int_vref_mv = 2048,
1326 .mode_list = max11607_mode_list,
1327 .num_modes = ARRAY_SIZE(max11607_mode_list),
1328 .default_mode = s0to3,
1329 .info = &max1238_info,
1330 .channels = max1363_channels,
1331 .num_channels = ARRAY_SIZE(max1363_channels),
1332 },
1333 [max11614] = {
1334 .bits = 12,
1335 .int_vref_mv = 4096,
1336 .mode_list = max11608_mode_list,
1337 .num_modes = ARRAY_SIZE(max11608_mode_list),
1338 .default_mode = s0to7,
1339 .info = &max1238_info,
1340 .channels = max11614_channels,
1341 .num_channels = ARRAY_SIZE(max11614_channels),
1342 },
1343 [max11615] = {
1344 .bits = 12,
1345 .int_vref_mv = 2048,
1346 .mode_list = max11608_mode_list,
1347 .num_modes = ARRAY_SIZE(max11608_mode_list),
1348 .default_mode = s0to7,
1349 .info = &max1238_info,
1350 .channels = max11614_channels,
1351 .num_channels = ARRAY_SIZE(max11614_channels),
1352 },
1353 [max11616] = {
1354 .bits = 12,
1355 .int_vref_mv = 4096,
1356 .mode_list = max1238_mode_list,
1357 .num_modes = ARRAY_SIZE(max1238_mode_list),
1358 .default_mode = s0to11,
1359 .info = &max1238_info,
1360 .channels = max1238_channels,
1361 .num_channels = ARRAY_SIZE(max1238_channels),
1362 },
1363 [max11617] = {
1364 .bits = 12,
1365 .int_vref_mv = 2048,
1366 .mode_list = max1238_mode_list,
1367 .num_modes = ARRAY_SIZE(max1238_mode_list),
1368 .default_mode = s0to11,
1369 .info = &max1238_info,
1370 .channels = max1238_channels,
1371 .num_channels = ARRAY_SIZE(max1238_channels),
1372 },
1373 [max11644] = {
1374 .bits = 12,
1375 .int_vref_mv = 4096,
1376 .mode_list = max11644_mode_list,
1377 .num_modes = ARRAY_SIZE(max11644_mode_list),
1378 .default_mode = s0to1,
1379 .info = &max1238_info,
1380 .channels = max11644_channels,
1381 .num_channels = ARRAY_SIZE(max11644_channels),
1382 },
1383 [max11645] = {
1384 .bits = 12,
1385 .int_vref_mv = 2048,
1386 .mode_list = max11644_mode_list,
1387 .num_modes = ARRAY_SIZE(max11644_mode_list),
1388 .default_mode = s0to1,
1389 .info = &max1238_info,
1390 .channels = max11644_channels,
1391 .num_channels = ARRAY_SIZE(max11644_channels),
1392 },
1393 [max11646] = {
1394 .bits = 10,
1395 .int_vref_mv = 4096,
1396 .mode_list = max11644_mode_list,
1397 .num_modes = ARRAY_SIZE(max11644_mode_list),
1398 .default_mode = s0to1,
1399 .info = &max1238_info,
1400 .channels = max11646_channels,
1401 .num_channels = ARRAY_SIZE(max11646_channels),
1402 },
1403 [max11647] = {
1404 .bits = 10,
1405 .int_vref_mv = 2048,
1406 .mode_list = max11644_mode_list,
1407 .num_modes = ARRAY_SIZE(max11644_mode_list),
1408 .default_mode = s0to1,
1409 .info = &max1238_info,
1410 .channels = max11646_channels,
1411 .num_channels = ARRAY_SIZE(max11646_channels),
1412 },
1413 };
1414
max1363_initial_setup(struct max1363_state * st)1415 static int max1363_initial_setup(struct max1363_state *st)
1416 {
1417 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1418 | MAX1363_SETUP_UNIPOLAR
1419 | MAX1363_SETUP_NORESET;
1420
1421 if (st->vref)
1422 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1423 else
1424 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1425 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1426
1427 /* Set scan mode writes the config anyway so wait until then */
1428 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1429 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1430 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1431
1432 return max1363_set_scan_mode(st);
1433 }
1434
max1363_alloc_scan_masks(struct iio_dev * indio_dev)1435 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1436 {
1437 struct max1363_state *st = iio_priv(indio_dev);
1438 unsigned long *masks;
1439 int i;
1440
1441 masks = devm_kzalloc(&indio_dev->dev,
1442 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1443 sizeof(long),
1444 st->chip_info->num_modes + 1),
1445 GFP_KERNEL);
1446 if (!masks)
1447 return -ENOMEM;
1448
1449 for (i = 0; i < st->chip_info->num_modes; i++)
1450 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1451 max1363_mode_table[st->chip_info->mode_list[i]]
1452 .modemask, MAX1363_MAX_CHANNELS);
1453
1454 indio_dev->available_scan_masks = masks;
1455
1456 return 0;
1457 }
1458
max1363_trigger_handler(int irq,void * p)1459 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1460 {
1461 struct iio_poll_func *pf = p;
1462 struct iio_dev *indio_dev = pf->indio_dev;
1463 struct max1363_state *st = iio_priv(indio_dev);
1464 __u8 *rxbuf;
1465 int b_sent;
1466 size_t d_size;
1467 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1468 MAX1363_MAX_CHANNELS);
1469
1470 /* Ensure the timestamp is 8 byte aligned */
1471 if (st->chip_info->bits != 8)
1472 d_size = numvals*2;
1473 else
1474 d_size = numvals;
1475 if (indio_dev->scan_timestamp) {
1476 d_size += sizeof(s64);
1477 if (d_size % sizeof(s64))
1478 d_size += sizeof(s64) - (d_size % sizeof(s64));
1479 }
1480 /* Monitor mode prevents reading. Whilst not currently implemented
1481 * might as well have this test in here in the meantime as it does
1482 * no harm.
1483 */
1484 if (numvals == 0)
1485 goto done;
1486
1487 rxbuf = kmalloc(d_size, GFP_KERNEL);
1488 if (rxbuf == NULL)
1489 goto done;
1490 if (st->chip_info->bits != 8)
1491 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1492 else
1493 b_sent = st->recv(st->client, rxbuf, numvals);
1494 if (b_sent < 0)
1495 goto done_free;
1496
1497 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1498 iio_get_time_ns(indio_dev));
1499
1500 done_free:
1501 kfree(rxbuf);
1502 done:
1503 iio_trigger_notify_done(indio_dev->trig);
1504
1505 return IRQ_HANDLED;
1506 }
1507
1508 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1509 .compatible = of_compatible, \
1510 .data = &max1363_chip_info_tbl[cfg], \
1511 }
1512
1513 static const struct of_device_id max1363_of_match[] = {
1514 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1515 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1516 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1517 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1518 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1519 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1520 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1521 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1522 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1523 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1524 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1525 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1526 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1527 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1528 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1529 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1530 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1531 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1532 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1533 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1534 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1535 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1536 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1537 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1538 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1539 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1540 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1541 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1542 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1543 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1544 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1545 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1546 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1547 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1548 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1549 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1550 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1551 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1552 { /* sentinel */ }
1553 };
1554 MODULE_DEVICE_TABLE(of, max1363_of_match);
1555
max1363_probe(struct i2c_client * client)1556 static int max1363_probe(struct i2c_client *client)
1557 {
1558 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1559 int ret;
1560 struct max1363_state *st;
1561 struct iio_dev *indio_dev;
1562
1563 indio_dev = devm_iio_device_alloc(&client->dev,
1564 sizeof(struct max1363_state));
1565 if (!indio_dev)
1566 return -ENOMEM;
1567
1568 st = iio_priv(indio_dev);
1569
1570 mutex_init(&st->lock);
1571 ret = devm_regulator_get_enable(&client->dev, "vcc");
1572 if (ret)
1573 return ret;
1574
1575 st->chip_info = i2c_get_match_data(client);
1576 st->client = client;
1577
1578 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref");
1579 if (ret < 0 && ret != -ENODEV)
1580 return ret;
1581
1582
1583 st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret;
1584
1585 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1586 st->send = i2c_master_send;
1587 st->recv = i2c_master_recv;
1588 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1589 && st->chip_info->bits == 8) {
1590 st->send = max1363_smbus_send;
1591 st->recv = max1363_smbus_recv;
1592 } else {
1593 return -EOPNOTSUPP;
1594 }
1595
1596 ret = max1363_alloc_scan_masks(indio_dev);
1597 if (ret)
1598 return ret;
1599
1600 indio_dev->name = id->name;
1601 indio_dev->channels = st->chip_info->channels;
1602 indio_dev->num_channels = st->chip_info->num_channels;
1603 indio_dev->info = st->chip_info->info;
1604 indio_dev->modes = INDIO_DIRECT_MODE;
1605 ret = max1363_initial_setup(st);
1606 if (ret < 0)
1607 return ret;
1608
1609 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1610 &max1363_trigger_handler, NULL);
1611 if (ret)
1612 return ret;
1613
1614 if (client->irq) {
1615 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1616 NULL,
1617 &max1363_event_handler,
1618 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1619 "max1363_event",
1620 indio_dev);
1621
1622 if (ret)
1623 return ret;
1624 }
1625
1626 return devm_iio_device_register(&client->dev, indio_dev);
1627 }
1628
1629 #define MAX1363_ID_TABLE(_name, cfg) { \
1630 .name = _name, \
1631 .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \
1632 }
1633
1634 static const struct i2c_device_id max1363_id[] = {
1635 MAX1363_ID_TABLE("max1361", max1361),
1636 MAX1363_ID_TABLE("max1362", max1362),
1637 MAX1363_ID_TABLE("max1363", max1363),
1638 MAX1363_ID_TABLE("max1364", max1364),
1639 MAX1363_ID_TABLE("max1036", max1036),
1640 MAX1363_ID_TABLE("max1037", max1037),
1641 MAX1363_ID_TABLE("max1038", max1038),
1642 MAX1363_ID_TABLE("max1039", max1039),
1643 MAX1363_ID_TABLE("max1136", max1136),
1644 MAX1363_ID_TABLE("max1137", max1137),
1645 MAX1363_ID_TABLE("max1138", max1138),
1646 MAX1363_ID_TABLE("max1139", max1139),
1647 MAX1363_ID_TABLE("max1236", max1236),
1648 MAX1363_ID_TABLE("max1237", max1237),
1649 MAX1363_ID_TABLE("max1238", max1238),
1650 MAX1363_ID_TABLE("max1239", max1239),
1651 MAX1363_ID_TABLE("max11600", max11600),
1652 MAX1363_ID_TABLE("max11601", max11601),
1653 MAX1363_ID_TABLE("max11602", max11602),
1654 MAX1363_ID_TABLE("max11603", max11603),
1655 MAX1363_ID_TABLE("max11604", max11604),
1656 MAX1363_ID_TABLE("max11605", max11605),
1657 MAX1363_ID_TABLE("max11606", max11606),
1658 MAX1363_ID_TABLE("max11607", max11607),
1659 MAX1363_ID_TABLE("max11608", max11608),
1660 MAX1363_ID_TABLE("max11609", max11609),
1661 MAX1363_ID_TABLE("max11610", max11610),
1662 MAX1363_ID_TABLE("max11611", max11611),
1663 MAX1363_ID_TABLE("max11612", max11612),
1664 MAX1363_ID_TABLE("max11613", max11613),
1665 MAX1363_ID_TABLE("max11614", max11614),
1666 MAX1363_ID_TABLE("max11615", max11615),
1667 MAX1363_ID_TABLE("max11616", max11616),
1668 MAX1363_ID_TABLE("max11617", max11617),
1669 MAX1363_ID_TABLE("max11644", max11644),
1670 MAX1363_ID_TABLE("max11645", max11645),
1671 MAX1363_ID_TABLE("max11646", max11646),
1672 MAX1363_ID_TABLE("max11647", max11647),
1673 { /* sentinel */ }
1674 };
1675
1676 MODULE_DEVICE_TABLE(i2c, max1363_id);
1677
1678 static struct i2c_driver max1363_driver = {
1679 .driver = {
1680 .name = "max1363",
1681 .of_match_table = max1363_of_match,
1682 },
1683 .probe = max1363_probe,
1684 .id_table = max1363_id,
1685 };
1686 module_i2c_driver(max1363_driver);
1687
1688 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1689 MODULE_DESCRIPTION("Maxim 1363 ADC");
1690 MODULE_LICENSE("GPL v2");
1691