| /linux/include/linux/soc/ti/ |
| H A D | knav_dma.h | 17 #define MASK(x) (BIT(x) - 1) macro
18 #define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22)
22 #define KNAV_DMA_DESC_TAG_MASK MASK(8)
30 #define KNAV_DMA_DESC_PSLEN_MASK MASK(6)
32 #define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4)
34 #define KNAV_DMA_DESC_PSFLAG_MASK MASK(4)
36 #define KNAV_DMA_DESC_RETQ_MASK MASK(14)
37 #define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22)
38 #define KNAV_DMA_DESC_EFLAGS_MASK MASK(4)
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| /linux/sound/soc/codecs/ |
| H A D | ak4613.c | 425 #define MASK(x) (1 << AK4613_CHANNEL_##x) in ak4613_hw_constraints() macro
428 [AK4613_CONFIG_MODE_STEREO] = { MASK(2), MASK(2), MASK(2), MASK(2)}, in ak4613_hw_constraints()
429 [AK4613_CONFIG_MODE_TDM512] = { MASK(4), MASK(12), MASK(12), MASK(12)}, in ak4613_hw_constraints()
430 [AK4613_CONFIG_MODE_TDM256] = { MASK(4), MASK(8), MASK(8)|MASK(12), MASK(8)|MASK(12)}, in ak4613_hw_constraints()
431 [AK4613_CONFIG_MODE_TDM128] = { MASK(4), MASK(4), MASK(4)|MASK(8), MASK(4)|MASK(8)|MASK(12)}, in ak4613_hw_constraints()
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| /linux/arch/x86/kernel/cpu/mce/ |
| H A D | severity.c | 66 #define MASK(x, y) .mask = x, .result = y macro
115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
173 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gk20a.h | 30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
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| H A D | gm20b.c | 41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
57 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_pllg_read_mnp()
201 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH)); in gm20b_dvfs_calc_det_coeff()
254 rem = ((u32)n) & MASK(DFS_DET_RANGE); in gm20b_dvfs_calc_ndiv()
259 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); in gm20b_dvfs_calc_ndiv()
536 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1), in gm20b_dvfs_program_ext_cal()
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); in gm20b_clk_init_dvfs()
[all …]
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| /linux/arch/x86/crypto/ |
| H A D | poly1305-x86_64-cryptogams.pl | 419 my ($H0,$H1,$H2,$H3,$H4, $T0,$T1,$T2,$T3,$T4, $D0,$D1,$D2,$D3,$D4, $MASK) =
888 vmovdqa 64(%rcx),$MASK # .Lmask26
898 vpand $MASK,$T0,$T0 # 0
900 vpand $MASK,$T1,$T1 # 1
902 vpand $MASK,$T2,$T2 # 2
903 vpand $MASK,$T3,$T3 # 3
1052 vpand $MASK,$H0,$H0 # 0
1054 vpand $MASK,$H1,$H1 # 1
1057 vpand $MASK,$H2,$H2 # 2
1058 vpand $MASK,$H3,$H3 # 3
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_gpio.c | 45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
164 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
168 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
172 REG_UPDATE(MASK_reg, MASK, 0); in dal_hw_gpio_config_mode()
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| /linux/arch/arm/mach-rpc/ |
| H A D | irq.c | 15 #define MASK 0x08 macro
130 val = readb(base + MASK); in iomd_irq_mask_ack()
131 writeb(val & ~mask, base + MASK); in iomd_irq_mask_ack()
140 val = readb(base + MASK); in iomd_irq_mask()
141 writeb(val & ~mask, base + MASK); in iomd_irq_mask()
149 val = readb(base + MASK); in iomd_irq_unmask()
150 writeb(val | mask, base + MASK); in iomd_irq_unmask()
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| /linux/drivers/scsi/sym53c8xx_2/ |
| H A D | sym_fw2.h | 228 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
316 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
348 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
438 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
462 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
521 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
681 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
898 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
904 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1073 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| H A D | sym_fw1.h | 236 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
363 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
453 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
478 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
538 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
704 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
949 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
955 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1187 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1207 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
[all …]
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| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | test_pkt_md_access.c | 11 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
14 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
19 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
23 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
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| /linux/tools/testing/selftests/kvm/include/aarch64/ |
| H A D | gic_v3.h | |
| /linux/include/linux/irqchip/ |
| H A D | arm-gic-v3.h | 181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
183 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
210 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
277 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
279 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
315 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
317 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
419 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
421 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
[all …]
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| /linux/arch/arm/crypto/ |
| H A D | poly1305-armv4.pl | 497 my ($T0,$T1,$MASK) = map("q$_",(15,4,0));
1101 vorn $MASK,$MASK,$MASK @ all-ones, can be redundant
1103 vshr.u64 $MASK,$MASK,#38
1145 vorn $MASK,$MASK,$MASK @ all-ones
1147 vshr.u64 $MASK,$MASK,#38
1166 vand.i64 $D3,$D3,$MASK
1168 vand.i64 $D0,$D0,$MASK
1173 vand.i64 $D4,$D4,$MASK
1175 vand.i64 $D1,$D1,$MASK
1181 vand.i64 $D2,$D2,$MASK
[all …]
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| H A D | ghash-ce-core.S | 59 MASK .req d28
163 vmull.p64 T1, XL_L, MASK
170 vmull.p64 XL, T1_H, MASK
229 vmov.i8 MASK, #0xe1
230 vshl.u64 MASK, MASK, #57
298 vmov.i8 MASK, #0xe1
299 vshl.u64 MASK, MASK, #57
341 vmov.i8 MASK, #0xe1
342 vshl.u64 MASK, MASK, #57
601 vmov.i8 MASK, #0xe1
[all …]
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| /linux/arch/arm64/crypto/ |
| H A D | poly1305-armv8.pl | 267 my ($T0,$T1,$MASK) = map("v$_",(29..31));
543 movi $MASK.2d,#-1
547 ushr $MASK.2d,$MASK.2d,#38
709 and $ACC0,$ACC0,$MASK.2d
849 and $ACC3,$ACC3,$MASK.2d
851 and $ACC0,$ACC0,$MASK.2d
857 and $ACC4,$ACC4,$MASK.2d
859 and $ACC1,$ACC1,$MASK.2d
865 and $ACC2,$ACC2,$MASK.2d
870 and $ACC0,$ACC0,$MASK.2d
[all …]
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| /linux/drivers/gpu/drm/hisilicon/kirin/ |
| H A D | kirin_ade_reg.h | 13 #define MASK(x) (BIT_ULL(x) - 1) macro
17 #define FRM_END_START_MASK MASK(2)
50 #define CH_OVLY_SEL_MASK MASK(2)
99 #define QOSGENERATOR_MODE_MASK MASK(2)
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| /linux/lib/raid6/ |
| H A D | s390vx.uc | 33 * For each of the 16 bytes in the vector register y the MASK()
38 #define MASK(x, y) fpu_vesravb(x, y, 24)
64 MASK(16+$$,8+$$);
98 MASK(16+$$,8+$$);
108 MASK(16+$$,8+$$);
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| H A D | int.uc | 62 * The MASK() operation returns 0xFF in any byte for which the high
65 static inline __attribute_const__ unative_t MASK(unative_t v)
92 w2$$ = MASK(wq$$);
122 w2$$ = MASK(wq$$);
130 w2$$ = MASK(wq$$);
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| H A D | neon.uc | 44 * The MASK() operation returns 0xFF in any byte for which the high
47 static inline unative_t MASK(unative_t v)
75 w2$$ = MASK(wq$$);
109 w2$$ = MASK(wq$$);
141 w2$$ = MASK(wq$$);
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| /linux/drivers/dma/dw/ |
| H A D | core.c | 122 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
123 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
488 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
489 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
512 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
513 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in dw_dma_interrupt()
514 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_interrupt()
523 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
524 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
525 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
[all …]
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | 130 #define MASK(x) (BIT(x) - 1) macro
135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
161 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
175 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
182 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
189 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
[all …]
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| /linux/net/openvswitch/ |
| H A D | datapath.h | 280 #define OVS_MASKED(OLD, KEY, MASK) ((KEY) | ((OLD) & ~(MASK))) argument
281 #define OVS_SET_MASKED(OLD, KEY, MASK) ((OLD) = OVS_MASKED(OLD, KEY, MASK)) argument
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| /linux/drivers/scsi/ |
| H A D | vmw_pvscsi.h | 31 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
410 #define PVSCSI_INTR_CMPL_MASK MASK(2)
414 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
416 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
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| /linux/tools/testing/selftests/ftrace/test.d/ftrace/ |
| H A D | func_cpumask.tc | 29 MASK=0x`cat tracing_cpumask`
30 test `printf "%d" $MASK` -eq 2 || do_reset
|