1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TC358775 DSI to LVDS bridge driver
4 *
5 * Copyright (C) 2020 SMART Wireless Computing
6 * Author: Vinay Simha BN <simhavcs@gmail.com>
7 *
8 */
9 /* #define DEBUG */
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/kernel.h>
16 #include <linux/media-bus-format.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21
22 #include <linux/unaligned.h>
23
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_bridge.h>
27 #include <drm/drm_mipi_dsi.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_panel.h>
30 #include <drm/drm_probe_helper.h>
31
32 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
33
34 /* Registers */
35
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
45 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
46 #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
47 #define D2W_CNTRL 0x004C /* Data Lane 2 Control */
48 #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
49 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
50
51 /* DSI PPI Layer Registers */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
53 #define PPI_START_FUNCTION 1
54
55 #define PPI_BUSYPPI 0x0108
56 #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
57 #define PPI_LPTXTIMECNT 0x0114
58 #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
59 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
60
61 /* Analog timer function enable */
62 #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
63 #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
64 #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
65 #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
66 #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
67
68 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
69 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
70 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
71 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
72
73 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
74 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
75 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
76 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
77 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
78 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
79 #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
80 #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
81 #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
82 #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
83 #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
84 #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
85 #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
86 #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
87 #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
88
89 #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
90 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
91 #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
92 #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
94 #define DSI_RX_START 1
95
96 #define DSI_BUSYDSI 0x0208
97 #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
98 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
99 #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
100
101 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */
102 #define DSI_INTMASK 0x0224 /* Interrupt Mask */
103 #define DSI_INTCLR 0x0228 /* Interrupt Clear */
104 #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
105
106 #define DSIERRCNT 0x0300 /* DSI Error Count */
107 #define APLCTRL 0x0400 /* Application Layer Control */
108 #define RDPKTLN 0x0404 /* Command Read Packet Length */
109
110 #define VPCTRL 0x0450 /* Video Path Control */
111 #define EVTMODE BIT(5) /* Video event mode enable, tc35876x only */
112 #define HTIM1 0x0454 /* Horizontal Timing Control 1 */
113 #define HTIM2 0x0458 /* Horizontal Timing Control 2 */
114 #define VTIM1 0x045C /* Vertical Timing Control 1 */
115 #define VTIM2 0x0460 /* Vertical Timing Control 2 */
116 #define VFUEN 0x0464 /* Video Frame Timing Update Enable */
117 #define VFUEN_EN BIT(0) /* Upload Enable */
118
119 /* Mux Input Select for LVDS LINK Input */
120 #define LV_MX0003 0x0480 /* Bit 0 to 3 */
121 #define LV_MX0407 0x0484 /* Bit 4 to 7 */
122 #define LV_MX0811 0x0488 /* Bit 8 to 11 */
123 #define LV_MX1215 0x048C /* Bit 12 to 15 */
124 #define LV_MX1619 0x0490 /* Bit 16 to 19 */
125 #define LV_MX2023 0x0494 /* Bit 20 to 23 */
126 #define LV_MX2427 0x0498 /* Bit 24 to 27 */
127 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
128 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
129
130 /* Input bit numbers used in mux registers */
131 enum {
132 LVI_R0,
133 LVI_R1,
134 LVI_R2,
135 LVI_R3,
136 LVI_R4,
137 LVI_R5,
138 LVI_R6,
139 LVI_R7,
140 LVI_G0,
141 LVI_G1,
142 LVI_G2,
143 LVI_G3,
144 LVI_G4,
145 LVI_G5,
146 LVI_G6,
147 LVI_G7,
148 LVI_B0,
149 LVI_B1,
150 LVI_B2,
151 LVI_B3,
152 LVI_B4,
153 LVI_B5,
154 LVI_B6,
155 LVI_B7,
156 LVI_HS,
157 LVI_VS,
158 LVI_DE,
159 LVI_L0
160 };
161
162 #define LVCFG 0x049C /* LVDS Configuration */
163 #define LVPHY0 0x04A0 /* LVDS PHY 0 */
164 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
165 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
166 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
167 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
168
169 #define LVPHY1 0x04A4 /* LVDS PHY 1 */
170 #define SYSSTAT 0x0500 /* System Status */
171 #define SYSRST 0x0504 /* System Reset */
172
173 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
174 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
175 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
176 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
177 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
178 #define SYS_RST_REG BIT(5) /* Reset Register module */
179
180 /* GPIO Registers */
181 #define GPIOC 0x0520 /* GPIO Control */
182 #define GPIOO 0x0524 /* GPIO Output */
183 #define GPIOI 0x0528 /* GPIO Input */
184
185 /* I2C Registers */
186 #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
187 #define I2CMADDR 0x0544 /* I2C Master Addressing */
188 #define WDATAQ 0x0548 /* Write Data Queue */
189 #define RDATAQ 0x054C /* Read Data Queue */
190
191 /* Chip ID and Revision ID Register */
192 #define IDREG 0x0580
193
194 #define LPX_PERIOD 4
195 #define TTA_GET 0x40000
196 #define TTA_SURE 6
197 #define SINGLE_LINK 1
198 #define DUAL_LINK 2
199
200 #define TC358775XBG_ID 0x00007500
201
202 /* Debug Registers */
203 #define DEBUG00 0x05A0 /* Debug */
204 #define DEBUG01 0x05A4 /* LVDS Data */
205
206 #define DSI_CLEN_BIT BIT(0)
207 #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
208 #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
209 #define LVCFG_LVEN_BIT BIT(0)
210
211 #define L0EN BIT(1)
212
213 #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000
214 #define TC358775_VPCTRL_VSDELAY__SHIFT 20
TC358775_VPCTRL_VSDELAY(uint32_t val)215 static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
216 {
217 return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
218 TC358775_VPCTRL_VSDELAY__MASK;
219 }
220
221 #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100
222 #define TC358775_VPCTRL_OPXLFMT__SHIFT 8
TC358775_VPCTRL_OPXLFMT(uint32_t val)223 static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
224 {
225 return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
226 TC358775_VPCTRL_OPXLFMT__MASK;
227 }
228
229 #define TC358775_VPCTRL_MSF__MASK 0x00000001
230 #define TC358775_VPCTRL_MSF__SHIFT 0
TC358775_VPCTRL_MSF(uint32_t val)231 static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
232 {
233 return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
234 TC358775_VPCTRL_MSF__MASK;
235 }
236
237 #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
238 #define TC358775_LVCFG_PCLKDIV__SHIFT 4
TC358775_LVCFG_PCLKDIV(uint32_t val)239 static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
240 {
241 return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
242 TC358775_LVCFG_PCLKDIV__MASK;
243 }
244
245 #define TC358775_LVCFG_LVDLINK__MASK 0x00000002
246 #define TC358775_LVCFG_LVDLINK__SHIFT 1
TC358775_LVCFG_LVDLINK(uint32_t val)247 static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
248 {
249 return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
250 TC358775_LVCFG_LVDLINK__MASK;
251 }
252
253 enum tc358775_ports {
254 TC358775_DSI_IN,
255 TC358775_LVDS_OUT0,
256 TC358775_LVDS_OUT1,
257 };
258
259 enum tc3587x5_type {
260 TC358765 = 0x65,
261 TC358775 = 0x75,
262 };
263
264 struct tc_data {
265 struct i2c_client *i2c;
266 struct device *dev;
267
268 struct drm_bridge bridge;
269 struct drm_bridge *panel_bridge;
270
271 struct device_node *host_node;
272 struct mipi_dsi_device *dsi;
273 u8 num_dsi_lanes;
274
275 struct regulator *vdd;
276 struct regulator *vddio;
277 struct gpio_desc *reset_gpio;
278 struct gpio_desc *stby_gpio;
279 u8 lvds_link; /* single-link or dual-link */
280 u8 bpc;
281
282 enum tc3587x5_type type;
283 };
284
bridge_to_tc(struct drm_bridge * b)285 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
286 {
287 return container_of(b, struct tc_data, bridge);
288 }
289
tc_bridge_pre_enable(struct drm_bridge * bridge)290 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
291 {
292 struct tc_data *tc = bridge_to_tc(bridge);
293 struct device *dev = &tc->dsi->dev;
294 int ret;
295
296 ret = regulator_enable(tc->vddio);
297 if (ret < 0)
298 dev_err(dev, "regulator vddio enable failed, %d\n", ret);
299 usleep_range(10000, 11000);
300
301 ret = regulator_enable(tc->vdd);
302 if (ret < 0)
303 dev_err(dev, "regulator vdd enable failed, %d\n", ret);
304 usleep_range(10000, 11000);
305
306 gpiod_set_value(tc->stby_gpio, 0);
307 usleep_range(10000, 11000);
308
309 gpiod_set_value(tc->reset_gpio, 0);
310 usleep_range(10, 20);
311 }
312
tc_bridge_post_disable(struct drm_bridge * bridge)313 static void tc_bridge_post_disable(struct drm_bridge *bridge)
314 {
315 struct tc_data *tc = bridge_to_tc(bridge);
316 struct device *dev = &tc->dsi->dev;
317 int ret;
318
319 gpiod_set_value(tc->reset_gpio, 1);
320 usleep_range(10, 20);
321
322 gpiod_set_value(tc->stby_gpio, 1);
323 usleep_range(10000, 11000);
324
325 ret = regulator_disable(tc->vdd);
326 if (ret < 0)
327 dev_err(dev, "regulator vdd disable failed, %d\n", ret);
328 usleep_range(10000, 11000);
329
330 ret = regulator_disable(tc->vddio);
331 if (ret < 0)
332 dev_err(dev, "regulator vddio disable failed, %d\n", ret);
333 usleep_range(10000, 11000);
334 }
335
d2l_read(struct i2c_client * i2c,u16 addr,u32 * val)336 static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
337 {
338 int ret;
339 u8 buf_addr[2];
340
341 put_unaligned_be16(addr, buf_addr);
342 ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
343 if (ret < 0)
344 goto fail;
345
346 ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
347 if (ret < 0)
348 goto fail;
349
350 pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
351 return;
352
353 fail:
354 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
355 ret, addr);
356 }
357
d2l_write(struct i2c_client * i2c,u16 addr,u32 val)358 static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
359 {
360 u8 data[6];
361 int ret;
362
363 put_unaligned_be16(addr, data);
364 put_unaligned_le32(val, data + 2);
365
366 ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
367 if (ret < 0)
368 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
369 ret, addr);
370 }
371
372 /* helper function to access bus_formats */
get_connector(struct drm_encoder * encoder)373 static struct drm_connector *get_connector(struct drm_encoder *encoder)
374 {
375 struct drm_device *dev = encoder->dev;
376 struct drm_connector *connector;
377
378 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
379 if (connector->encoder == encoder)
380 return connector;
381
382 return NULL;
383 }
384
tc_bridge_enable(struct drm_bridge * bridge)385 static void tc_bridge_enable(struct drm_bridge *bridge)
386 {
387 struct tc_data *tc = bridge_to_tc(bridge);
388 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
389 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
390 u32 val = 0;
391 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
392 struct drm_display_mode *mode;
393 struct drm_connector *connector = get_connector(bridge->encoder);
394
395 mode = &bridge->encoder->crtc->state->adjusted_mode;
396
397 hback_porch = mode->htotal - mode->hsync_end;
398 hsync_len = mode->hsync_end - mode->hsync_start;
399 vback_porch = mode->vtotal - mode->vsync_end;
400 vsync_len = mode->vsync_end - mode->vsync_start;
401
402 htime1 = (hback_porch << 16) + hsync_len;
403 vtime1 = (vback_porch << 16) + vsync_len;
404
405 hfront_porch = mode->hsync_start - mode->hdisplay;
406 hactive = mode->hdisplay;
407 vfront_porch = mode->vsync_start - mode->vdisplay;
408 vactive = mode->vdisplay;
409
410 htime2 = (hfront_porch << 16) + hactive;
411 vtime2 = (vfront_porch << 16) + vactive;
412
413 d2l_read(tc->i2c, IDREG, &val);
414
415 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
416 (val >> 8) & 0xFF, val & 0xFF);
417
418 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
419 SYS_RST_LCD | SYS_RST_I2CM);
420 usleep_range(30000, 40000);
421
422 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
423 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
424 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
425 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
426 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
427 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
428
429 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
430 d2l_write(tc->i2c, PPI_LANEENABLE, val);
431 d2l_write(tc->i2c, DSI_LANEENABLE, val);
432
433 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
434 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
435
436 /* Video event mode vs pulse mode bit, does not exist for tc358775 */
437 if (tc->type == TC358765)
438 val = EVTMODE;
439 else
440 val = 0;
441
442 if (tc->bpc == 8)
443 val |= TC358775_VPCTRL_OPXLFMT(1);
444 else /* bpc = 6; */
445 val |= TC358775_VPCTRL_MSF(1);
446
447 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
448 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);
449 byteclk = dsiclk / 4;
450 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
451 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
452 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
453 tc->num_dsi_lanes);
454
455 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
456
457 val |= TC358775_VPCTRL_VSDELAY(vsdelay);
458 d2l_write(tc->i2c, VPCTRL, val);
459
460 d2l_write(tc->i2c, HTIM1, htime1);
461 d2l_write(tc->i2c, VTIM1, vtime1);
462 d2l_write(tc->i2c, HTIM2, htime2);
463 d2l_write(tc->i2c, VTIM2, vtime2);
464
465 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
466 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
467 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
468
469 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
470 connector->display_info.bus_formats[0],
471 tc->bpc);
472 if (connector->display_info.bus_formats[0] ==
473 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
474 /* VESA-24 */
475 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
476 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
477 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
478 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
479 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
480 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
481 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
482 } else {
483 /* JEIDA-18 and JEIDA-24 */
484 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5));
485 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2));
486 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1));
487 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2));
488 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4));
489 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0));
490 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0));
491 }
492
493 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
494
495 val = LVCFG_LVEN_BIT;
496 if (tc->lvds_link == DUAL_LINK) {
497 val |= TC358775_LVCFG_LVDLINK(1);
498 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
499 } else {
500 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
501 }
502 d2l_write(tc->i2c, LVCFG, val);
503 }
504
505 static enum drm_mode_status
tc_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)506 tc_mode_valid(struct drm_bridge *bridge,
507 const struct drm_display_info *info,
508 const struct drm_display_mode *mode)
509 {
510 struct tc_data *tc = bridge_to_tc(bridge);
511
512 /*
513 * Maximum pixel clock speed 135MHz for single-link
514 * 270MHz for dual-link
515 */
516 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
517 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
518 return MODE_CLOCK_HIGH;
519
520 switch (info->bus_formats[0]) {
521 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
522 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
523 /* RGB888 */
524 tc->bpc = 8;
525 break;
526 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
527 /* RGB666 */
528 tc->bpc = 6;
529 break;
530 default:
531 dev_warn(tc->dev,
532 "unsupported LVDS bus format 0x%04x\n",
533 info->bus_formats[0]);
534 return MODE_NOMODE;
535 }
536
537 return MODE_OK;
538 }
539
tc358775_parse_dt(struct device_node * np,struct tc_data * tc)540 static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
541 {
542 struct device_node *endpoint;
543 struct device_node *remote;
544 int dsi_lanes = -1;
545
546 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
547 TC358775_DSI_IN, -1);
548 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
549
550 /* Quirk old dtb: Use data lanes from the DSI host side instead of bridge */
551 if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) {
552 remote = of_graph_get_remote_endpoint(endpoint);
553 dsi_lanes = drm_of_get_data_lanes_count(remote, 1, 4);
554 of_node_put(remote);
555 if (dsi_lanes >= 1)
556 dev_warn(tc->dev, "no dsi-lanes for the bridge, using host lanes\n");
557 }
558
559 of_node_put(endpoint);
560
561 if (dsi_lanes < 0)
562 return dsi_lanes;
563
564 tc->num_dsi_lanes = dsi_lanes;
565
566 tc->host_node = of_graph_get_remote_node(np, 0, 0);
567 if (!tc->host_node)
568 return -ENODEV;
569
570 of_node_put(tc->host_node);
571
572 tc->lvds_link = SINGLE_LINK;
573 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
574 TC358775_LVDS_OUT1, -1);
575 if (endpoint) {
576 remote = of_graph_get_remote_port_parent(endpoint);
577 of_node_put(endpoint);
578
579 if (remote) {
580 if (of_device_is_available(remote))
581 tc->lvds_link = DUAL_LINK;
582 of_node_put(remote);
583 }
584 }
585
586 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
587 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
588
589 return 0;
590 }
591
tc_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)592 static int tc_bridge_attach(struct drm_bridge *bridge,
593 enum drm_bridge_attach_flags flags)
594 {
595 struct tc_data *tc = bridge_to_tc(bridge);
596
597 /* Attach the panel-bridge to the dsi bridge */
598 return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
599 &tc->bridge, flags);
600 }
601
602 static const struct drm_bridge_funcs tc_bridge_funcs = {
603 .attach = tc_bridge_attach,
604 .pre_enable = tc_bridge_pre_enable,
605 .enable = tc_bridge_enable,
606 .mode_valid = tc_mode_valid,
607 .post_disable = tc_bridge_post_disable,
608 };
609
tc_attach_host(struct tc_data * tc)610 static int tc_attach_host(struct tc_data *tc)
611 {
612 struct device *dev = &tc->i2c->dev;
613 struct mipi_dsi_host *host;
614 struct mipi_dsi_device *dsi;
615 int ret;
616 const struct mipi_dsi_device_info info = { .type = "tc358775",
617 .channel = 0,
618 .node = NULL,
619 };
620
621 host = of_find_mipi_dsi_host_by_node(tc->host_node);
622 if (!host)
623 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
624
625 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
626 if (IS_ERR(dsi)) {
627 dev_err(dev, "failed to create dsi device\n");
628 return PTR_ERR(dsi);
629 }
630
631 tc->dsi = dsi;
632
633 dsi->lanes = tc->num_dsi_lanes;
634 dsi->format = MIPI_DSI_FMT_RGB888;
635 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
636 MIPI_DSI_MODE_LPM;
637
638 /*
639 * The hs_rate and lp_rate are data rate values. The HS mode is
640 * differential, while the LP mode is single ended. As the HS mode
641 * uses DDR, the DSI clock frequency is half the hs_rate. The 10 Mbs
642 * data rate for LP mode is not specified in the bridge data sheet,
643 * but seems to be part of the MIPI DSI spec.
644 */
645 if (tc->type == TC358765)
646 dsi->hs_rate = 800000000;
647 else
648 dsi->hs_rate = 1000000000;
649 dsi->lp_rate = 10000000;
650
651 ret = devm_mipi_dsi_attach(dev, dsi);
652 if (ret < 0) {
653 dev_err(dev, "failed to attach dsi to host\n");
654 return ret;
655 }
656
657 return 0;
658 }
659
tc_probe(struct i2c_client * client)660 static int tc_probe(struct i2c_client *client)
661 {
662 struct device *dev = &client->dev;
663 struct tc_data *tc;
664 int ret;
665
666 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
667 if (!tc)
668 return -ENOMEM;
669
670 tc->dev = dev;
671 tc->i2c = client;
672 tc->type = (enum tc3587x5_type)(unsigned long)of_device_get_match_data(dev);
673
674 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
675 TC358775_LVDS_OUT0, 0);
676 if (IS_ERR(tc->panel_bridge))
677 return PTR_ERR(tc->panel_bridge);
678
679 ret = tc358775_parse_dt(dev->of_node, tc);
680 if (ret)
681 return ret;
682
683 tc->vddio = devm_regulator_get(dev, "vddio-supply");
684 if (IS_ERR(tc->vddio)) {
685 ret = PTR_ERR(tc->vddio);
686 dev_err(dev, "vddio-supply not found\n");
687 return ret;
688 }
689
690 tc->vdd = devm_regulator_get(dev, "vdd-supply");
691 if (IS_ERR(tc->vdd)) {
692 ret = PTR_ERR(tc->vdd);
693 dev_err(dev, "vdd-supply not found\n");
694 return ret;
695 }
696
697 tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH);
698 if (IS_ERR(tc->stby_gpio))
699 return PTR_ERR(tc->stby_gpio);
700
701 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
702 if (IS_ERR(tc->reset_gpio)) {
703 ret = PTR_ERR(tc->reset_gpio);
704 dev_err(dev, "cannot get reset-gpios %d\n", ret);
705 return ret;
706 }
707
708 tc->bridge.funcs = &tc_bridge_funcs;
709 tc->bridge.of_node = dev->of_node;
710 tc->bridge.pre_enable_prev_first = true;
711 drm_bridge_add(&tc->bridge);
712
713 i2c_set_clientdata(client, tc);
714
715 ret = tc_attach_host(tc);
716 if (ret)
717 goto err_bridge_remove;
718
719 return 0;
720
721 err_bridge_remove:
722 drm_bridge_remove(&tc->bridge);
723 return ret;
724 }
725
tc_remove(struct i2c_client * client)726 static void tc_remove(struct i2c_client *client)
727 {
728 struct tc_data *tc = i2c_get_clientdata(client);
729
730 drm_bridge_remove(&tc->bridge);
731 }
732
733 static const struct i2c_device_id tc358775_i2c_ids[] = {
734 { "tc358765", TC358765, },
735 { "tc358775", TC358775, },
736 { }
737 };
738 MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
739
740 static const struct of_device_id tc358775_of_ids[] = {
741 { .compatible = "toshiba,tc358765", .data = (void *)TC358765, },
742 { .compatible = "toshiba,tc358775", .data = (void *)TC358775, },
743 { }
744 };
745 MODULE_DEVICE_TABLE(of, tc358775_of_ids);
746
747 static struct i2c_driver tc358775_driver = {
748 .driver = {
749 .name = "tc358775",
750 .of_match_table = tc358775_of_ids,
751 },
752 .id_table = tc358775_i2c_ids,
753 .probe = tc_probe,
754 .remove = tc_remove,
755 };
756 module_i2c_driver(tc358775_driver);
757
758 MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
759 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
760 MODULE_LICENSE("GPL v2");
761