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Searched refs:LVDS (Results 1 – 25 of 64) sorted by relevance

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/linux/drivers/gpu/drm/stm/
H A DKconfig27 tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver"
30 Enable support for LVDS encoders on STMicroelectronics SoC.
31 The STM LVDS is a bridge which serialize pixel stream onto
32 a LVDS protocol.
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-colibri-wifi-iris-v2.dts31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
H A Dimx7s-colibri-iris-v2.dts31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
H A Dimx7d-colibri-iris-v2.dts31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
H A Dimx6ull-colibri-iris-v2.dts31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0-ek874-idk-2121wr.dts4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
68 * When GP0_17 is low LVDS[01] are connected to the LVDS connector
69 * When GP0_17 is high LVDS[01] are connected to the LT8918L
H A Dhihope-rzg2-ex-lvds.dtsi3 * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts
20 * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
H A Dr8a774e1-hihope-rzg2h-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774b1-hihope-rzg2n-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774a1-hihope-rzg2m-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts4 * Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Drzg2-advantech-idk-1110wr-panel.dtsi3 * Device Tree Source for the Advantech idk-1110wr LVDS panel connected
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-lvds-display.dtsi3 /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */
35 /* Texas Instruments SN75LVDS83B LVDS Transmitter */
/linux/drivers/gpu/drm/renesas/rcar-du/
H A DKconfig37 bool "R-Car DU LVDS Encoder Support"
42 Enable support for the R-Car Display Unit embedded LVDS encoders.
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c231 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
251 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
252 REG_READ(LVDS); in psb_intel_crtc_mode_set()
323 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in psb_intel_crtc_clock_get()
H A Dcdv_intel_display.c705 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
736 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set()
755 REG_WRITE(LVDS, lvds); in cdv_intel_crtc_mode_set()
756 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
855 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h12 #define LVDS _MMIO(0x61180) macro
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-phyboard-pollux-etml1010g3dra.dtso29 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
H A Dimx8mp-phyboard-pollux-ph128800t006.dtso29 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
H A Dimx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso30 * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
H A Dimx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso30 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
H A Dfsl-ls1028a-kontron-sl28.dts277 "eMMC reset", "LVDS bridge reset",
278 "LVDS bridge power-down",
/linux/drivers/phy/rockchip/
H A DKconfig61 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
66 Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c634 par->LVDS = 0; in NVCommonSetup()
638 par->LVDS = 1; in NVCommonSetup()
639 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); in NVCommonSetup()

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