1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023, Collabora
4 *
5 * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
6 */
7
8 #include <media/v4l2-mem2mem.h>
9 #include "hantro.h"
10 #include "hantro_v4l2.h"
11 #include "rockchip_vpu981_regs.h"
12
13 #define AV1_DEC_MODE 17
14 #define GM_GLOBAL_MODELS_PER_FRAME 7
15 #define GLOBAL_MODEL_TOTAL_SIZE (6 * 4 + 4 * 2)
16 #define GLOBAL_MODEL_SIZE ALIGN(GM_GLOBAL_MODELS_PER_FRAME * GLOBAL_MODEL_TOTAL_SIZE, 2048)
17 #define AV1_MAX_TILES 128
18 #define AV1_TILE_INFO_SIZE (AV1_MAX_TILES * 16)
19 #define AV1DEC_MAX_PIC_BUFFERS 24
20 #define AV1_REF_SCALE_SHIFT 14
21 #define AV1_INVALID_IDX -1
22 #define MAX_FRAME_DISTANCE 31
23 #define AV1_PRIMARY_REF_NONE 7
24 #define AV1_TILE_SIZE ALIGN(32 * 128, 4096)
25 /*
26 * These 3 values aren't defined enum v4l2_av1_segment_feature because
27 * they are not part of the specification
28 */
29 #define V4L2_AV1_SEG_LVL_ALT_LF_Y_H 2
30 #define V4L2_AV1_SEG_LVL_ALT_LF_U 3
31 #define V4L2_AV1_SEG_LVL_ALT_LF_V 4
32
33 #define SUPERRES_SCALE_BITS 3
34 #define SCALE_NUMERATOR 8
35 #define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1)
36
37 #define RS_SUBPEL_BITS 6
38 #define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1)
39 #define RS_SCALE_SUBPEL_BITS 14
40 #define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1)
41 #define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS)
42 #define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1))
43
44 #define IS_INTRA(type) ((type == V4L2_AV1_KEY_FRAME) || (type == V4L2_AV1_INTRA_ONLY_FRAME))
45
46 #define LST_BUF_IDX (V4L2_AV1_REF_LAST_FRAME - V4L2_AV1_REF_LAST_FRAME)
47 #define LST2_BUF_IDX (V4L2_AV1_REF_LAST2_FRAME - V4L2_AV1_REF_LAST_FRAME)
48 #define LST3_BUF_IDX (V4L2_AV1_REF_LAST3_FRAME - V4L2_AV1_REF_LAST_FRAME)
49 #define GLD_BUF_IDX (V4L2_AV1_REF_GOLDEN_FRAME - V4L2_AV1_REF_LAST_FRAME)
50 #define BWD_BUF_IDX (V4L2_AV1_REF_BWDREF_FRAME - V4L2_AV1_REF_LAST_FRAME)
51 #define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME)
52 #define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME)
53
54 #define DIV_LUT_PREC_BITS 14
55 #define DIV_LUT_BITS 8
56 #define DIV_LUT_NUM BIT(DIV_LUT_BITS)
57 #define WARP_PARAM_REDUCE_BITS 6
58 #define WARPEDMODEL_PREC_BITS 16
59
60 #define AV1_DIV_ROUND_UP_POW2(value, n) \
61 ({ \
62 typeof(n) _n = n; \
63 typeof(value) _value = value; \
64 (_value + (BIT(_n) >> 1)) >> _n; \
65 })
66
67 #define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \
68 ({ \
69 typeof(n) _n_ = n; \
70 typeof(value) _value_ = value; \
71 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
72 : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \
73 })
74
75 enum rockchip_av1_tx_mode {
76 ROCKCHIP_AV1_TX_MODE_ONLY_4X4 = 0,
77 ROCKCHIP_AV1_TX_MODE_8X8 = 1,
78 ROCKCHIP_AV1_TX_MODE_16x16 = 2,
79 ROCKCHIP_AV1_TX_MODE_32x32 = 3,
80 ROCKCHIP_AV1_TX_MODE_SELECT = 4,
81 };
82
83 struct rockchip_av1_film_grain {
84 u8 scaling_lut_y[256];
85 u8 scaling_lut_cb[256];
86 u8 scaling_lut_cr[256];
87 s16 cropped_luma_grain_block[4096];
88 s16 cropped_chroma_grain_block[1024 * 2];
89 };
90
91 static const short div_lut[DIV_LUT_NUM + 1] = {
92 16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768,
93 15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142,
94 15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564,
95 14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028,
96 13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530,
97 13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066,
98 13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633,
99 12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228,
100 12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848,
101 11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491,
102 11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155,
103 11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838,
104 10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538,
105 10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255,
106 10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986,
107 9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732,
108 9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489,
109 9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259,
110 9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039,
111 9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830,
112 8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630,
113 8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439,
114 8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257,
115 8240, 8224, 8208, 8192,
116 };
117
rockchip_vpu981_get_frame_index(struct hantro_ctx * ctx,int ref)118 static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref)
119 {
120 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
121 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
122 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
123 u64 timestamp;
124 int i, idx = frame->ref_frame_idx[ref];
125
126 if (idx >= V4L2_AV1_TOTAL_REFS_PER_FRAME || idx < 0)
127 return AV1_INVALID_IDX;
128
129 timestamp = frame->reference_frame_ts[idx];
130 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) {
131 if (!av1_dec->frame_refs[i].used)
132 continue;
133 if (av1_dec->frame_refs[i].timestamp == timestamp)
134 return i;
135 }
136
137 return AV1_INVALID_IDX;
138 }
139
rockchip_vpu981_get_order_hint(struct hantro_ctx * ctx,int ref)140 static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref)
141 {
142 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
143 int idx = rockchip_vpu981_get_frame_index(ctx, ref);
144
145 if (idx != AV1_INVALID_IDX)
146 return av1_dec->frame_refs[idx].order_hint;
147
148 return 0;
149 }
150
rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx * ctx,u64 timestamp)151 static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx,
152 u64 timestamp)
153 {
154 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
155 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
156 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
157 int i;
158
159 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) {
160 int j;
161
162 if (av1_dec->frame_refs[i].used)
163 continue;
164
165 av1_dec->frame_refs[i].width = frame->frame_width_minus_1 + 1;
166 av1_dec->frame_refs[i].height = frame->frame_height_minus_1 + 1;
167 av1_dec->frame_refs[i].mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8);
168 av1_dec->frame_refs[i].mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8);
169 av1_dec->frame_refs[i].timestamp = timestamp;
170 av1_dec->frame_refs[i].frame_type = frame->frame_type;
171 av1_dec->frame_refs[i].order_hint = frame->order_hint;
172 av1_dec->frame_refs[i].vb2_ref = hantro_get_dst_buf(ctx);
173
174 for (j = 0; j < V4L2_AV1_TOTAL_REFS_PER_FRAME; j++)
175 av1_dec->frame_refs[i].order_hints[j] = frame->order_hints[j];
176 av1_dec->frame_refs[i].used = true;
177 av1_dec->current_frame_index = i;
178
179 return i;
180 }
181
182 return AV1_INVALID_IDX;
183 }
184
rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx * ctx,int idx)185 static void rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx *ctx, int idx)
186 {
187 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
188
189 if (idx >= 0)
190 av1_dec->frame_refs[idx].used = false;
191 }
192
rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx * ctx)193 static void rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx *ctx)
194 {
195 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
196 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
197
198 int ref, idx;
199
200 for (idx = 0; idx < AV1_MAX_FRAME_BUF_COUNT; idx++) {
201 u64 timestamp = av1_dec->frame_refs[idx].timestamp;
202 bool used = false;
203
204 if (!av1_dec->frame_refs[idx].used)
205 continue;
206
207 for (ref = 0; ref < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref++) {
208 if (ctrls->frame->reference_frame_ts[ref] == timestamp)
209 used = true;
210 }
211
212 if (!used)
213 rockchip_vpu981_av1_dec_frame_unref(ctx, idx);
214 }
215 }
216
rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx * ctx)217 static size_t rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx *ctx)
218 {
219 return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
220 }
221
rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx * ctx)222 static size_t rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx *ctx)
223 {
224 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx);
225
226 return ALIGN((cr_offset * 3) / 2, 64);
227 }
228
rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx * ctx)229 static void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx)
230 {
231 struct hantro_dev *vpu = ctx->dev;
232 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
233
234 if (av1_dec->db_data_col.cpu)
235 dma_free_coherent(vpu->dev, av1_dec->db_data_col.size,
236 av1_dec->db_data_col.cpu,
237 av1_dec->db_data_col.dma);
238 av1_dec->db_data_col.cpu = NULL;
239
240 if (av1_dec->db_ctrl_col.cpu)
241 dma_free_coherent(vpu->dev, av1_dec->db_ctrl_col.size,
242 av1_dec->db_ctrl_col.cpu,
243 av1_dec->db_ctrl_col.dma);
244 av1_dec->db_ctrl_col.cpu = NULL;
245
246 if (av1_dec->cdef_col.cpu)
247 dma_free_coherent(vpu->dev, av1_dec->cdef_col.size,
248 av1_dec->cdef_col.cpu, av1_dec->cdef_col.dma);
249 av1_dec->cdef_col.cpu = NULL;
250
251 if (av1_dec->sr_col.cpu)
252 dma_free_coherent(vpu->dev, av1_dec->sr_col.size,
253 av1_dec->sr_col.cpu, av1_dec->sr_col.dma);
254 av1_dec->sr_col.cpu = NULL;
255
256 if (av1_dec->lr_col.cpu)
257 dma_free_coherent(vpu->dev, av1_dec->lr_col.size,
258 av1_dec->lr_col.cpu, av1_dec->lr_col.dma);
259 av1_dec->lr_col.cpu = NULL;
260 }
261
rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx * ctx)262 static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx)
263 {
264 struct hantro_dev *vpu = ctx->dev;
265 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
266 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
267 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info;
268 unsigned int num_tile_cols = tile_info->tile_cols;
269 unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 + 1, 64);
270 unsigned int height_in_sb = height / 64;
271 unsigned int stripe_num = ((height + 8) + 63) / 64;
272 size_t size;
273
274 if (av1_dec->db_data_col.size >=
275 ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols)
276 return 0;
277
278 rockchip_vpu981_av1_dec_tiles_free(ctx);
279
280 size = ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols;
281 av1_dec->db_data_col.cpu = dma_alloc_coherent(vpu->dev, size,
282 &av1_dec->db_data_col.dma,
283 GFP_KERNEL);
284 if (!av1_dec->db_data_col.cpu)
285 goto buffer_allocation_error;
286 av1_dec->db_data_col.size = size;
287
288 size = ALIGN(height * 2 * 16 / 4, 128) * num_tile_cols;
289 av1_dec->db_ctrl_col.cpu = dma_alloc_coherent(vpu->dev, size,
290 &av1_dec->db_ctrl_col.dma,
291 GFP_KERNEL);
292 if (!av1_dec->db_ctrl_col.cpu)
293 goto buffer_allocation_error;
294 av1_dec->db_ctrl_col.size = size;
295
296 size = ALIGN(height_in_sb * 44 * ctx->bit_depth * 16 / 8, 128) * num_tile_cols;
297 av1_dec->cdef_col.cpu = dma_alloc_coherent(vpu->dev, size,
298 &av1_dec->cdef_col.dma,
299 GFP_KERNEL);
300 if (!av1_dec->cdef_col.cpu)
301 goto buffer_allocation_error;
302 av1_dec->cdef_col.size = size;
303
304 size = ALIGN(height_in_sb * (3040 + 1280), 128) * num_tile_cols;
305 av1_dec->sr_col.cpu = dma_alloc_coherent(vpu->dev, size,
306 &av1_dec->sr_col.dma,
307 GFP_KERNEL);
308 if (!av1_dec->sr_col.cpu)
309 goto buffer_allocation_error;
310 av1_dec->sr_col.size = size;
311
312 size = ALIGN(stripe_num * 1536 * ctx->bit_depth / 8, 128) * num_tile_cols;
313 av1_dec->lr_col.cpu = dma_alloc_coherent(vpu->dev, size,
314 &av1_dec->lr_col.dma,
315 GFP_KERNEL);
316 if (!av1_dec->lr_col.cpu)
317 goto buffer_allocation_error;
318 av1_dec->lr_col.size = size;
319
320 av1_dec->num_tile_cols_allocated = num_tile_cols;
321 return 0;
322
323 buffer_allocation_error:
324 rockchip_vpu981_av1_dec_tiles_free(ctx);
325 return -ENOMEM;
326 }
327
rockchip_vpu981_av1_dec_exit(struct hantro_ctx * ctx)328 void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx)
329 {
330 struct hantro_dev *vpu = ctx->dev;
331 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
332
333 if (av1_dec->global_model.cpu)
334 dma_free_coherent(vpu->dev, av1_dec->global_model.size,
335 av1_dec->global_model.cpu,
336 av1_dec->global_model.dma);
337 av1_dec->global_model.cpu = NULL;
338
339 if (av1_dec->tile_info.cpu)
340 dma_free_coherent(vpu->dev, av1_dec->tile_info.size,
341 av1_dec->tile_info.cpu,
342 av1_dec->tile_info.dma);
343 av1_dec->tile_info.cpu = NULL;
344
345 if (av1_dec->film_grain.cpu)
346 dma_free_coherent(vpu->dev, av1_dec->film_grain.size,
347 av1_dec->film_grain.cpu,
348 av1_dec->film_grain.dma);
349 av1_dec->film_grain.cpu = NULL;
350
351 if (av1_dec->prob_tbl.cpu)
352 dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size,
353 av1_dec->prob_tbl.cpu, av1_dec->prob_tbl.dma);
354 av1_dec->prob_tbl.cpu = NULL;
355
356 if (av1_dec->prob_tbl_out.cpu)
357 dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size,
358 av1_dec->prob_tbl_out.cpu,
359 av1_dec->prob_tbl_out.dma);
360 av1_dec->prob_tbl_out.cpu = NULL;
361
362 if (av1_dec->tile_buf.cpu)
363 dma_free_coherent(vpu->dev, av1_dec->tile_buf.size,
364 av1_dec->tile_buf.cpu, av1_dec->tile_buf.dma);
365 av1_dec->tile_buf.cpu = NULL;
366
367 rockchip_vpu981_av1_dec_tiles_free(ctx);
368 }
369
rockchip_vpu981_av1_dec_init(struct hantro_ctx * ctx)370 int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx)
371 {
372 struct hantro_dev *vpu = ctx->dev;
373 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
374
375 memset(av1_dec, 0, sizeof(*av1_dec));
376
377 av1_dec->global_model.cpu = dma_alloc_coherent(vpu->dev, GLOBAL_MODEL_SIZE,
378 &av1_dec->global_model.dma,
379 GFP_KERNEL);
380 if (!av1_dec->global_model.cpu)
381 return -ENOMEM;
382 av1_dec->global_model.size = GLOBAL_MODEL_SIZE;
383
384 av1_dec->tile_info.cpu = dma_alloc_coherent(vpu->dev, AV1_TILE_INFO_SIZE,
385 &av1_dec->tile_info.dma,
386 GFP_KERNEL);
387 if (!av1_dec->tile_info.cpu)
388 return -ENOMEM;
389 av1_dec->tile_info.size = AV1_TILE_INFO_SIZE;
390
391 av1_dec->film_grain.cpu = dma_alloc_coherent(vpu->dev,
392 ALIGN(sizeof(struct rockchip_av1_film_grain), 2048),
393 &av1_dec->film_grain.dma,
394 GFP_KERNEL);
395 if (!av1_dec->film_grain.cpu)
396 return -ENOMEM;
397 av1_dec->film_grain.size = ALIGN(sizeof(struct rockchip_av1_film_grain), 2048);
398
399 av1_dec->prob_tbl.cpu = dma_alloc_coherent(vpu->dev,
400 ALIGN(sizeof(struct av1cdfs), 2048),
401 &av1_dec->prob_tbl.dma,
402 GFP_KERNEL);
403 if (!av1_dec->prob_tbl.cpu)
404 return -ENOMEM;
405 av1_dec->prob_tbl.size = ALIGN(sizeof(struct av1cdfs), 2048);
406
407 av1_dec->prob_tbl_out.cpu = dma_alloc_coherent(vpu->dev,
408 ALIGN(sizeof(struct av1cdfs), 2048),
409 &av1_dec->prob_tbl_out.dma,
410 GFP_KERNEL);
411 if (!av1_dec->prob_tbl_out.cpu)
412 return -ENOMEM;
413 av1_dec->prob_tbl_out.size = ALIGN(sizeof(struct av1cdfs), 2048);
414 av1_dec->cdfs = &av1_dec->default_cdfs;
415 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc;
416
417 rockchip_av1_set_default_cdfs(av1_dec->cdfs, av1_dec->cdfs_ndvc);
418
419 av1_dec->tile_buf.cpu = dma_alloc_coherent(vpu->dev,
420 AV1_TILE_SIZE,
421 &av1_dec->tile_buf.dma,
422 GFP_KERNEL);
423 if (!av1_dec->tile_buf.cpu)
424 return -ENOMEM;
425 av1_dec->tile_buf.size = AV1_TILE_SIZE;
426
427 return 0;
428 }
429
rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx * ctx)430 static int rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx *ctx)
431 {
432 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
433 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
434 const struct v4l2_av1_tile_info *tile_info;
435 struct v4l2_ctrl *tge;
436 u32 num_tiles;
437
438 ctrls->sequence = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE);
439 if (WARN_ON(!ctrls->sequence))
440 return -EINVAL;
441
442 tge = v4l2_ctrl_find(&ctx->ctrl_handler,
443 V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY);
444 if (WARN_ON(!tge))
445 return -EINVAL;
446 ctrls->tile_group_entry = tge->p_cur.p;
447
448 ctrls->frame = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FRAME);
449 if (WARN_ON(!ctrls->frame))
450 return -EINVAL;
451
452 /*
453 * rockchip_vpu981_av1_dec_set_tile_info() indexes the tile group
454 * entry array by tile1 * tile_cols + tile0, so it reads up to
455 * tile_cols * tile_rows entries, and lays out one descriptor per tile
456 * in the AV1_MAX_TILES tile_info buffer while programming the real
457 * tile geometry into the hardware. Reject a frame that claims more
458 * tiles than userspace submitted, or more than the hardware tile
459 * buffer holds, so the read stays in bounds and the programmed
460 * geometry matches the descriptors written.
461 */
462 tile_info = &ctrls->frame->tile_info;
463 num_tiles = (u32)tile_info->tile_cols * tile_info->tile_rows;
464 if (num_tiles > tge->elems || num_tiles > AV1_MAX_TILES)
465 return -EINVAL;
466
467 ctrls->film_grain =
468 hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FILM_GRAIN);
469
470 return rockchip_vpu981_av1_dec_tiles_reallocate(ctx);
471 }
472
rockchip_vpu981_av1_dec_get_msb(u32 n)473 static inline int rockchip_vpu981_av1_dec_get_msb(u32 n)
474 {
475 if (n == 0)
476 return 0;
477 return 31 ^ __builtin_clz(n);
478 }
479
rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d,short * shift)480 static short rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d, short *shift)
481 {
482 int f;
483 u64 e;
484
485 *shift = rockchip_vpu981_av1_dec_get_msb(d);
486 /* e is obtained from D after resetting the most significant 1 bit. */
487 e = d - ((u32)1 << *shift);
488 /* Get the most significant DIV_LUT_BITS (8) bits of e into f */
489 if (*shift > DIV_LUT_BITS)
490 f = AV1_DIV_ROUND_UP_POW2(e, *shift - DIV_LUT_BITS);
491 else
492 f = e << (DIV_LUT_BITS - *shift);
493 if (f > DIV_LUT_NUM)
494 return -1;
495 *shift += DIV_LUT_PREC_BITS;
496 /* Use f as lookup into the precomputed table of multipliers */
497 return div_lut[f];
498 }
499
500 static void
rockchip_vpu981_av1_dec_get_shear_params(const u32 * params,s64 * alpha,s64 * beta,s64 * gamma,s64 * delta)501 rockchip_vpu981_av1_dec_get_shear_params(const u32 *params, s64 *alpha,
502 s64 *beta, s64 *gamma, s64 *delta)
503 {
504 const int *mat = params;
505 short shift;
506 short y;
507 long long gv, dv;
508
509 if (mat[2] <= 0)
510 return;
511
512 *alpha = clamp_val(mat[2] - (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX);
513 *beta = clamp_val(mat[3], S16_MIN, S16_MAX);
514
515 y = rockchip_vpu981_av1_dec_resolve_divisor_32(abs(mat[2]), &shift) * (mat[2] < 0 ? -1 : 1);
516
517 gv = ((long long)mat[4] * (1 << WARPEDMODEL_PREC_BITS)) * y;
518
519 *gamma = clamp_val((int)AV1_DIV_ROUND_UP_POW2_SIGNED(gv, shift), S16_MIN, S16_MAX);
520
521 dv = ((long long)mat[3] * mat[4]) * y;
522 *delta = clamp_val(mat[5] -
523 (int)AV1_DIV_ROUND_UP_POW2_SIGNED(dv, shift) - (1 << WARPEDMODEL_PREC_BITS),
524 S16_MIN, S16_MAX);
525
526 *alpha = AV1_DIV_ROUND_UP_POW2_SIGNED(*alpha, WARP_PARAM_REDUCE_BITS)
527 * (1 << WARP_PARAM_REDUCE_BITS);
528 *beta = AV1_DIV_ROUND_UP_POW2_SIGNED(*beta, WARP_PARAM_REDUCE_BITS)
529 * (1 << WARP_PARAM_REDUCE_BITS);
530 *gamma = AV1_DIV_ROUND_UP_POW2_SIGNED(*gamma, WARP_PARAM_REDUCE_BITS)
531 * (1 << WARP_PARAM_REDUCE_BITS);
532 *delta = AV1_DIV_ROUND_UP_POW2_SIGNED(*delta, WARP_PARAM_REDUCE_BITS)
533 * (1 << WARP_PARAM_REDUCE_BITS);
534 }
535
rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx * ctx)536 static void rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx *ctx)
537 {
538 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
539 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
540 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
541 const struct v4l2_av1_global_motion *gm = &frame->global_motion;
542 u8 *dst = av1_dec->global_model.cpu;
543 struct hantro_dev *vpu = ctx->dev;
544 int ref_frame, i;
545
546 memset(dst, 0, GLOBAL_MODEL_SIZE);
547 for (ref_frame = 0; ref_frame < V4L2_AV1_REFS_PER_FRAME; ++ref_frame) {
548 s64 alpha = 0, beta = 0, gamma = 0, delta = 0;
549
550 for (i = 0; i < 6; ++i) {
551 if (i == 2)
552 *(s32 *)dst =
553 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][3];
554 else if (i == 3)
555 *(s32 *)dst =
556 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][2];
557 else
558 *(s32 *)dst =
559 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][i];
560 dst += 4;
561 }
562
563 if (gm->type[V4L2_AV1_REF_LAST_FRAME + ref_frame] <= V4L2_AV1_WARP_MODEL_AFFINE)
564 rockchip_vpu981_av1_dec_get_shear_params(&gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][0],
565 &alpha, &beta, &gamma, &delta);
566
567 *(s16 *)dst = alpha;
568 dst += 2;
569 *(s16 *)dst = beta;
570 dst += 2;
571 *(s16 *)dst = gamma;
572 dst += 2;
573 *(s16 *)dst = delta;
574 dst += 2;
575 }
576
577 hantro_write_addr(vpu, AV1_GLOBAL_MODEL, av1_dec->global_model.dma);
578 }
579
rockchip_vpu981_av1_tile_log2(int target)580 static int rockchip_vpu981_av1_tile_log2(int target)
581 {
582 int k;
583
584 /*
585 * returns the smallest value for k such that 1 << k is greater
586 * than or equal to target
587 */
588 for (k = 0; (1 << k) < target; k++);
589
590 return k;
591 }
592
rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx * ctx)593 static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx)
594 {
595 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
596 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
597 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info;
598 const struct v4l2_ctrl_av1_tile_group_entry *group_entry =
599 ctrls->tile_group_entry;
600 int context_update_y = 0;
601 int context_update_x = 0;
602 int context_update_tile_id = 0;
603 u8 *dst = av1_dec->tile_info.cpu;
604 u8 *dst_end = dst + av1_dec->tile_info.size;
605 struct hantro_dev *vpu = ctx->dev;
606 int tile0, tile1;
607
608 /*
609 * tile_cols and tile_rows are bounded by the V4L2 control validation
610 * (V4L2_AV1_MAX_TILE_{COLS,ROWS} and V4L2_AV1_MAX_TILE_COUNT). Guard
611 * the divisor here, and keep the descriptor writes within the
612 * AV1_MAX_TILES tile_info buffer below; the register values use the
613 * unmodified tile geometry.
614 */
615 if (tile_info->tile_cols) {
616 context_update_y =
617 tile_info->context_update_tile_id / tile_info->tile_cols;
618 context_update_x =
619 tile_info->context_update_tile_id % tile_info->tile_cols;
620 context_update_tile_id =
621 context_update_x * tile_info->tile_rows + context_update_y;
622 }
623
624 memset(dst, 0, av1_dec->tile_info.size);
625
626 for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) {
627 for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) {
628 int tile_id = tile1 * tile_info->tile_cols + tile0;
629 u32 start, end;
630 u32 y0 =
631 tile_info->height_in_sbs_minus_1[tile1] + 1;
632 u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1;
633
634 /* Stop once the tile_info descriptor buffer is full. */
635 if (dst + 16 > dst_end)
636 break;
637
638 /* tile size in SB units (width,height) */
639 *dst++ = x0;
640 *dst++ = 0;
641 *dst++ = 0;
642 *dst++ = 0;
643 *dst++ = y0;
644 *dst++ = 0;
645 *dst++ = 0;
646 *dst++ = 0;
647
648 /* tile start position */
649 start = group_entry[tile_id].tile_offset - group_entry[0].tile_offset;
650 *dst++ = start & 255;
651 *dst++ = (start >> 8) & 255;
652 *dst++ = (start >> 16) & 255;
653 *dst++ = (start >> 24) & 255;
654
655 /* number of bytes in tile data */
656 end = start + group_entry[tile_id].tile_size;
657 *dst++ = end & 255;
658 *dst++ = (end >> 8) & 255;
659 *dst++ = (end >> 16) & 255;
660 *dst++ = (end >> 24) & 255;
661 }
662 if (dst + 16 > dst_end)
663 break;
664 }
665
666 hantro_reg_write(vpu, &av1_multicore_expect_context_update, !!(context_update_x == 0));
667 hantro_reg_write(vpu, &av1_tile_enable,
668 !!((tile_info->tile_cols > 1) || (tile_info->tile_rows > 1)));
669 hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info->tile_cols);
670 hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows);
671 hantro_reg_write(vpu, &av1_context_update_tile_id, context_update_tile_id);
672 hantro_reg_write(vpu, &av1_tile_transpose, 1);
673 if (rockchip_vpu981_av1_tile_log2(tile_info->tile_cols) ||
674 rockchip_vpu981_av1_tile_log2(tile_info->tile_rows))
675 hantro_reg_write(vpu, &av1_dec_tile_size_mag, tile_info->tile_size_bytes - 1);
676 else
677 hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3);
678
679 hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma);
680 }
681
rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx * ctx,int a,int b)682 static int rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx *ctx,
683 int a, int b)
684 {
685 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
686 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
687 int bits = ctrls->sequence->order_hint_bits - 1;
688 int diff, m;
689
690 if (!ctrls->sequence->order_hint_bits)
691 return 0;
692
693 diff = a - b;
694 m = 1 << bits;
695 diff = (diff & (m - 1)) - (diff & m);
696
697 return diff;
698 }
699
rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx * ctx)700 static void rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx *ctx)
701 {
702 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
703 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
704 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
705 const struct v4l2_ctrl_av1_sequence *sequence = ctrls->sequence;
706 int i;
707
708 if (!sequence->order_hint_bits || IS_INTRA(frame->frame_type)) {
709 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++)
710 av1_dec->ref_frame_sign_bias[i] = 0;
711
712 return;
713 }
714 // Identify the nearest forward and backward references.
715 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; i++) {
716 if (rockchip_vpu981_get_frame_index(ctx, i) >= 0) {
717 int rel_off =
718 rockchip_vpu981_av1_dec_get_dist(ctx,
719 rockchip_vpu981_get_order_hint(ctx, i),
720 frame->order_hint);
721 av1_dec->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1;
722 }
723 }
724 }
725
726 static bool
rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx * ctx,int ref,int idx,int width,int height)727 rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
728 int width, int height)
729 {
730 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
731 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
732 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
733 struct hantro_dev *vpu = ctx->dev;
734 struct hantro_decoded_buffer *dst;
735 dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
736 int cur_width = frame->frame_width_minus_1 + 1;
737 int cur_height = frame->frame_height_minus_1 + 1;
738 int scale_width =
739 ((width << AV1_REF_SCALE_SHIFT) + cur_width / 2) / cur_width;
740 int scale_height =
741 ((height << AV1_REF_SCALE_SHIFT) + cur_height / 2) / cur_height;
742
743 switch (ref) {
744 case 0:
745 hantro_reg_write(vpu, &av1_ref0_height, height);
746 hantro_reg_write(vpu, &av1_ref0_width, width);
747 hantro_reg_write(vpu, &av1_ref0_ver_scale, scale_width);
748 hantro_reg_write(vpu, &av1_ref0_hor_scale, scale_height);
749 break;
750 case 1:
751 hantro_reg_write(vpu, &av1_ref1_height, height);
752 hantro_reg_write(vpu, &av1_ref1_width, width);
753 hantro_reg_write(vpu, &av1_ref1_ver_scale, scale_width);
754 hantro_reg_write(vpu, &av1_ref1_hor_scale, scale_height);
755 break;
756 case 2:
757 hantro_reg_write(vpu, &av1_ref2_height, height);
758 hantro_reg_write(vpu, &av1_ref2_width, width);
759 hantro_reg_write(vpu, &av1_ref2_ver_scale, scale_width);
760 hantro_reg_write(vpu, &av1_ref2_hor_scale, scale_height);
761 break;
762 case 3:
763 hantro_reg_write(vpu, &av1_ref3_height, height);
764 hantro_reg_write(vpu, &av1_ref3_width, width);
765 hantro_reg_write(vpu, &av1_ref3_ver_scale, scale_width);
766 hantro_reg_write(vpu, &av1_ref3_hor_scale, scale_height);
767 break;
768 case 4:
769 hantro_reg_write(vpu, &av1_ref4_height, height);
770 hantro_reg_write(vpu, &av1_ref4_width, width);
771 hantro_reg_write(vpu, &av1_ref4_ver_scale, scale_width);
772 hantro_reg_write(vpu, &av1_ref4_hor_scale, scale_height);
773 break;
774 case 5:
775 hantro_reg_write(vpu, &av1_ref5_height, height);
776 hantro_reg_write(vpu, &av1_ref5_width, width);
777 hantro_reg_write(vpu, &av1_ref5_ver_scale, scale_width);
778 hantro_reg_write(vpu, &av1_ref5_hor_scale, scale_height);
779 break;
780 case 6:
781 hantro_reg_write(vpu, &av1_ref6_height, height);
782 hantro_reg_write(vpu, &av1_ref6_width, width);
783 hantro_reg_write(vpu, &av1_ref6_ver_scale, scale_width);
784 hantro_reg_write(vpu, &av1_ref6_hor_scale, scale_height);
785 break;
786 default:
787 pr_warn("AV1 invalid reference frame index\n");
788 }
789
790 dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf);
791 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
792 chroma_addr = luma_addr + dst->av1.chroma_offset;
793 mv_addr = luma_addr + dst->av1.mv_offset;
794
795 hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr);
796 hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr);
797 hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr);
798
799 return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) ||
800 (scale_height != (1 << AV1_REF_SCALE_SHIFT));
801 }
802
rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx * ctx,int ref,int val)803 static void rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx *ctx,
804 int ref, int val)
805 {
806 struct hantro_dev *vpu = ctx->dev;
807
808 switch (ref) {
809 case 0:
810 hantro_reg_write(vpu, &av1_ref0_sign_bias, val);
811 break;
812 case 1:
813 hantro_reg_write(vpu, &av1_ref1_sign_bias, val);
814 break;
815 case 2:
816 hantro_reg_write(vpu, &av1_ref2_sign_bias, val);
817 break;
818 case 3:
819 hantro_reg_write(vpu, &av1_ref3_sign_bias, val);
820 break;
821 case 4:
822 hantro_reg_write(vpu, &av1_ref4_sign_bias, val);
823 break;
824 case 5:
825 hantro_reg_write(vpu, &av1_ref5_sign_bias, val);
826 break;
827 case 6:
828 hantro_reg_write(vpu, &av1_ref6_sign_bias, val);
829 break;
830 default:
831 pr_warn("AV1 invalid sign bias index\n");
832 break;
833 }
834 }
835
rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx * ctx)836 static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx)
837 {
838 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
839 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
840 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
841 const struct v4l2_av1_segmentation *seg = &frame->segmentation;
842 u32 segval[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX] = { 0 };
843 struct hantro_dev *vpu = ctx->dev;
844 u8 segsign = 0, preskip_segid = 0, last_active_seg = 0, i, j;
845
846 if (!!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) &&
847 frame->primary_ref_frame < V4L2_AV1_REFS_PER_FRAME) {
848 int idx = rockchip_vpu981_get_frame_index(ctx, frame->primary_ref_frame);
849
850 if (idx >= 0) {
851 dma_addr_t luma_addr, mv_addr = 0;
852 struct hantro_decoded_buffer *seg;
853 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx);
854
855 seg = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf);
856 luma_addr = hantro_get_dec_buf_addr(ctx, &seg->base.vb.vb2_buf);
857 mv_addr = luma_addr + mv_offset;
858
859 hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr);
860 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1);
861 }
862 }
863
864 hantro_reg_write(vpu, &av1_segment_temp_upd_e,
865 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE));
866 hantro_reg_write(vpu, &av1_segment_upd_e,
867 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP));
868 hantro_reg_write(vpu, &av1_segment_e,
869 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED));
870
871 hantro_reg_write(vpu, &av1_error_resilient,
872 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE));
873
874 if (IS_INTRA(frame->frame_type) ||
875 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)) {
876 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0);
877 }
878
879 if (seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) {
880 int s;
881
882 for (s = 0; s < V4L2_AV1_MAX_SEGMENTS; s++) {
883 if (seg->feature_enabled[s] &
884 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) {
885 segval[s][V4L2_AV1_SEG_LVL_ALT_Q] =
886 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q]),
887 0, 255);
888 segsign |=
889 (seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q] < 0) << s;
890 }
891
892 if (seg->feature_enabled[s] &
893 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_V))
894 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V] =
895 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]),
896 -63, 63);
897
898 if (seg->feature_enabled[s] &
899 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_H))
900 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H] =
901 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]),
902 -63, 63);
903
904 if (seg->feature_enabled[s] &
905 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_U))
906 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_U] =
907 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_U]),
908 -63, 63);
909
910 if (seg->feature_enabled[s] &
911 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_V))
912 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_V] =
913 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_V]),
914 -63, 63);
915
916 if (frame->frame_type && seg->feature_enabled[s] &
917 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_FRAME))
918 segval[s][V4L2_AV1_SEG_LVL_REF_FRAME]++;
919
920 if (seg->feature_enabled[s] &
921 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_SKIP))
922 segval[s][V4L2_AV1_SEG_LVL_REF_SKIP] = 1;
923
924 if (seg->feature_enabled[s] &
925 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_GLOBALMV))
926 segval[s][V4L2_AV1_SEG_LVL_REF_GLOBALMV] = 1;
927 }
928 }
929
930 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) {
931 for (j = 0; j < V4L2_AV1_SEG_LVL_MAX; j++) {
932 if (seg->feature_enabled[i]
933 & V4L2_AV1_SEGMENT_FEATURE_ENABLED(j)) {
934 preskip_segid |= (j >= V4L2_AV1_SEG_LVL_REF_FRAME);
935 last_active_seg = max(i, last_active_seg);
936 }
937 }
938 }
939
940 hantro_reg_write(vpu, &av1_last_active_seg, last_active_seg);
941 hantro_reg_write(vpu, &av1_preskip_segid, preskip_segid);
942
943 hantro_reg_write(vpu, &av1_seg_quant_sign, segsign);
944
945 /* Write QP, filter level, ref frame and skip for every segment */
946 hantro_reg_write(vpu, &av1_quant_seg0,
947 segval[0][V4L2_AV1_SEG_LVL_ALT_Q]);
948 hantro_reg_write(vpu, &av1_filt_level_delta0_seg0,
949 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
950 hantro_reg_write(vpu, &av1_filt_level_delta1_seg0,
951 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
952 hantro_reg_write(vpu, &av1_filt_level_delta2_seg0,
953 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_U]);
954 hantro_reg_write(vpu, &av1_filt_level_delta3_seg0,
955 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_V]);
956 hantro_reg_write(vpu, &av1_refpic_seg0,
957 segval[0][V4L2_AV1_SEG_LVL_REF_FRAME]);
958 hantro_reg_write(vpu, &av1_skip_seg0,
959 segval[0][V4L2_AV1_SEG_LVL_REF_SKIP]);
960 hantro_reg_write(vpu, &av1_global_mv_seg0,
961 segval[0][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
962
963 hantro_reg_write(vpu, &av1_quant_seg1,
964 segval[1][V4L2_AV1_SEG_LVL_ALT_Q]);
965 hantro_reg_write(vpu, &av1_filt_level_delta0_seg1,
966 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
967 hantro_reg_write(vpu, &av1_filt_level_delta1_seg1,
968 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
969 hantro_reg_write(vpu, &av1_filt_level_delta2_seg1,
970 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_U]);
971 hantro_reg_write(vpu, &av1_filt_level_delta3_seg1,
972 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_V]);
973 hantro_reg_write(vpu, &av1_refpic_seg1,
974 segval[1][V4L2_AV1_SEG_LVL_REF_FRAME]);
975 hantro_reg_write(vpu, &av1_skip_seg1,
976 segval[1][V4L2_AV1_SEG_LVL_REF_SKIP]);
977 hantro_reg_write(vpu, &av1_global_mv_seg1,
978 segval[1][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
979
980 hantro_reg_write(vpu, &av1_quant_seg2,
981 segval[2][V4L2_AV1_SEG_LVL_ALT_Q]);
982 hantro_reg_write(vpu, &av1_filt_level_delta0_seg2,
983 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
984 hantro_reg_write(vpu, &av1_filt_level_delta1_seg2,
985 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
986 hantro_reg_write(vpu, &av1_filt_level_delta2_seg2,
987 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_U]);
988 hantro_reg_write(vpu, &av1_filt_level_delta3_seg2,
989 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_V]);
990 hantro_reg_write(vpu, &av1_refpic_seg2,
991 segval[2][V4L2_AV1_SEG_LVL_REF_FRAME]);
992 hantro_reg_write(vpu, &av1_skip_seg2,
993 segval[2][V4L2_AV1_SEG_LVL_REF_SKIP]);
994 hantro_reg_write(vpu, &av1_global_mv_seg2,
995 segval[2][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
996
997 hantro_reg_write(vpu, &av1_quant_seg3,
998 segval[3][V4L2_AV1_SEG_LVL_ALT_Q]);
999 hantro_reg_write(vpu, &av1_filt_level_delta0_seg3,
1000 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
1001 hantro_reg_write(vpu, &av1_filt_level_delta1_seg3,
1002 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
1003 hantro_reg_write(vpu, &av1_filt_level_delta2_seg3,
1004 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_U]);
1005 hantro_reg_write(vpu, &av1_filt_level_delta3_seg3,
1006 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_V]);
1007 hantro_reg_write(vpu, &av1_refpic_seg3,
1008 segval[3][V4L2_AV1_SEG_LVL_REF_FRAME]);
1009 hantro_reg_write(vpu, &av1_skip_seg3,
1010 segval[3][V4L2_AV1_SEG_LVL_REF_SKIP]);
1011 hantro_reg_write(vpu, &av1_global_mv_seg3,
1012 segval[3][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
1013
1014 hantro_reg_write(vpu, &av1_quant_seg4,
1015 segval[4][V4L2_AV1_SEG_LVL_ALT_Q]);
1016 hantro_reg_write(vpu, &av1_filt_level_delta0_seg4,
1017 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
1018 hantro_reg_write(vpu, &av1_filt_level_delta1_seg4,
1019 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
1020 hantro_reg_write(vpu, &av1_filt_level_delta2_seg4,
1021 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_U]);
1022 hantro_reg_write(vpu, &av1_filt_level_delta3_seg4,
1023 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_V]);
1024 hantro_reg_write(vpu, &av1_refpic_seg4,
1025 segval[4][V4L2_AV1_SEG_LVL_REF_FRAME]);
1026 hantro_reg_write(vpu, &av1_skip_seg4,
1027 segval[4][V4L2_AV1_SEG_LVL_REF_SKIP]);
1028 hantro_reg_write(vpu, &av1_global_mv_seg4,
1029 segval[4][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
1030
1031 hantro_reg_write(vpu, &av1_quant_seg5,
1032 segval[5][V4L2_AV1_SEG_LVL_ALT_Q]);
1033 hantro_reg_write(vpu, &av1_filt_level_delta0_seg5,
1034 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
1035 hantro_reg_write(vpu, &av1_filt_level_delta1_seg5,
1036 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
1037 hantro_reg_write(vpu, &av1_filt_level_delta2_seg5,
1038 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_U]);
1039 hantro_reg_write(vpu, &av1_filt_level_delta3_seg5,
1040 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_V]);
1041 hantro_reg_write(vpu, &av1_refpic_seg5,
1042 segval[5][V4L2_AV1_SEG_LVL_REF_FRAME]);
1043 hantro_reg_write(vpu, &av1_skip_seg5,
1044 segval[5][V4L2_AV1_SEG_LVL_REF_SKIP]);
1045 hantro_reg_write(vpu, &av1_global_mv_seg5,
1046 segval[5][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
1047
1048 hantro_reg_write(vpu, &av1_quant_seg6,
1049 segval[6][V4L2_AV1_SEG_LVL_ALT_Q]);
1050 hantro_reg_write(vpu, &av1_filt_level_delta0_seg6,
1051 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
1052 hantro_reg_write(vpu, &av1_filt_level_delta1_seg6,
1053 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
1054 hantro_reg_write(vpu, &av1_filt_level_delta2_seg6,
1055 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_U]);
1056 hantro_reg_write(vpu, &av1_filt_level_delta3_seg6,
1057 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_V]);
1058 hantro_reg_write(vpu, &av1_refpic_seg6,
1059 segval[6][V4L2_AV1_SEG_LVL_REF_FRAME]);
1060 hantro_reg_write(vpu, &av1_skip_seg6,
1061 segval[6][V4L2_AV1_SEG_LVL_REF_SKIP]);
1062 hantro_reg_write(vpu, &av1_global_mv_seg6,
1063 segval[6][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
1064
1065 hantro_reg_write(vpu, &av1_quant_seg7,
1066 segval[7][V4L2_AV1_SEG_LVL_ALT_Q]);
1067 hantro_reg_write(vpu, &av1_filt_level_delta0_seg7,
1068 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]);
1069 hantro_reg_write(vpu, &av1_filt_level_delta1_seg7,
1070 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]);
1071 hantro_reg_write(vpu, &av1_filt_level_delta2_seg7,
1072 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_U]);
1073 hantro_reg_write(vpu, &av1_filt_level_delta3_seg7,
1074 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_V]);
1075 hantro_reg_write(vpu, &av1_refpic_seg7,
1076 segval[7][V4L2_AV1_SEG_LVL_REF_FRAME]);
1077 hantro_reg_write(vpu, &av1_skip_seg7,
1078 segval[7][V4L2_AV1_SEG_LVL_REF_SKIP]);
1079 hantro_reg_write(vpu, &av1_global_mv_seg7,
1080 segval[7][V4L2_AV1_SEG_LVL_REF_GLOBALMV]);
1081 }
1082
rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx * ctx)1083 static bool rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx *ctx)
1084 {
1085 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1086 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1087 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1088 const struct v4l2_av1_segmentation *segmentation = &frame->segmentation;
1089 const struct v4l2_av1_quantization *quantization = &frame->quantization;
1090 int i;
1091
1092 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) {
1093 int qindex = quantization->base_q_idx;
1094
1095 if (segmentation->feature_enabled[i] &
1096 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) {
1097 qindex += segmentation->feature_data[i][V4L2_AV1_SEG_LVL_ALT_Q];
1098 }
1099 qindex = clamp(qindex, 0, 255);
1100
1101 if (qindex ||
1102 quantization->delta_q_y_dc ||
1103 quantization->delta_q_u_dc ||
1104 quantization->delta_q_u_ac ||
1105 quantization->delta_q_v_dc ||
1106 quantization->delta_q_v_ac)
1107 return false;
1108 }
1109 return true;
1110 }
1111
rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx * ctx)1112 static void rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx *ctx)
1113 {
1114 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1115 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1116 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1117 const struct v4l2_av1_loop_filter *loop_filter = &frame->loop_filter;
1118 bool filtering_dis = (loop_filter->level[0] == 0) && (loop_filter->level[1] == 0);
1119 struct hantro_dev *vpu = ctx->dev;
1120
1121 hantro_reg_write(vpu, &av1_filtering_dis, filtering_dis);
1122 hantro_reg_write(vpu, &av1_filt_level_base_gt32, loop_filter->level[0] > 32);
1123 hantro_reg_write(vpu, &av1_filt_sharpness, loop_filter->sharpness);
1124
1125 hantro_reg_write(vpu, &av1_filt_level0, loop_filter->level[0]);
1126 hantro_reg_write(vpu, &av1_filt_level1, loop_filter->level[1]);
1127 hantro_reg_write(vpu, &av1_filt_level2, loop_filter->level[2]);
1128 hantro_reg_write(vpu, &av1_filt_level3, loop_filter->level[3]);
1129
1130 if (loop_filter->flags & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED &&
1131 !rockchip_vpu981_av1_dec_is_lossless(ctx) &&
1132 !(frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)) {
1133 hantro_reg_write(vpu, &av1_filt_ref_adj_0,
1134 loop_filter->ref_deltas[0]);
1135 hantro_reg_write(vpu, &av1_filt_ref_adj_1,
1136 loop_filter->ref_deltas[1]);
1137 hantro_reg_write(vpu, &av1_filt_ref_adj_2,
1138 loop_filter->ref_deltas[2]);
1139 hantro_reg_write(vpu, &av1_filt_ref_adj_3,
1140 loop_filter->ref_deltas[3]);
1141 hantro_reg_write(vpu, &av1_filt_ref_adj_4,
1142 loop_filter->ref_deltas[4]);
1143 hantro_reg_write(vpu, &av1_filt_ref_adj_5,
1144 loop_filter->ref_deltas[5]);
1145 hantro_reg_write(vpu, &av1_filt_ref_adj_6,
1146 loop_filter->ref_deltas[6]);
1147 hantro_reg_write(vpu, &av1_filt_ref_adj_7,
1148 loop_filter->ref_deltas[7]);
1149 hantro_reg_write(vpu, &av1_filt_mb_adj_0,
1150 loop_filter->mode_deltas[0]);
1151 hantro_reg_write(vpu, &av1_filt_mb_adj_1,
1152 loop_filter->mode_deltas[1]);
1153 } else {
1154 hantro_reg_write(vpu, &av1_filt_ref_adj_0, 0);
1155 hantro_reg_write(vpu, &av1_filt_ref_adj_1, 0);
1156 hantro_reg_write(vpu, &av1_filt_ref_adj_2, 0);
1157 hantro_reg_write(vpu, &av1_filt_ref_adj_3, 0);
1158 hantro_reg_write(vpu, &av1_filt_ref_adj_4, 0);
1159 hantro_reg_write(vpu, &av1_filt_ref_adj_5, 0);
1160 hantro_reg_write(vpu, &av1_filt_ref_adj_6, 0);
1161 hantro_reg_write(vpu, &av1_filt_ref_adj_7, 0);
1162 hantro_reg_write(vpu, &av1_filt_mb_adj_0, 0);
1163 hantro_reg_write(vpu, &av1_filt_mb_adj_1, 0);
1164 }
1165
1166 hantro_write_addr(vpu, AV1_DB_DATA_COL, av1_dec->db_data_col.dma);
1167 hantro_write_addr(vpu, AV1_DB_CTRL_COL, av1_dec->db_ctrl_col.dma);
1168 }
1169
rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx * ctx)1170 static void rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx *ctx)
1171 {
1172 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1173 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1174 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1175 bool frame_is_intra = IS_INTRA(frame->frame_type);
1176 struct av1cdfs *out_cdfs = (struct av1cdfs *)av1_dec->prob_tbl_out.cpu;
1177 int i;
1178
1179 if (frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF)
1180 return;
1181
1182 for (i = 0; i < NUM_REF_FRAMES; i++) {
1183 if (frame->refresh_frame_flags & BIT(i)) {
1184 struct mvcdfs stored_mv_cdf;
1185
1186 rockchip_av1_get_cdfs(ctx, i);
1187 stored_mv_cdf = av1_dec->cdfs->mv_cdf;
1188 *av1_dec->cdfs = *out_cdfs;
1189 if (frame_is_intra) {
1190 av1_dec->cdfs->mv_cdf = stored_mv_cdf;
1191 *av1_dec->cdfs_ndvc = out_cdfs->mv_cdf;
1192 }
1193 rockchip_av1_store_cdfs(ctx,
1194 frame->refresh_frame_flags);
1195 break;
1196 }
1197 }
1198 }
1199
rockchip_vpu981_av1_dec_done(struct hantro_ctx * ctx)1200 void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx)
1201 {
1202 rockchip_vpu981_av1_dec_update_prob(ctx);
1203 }
1204
rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx * ctx)1205 static void rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx *ctx)
1206 {
1207 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1208 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1209 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1210 const struct v4l2_av1_quantization *quantization = &frame->quantization;
1211 struct hantro_dev *vpu = ctx->dev;
1212 bool error_resilient_mode =
1213 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE);
1214 bool frame_is_intra = IS_INTRA(frame->frame_type);
1215
1216 if (error_resilient_mode || frame_is_intra ||
1217 frame->primary_ref_frame == AV1_PRIMARY_REF_NONE) {
1218 av1_dec->cdfs = &av1_dec->default_cdfs;
1219 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc;
1220 rockchip_av1_default_coeff_probs(quantization->base_q_idx,
1221 av1_dec->cdfs);
1222 } else {
1223 rockchip_av1_get_cdfs(ctx, frame->ref_frame_idx[frame->primary_ref_frame]);
1224 }
1225 rockchip_av1_store_cdfs(ctx, frame->refresh_frame_flags);
1226
1227 memcpy(av1_dec->prob_tbl.cpu, av1_dec->cdfs, sizeof(struct av1cdfs));
1228
1229 if (frame_is_intra) {
1230 int mv_offset = offsetof(struct av1cdfs, mv_cdf);
1231 /* Overwrite MV context area with intrabc MV context */
1232 memcpy(av1_dec->prob_tbl.cpu + mv_offset, av1_dec->cdfs_ndvc,
1233 sizeof(struct mvcdfs));
1234 }
1235
1236 hantro_write_addr(vpu, AV1_PROP_TABLE_OUT, av1_dec->prob_tbl_out.dma);
1237 hantro_write_addr(vpu, AV1_PROP_TABLE, av1_dec->prob_tbl.dma);
1238 }
1239
1240 static void
rockchip_vpu981_av1_dec_init_scaling_function(const u8 * values,const u8 * scaling,u8 num_points,u8 * scaling_lut)1241 rockchip_vpu981_av1_dec_init_scaling_function(const u8 *values, const u8 *scaling,
1242 u8 num_points, u8 *scaling_lut)
1243 {
1244 int i, point;
1245
1246 if (num_points == 0) {
1247 memset(scaling_lut, 0, 256);
1248 return;
1249 }
1250
1251 for (point = 0; point < num_points - 1; point++) {
1252 int x;
1253 s32 delta_y = scaling[point + 1] - scaling[point];
1254 s32 delta_x = values[point + 1] - values[point];
1255 s64 delta =
1256 delta_x ? delta_y * ((65536 + (delta_x >> 1)) /
1257 delta_x) : 0;
1258
1259 for (x = 0; x < delta_x; x++) {
1260 scaling_lut[values[point] + x] =
1261 scaling[point] +
1262 (s32)((x * delta + 32768) >> 16);
1263 }
1264 }
1265
1266 for (i = values[num_points - 1]; i < 256; i++)
1267 scaling_lut[i] = scaling[num_points - 1];
1268 }
1269
rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx * ctx)1270 static void rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx *ctx)
1271 {
1272 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1273 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1274 const struct v4l2_ctrl_av1_film_grain *film_grain = ctrls->film_grain;
1275 struct rockchip_av1_film_grain *fgmem = av1_dec->film_grain.cpu;
1276 struct hantro_dev *vpu = ctx->dev;
1277 bool scaling_from_luma =
1278 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA);
1279 s32 (*ar_coeffs_y)[24];
1280 s32 (*ar_coeffs_cb)[25];
1281 s32 (*ar_coeffs_cr)[25];
1282 s32 (*luma_grain_block)[73][82];
1283 s32 (*cb_grain_block)[38][44];
1284 s32 (*cr_grain_block)[38][44];
1285 s32 ar_coeff_lag, ar_coeff_shift;
1286 s32 grain_scale_shift, bitdepth;
1287 s32 grain_center, grain_min, grain_max;
1288 int i, j;
1289
1290 hantro_reg_write(vpu, &av1_apply_grain, 0);
1291
1292 if (!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN)) {
1293 hantro_reg_write(vpu, &av1_num_y_points_b, 0);
1294 hantro_reg_write(vpu, &av1_num_cb_points_b, 0);
1295 hantro_reg_write(vpu, &av1_num_cr_points_b, 0);
1296 hantro_reg_write(vpu, &av1_scaling_shift, 0);
1297 hantro_reg_write(vpu, &av1_cb_mult, 0);
1298 hantro_reg_write(vpu, &av1_cb_luma_mult, 0);
1299 hantro_reg_write(vpu, &av1_cb_offset, 0);
1300 hantro_reg_write(vpu, &av1_cr_mult, 0);
1301 hantro_reg_write(vpu, &av1_cr_luma_mult, 0);
1302 hantro_reg_write(vpu, &av1_cr_offset, 0);
1303 hantro_reg_write(vpu, &av1_overlap_flag, 0);
1304 hantro_reg_write(vpu, &av1_clip_to_restricted_range, 0);
1305 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, 0);
1306 hantro_reg_write(vpu, &av1_random_seed, 0);
1307 hantro_write_addr(vpu, AV1_FILM_GRAIN, 0);
1308 return;
1309 }
1310
1311 ar_coeffs_y = kzalloc(sizeof(int32_t) * 24, GFP_KERNEL);
1312 ar_coeffs_cb = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL);
1313 ar_coeffs_cr = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL);
1314 luma_grain_block = kzalloc(sizeof(int32_t) * 73 * 82, GFP_KERNEL);
1315 cb_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL);
1316 cr_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL);
1317
1318 if (!ar_coeffs_y || !ar_coeffs_cb || !ar_coeffs_cr ||
1319 !luma_grain_block || !cb_grain_block || !cr_grain_block) {
1320 pr_warn("Fail allocating memory for film grain parameters\n");
1321 goto alloc_fail;
1322 }
1323
1324 hantro_reg_write(vpu, &av1_apply_grain, 1);
1325
1326 hantro_reg_write(vpu, &av1_num_y_points_b,
1327 film_grain->num_y_points > 0);
1328 hantro_reg_write(vpu, &av1_num_cb_points_b,
1329 film_grain->num_cb_points > 0);
1330 hantro_reg_write(vpu, &av1_num_cr_points_b,
1331 film_grain->num_cr_points > 0);
1332 hantro_reg_write(vpu, &av1_scaling_shift,
1333 film_grain->grain_scaling_minus_8 + 8);
1334
1335 if (!scaling_from_luma) {
1336 hantro_reg_write(vpu, &av1_cb_mult, film_grain->cb_mult - 128);
1337 hantro_reg_write(vpu, &av1_cb_luma_mult, film_grain->cb_luma_mult - 128);
1338 hantro_reg_write(vpu, &av1_cb_offset, film_grain->cb_offset - 256);
1339 hantro_reg_write(vpu, &av1_cr_mult, film_grain->cr_mult - 128);
1340 hantro_reg_write(vpu, &av1_cr_luma_mult, film_grain->cr_luma_mult - 128);
1341 hantro_reg_write(vpu, &av1_cr_offset, film_grain->cr_offset - 256);
1342 } else {
1343 hantro_reg_write(vpu, &av1_cb_mult, 0);
1344 hantro_reg_write(vpu, &av1_cb_luma_mult, 0);
1345 hantro_reg_write(vpu, &av1_cb_offset, 0);
1346 hantro_reg_write(vpu, &av1_cr_mult, 0);
1347 hantro_reg_write(vpu, &av1_cr_luma_mult, 0);
1348 hantro_reg_write(vpu, &av1_cr_offset, 0);
1349 }
1350
1351 hantro_reg_write(vpu, &av1_overlap_flag,
1352 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP));
1353 hantro_reg_write(vpu, &av1_clip_to_restricted_range,
1354 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE));
1355 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, scaling_from_luma);
1356 hantro_reg_write(vpu, &av1_random_seed, film_grain->grain_seed);
1357
1358 rockchip_vpu981_av1_dec_init_scaling_function(film_grain->point_y_value,
1359 film_grain->point_y_scaling,
1360 film_grain->num_y_points,
1361 fgmem->scaling_lut_y);
1362
1363 if (film_grain->flags &
1364 V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA) {
1365 memcpy(fgmem->scaling_lut_cb, fgmem->scaling_lut_y,
1366 sizeof(*fgmem->scaling_lut_y) * 256);
1367 memcpy(fgmem->scaling_lut_cr, fgmem->scaling_lut_y,
1368 sizeof(*fgmem->scaling_lut_y) * 256);
1369 } else {
1370 rockchip_vpu981_av1_dec_init_scaling_function
1371 (film_grain->point_cb_value, film_grain->point_cb_scaling,
1372 film_grain->num_cb_points, fgmem->scaling_lut_cb);
1373 rockchip_vpu981_av1_dec_init_scaling_function
1374 (film_grain->point_cr_value, film_grain->point_cr_scaling,
1375 film_grain->num_cr_points, fgmem->scaling_lut_cr);
1376 }
1377
1378 for (i = 0; i < V4L2_AV1_AR_COEFFS_SIZE; i++) {
1379 if (i < 24)
1380 (*ar_coeffs_y)[i] = film_grain->ar_coeffs_y_plus_128[i] - 128;
1381 (*ar_coeffs_cb)[i] = film_grain->ar_coeffs_cb_plus_128[i] - 128;
1382 (*ar_coeffs_cr)[i] = film_grain->ar_coeffs_cr_plus_128[i] - 128;
1383 }
1384
1385 ar_coeff_lag = film_grain->ar_coeff_lag;
1386 ar_coeff_shift = film_grain->ar_coeff_shift_minus_6 + 6;
1387 grain_scale_shift = film_grain->grain_scale_shift;
1388 bitdepth = ctx->bit_depth;
1389 grain_center = 128 << (bitdepth - 8);
1390 grain_min = 0 - grain_center;
1391 grain_max = (256 << (bitdepth - 8)) - 1 - grain_center;
1392
1393 rockchip_av1_generate_luma_grain_block(luma_grain_block, bitdepth,
1394 film_grain->num_y_points, grain_scale_shift,
1395 ar_coeff_lag, ar_coeffs_y, ar_coeff_shift,
1396 grain_min, grain_max, film_grain->grain_seed);
1397
1398 rockchip_av1_generate_chroma_grain_block(luma_grain_block, cb_grain_block,
1399 cr_grain_block, bitdepth,
1400 film_grain->num_y_points,
1401 film_grain->num_cb_points,
1402 film_grain->num_cr_points,
1403 grain_scale_shift, ar_coeff_lag, ar_coeffs_cb,
1404 ar_coeffs_cr, ar_coeff_shift, grain_min,
1405 grain_max,
1406 scaling_from_luma,
1407 film_grain->grain_seed);
1408
1409 for (i = 0; i < 64; i++) {
1410 for (j = 0; j < 64; j++)
1411 fgmem->cropped_luma_grain_block[i * 64 + j] =
1412 (*luma_grain_block)[i + 9][j + 9];
1413 }
1414
1415 for (i = 0; i < 32; i++) {
1416 for (j = 0; j < 32; j++) {
1417 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j] =
1418 (*cb_grain_block)[i + 6][j + 6];
1419 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j + 1] =
1420 (*cr_grain_block)[i + 6][j + 6];
1421 }
1422 }
1423
1424 hantro_write_addr(vpu, AV1_FILM_GRAIN, av1_dec->film_grain.dma);
1425
1426 alloc_fail:
1427 kfree(ar_coeffs_y);
1428 kfree(ar_coeffs_cb);
1429 kfree(ar_coeffs_cr);
1430 kfree(luma_grain_block);
1431 kfree(cb_grain_block);
1432 kfree(cr_grain_block);
1433 }
1434
rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx * ctx)1435 static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx)
1436 {
1437 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1438 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1439 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1440 const struct v4l2_av1_cdef *cdef = &frame->cdef;
1441 struct hantro_dev *vpu = ctx->dev;
1442 u32 luma_pri_strength = 0;
1443 u16 luma_sec_strength = 0;
1444 u32 chroma_pri_strength = 0;
1445 u16 chroma_sec_strength = 0;
1446 bool enable_cdef;
1447 int i;
1448
1449 enable_cdef = !(cdef->bits == 0 &&
1450 cdef->damping_minus_3 == 0 &&
1451 cdef->y_pri_strength[0] == 0 &&
1452 cdef->y_sec_strength[0] == 0 &&
1453 cdef->uv_pri_strength[0] == 0 &&
1454 cdef->uv_sec_strength[0] == 0);
1455 hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef);
1456 hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits);
1457 hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3);
1458
1459 for (i = 0; i < BIT(cdef->bits); i++) {
1460 luma_pri_strength |= cdef->y_pri_strength[i] << (i * 4);
1461 if (cdef->y_sec_strength[i] == 4)
1462 luma_sec_strength |= 3 << (i * 2);
1463 else
1464 luma_sec_strength |= cdef->y_sec_strength[i] << (i * 2);
1465
1466 chroma_pri_strength |= cdef->uv_pri_strength[i] << (i * 4);
1467 if (cdef->uv_sec_strength[i] == 4)
1468 chroma_sec_strength |= 3 << (i * 2);
1469 else
1470 chroma_sec_strength |= cdef->uv_sec_strength[i] << (i * 2);
1471 }
1472
1473 hantro_reg_write(vpu, &av1_cdef_luma_primary_strength,
1474 luma_pri_strength);
1475 hantro_reg_write(vpu, &av1_cdef_luma_secondary_strength,
1476 luma_sec_strength);
1477 hantro_reg_write(vpu, &av1_cdef_chroma_primary_strength,
1478 chroma_pri_strength);
1479 hantro_reg_write(vpu, &av1_cdef_chroma_secondary_strength,
1480 chroma_sec_strength);
1481
1482 hantro_write_addr(vpu, AV1_CDEF_COL, av1_dec->cdef_col.dma);
1483 }
1484
rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx * ctx)1485 static void rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx *ctx)
1486 {
1487 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1488 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1489 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1490 const struct v4l2_av1_loop_restoration *loop_restoration =
1491 &frame->loop_restoration;
1492 struct hantro_dev *vpu = ctx->dev;
1493 u16 lr_type = 0, lr_unit_size = 0;
1494 u8 restoration_unit_size[V4L2_AV1_NUM_PLANES_MAX] = { 3, 3, 3 };
1495 int i;
1496
1497 if (loop_restoration->flags & V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR) {
1498 restoration_unit_size[0] = 1 + loop_restoration->lr_unit_shift;
1499 restoration_unit_size[1] =
1500 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift;
1501 restoration_unit_size[2] =
1502 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift;
1503 }
1504
1505 for (i = 0; i < V4L2_AV1_NUM_PLANES_MAX; i++) {
1506 lr_type |=
1507 loop_restoration->frame_restoration_type[i] << (i * 2);
1508 lr_unit_size |= restoration_unit_size[i] << (i * 2);
1509 }
1510
1511 hantro_reg_write(vpu, &av1_lr_type, lr_type);
1512 hantro_reg_write(vpu, &av1_lr_unit_size, lr_unit_size);
1513 hantro_write_addr(vpu, AV1_LR_COL, av1_dec->lr_col.dma);
1514 }
1515
rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx * ctx)1516 static void rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx *ctx)
1517 {
1518 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1519 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1520 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1521 struct hantro_dev *vpu = ctx->dev;
1522 u8 superres_scale_denominator = SCALE_NUMERATOR;
1523 int superres_luma_step = RS_SCALE_SUBPEL_BITS;
1524 int superres_chroma_step = RS_SCALE_SUBPEL_BITS;
1525 int superres_luma_step_invra = RS_SCALE_SUBPEL_BITS;
1526 int superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS;
1527 int superres_init_luma_subpel_x = 0;
1528 int superres_init_chroma_subpel_x = 0;
1529 int superres_is_scaled = 0;
1530 int min_w = min_t(uint32_t, 16, frame->upscaled_width);
1531 int upscaled_luma, downscaled_luma;
1532 int downscaled_chroma, upscaled_chroma;
1533 int step_luma, step_chroma;
1534 int err_luma, err_chroma;
1535 int initial_luma, initial_chroma;
1536 int width = 0;
1537
1538 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES)
1539 superres_scale_denominator = frame->superres_denom;
1540
1541 if (superres_scale_denominator <= SCALE_NUMERATOR)
1542 goto set_regs;
1543
1544 width = (frame->upscaled_width * SCALE_NUMERATOR +
1545 (superres_scale_denominator / 2)) / superres_scale_denominator;
1546
1547 if (width < min_w)
1548 width = min_w;
1549
1550 if (width == frame->upscaled_width)
1551 goto set_regs;
1552
1553 superres_is_scaled = 1;
1554 upscaled_luma = frame->upscaled_width;
1555 downscaled_luma = width;
1556 downscaled_chroma = (downscaled_luma + 1) >> 1;
1557 upscaled_chroma = (upscaled_luma + 1) >> 1;
1558 step_luma =
1559 ((downscaled_luma << RS_SCALE_SUBPEL_BITS) +
1560 (upscaled_luma / 2)) / upscaled_luma;
1561 step_chroma =
1562 ((downscaled_chroma << RS_SCALE_SUBPEL_BITS) +
1563 (upscaled_chroma / 2)) / upscaled_chroma;
1564 err_luma =
1565 (upscaled_luma * step_luma)
1566 - (downscaled_luma << RS_SCALE_SUBPEL_BITS);
1567 err_chroma =
1568 (upscaled_chroma * step_chroma)
1569 - (downscaled_chroma << RS_SCALE_SUBPEL_BITS);
1570 initial_luma =
1571 ((-((upscaled_luma - downscaled_luma) << (RS_SCALE_SUBPEL_BITS - 1))
1572 + upscaled_luma / 2)
1573 / upscaled_luma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_luma / 2)
1574 & RS_SCALE_SUBPEL_MASK;
1575 initial_chroma =
1576 ((-((upscaled_chroma - downscaled_chroma) << (RS_SCALE_SUBPEL_BITS - 1))
1577 + upscaled_chroma / 2)
1578 / upscaled_chroma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_chroma / 2)
1579 & RS_SCALE_SUBPEL_MASK;
1580 superres_luma_step = step_luma;
1581 superres_chroma_step = step_chroma;
1582 superres_luma_step_invra =
1583 ((upscaled_luma << RS_SCALE_SUBPEL_BITS) + (downscaled_luma / 2))
1584 / downscaled_luma;
1585 superres_chroma_step_invra =
1586 ((upscaled_chroma << RS_SCALE_SUBPEL_BITS) + (downscaled_chroma / 2))
1587 / downscaled_chroma;
1588 superres_init_luma_subpel_x = initial_luma;
1589 superres_init_chroma_subpel_x = initial_chroma;
1590
1591 set_regs:
1592 hantro_reg_write(vpu, &av1_superres_pic_width, frame->upscaled_width);
1593
1594 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES)
1595 hantro_reg_write(vpu, &av1_scale_denom_minus9,
1596 frame->superres_denom - SUPERRES_SCALE_DENOMINATOR_MIN);
1597 else
1598 hantro_reg_write(vpu, &av1_scale_denom_minus9, frame->superres_denom);
1599
1600 hantro_reg_write(vpu, &av1_superres_luma_step, superres_luma_step);
1601 hantro_reg_write(vpu, &av1_superres_chroma_step, superres_chroma_step);
1602 hantro_reg_write(vpu, &av1_superres_luma_step_invra,
1603 superres_luma_step_invra);
1604 hantro_reg_write(vpu, &av1_superres_chroma_step_invra,
1605 superres_chroma_step_invra);
1606 hantro_reg_write(vpu, &av1_superres_init_luma_subpel_x,
1607 superres_init_luma_subpel_x);
1608 hantro_reg_write(vpu, &av1_superres_init_chroma_subpel_x,
1609 superres_init_chroma_subpel_x);
1610 hantro_reg_write(vpu, &av1_superres_is_scaled, superres_is_scaled);
1611
1612 hantro_write_addr(vpu, AV1_SR_COL, av1_dec->sr_col.dma);
1613 }
1614
rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx * ctx)1615 static void rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx *ctx)
1616 {
1617 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1618 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1619 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1620 struct hantro_dev *vpu = ctx->dev;
1621 int pic_width_in_cbs = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8);
1622 int pic_height_in_cbs = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8);
1623 int pic_width_pad = ALIGN(frame->frame_width_minus_1 + 1, 8)
1624 - (frame->frame_width_minus_1 + 1);
1625 int pic_height_pad = ALIGN(frame->frame_height_minus_1 + 1, 8)
1626 - (frame->frame_height_minus_1 + 1);
1627
1628 hantro_reg_write(vpu, &av1_pic_width_in_cbs, pic_width_in_cbs);
1629 hantro_reg_write(vpu, &av1_pic_height_in_cbs, pic_height_in_cbs);
1630 hantro_reg_write(vpu, &av1_pic_width_pad, pic_width_pad);
1631 hantro_reg_write(vpu, &av1_pic_height_pad, pic_height_pad);
1632
1633 rockchip_vpu981_av1_dec_set_superres_params(ctx);
1634 }
1635
rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx * ctx)1636 static void rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx *ctx)
1637 {
1638 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1639 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1640 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1641 struct hantro_dev *vpu = ctx->dev;
1642 bool use_ref_frame_mvs =
1643 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS);
1644 int cur_frame_offset = frame->order_hint;
1645 int alt_frame_offset = 0;
1646 int gld_frame_offset = 0;
1647 int bwd_frame_offset = 0;
1648 int alt2_frame_offset = 0;
1649 int refs_selected[3] = { 0, 0, 0 };
1650 int cur_mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8);
1651 int cur_mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8);
1652 int cur_offset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1];
1653 int cur_roffset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1];
1654 int mf_types[3] = { 0, 0, 0 };
1655 int ref_stamp = 2;
1656 int ref_ind = 0;
1657 int rf, idx;
1658
1659 alt_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT_BUF_IDX);
1660 gld_frame_offset = rockchip_vpu981_get_order_hint(ctx, GLD_BUF_IDX);
1661 bwd_frame_offset = rockchip_vpu981_get_order_hint(ctx, BWD_BUF_IDX);
1662 alt2_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT2_BUF_IDX);
1663
1664 idx = rockchip_vpu981_get_frame_index(ctx, LST_BUF_IDX);
1665 if (idx >= 0) {
1666 int alt_frame_offset_in_lst =
1667 av1_dec->frame_refs[idx].order_hints[V4L2_AV1_REF_ALTREF_FRAME];
1668 bool is_lst_overlay =
1669 (alt_frame_offset_in_lst == gld_frame_offset);
1670
1671 if (!is_lst_overlay) {
1672 int lst_mi_cols = av1_dec->frame_refs[idx].mi_cols;
1673 int lst_mi_rows = av1_dec->frame_refs[idx].mi_rows;
1674 bool lst_intra_only =
1675 IS_INTRA(av1_dec->frame_refs[idx].frame_type);
1676
1677 if (lst_mi_cols == cur_mi_cols &&
1678 lst_mi_rows == cur_mi_rows && !lst_intra_only) {
1679 mf_types[ref_ind] = V4L2_AV1_REF_LAST_FRAME;
1680 refs_selected[ref_ind++] = LST_BUF_IDX;
1681 }
1682 }
1683 ref_stamp--;
1684 }
1685
1686 idx = rockchip_vpu981_get_frame_index(ctx, BWD_BUF_IDX);
1687 if (rockchip_vpu981_av1_dec_get_dist(ctx, bwd_frame_offset, cur_frame_offset) > 0) {
1688 int bwd_mi_cols = av1_dec->frame_refs[idx].mi_cols;
1689 int bwd_mi_rows = av1_dec->frame_refs[idx].mi_rows;
1690 bool bwd_intra_only =
1691 IS_INTRA(av1_dec->frame_refs[idx].frame_type);
1692
1693 if (bwd_mi_cols == cur_mi_cols && bwd_mi_rows == cur_mi_rows &&
1694 !bwd_intra_only) {
1695 mf_types[ref_ind] = V4L2_AV1_REF_BWDREF_FRAME;
1696 refs_selected[ref_ind++] = BWD_BUF_IDX;
1697 ref_stamp--;
1698 }
1699 }
1700
1701 idx = rockchip_vpu981_get_frame_index(ctx, ALT2_BUF_IDX);
1702 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt2_frame_offset, cur_frame_offset) > 0) {
1703 int alt2_mi_cols = av1_dec->frame_refs[idx].mi_cols;
1704 int alt2_mi_rows = av1_dec->frame_refs[idx].mi_rows;
1705 bool alt2_intra_only =
1706 IS_INTRA(av1_dec->frame_refs[idx].frame_type);
1707
1708 if (alt2_mi_cols == cur_mi_cols && alt2_mi_rows == cur_mi_rows &&
1709 !alt2_intra_only) {
1710 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF2_FRAME;
1711 refs_selected[ref_ind++] = ALT2_BUF_IDX;
1712 ref_stamp--;
1713 }
1714 }
1715
1716 idx = rockchip_vpu981_get_frame_index(ctx, ALT_BUF_IDX);
1717 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt_frame_offset, cur_frame_offset) > 0 &&
1718 ref_stamp >= 0) {
1719 int alt_mi_cols = av1_dec->frame_refs[idx].mi_cols;
1720 int alt_mi_rows = av1_dec->frame_refs[idx].mi_rows;
1721 bool alt_intra_only =
1722 IS_INTRA(av1_dec->frame_refs[idx].frame_type);
1723
1724 if (alt_mi_cols == cur_mi_cols && alt_mi_rows == cur_mi_rows &&
1725 !alt_intra_only) {
1726 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF_FRAME;
1727 refs_selected[ref_ind++] = ALT_BUF_IDX;
1728 ref_stamp--;
1729 }
1730 }
1731
1732 idx = rockchip_vpu981_get_frame_index(ctx, LST2_BUF_IDX);
1733 if (idx >= 0 && ref_stamp >= 0) {
1734 int lst2_mi_cols = av1_dec->frame_refs[idx].mi_cols;
1735 int lst2_mi_rows = av1_dec->frame_refs[idx].mi_rows;
1736 bool lst2_intra_only =
1737 IS_INTRA(av1_dec->frame_refs[idx].frame_type);
1738
1739 if (lst2_mi_cols == cur_mi_cols && lst2_mi_rows == cur_mi_rows &&
1740 !lst2_intra_only) {
1741 mf_types[ref_ind] = V4L2_AV1_REF_LAST2_FRAME;
1742 refs_selected[ref_ind++] = LST2_BUF_IDX;
1743 ref_stamp--;
1744 }
1745 }
1746
1747 for (rf = 0; rf < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; ++rf) {
1748 idx = rockchip_vpu981_get_frame_index(ctx, rf);
1749 if (idx >= 0) {
1750 int rf_order_hint = rockchip_vpu981_get_order_hint(ctx, rf);
1751
1752 cur_offset[rf] =
1753 rockchip_vpu981_av1_dec_get_dist(ctx, cur_frame_offset, rf_order_hint);
1754 cur_roffset[rf] =
1755 rockchip_vpu981_av1_dec_get_dist(ctx, rf_order_hint, cur_frame_offset);
1756 } else {
1757 cur_offset[rf] = 0;
1758 cur_roffset[rf] = 0;
1759 }
1760 }
1761
1762 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 0);
1763 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 0);
1764 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 0);
1765 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0);
1766
1767 hantro_reg_write(vpu, &av1_mf1_last_offset, 0);
1768 hantro_reg_write(vpu, &av1_mf1_last2_offset, 0);
1769 hantro_reg_write(vpu, &av1_mf1_last3_offset, 0);
1770 hantro_reg_write(vpu, &av1_mf1_golden_offset, 0);
1771 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, 0);
1772 hantro_reg_write(vpu, &av1_mf1_altref2_offset, 0);
1773 hantro_reg_write(vpu, &av1_mf1_altref_offset, 0);
1774
1775 if (use_ref_frame_mvs && ref_ind > 0 &&
1776 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE &&
1777 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) {
1778 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[0]);
1779 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[0]);
1780 u32 *oh = av1_dec->frame_refs[idx].order_hints;
1781 int val;
1782
1783 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 1);
1784
1785 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]);
1786 hantro_reg_write(vpu, &av1_mf1_last_offset, val);
1787
1788 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]);
1789 hantro_reg_write(vpu, &av1_mf1_last2_offset, val);
1790
1791 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]);
1792 hantro_reg_write(vpu, &av1_mf1_last3_offset, val);
1793
1794 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]);
1795 hantro_reg_write(vpu, &av1_mf1_golden_offset, val);
1796
1797 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]);
1798 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, val);
1799
1800 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]);
1801 hantro_reg_write(vpu, &av1_mf1_altref2_offset, val);
1802
1803 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]);
1804 hantro_reg_write(vpu, &av1_mf1_altref_offset, val);
1805 }
1806
1807 hantro_reg_write(vpu, &av1_mf2_last_offset, 0);
1808 hantro_reg_write(vpu, &av1_mf2_last2_offset, 0);
1809 hantro_reg_write(vpu, &av1_mf2_last3_offset, 0);
1810 hantro_reg_write(vpu, &av1_mf2_golden_offset, 0);
1811 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, 0);
1812 hantro_reg_write(vpu, &av1_mf2_altref2_offset, 0);
1813 hantro_reg_write(vpu, &av1_mf2_altref_offset, 0);
1814
1815 if (use_ref_frame_mvs && ref_ind > 1 &&
1816 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE &&
1817 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) {
1818 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[1]);
1819 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[1]);
1820 u32 *oh = av1_dec->frame_refs[idx].order_hints;
1821 int val;
1822
1823 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 1);
1824
1825 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]);
1826 hantro_reg_write(vpu, &av1_mf2_last_offset, val);
1827
1828 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]);
1829 hantro_reg_write(vpu, &av1_mf2_last2_offset, val);
1830
1831 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]);
1832 hantro_reg_write(vpu, &av1_mf2_last3_offset, val);
1833
1834 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]);
1835 hantro_reg_write(vpu, &av1_mf2_golden_offset, val);
1836
1837 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]);
1838 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, val);
1839
1840 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]);
1841 hantro_reg_write(vpu, &av1_mf2_altref2_offset, val);
1842
1843 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]);
1844 hantro_reg_write(vpu, &av1_mf2_altref_offset, val);
1845 }
1846
1847 hantro_reg_write(vpu, &av1_mf3_last_offset, 0);
1848 hantro_reg_write(vpu, &av1_mf3_last2_offset, 0);
1849 hantro_reg_write(vpu, &av1_mf3_last3_offset, 0);
1850 hantro_reg_write(vpu, &av1_mf3_golden_offset, 0);
1851 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, 0);
1852 hantro_reg_write(vpu, &av1_mf3_altref2_offset, 0);
1853 hantro_reg_write(vpu, &av1_mf3_altref_offset, 0);
1854
1855 if (use_ref_frame_mvs && ref_ind > 2 &&
1856 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE &&
1857 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) {
1858 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[2]);
1859 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[2]);
1860 u32 *oh = av1_dec->frame_refs[idx].order_hints;
1861 int val;
1862
1863 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 1);
1864
1865 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]);
1866 hantro_reg_write(vpu, &av1_mf3_last_offset, val);
1867
1868 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]);
1869 hantro_reg_write(vpu, &av1_mf3_last2_offset, val);
1870
1871 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]);
1872 hantro_reg_write(vpu, &av1_mf3_last3_offset, val);
1873
1874 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]);
1875 hantro_reg_write(vpu, &av1_mf3_golden_offset, val);
1876
1877 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]);
1878 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, val);
1879
1880 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]);
1881 hantro_reg_write(vpu, &av1_mf3_altref2_offset, val);
1882
1883 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]);
1884 hantro_reg_write(vpu, &av1_mf3_altref_offset, val);
1885 }
1886
1887 hantro_reg_write(vpu, &av1_cur_last_offset, cur_offset[0]);
1888 hantro_reg_write(vpu, &av1_cur_last2_offset, cur_offset[1]);
1889 hantro_reg_write(vpu, &av1_cur_last3_offset, cur_offset[2]);
1890 hantro_reg_write(vpu, &av1_cur_golden_offset, cur_offset[3]);
1891 hantro_reg_write(vpu, &av1_cur_bwdref_offset, cur_offset[4]);
1892 hantro_reg_write(vpu, &av1_cur_altref2_offset, cur_offset[5]);
1893 hantro_reg_write(vpu, &av1_cur_altref_offset, cur_offset[6]);
1894
1895 hantro_reg_write(vpu, &av1_cur_last_roffset, cur_roffset[0]);
1896 hantro_reg_write(vpu, &av1_cur_last2_roffset, cur_roffset[1]);
1897 hantro_reg_write(vpu, &av1_cur_last3_roffset, cur_roffset[2]);
1898 hantro_reg_write(vpu, &av1_cur_golden_roffset, cur_roffset[3]);
1899 hantro_reg_write(vpu, &av1_cur_bwdref_roffset, cur_roffset[4]);
1900 hantro_reg_write(vpu, &av1_cur_altref2_roffset, cur_roffset[5]);
1901 hantro_reg_write(vpu, &av1_cur_altref_roffset, cur_roffset[6]);
1902
1903 hantro_reg_write(vpu, &av1_mf1_type, mf_types[0] - V4L2_AV1_REF_LAST_FRAME);
1904 hantro_reg_write(vpu, &av1_mf2_type, mf_types[1] - V4L2_AV1_REF_LAST_FRAME);
1905 hantro_reg_write(vpu, &av1_mf3_type, mf_types[2] - V4L2_AV1_REF_LAST_FRAME);
1906 }
1907
rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx * ctx)1908 static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx)
1909 {
1910 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
1911 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
1912 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
1913 int frame_type = frame->frame_type;
1914 bool allow_intrabc = !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC);
1915 int ref_count[AV1DEC_MAX_PIC_BUFFERS] = { 0 };
1916 struct hantro_dev *vpu = ctx->dev;
1917 int i, ref_frames = 0;
1918 bool scale_enable = false;
1919
1920 if (IS_INTRA(frame_type) && !allow_intrabc)
1921 return;
1922
1923 if (!allow_intrabc) {
1924 for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) {
1925 int idx = rockchip_vpu981_get_frame_index(ctx, i);
1926
1927 if (idx >= 0)
1928 ref_count[idx]++;
1929 }
1930
1931 for (i = 0; i < AV1DEC_MAX_PIC_BUFFERS; i++) {
1932 if (ref_count[i])
1933 ref_frames++;
1934 }
1935 } else {
1936 ref_frames = 1;
1937 }
1938 hantro_reg_write(vpu, &av1_ref_frames, ref_frames);
1939
1940 rockchip_vpu981_av1_dec_set_frame_sign_bias(ctx);
1941
1942 for (i = V4L2_AV1_REF_LAST_FRAME; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) {
1943 u32 ref = i - 1;
1944 int idx = 0;
1945 int width, height;
1946
1947 if (allow_intrabc) {
1948 idx = av1_dec->current_frame_index;
1949 width = frame->frame_width_minus_1 + 1;
1950 height = frame->frame_height_minus_1 + 1;
1951 } else {
1952 if (rockchip_vpu981_get_frame_index(ctx, ref) > 0)
1953 idx = rockchip_vpu981_get_frame_index(ctx, ref);
1954 width = av1_dec->frame_refs[idx].width;
1955 height = av1_dec->frame_refs[idx].height;
1956 }
1957
1958 scale_enable |=
1959 rockchip_vpu981_av1_dec_set_ref(ctx, ref, idx, width,
1960 height);
1961
1962 rockchip_vpu981_av1_dec_set_sign_bias(ctx, ref,
1963 av1_dec->ref_frame_sign_bias[i]);
1964 }
1965 hantro_reg_write(vpu, &av1_ref_scaling_enable, scale_enable);
1966
1967 hantro_reg_write(vpu, &av1_ref0_gm_mode,
1968 frame->global_motion.type[V4L2_AV1_REF_LAST_FRAME]);
1969 hantro_reg_write(vpu, &av1_ref1_gm_mode,
1970 frame->global_motion.type[V4L2_AV1_REF_LAST2_FRAME]);
1971 hantro_reg_write(vpu, &av1_ref2_gm_mode,
1972 frame->global_motion.type[V4L2_AV1_REF_LAST3_FRAME]);
1973 hantro_reg_write(vpu, &av1_ref3_gm_mode,
1974 frame->global_motion.type[V4L2_AV1_REF_GOLDEN_FRAME]);
1975 hantro_reg_write(vpu, &av1_ref4_gm_mode,
1976 frame->global_motion.type[V4L2_AV1_REF_BWDREF_FRAME]);
1977 hantro_reg_write(vpu, &av1_ref5_gm_mode,
1978 frame->global_motion.type[V4L2_AV1_REF_ALTREF2_FRAME]);
1979 hantro_reg_write(vpu, &av1_ref6_gm_mode,
1980 frame->global_motion.type[V4L2_AV1_REF_ALTREF_FRAME]);
1981
1982 rockchip_vpu981_av1_dec_set_other_frames(ctx);
1983 }
1984
rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode)1985 static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode)
1986 {
1987 switch (tx_mode) {
1988 case V4L2_AV1_TX_MODE_ONLY_4X4:
1989 return ROCKCHIP_AV1_TX_MODE_ONLY_4X4;
1990 case V4L2_AV1_TX_MODE_LARGEST:
1991 return ROCKCHIP_AV1_TX_MODE_32x32;
1992 case V4L2_AV1_TX_MODE_SELECT:
1993 return ROCKCHIP_AV1_TX_MODE_SELECT;
1994 }
1995
1996 return ROCKCHIP_AV1_TX_MODE_32x32;
1997 }
1998
rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx * ctx)1999 static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
2000 {
2001 struct hantro_dev *vpu = ctx->dev;
2002 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
2003 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
2004 int tx_mode;
2005
2006 hantro_reg_write(vpu, &av1_skip_mode,
2007 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT));
2008 hantro_reg_write(vpu, &av1_tempor_mvp_e,
2009 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS));
2010 hantro_reg_write(vpu, &av1_delta_lf_res_log,
2011 ctrls->frame->loop_filter.delta_lf_res);
2012 hantro_reg_write(vpu, &av1_delta_lf_multi,
2013 !!(ctrls->frame->loop_filter.flags
2014 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI));
2015 hantro_reg_write(vpu, &av1_delta_lf_present,
2016 !!(ctrls->frame->loop_filter.flags
2017 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT));
2018 hantro_reg_write(vpu, &av1_disable_cdf_update,
2019 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE));
2020 hantro_reg_write(vpu, &av1_allow_warp,
2021 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION));
2022 hantro_reg_write(vpu, &av1_show_frame,
2023 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME));
2024 hantro_reg_write(vpu, &av1_switchable_motion_mode,
2025 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE));
2026 hantro_reg_write(vpu, &av1_allow_masked_compound,
2027 !!(ctrls->sequence->flags
2028 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND));
2029 hantro_reg_write(vpu, &av1_allow_interintra,
2030 !!(ctrls->sequence->flags
2031 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND));
2032 hantro_reg_write(vpu, &av1_enable_intra_edge_filter,
2033 !!(ctrls->sequence->flags
2034 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER));
2035 hantro_reg_write(vpu, &av1_allow_filter_intra,
2036 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA));
2037 hantro_reg_write(vpu, &av1_enable_jnt_comp,
2038 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP));
2039 hantro_reg_write(vpu, &av1_enable_dual_filter,
2040 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER));
2041 hantro_reg_write(vpu, &av1_reduced_tx_set_used,
2042 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET));
2043 hantro_reg_write(vpu, &av1_allow_screen_content_tools,
2044 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS));
2045 hantro_reg_write(vpu, &av1_allow_intrabc,
2046 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC));
2047
2048 if (!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS))
2049 hantro_reg_write(vpu, &av1_force_interger_mv, 0);
2050 else
2051 hantro_reg_write(vpu, &av1_force_interger_mv,
2052 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV));
2053
2054 hantro_reg_write(vpu, &av1_blackwhite_e, 0);
2055 hantro_reg_write(vpu, &av1_delta_q_res_log, ctrls->frame->quantization.delta_q_res);
2056 hantro_reg_write(vpu, &av1_delta_q_present,
2057 !!(ctrls->frame->quantization.flags
2058 & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT));
2059
2060 hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type));
2061 hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx);
2062 hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);
2063 hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);
2064
2065 hantro_reg_write(vpu, &av1_mcomp_filt_type, ctrls->frame->interpolation_filter);
2066 hantro_reg_write(vpu, &av1_high_prec_mv_e,
2067 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV));
2068 hantro_reg_write(vpu, &av1_comp_pred_mode,
2069 (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0);
2070
2071 tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode);
2072 hantro_reg_write(vpu, &av1_transform_mode, tx_mode);
2073 hantro_reg_write(vpu, &av1_max_cb_size,
2074 (ctrls->sequence->flags
2075 & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6);
2076 hantro_reg_write(vpu, &av1_min_cb_size, 3);
2077
2078 hantro_reg_write(vpu, &av1_comp_pred_fixed_ref, 0);
2079 hantro_reg_write(vpu, &av1_comp_pred_var_ref0_av1, 0);
2080 hantro_reg_write(vpu, &av1_comp_pred_var_ref1_av1, 0);
2081 hantro_reg_write(vpu, &av1_filt_level_seg0, 0);
2082 hantro_reg_write(vpu, &av1_filt_level_seg1, 0);
2083 hantro_reg_write(vpu, &av1_filt_level_seg2, 0);
2084 hantro_reg_write(vpu, &av1_filt_level_seg3, 0);
2085 hantro_reg_write(vpu, &av1_filt_level_seg4, 0);
2086 hantro_reg_write(vpu, &av1_filt_level_seg5, 0);
2087 hantro_reg_write(vpu, &av1_filt_level_seg6, 0);
2088 hantro_reg_write(vpu, &av1_filt_level_seg7, 0);
2089
2090 hantro_reg_write(vpu, &av1_qp_delta_y_dc_av1, ctrls->frame->quantization.delta_q_y_dc);
2091 hantro_reg_write(vpu, &av1_qp_delta_ch_dc_av1, ctrls->frame->quantization.delta_q_u_dc);
2092 hantro_reg_write(vpu, &av1_qp_delta_ch_ac_av1, ctrls->frame->quantization.delta_q_u_ac);
2093 if (ctrls->frame->quantization.flags & V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX) {
2094 hantro_reg_write(vpu, &av1_qmlevel_y, ctrls->frame->quantization.qm_y);
2095 hantro_reg_write(vpu, &av1_qmlevel_u, ctrls->frame->quantization.qm_u);
2096 hantro_reg_write(vpu, &av1_qmlevel_v, ctrls->frame->quantization.qm_v);
2097 } else {
2098 hantro_reg_write(vpu, &av1_qmlevel_y, 0xff);
2099 hantro_reg_write(vpu, &av1_qmlevel_u, 0xff);
2100 hantro_reg_write(vpu, &av1_qmlevel_v, 0xff);
2101 }
2102
2103 hantro_reg_write(vpu, &av1_lossless_e, rockchip_vpu981_av1_dec_is_lossless(ctx));
2104 hantro_reg_write(vpu, &av1_quant_delta_v_dc, ctrls->frame->quantization.delta_q_v_dc);
2105 hantro_reg_write(vpu, &av1_quant_delta_v_ac, ctrls->frame->quantization.delta_q_v_ac);
2106
2107 hantro_reg_write(vpu, &av1_skip_ref0,
2108 (ctrls->frame->skip_mode_frame[0]) ? ctrls->frame->skip_mode_frame[0] : 1);
2109 hantro_reg_write(vpu, &av1_skip_ref1,
2110 (ctrls->frame->skip_mode_frame[1]) ? ctrls->frame->skip_mode_frame[1] : 1);
2111
2112 hantro_write_addr(vpu, AV1_MC_SYNC_CURR, av1_dec->tile_buf.dma);
2113 hantro_write_addr(vpu, AV1_MC_SYNC_LEFT, av1_dec->tile_buf.dma);
2114 }
2115
2116 static void
rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx * ctx,struct vb2_v4l2_buffer * vb2_src)2117 rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx *ctx,
2118 struct vb2_v4l2_buffer *vb2_src)
2119 {
2120 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
2121 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
2122 const struct v4l2_ctrl_av1_tile_group_entry *group_entry =
2123 ctrls->tile_group_entry;
2124 struct hantro_dev *vpu = ctx->dev;
2125 dma_addr_t src_dma;
2126 u32 src_len, src_buf_len;
2127 int start_bit, offset;
2128
2129 src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0);
2130 src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0);
2131 src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
2132
2133 start_bit = (group_entry[0].tile_offset & 0xf) * 8;
2134 offset = group_entry[0].tile_offset & ~0xf;
2135
2136 hantro_reg_write(vpu, &av1_strm_buffer_len, src_buf_len);
2137 hantro_reg_write(vpu, &av1_strm_start_bit, start_bit);
2138 hantro_reg_write(vpu, &av1_stream_len, src_len);
2139 hantro_reg_write(vpu, &av1_strm_start_offset, 0);
2140 hantro_write_addr(vpu, AV1_INPUT_STREAM, src_dma + offset);
2141 }
2142
2143 static void
rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx * ctx)2144 rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx)
2145 {
2146 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
2147 struct hantro_dev *vpu = ctx->dev;
2148 struct hantro_decoded_buffer *dst;
2149 struct vb2_v4l2_buffer *vb2_dst;
2150 dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
2151 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx);
2152 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx);
2153
2154 vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref;
2155 dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
2156 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
2157 chroma_addr = luma_addr + cr_offset;
2158 mv_addr = luma_addr + mv_offset;
2159
2160 dst->av1.chroma_offset = cr_offset;
2161 dst->av1.mv_offset = mv_offset;
2162
2163 hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr);
2164 hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr);
2165 hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);
2166 }
2167
rockchip_vpu981_av1_dec_run(struct hantro_ctx * ctx)2168 int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx)
2169 {
2170 struct hantro_dev *vpu = ctx->dev;
2171 struct vb2_v4l2_buffer *vb2_src;
2172 int ret;
2173
2174 hantro_start_prepare_run(ctx);
2175
2176 ret = rockchip_vpu981_av1_dec_prepare_run(ctx);
2177 if (ret)
2178 goto prepare_error;
2179
2180 vb2_src = hantro_get_src_buf(ctx);
2181 if (!vb2_src) {
2182 ret = -EINVAL;
2183 goto prepare_error;
2184 }
2185
2186 rockchip_vpu981_av1_dec_clean_refs(ctx);
2187 rockchip_vpu981_av1_dec_frame_ref(ctx, vb2_src->vb2_buf.timestamp);
2188
2189 rockchip_vpu981_av1_dec_set_parameters(ctx);
2190 rockchip_vpu981_av1_dec_set_global_model(ctx);
2191 rockchip_vpu981_av1_dec_set_tile_info(ctx);
2192 rockchip_vpu981_av1_dec_set_reference_frames(ctx);
2193 rockchip_vpu981_av1_dec_set_segmentation(ctx);
2194 rockchip_vpu981_av1_dec_set_loopfilter(ctx);
2195 rockchip_vpu981_av1_dec_set_picture_dimensions(ctx);
2196 rockchip_vpu981_av1_dec_set_cdef(ctx);
2197 rockchip_vpu981_av1_dec_set_lr(ctx);
2198 rockchip_vpu981_av1_dec_set_fgs(ctx);
2199 rockchip_vpu981_av1_dec_set_prob(ctx);
2200
2201 hantro_reg_write(vpu, &av1_dec_mode, AV1_DEC_MODE);
2202 hantro_reg_write(vpu, &av1_dec_out_ec_byte_word, 0);
2203 hantro_reg_write(vpu, &av1_write_mvs_e, 1);
2204 hantro_reg_write(vpu, &av1_dec_out_ec_bypass, 1);
2205 hantro_reg_write(vpu, &av1_dec_clk_gate_e, 1);
2206
2207 hantro_reg_write(vpu, &av1_dec_abort_e, 0);
2208 hantro_reg_write(vpu, &av1_dec_tile_int_e, 0);
2209
2210 hantro_reg_write(vpu, &av1_dec_alignment, 64);
2211 hantro_reg_write(vpu, &av1_apf_disable, 0);
2212 hantro_reg_write(vpu, &av1_apf_threshold, 8);
2213 hantro_reg_write(vpu, &av1_dec_buswidth, 2);
2214 hantro_reg_write(vpu, &av1_dec_max_burst, 16);
2215 hantro_reg_write(vpu, &av1_error_conceal_e, 0);
2216 hantro_reg_write(vpu, &av1_axi_rd_ostd_threshold, 64);
2217 hantro_reg_write(vpu, &av1_axi_wr_ostd_threshold, 64);
2218
2219 hantro_reg_write(vpu, &av1_ext_timeout_cycles, 0xfffffff);
2220 hantro_reg_write(vpu, &av1_ext_timeout_override_e, 1);
2221 hantro_reg_write(vpu, &av1_timeout_cycles, 0xfffffff);
2222 hantro_reg_write(vpu, &av1_timeout_override_e, 1);
2223
2224 rockchip_vpu981_av1_dec_set_output_buffer(ctx);
2225 rockchip_vpu981_av1_dec_set_input_buffer(ctx, vb2_src);
2226
2227 hantro_end_prepare_run(ctx);
2228
2229 hantro_reg_write(vpu, &av1_dec_e, 1);
2230
2231 return 0;
2232
2233 prepare_error:
2234 hantro_end_prepare_run(ctx);
2235 hantro_irq_done(vpu, VB2_BUF_STATE_ERROR);
2236 return ret;
2237 }
2238
rockchip_vpu981_postproc_enable(struct hantro_ctx * ctx)2239 static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx)
2240 {
2241 struct hantro_dev *vpu = ctx->dev;
2242 int width = ctx->dst_fmt.width;
2243 int height = ctx->dst_fmt.height;
2244 struct vb2_v4l2_buffer *vb2_dst;
2245 size_t chroma_offset;
2246 dma_addr_t dst_dma;
2247
2248 vb2_dst = hantro_get_dst_buf(ctx);
2249
2250 dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
2251 chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline *
2252 ctx->dst_fmt.height;
2253
2254 /* enable post processor */
2255 hantro_reg_write(vpu, &av1_pp_out_e, 1);
2256 hantro_reg_write(vpu, &av1_pp_in_format, 0);
2257 hantro_reg_write(vpu, &av1_pp0_dup_hor, 1);
2258 hantro_reg_write(vpu, &av1_pp0_dup_ver, 1);
2259
2260 hantro_reg_write(vpu, &av1_pp_in_height, height / 2);
2261 hantro_reg_write(vpu, &av1_pp_in_width, width / 2);
2262 hantro_reg_write(vpu, &av1_pp_out_height, height);
2263 hantro_reg_write(vpu, &av1_pp_out_width, width);
2264 hantro_reg_write(vpu, &av1_pp_out_y_stride,
2265 ctx->dst_fmt.plane_fmt[0].bytesperline);
2266 hantro_reg_write(vpu, &av1_pp_out_c_stride,
2267 ctx->dst_fmt.plane_fmt[0].bytesperline);
2268 switch (ctx->dst_fmt.pixelformat) {
2269 case V4L2_PIX_FMT_P010:
2270 hantro_reg_write(vpu, &av1_pp_out_format, 1);
2271 break;
2272 case V4L2_PIX_FMT_NV12:
2273 hantro_reg_write(vpu, &av1_pp_out_format, 3);
2274 break;
2275 case V4L2_PIX_FMT_NV15:
2276 /* this mapping is RK specific */
2277 hantro_reg_write(vpu, &av1_pp_out_format, 10);
2278 break;
2279 default:
2280 hantro_reg_write(vpu, &av1_pp_out_format, 0);
2281 }
2282
2283 hantro_reg_write(vpu, &av1_ppd_blend_exist, 0);
2284 hantro_reg_write(vpu, &av1_ppd_dith_exist, 0);
2285 hantro_reg_write(vpu, &av1_ablend_crop_e, 0);
2286 hantro_reg_write(vpu, &av1_pp_format_customer1_e, 0);
2287 hantro_reg_write(vpu, &av1_pp_crop_exist, 0);
2288 hantro_reg_write(vpu, &av1_pp_up_level, 0);
2289 hantro_reg_write(vpu, &av1_pp_down_level, 0);
2290 hantro_reg_write(vpu, &av1_pp_exist, 0);
2291
2292 hantro_write_addr(vpu, AV1_PP_OUT_LU, dst_dma);
2293 hantro_write_addr(vpu, AV1_PP_OUT_CH, dst_dma + chroma_offset);
2294 }
2295
rockchip_vpu981_postproc_disable(struct hantro_ctx * ctx)2296 static void rockchip_vpu981_postproc_disable(struct hantro_ctx *ctx)
2297 {
2298 struct hantro_dev *vpu = ctx->dev;
2299
2300 /* disable post processor */
2301 hantro_reg_write(vpu, &av1_pp_out_e, 0);
2302 }
2303
2304 const struct hantro_postproc_ops rockchip_vpu981_postproc_ops = {
2305 .enable = rockchip_vpu981_postproc_enable,
2306 .disable = rockchip_vpu981_postproc_disable,
2307 };
2308