Searched refs:LSC_CHICKEN_BIT_0_UDW (Results 1 – 2 of 2) sorted by relevance
264 SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))358 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))368 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))430 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,445 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,462 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))467 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))593 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))598 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
580 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) macro