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Searched refs:LSC_CHICKEN_BIT_0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_wa.c359 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
376 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
426 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
467 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
490 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
547 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
568 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h503 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) macro
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c2834 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); in general_render_compute_wa_init()
2861 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, in general_render_compute_wa_init()
H A Dintel_gt_regs.h1186 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) macro