1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define NUM_PIXEL_FORMATS 10 80 #define DTBCLK_LIMIT 2920 81 82 enum tiling_mode { 83 TILING_MODE_INVALID, 84 TILING_MODE_LINEAR, 85 TILING_MODE_TILED, 86 TILING_MODE_COUNT 87 }; 88 89 enum view_3d_format { 90 VIEW_3D_FORMAT_NONE = 0, 91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 92 VIEW_3D_FORMAT_SIDE_BY_SIDE, 93 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 94 VIEW_3D_FORMAT_COUNT, 95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 96 }; 97 98 enum plane_stereo_format { 99 PLANE_STEREO_FORMAT_NONE = 0, 100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 106 }; 107 108 /* TODO: Find way to calculate number of bits 109 * Please increase if pixel_format enum increases 110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 111 */ 112 113 enum dc_edid_connector_type { 114 DC_EDID_CONNECTOR_UNKNOWN = 0, 115 DC_EDID_CONNECTOR_ANALOG = 1, 116 DC_EDID_CONNECTOR_DIGITAL = 10, 117 DC_EDID_CONNECTOR_DVI = 11, 118 DC_EDID_CONNECTOR_HDMIA = 12, 119 DC_EDID_CONNECTOR_MDDI = 14, 120 DC_EDID_CONNECTOR_DISPLAYPORT = 15 121 }; 122 123 enum dc_edid_status { 124 EDID_OK, 125 EDID_BAD_INPUT, 126 EDID_NO_RESPONSE, 127 EDID_BAD_CHECKSUM, 128 EDID_THE_SAME, 129 EDID_FALL_BACK, 130 EDID_PARTIAL_VALID, 131 }; 132 133 enum act_return_status { 134 ACT_SUCCESS, 135 ACT_LINK_LOST, 136 ACT_FAILED 137 }; 138 139 /* audio capability from EDID*/ 140 struct dc_cea_audio_mode { 141 uint8_t format_code; /* ucData[0] [6:3]*/ 142 uint8_t channel_count; /* ucData[0] [2:0]*/ 143 uint8_t sample_rate; /* ucData[1]*/ 144 union { 145 uint8_t sample_size; /* for LPCM*/ 146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 147 uint8_t max_bit_rate; 148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 149 }; 150 }; 151 152 struct dc_edid { 153 uint32_t length; 154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 155 }; 156 157 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 158 * is used. In this case we assume speaker location are: front left, front 159 * right and front center. */ 160 #define DEFAULT_SPEAKER_LOCATION 5 161 162 #define DC_MAX_AUDIO_DESC_COUNT 16 163 164 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 165 166 struct dc_panel_patch { 167 unsigned int dppowerup_delay; 168 unsigned int extra_t12_ms; 169 unsigned int extra_delay_backlight_off; 170 unsigned int extra_t7_ms; 171 unsigned int skip_scdc_overwrite; 172 unsigned int delay_ignore_msa; 173 unsigned int disable_fec; 174 unsigned int extra_t3_ms; 175 unsigned int max_dsc_target_bpp_limit; 176 unsigned int embedded_tiled_slave; 177 unsigned int disable_fams; 178 unsigned int hdmi_spe_handling; 179 unsigned int block_420_Freesync; 180 unsigned int block_10g; 181 unsigned int hdmi_comp_manual; 182 unsigned int hdmi_comp_auto; 183 unsigned int force_frl; 184 unsigned int vsdb_rcc_wa; 185 unsigned int delay_hdmi_link_training; 186 unsigned int skip_avmute; 187 unsigned int skip_audio_sab_check; 188 unsigned int mst_start_top_delay; 189 unsigned int remove_sink_ext_caps; 190 unsigned int disable_colorimetry; 191 uint8_t blankstream_before_otg_off; 192 bool oled_optimize_display_on; 193 unsigned int force_mst_blocked_discovery; 194 unsigned int wait_after_dpcd_poweroff_ms; 195 }; 196 197 /** 198 * struct dc_edid_caps - Capabilities read from EDID. 199 * @analog: Whether the monitor is analog. Used by DVI-I handling. 200 */ 201 struct dc_edid_caps { 202 /* sink identification */ 203 uint16_t manufacturer_id; 204 uint16_t product_id; 205 uint32_t serial_number; 206 uint8_t manufacture_week; 207 uint8_t manufacture_year; 208 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 209 210 /* audio caps */ 211 uint8_t speaker_flags; 212 uint32_t audio_mode_count; 213 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 214 uint32_t audio_latency; 215 uint32_t video_latency; 216 217 unsigned char freesync_vcp_code; 218 219 uint8_t qs_bit; 220 uint8_t qy_bit; 221 222 uint32_t max_tmds_clk_mhz; 223 224 /*HDMI 2.0 caps*/ 225 bool lte_340mcsc_scramble; 226 227 bool edid_hdmi; 228 bool hdr_supported; 229 bool rr_capable; 230 bool scdc_present; 231 bool analog; 232 233 /*HDMI 2.1 caps*/ 234 uint8_t max_frl_rate; 235 bool frl_dsc_support; 236 bool frl_dsc_10bpc; 237 bool frl_dsc_12bpc; 238 bool frl_dsc_all_bpp; 239 bool frl_dsc_native_420; 240 uint8_t frl_dsc_max_slices; 241 uint8_t frl_dsc_max_frl_rate; 242 uint8_t frl_dsc_total_chunk_kbytes; 243 244 struct dc_panel_patch panel_patch; 245 }; 246 247 struct dc_mode_flags { 248 /* note: part of refresh rate flag*/ 249 uint32_t INTERLACE :1; 250 /* native display timing*/ 251 uint32_t NATIVE :1; 252 /* preferred is the recommended mode, one per display */ 253 uint32_t PREFERRED :1; 254 /* true if this mode should use reduced blanking timings 255 *_not_ related to the Reduced Blanking adjustment*/ 256 uint32_t REDUCED_BLANKING :1; 257 /* note: part of refreshrate flag*/ 258 uint32_t VIDEO_OPTIMIZED_RATE :1; 259 /* should be reported to upper layers as mode_flags*/ 260 uint32_t PACKED_PIXEL_FORMAT :1; 261 /*< preferred view*/ 262 uint32_t PREFERRED_VIEW :1; 263 /* this timing should be used only in tiled mode*/ 264 uint32_t TILED_MODE :1; 265 uint32_t DSE_MODE :1; 266 /* Refresh rate divider when Miracast sink is using a 267 different rate than the output display device 268 Must be zero for wired displays and non-zero for 269 Miracast displays*/ 270 uint32_t MIRACAST_REFRESH_DIVIDER; 271 }; 272 273 274 enum dc_timing_source { 275 TIMING_SOURCE_UNDEFINED, 276 277 /* explicitly specifed by user, most important*/ 278 TIMING_SOURCE_USER_FORCED, 279 TIMING_SOURCE_USER_OVERRIDE, 280 TIMING_SOURCE_CUSTOM, 281 TIMING_SOURCE_EXPLICIT, 282 283 /* explicitly specified by the display device, more important*/ 284 TIMING_SOURCE_EDID_CEA_SVD_3D, 285 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 286 TIMING_SOURCE_EDID_CEA_SVD_420, 287 TIMING_SOURCE_EDID_DETAILED, 288 TIMING_SOURCE_EDID_ESTABLISHED, 289 TIMING_SOURCE_EDID_STANDARD, 290 TIMING_SOURCE_EDID_CEA_SVD, 291 TIMING_SOURCE_EDID_CVT_3BYTE, 292 TIMING_SOURCE_EDID_4BYTE, 293 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 294 TIMING_SOURCE_EDID_CEA_RID, 295 TIMING_SOURCE_EDID_DISPLAYID_TYPE5, 296 TIMING_SOURCE_VBIOS, 297 TIMING_SOURCE_CV, 298 TIMING_SOURCE_TV, 299 TIMING_SOURCE_HDMI_VIC, 300 TIMING_SOURCE_CEA_VIC, 301 302 /* implicitly specified by display device, still safe but less important*/ 303 TIMING_SOURCE_DEFAULT, 304 305 /* only used for custom base modes */ 306 TIMING_SOURCE_CUSTOM_BASE, 307 308 /* these timing might not work, least important*/ 309 TIMING_SOURCE_RANGELIMIT, 310 TIMING_SOURCE_OS_FORCED, 311 TIMING_SOURCE_IMPLICIT, 312 313 /* only used by default mode list*/ 314 TIMING_SOURCE_BASICMODE, 315 316 TIMING_SOURCE_COUNT 317 }; 318 319 320 struct stereo_3d_features { 321 bool supported ; 322 bool allTimings ; 323 bool cloneMode ; 324 bool scaling ; 325 bool singleFrameSWPacked; 326 }; 327 328 enum dc_timing_support_method { 329 TIMING_SUPPORT_METHOD_UNDEFINED, 330 TIMING_SUPPORT_METHOD_EXPLICIT, 331 TIMING_SUPPORT_METHOD_IMPLICIT, 332 TIMING_SUPPORT_METHOD_NATIVE 333 }; 334 335 struct dc_mode_info { 336 uint32_t pixel_width; 337 uint32_t pixel_height; 338 uint32_t field_rate; 339 /* Vertical refresh rate for progressive modes. 340 * Field rate for interlaced modes.*/ 341 342 enum dc_timing_standard timing_standard; 343 enum dc_timing_source timing_source; 344 struct dc_mode_flags flags; 345 }; 346 347 enum dc_power_state { 348 DC_POWER_STATE_ON = 1, 349 DC_POWER_STATE_STANDBY, 350 DC_POWER_STATE_SUSPEND, 351 DC_POWER_STATE_OFF 352 }; 353 354 /* DC PowerStates */ 355 enum dc_video_power_state { 356 DC_VIDEO_POWER_UNSPECIFIED = 0, 357 DC_VIDEO_POWER_ON = 1, 358 DC_VIDEO_POWER_STANDBY, 359 DC_VIDEO_POWER_SUSPEND, 360 DC_VIDEO_POWER_OFF, 361 DC_VIDEO_POWER_HIBERNATE, 362 DC_VIDEO_POWER_SHUTDOWN, 363 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 364 DC_VIDEO_POWER_AFTER_RESET, 365 DC_VIDEO_POWER_MAXIMUM 366 }; 367 368 enum dc_acpi_cm_power_state { 369 DC_ACPI_CM_POWER_STATE_D0 = 1, 370 DC_ACPI_CM_POWER_STATE_D1 = 2, 371 DC_ACPI_CM_POWER_STATE_D2 = 4, 372 DC_ACPI_CM_POWER_STATE_D3 = 8 373 }; 374 375 enum dc_connection_type { 376 dc_connection_none, 377 dc_connection_single, 378 dc_connection_mst_branch, 379 dc_connection_sst_branch, 380 dc_connection_analog_load 381 }; 382 383 struct dc_csc_adjustments { 384 struct fixed31_32 contrast; 385 struct fixed31_32 saturation; 386 struct fixed31_32 brightness; 387 struct fixed31_32 hue; 388 }; 389 390 /* Scaling format */ 391 enum scaling_transformation { 392 SCALING_TRANSFORMATION_UNINITIALIZED, 393 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 394 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 395 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 396 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 397 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 398 SCALING_TRANSFORMATION_INVALID = 0x80000000, 399 400 /* Flag the first and last */ 401 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 402 SCALING_TRANSFORMATION_END = 403 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 404 }; 405 406 enum display_content_type { 407 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 408 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 409 DISPLAY_CONTENT_TYPE_PHOTO = 2, 410 DISPLAY_CONTENT_TYPE_CINEMA = 4, 411 DISPLAY_CONTENT_TYPE_GAME = 8 412 }; 413 414 enum cm_gamut_adjust_type { 415 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 416 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 417 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 418 }; 419 420 struct cm_grph_csc_adjustment { 421 struct fixed31_32 temperature_matrix[12]; 422 enum cm_gamut_adjust_type gamut_adjust_type; 423 enum cm_gamut_coef_format gamut_coef_format; 424 }; 425 426 /* writeback */ 427 struct dwb_stereo_params { 428 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 429 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 430 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 431 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 432 }; 433 434 struct dc_dwb_cnv_params { 435 unsigned int src_width; /* input active width */ 436 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 437 unsigned int crop_width; /* cropped window width at cnv output */ 438 bool crop_en; /* window cropping enable in cnv */ 439 unsigned int crop_height; /* cropped window height at cnv output */ 440 unsigned int crop_x; /* cropped window start x value at cnv output */ 441 unsigned int crop_y; /* cropped window start y value at cnv output */ 442 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 443 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 444 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 445 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 446 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 447 }; 448 449 struct dc_dwb_params { 450 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 451 unsigned int hdr_mult; /* must be in FP1.6.12 */ 452 struct cm_grph_csc_adjustment csc_params; 453 struct dwb_stereo_params stereo_params; 454 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 455 unsigned int dest_width; /* Destination width */ 456 unsigned int dest_height; /* Destination height */ 457 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 458 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 459 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 460 struct scaling_taps scaler_taps; /* Scaling taps */ 461 enum dwb_subsample_position subsample_position; 462 const struct dc_transfer_func *out_transfer_func; 463 }; 464 465 /* audio*/ 466 467 union audio_sample_rates { 468 struct sample_rates { 469 uint8_t RATE_32:1; 470 uint8_t RATE_44_1:1; 471 uint8_t RATE_48:1; 472 uint8_t RATE_88_2:1; 473 uint8_t RATE_96:1; 474 uint8_t RATE_176_4:1; 475 uint8_t RATE_192:1; 476 } rate; 477 478 uint8_t all; 479 }; 480 481 struct audio_speaker_flags { 482 uint32_t FL_FR:1; 483 uint32_t LFE:1; 484 uint32_t FC:1; 485 uint32_t RL_RR:1; 486 uint32_t RC:1; 487 uint32_t FLC_FRC:1; 488 uint32_t RLC_RRC:1; 489 uint32_t SUPPORT_AI:1; 490 }; 491 492 struct audio_speaker_info { 493 uint32_t ALLSPEAKERS:7; 494 uint32_t SUPPORT_AI:1; 495 }; 496 497 498 struct audio_info_flags { 499 500 union { 501 502 struct audio_speaker_flags speaker_flags; 503 struct audio_speaker_info info; 504 505 uint8_t all; 506 }; 507 }; 508 509 enum audio_format_code { 510 AUDIO_FORMAT_CODE_FIRST = 1, 511 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 512 513 AUDIO_FORMAT_CODE_AC3, 514 /*Layers 1 & 2 */ 515 AUDIO_FORMAT_CODE_MPEG1, 516 /*MPEG1 Layer 3 */ 517 AUDIO_FORMAT_CODE_MP3, 518 /*multichannel */ 519 AUDIO_FORMAT_CODE_MPEG2, 520 AUDIO_FORMAT_CODE_AAC, 521 AUDIO_FORMAT_CODE_DTS, 522 AUDIO_FORMAT_CODE_ATRAC, 523 AUDIO_FORMAT_CODE_1BITAUDIO, 524 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 525 AUDIO_FORMAT_CODE_DTS_HD, 526 AUDIO_FORMAT_CODE_MAT_MLP, 527 AUDIO_FORMAT_CODE_DST, 528 AUDIO_FORMAT_CODE_WMAPRO, 529 AUDIO_FORMAT_CODE_LAST, 530 AUDIO_FORMAT_CODE_COUNT = 531 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 532 }; 533 534 struct audio_mode { 535 /* ucData[0] [6:3] */ 536 enum audio_format_code format_code; 537 /* ucData[0] [2:0] */ 538 uint8_t channel_count; 539 /* ucData[1] */ 540 union audio_sample_rates sample_rates; 541 union { 542 /* for LPCM */ 543 uint8_t sample_size; 544 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 545 uint8_t max_bit_rate; 546 /* for Audio Formats 9-15 */ 547 uint8_t vendor_specific; 548 }; 549 }; 550 551 struct audio_info { 552 struct audio_info_flags flags; 553 uint32_t video_latency; 554 uint32_t audio_latency; 555 uint32_t display_index; 556 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 557 uint32_t manufacture_id; 558 uint32_t product_id; 559 /* PortID used for ContainerID when defined */ 560 uint32_t port_id[2]; 561 uint32_t mode_count; 562 /* this field must be last in this struct */ 563 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 564 }; 565 struct audio_check { 566 unsigned int audio_packet_type; 567 unsigned int max_audiosample_rate; 568 unsigned int max_channel_count; 569 unsigned int acat; 570 }; 571 enum dc_infoframe_type { 572 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 573 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 574 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 575 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 576 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 577 }; 578 579 struct dc_info_packet { 580 bool valid; 581 uint8_t hb0; 582 uint8_t hb1; 583 uint8_t hb2; 584 uint8_t hb3; 585 uint8_t sb[32]; 586 }; 587 588 struct dc_info_packet_128 { 589 bool valid; 590 uint8_t hb0; 591 uint8_t hb1; 592 uint8_t hb2; 593 uint8_t hb3; 594 uint8_t sb[128]; 595 }; 596 597 struct dc_edid_read_policy { 598 uint32_t max_retry_count; 599 uint32_t delay_time_ms; 600 uint32_t ignore_checksum; 601 }; 602 603 #define DC_PLANE_UPDATE_TIMES_MAX 10 604 605 struct dc_plane_flip_time { 606 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 607 unsigned int index; 608 unsigned int prev_update_time_in_us; 609 }; 610 611 enum dc_alpm_mode { 612 DC_ALPM_AUXWAKE = 0, 613 DC_ALPM_AUXLESS = 1, 614 DC_ALPM_UNSUPPORTED = 0xF, 615 }; 616 617 enum dc_psr_state { 618 PSR_STATE0 = 0x0, 619 PSR_STATE1, 620 PSR_STATE1a, 621 PSR_STATE2, 622 PSR_STATE2a, 623 PSR_STATE2b, 624 PSR_STATE3, 625 PSR_STATE3Init, 626 PSR_STATE4, 627 PSR_STATE4a, 628 PSR_STATE4b, 629 PSR_STATE4c, 630 PSR_STATE4d, 631 PSR_STATE4_FULL_FRAME, 632 PSR_STATE4a_FULL_FRAME, 633 PSR_STATE4b_FULL_FRAME, 634 PSR_STATE4c_FULL_FRAME, 635 PSR_STATE4_FULL_FRAME_POWERUP, 636 PSR_STATE4_FULL_FRAME_HW_LOCK, 637 PSR_STATE5, 638 PSR_STATE5a, 639 PSR_STATE5b, 640 PSR_STATE5c, 641 PSR_STATE_HWLOCK_MGR, 642 PSR_STATE_POLLVUPDATE, 643 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 644 PSR_STATE_INVALID = 0xFF 645 }; 646 647 struct psr_config { 648 unsigned char psr_version; 649 unsigned int psr_rfb_setup_time; 650 bool psr_exit_link_training_required; 651 bool psr_frame_capture_indication_req; 652 unsigned int psr_sdp_transmit_line_num_deadline; 653 bool allow_smu_optimizations; 654 bool allow_multi_disp_optimizations; 655 /* Panel self refresh 2 selective update granularity required */ 656 bool su_granularity_required; 657 /* psr2 selective update y granularity capability */ 658 uint8_t su_y_granularity; 659 unsigned int line_time_in_us; 660 uint8_t rate_control_caps; 661 uint16_t dsc_slice_height; 662 bool os_request_force_ffu; 663 }; 664 665 union dmcu_psr_level { 666 struct { 667 unsigned int SKIP_CRC:1; 668 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 669 unsigned int SKIP_PHY_POWER_DOWN:1; 670 unsigned int SKIP_AUX_ACK_CHECK:1; 671 unsigned int SKIP_CRTC_DISABLE:1; 672 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 673 unsigned int SKIP_SMU_NOTIFICATION:1; 674 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 675 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 676 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 677 unsigned int DISABLE_ALPM:1; 678 unsigned int ALPM_DEFAULT_PD_MODE:1; 679 unsigned int RESERVED:20; 680 } bits; 681 unsigned int u32all; 682 }; 683 684 enum physical_phy_id { 685 PHYLD_0, 686 PHYLD_1, 687 PHYLD_2, 688 PHYLD_3, 689 PHYLD_4, 690 PHYLD_5, 691 PHYLD_6, 692 PHYLD_7, 693 PHYLD_8, 694 PHYLD_9, 695 PHYLD_COUNT, 696 PHYLD_UNKNOWN = (-1L) 697 }; 698 699 enum phy_type { 700 PHY_TYPE_UNKNOWN = 1, 701 PHY_TYPE_PCIE_PHY = 2, 702 PHY_TYPE_UNIPHY = 3, 703 }; 704 705 struct psr_context { 706 /* ddc line */ 707 enum channel_id channel; 708 /* Transmitter id */ 709 enum transmitter transmitterId; 710 /* Engine Id is used for Dig Be source select */ 711 enum engine_id engineId; 712 /* Controller Id used for Dig Fe source select */ 713 enum controller_id controllerId; 714 /* Pcie or Uniphy */ 715 enum phy_type phyType; 716 /* Physical PHY Id used by SMU interpretation */ 717 enum physical_phy_id smuPhyId; 718 /* Vertical total pixels from crtc timing. 719 * This is used for static screen detection. 720 * ie. If we want to detect half a frame, 721 * we use this to determine the hyst lines. 722 */ 723 unsigned int crtcTimingVerticalTotal; 724 /* PSR supported from panel capabilities and 725 * current display configuration 726 */ 727 bool psrSupportedDisplayConfig; 728 /* Whether fast link training is supported by the panel */ 729 bool psrExitLinkTrainingRequired; 730 /* If RFB setup time is greater than the total VBLANK time, 731 * it is not possible for the sink to capture the video frame 732 * in the same frame the SDP is sent. In this case, 733 * the frame capture indication bit should be set and an extra 734 * static frame should be transmitted to the sink. 735 */ 736 bool psrFrameCaptureIndicationReq; 737 /* Set the last possible line SDP may be transmitted without violating 738 * the RFB setup time or entering the active video frame. 739 */ 740 unsigned int sdpTransmitLineNumDeadline; 741 /* The VSync rate in Hz used to calculate the 742 * step size for smooth brightness feature 743 */ 744 unsigned int vsync_rate_hz; 745 unsigned int skipPsrWaitForPllLock; 746 unsigned int numberOfControllers; 747 /* Unused, for future use. To indicate that first changed frame from 748 * state3 shouldn't result in psr_inactive, but rather to perform 749 * an automatic single frame rfb_update. 750 */ 751 bool rfb_update_auto_en; 752 /* Number of frame before entering static screen */ 753 unsigned int timehyst_frames; 754 /* Partial frames before entering static screen */ 755 unsigned int hyst_lines; 756 /* # of repeated AUX transaction attempts to make before 757 * indicating failure to the driver 758 */ 759 unsigned int aux_repeats; 760 /* Controls hw blocks to power down during PSR active state */ 761 union dmcu_psr_level psr_level; 762 /* Controls additional delay after remote frame capture before 763 * continuing powerd own 764 */ 765 unsigned int frame_delay; 766 bool allow_smu_optimizations; 767 bool allow_multi_disp_optimizations; 768 /* Panel self refresh 2 selective update granularity required */ 769 bool su_granularity_required; 770 /* psr2 selective update y granularity capability */ 771 uint8_t su_y_granularity; 772 unsigned int line_time_in_us; 773 uint8_t rate_control_caps; 774 uint16_t dsc_slice_height; 775 bool os_request_force_ffu; 776 }; 777 778 struct colorspace_transform { 779 struct fixed31_32 matrix[12]; 780 bool enable_remap; 781 }; 782 783 enum i2c_mot_mode { 784 I2C_MOT_UNDEF, 785 I2C_MOT_TRUE, 786 I2C_MOT_FALSE 787 }; 788 789 struct AsicStateEx { 790 unsigned int memoryClock; 791 unsigned int displayClock; 792 unsigned int engineClock; 793 unsigned int maxSupportedDppClock; 794 unsigned int dppClock; 795 unsigned int socClock; 796 unsigned int dcfClockDeepSleep; 797 unsigned int fClock; 798 unsigned int phyClock; 799 }; 800 801 802 enum dc_clock_type { 803 DC_CLOCK_TYPE_DISPCLK = 0, 804 DC_CLOCK_TYPE_DPPCLK = 1, 805 }; 806 807 struct dc_clock_config { 808 uint32_t max_clock_khz; 809 uint32_t min_clock_khz; 810 uint32_t bw_requirequired_clock_khz; 811 uint32_t current_clock_khz;/*current clock in use*/ 812 }; 813 814 enum hubp_dmdata_mode { 815 DMDATA_SW_MODE, 816 DMDATA_HW_MODE 817 }; 818 819 struct dc_dmdata_attributes { 820 /* Specifies whether dynamic meta data will be updated by software 821 * or has to be fetched by hardware (DMA mode) 822 */ 823 enum hubp_dmdata_mode dmdata_mode; 824 /* Specifies if current dynamic meta data is to be used only for the current frame */ 825 bool dmdata_repeat; 826 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 827 uint32_t dmdata_size; 828 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 829 bool dmdata_updated; 830 /* If hardware mode is used, the base address where DMDATA surface is located */ 831 PHYSICAL_ADDRESS_LOC address; 832 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 833 bool dmdata_qos_mode; 834 /* If qos_mode = 1, this is the QOS value to be used: */ 835 uint32_t dmdata_qos_level; 836 /* Specifies the value in unit of REFCLK cycles to be added to the 837 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 838 */ 839 uint32_t dmdata_dl_delta; 840 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 841 uint32_t *dmdata_sw_data; 842 }; 843 844 struct hw_asic_id { 845 uint32_t chip_id; 846 uint32_t chip_family; 847 uint32_t pci_revision_id; 848 uint32_t hw_internal_rev; 849 uint32_t vram_type; 850 uint32_t vram_width; 851 uint32_t feature_flags; 852 uint32_t fake_paths_num; 853 void *atombios_base_address; 854 }; 855 856 struct dc_context { 857 struct dc *dc; 858 859 void *driver_context; /* e.g. amdgpu_device */ 860 struct dal_logger *logger; 861 struct dc_perf_trace *perf_trace; 862 void *cgs_device; 863 864 enum dce_environment dce_environment; 865 struct hw_asic_id asic_id; 866 867 /* todo: below should probably move to dc. to facilitate removal 868 * of AS we will store these here 869 */ 870 enum dce_version dce_version; 871 struct dc_bios *dc_bios; 872 bool created_bios; 873 struct gpio_service *gpio_service; 874 uint32_t dc_sink_id_count; 875 uint32_t dc_stream_id_count; 876 uint32_t dc_edp_id_count; 877 uint64_t fbc_gpu_addr; 878 struct dc_dmub_srv *dmub_srv; 879 struct cp_psp cp_psp; 880 uint32_t *dcn_reg_offsets; 881 uint32_t *nbio_reg_offsets; 882 uint32_t *clk_reg_offsets; 883 }; 884 885 /* DSC DPCD capabilities */ 886 union dsc_slice_caps1 { 887 struct { 888 uint8_t NUM_SLICES_1 : 1; 889 uint8_t NUM_SLICES_2 : 1; 890 uint8_t RESERVED : 1; 891 uint8_t NUM_SLICES_4 : 1; 892 uint8_t NUM_SLICES_6 : 1; 893 uint8_t NUM_SLICES_8 : 1; 894 uint8_t NUM_SLICES_10 : 1; 895 uint8_t NUM_SLICES_12 : 1; 896 } bits; 897 uint8_t raw; 898 }; 899 900 union dsc_slice_caps2 { 901 struct { 902 uint8_t NUM_SLICES_16 : 1; 903 uint8_t NUM_SLICES_20 : 1; 904 uint8_t NUM_SLICES_24 : 1; 905 uint8_t RESERVED : 5; 906 } bits; 907 uint8_t raw; 908 }; 909 910 union dsc_color_formats { 911 struct { 912 uint8_t RGB : 1; 913 uint8_t YCBCR_444 : 1; 914 uint8_t YCBCR_SIMPLE_422 : 1; 915 uint8_t YCBCR_NATIVE_422 : 1; 916 uint8_t YCBCR_NATIVE_420 : 1; 917 uint8_t RESERVED : 3; 918 } bits; 919 uint8_t raw; 920 }; 921 922 union dsc_color_depth { 923 struct { 924 uint8_t RESERVED1 : 1; 925 uint8_t COLOR_DEPTH_8_BPC : 1; 926 uint8_t COLOR_DEPTH_10_BPC : 1; 927 uint8_t COLOR_DEPTH_12_BPC : 1; 928 uint8_t RESERVED2 : 3; 929 } bits; 930 uint8_t raw; 931 }; 932 933 struct dsc_dec_dpcd_caps { 934 bool is_dsc_supported; 935 uint8_t dsc_version; 936 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 937 union dsc_slice_caps1 slice_caps1; 938 union dsc_slice_caps2 slice_caps2; 939 int32_t lb_bit_depth; 940 bool is_block_pred_supported; 941 uint32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 942 union dsc_color_formats color_formats; 943 union dsc_color_depth color_depth; 944 int32_t throughput_mode_0_mps; /* In MPs */ 945 int32_t throughput_mode_1_mps; /* In MPs */ 946 int32_t max_slice_width; 947 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 948 949 /* Extended DSC caps */ 950 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 951 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 952 uint32_t branch_max_line_width; 953 bool is_frl; /* Decoded format */ 954 bool is_vic_all_bpp; 955 uint32_t total_chunk_kbytes; 956 bool is_dp; /* Decoded format */ 957 }; 958 959 struct hblank_expansion_dpcd_caps { 960 bool expansion_supported; 961 bool reduction_supported; 962 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/ 963 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/ 964 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */ 965 }; 966 967 struct dc_golden_table { 968 uint16_t dc_golden_table_ver; 969 uint32_t aux_dphy_rx_control0_val; 970 uint32_t aux_dphy_tx_control_val; 971 uint32_t aux_dphy_rx_control1_val; 972 uint32_t dc_gpio_aux_ctrl_0_val; 973 uint32_t dc_gpio_aux_ctrl_1_val; 974 uint32_t dc_gpio_aux_ctrl_2_val; 975 uint32_t dc_gpio_aux_ctrl_3_val; 976 uint32_t dc_gpio_aux_ctrl_4_val; 977 uint32_t dc_gpio_aux_ctrl_5_val; 978 }; 979 980 enum dc_gpu_mem_alloc_type { 981 DC_MEM_ALLOC_TYPE_GART, 982 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 983 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 984 DC_MEM_ALLOC_TYPE_AGP 985 }; 986 987 enum dc_link_encoding_format { 988 DC_LINK_ENCODING_UNSPECIFIED = 0, 989 DC_LINK_ENCODING_DP_8b_10b, 990 DC_LINK_ENCODING_DP_128b_132b, 991 DC_LINK_ENCODING_HDMI_TMDS, 992 DC_LINK_ENCODING_HDMI_FRL 993 }; 994 995 enum dc_psr_version { 996 DC_PSR_VERSION_1 = 0, 997 DC_PSR_VERSION_SU_1 = 1, 998 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 999 }; 1000 1001 enum dc_replay_version { 1002 DC_FREESYNC_REPLAY = 0, 1003 DC_VESA_PANEL_REPLAY = 1, 1004 DC_REPLAY_VERSION_UNSUPPORTED = 0XFF, 1005 }; 1006 1007 /* Possible values of display_endpoint_id.endpoint */ 1008 enum display_endpoint_type { 1009 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 1010 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 1011 DISPLAY_ENDPOINT_UNKNOWN = -1 1012 }; 1013 1014 /* Extends graphics_object_id with an additional member 'ep_type' for 1015 * distinguishing between physical endpoints (with entries in BIOS connector table) and 1016 * logical endpoints. 1017 */ 1018 struct display_endpoint_id { 1019 struct graphics_object_id link_id; 1020 enum display_endpoint_type ep_type; 1021 }; 1022 1023 enum dc_panel_type { 1024 PANEL_TYPE_NONE = 0, // UNKONWN, not determined yet 1025 PANEL_TYPE_LCD = 1, 1026 PANEL_TYPE_OLED = 2, 1027 PANEL_TYPE_MINILED = 3, 1028 }; 1029 1030 enum backlight_control_type { 1031 BACKLIGHT_CONTROL_PWM = 0, 1032 BACKLIGHT_CONTROL_VESA_AUX = 1, 1033 BACKLIGHT_CONTROL_AMD_AUX = 2, 1034 }; 1035 1036 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1037 #define MAX_CRC_WINDOW_NUM 2 1038 1039 struct otg_phy_mux { 1040 uint8_t phy_output_num; 1041 uint8_t otg_output_num; 1042 }; 1043 1044 struct crc_window { 1045 struct rect rect; 1046 bool enable; 1047 }; 1048 #endif 1049 1050 enum dc_detect_reason { 1051 DETECT_REASON_BOOT, 1052 DETECT_REASON_RESUMEFROMS3S4, 1053 DETECT_REASON_HPD, 1054 DETECT_REASON_HPDRX, 1055 DETECT_REASON_FALLBACK, 1056 DETECT_REASON_RETRAIN, 1057 DETECT_REASON_TDR, 1058 }; 1059 1060 struct dc_link_status { 1061 bool link_active; 1062 struct dpcd_caps *dpcd_caps; 1063 }; 1064 1065 union hdcp_rx_caps { 1066 struct { 1067 uint8_t version; 1068 uint8_t reserved; 1069 struct { 1070 uint8_t repeater : 1; 1071 uint8_t hdcp_capable : 1; 1072 uint8_t reserved : 6; 1073 } byte0; 1074 } fields; 1075 uint8_t raw[3]; 1076 }; 1077 1078 union hdcp_bcaps { 1079 struct { 1080 uint8_t HDCP_CAPABLE:1; 1081 uint8_t REPEATER:1; 1082 uint8_t RESERVED:6; 1083 } bits; 1084 uint8_t raw; 1085 }; 1086 1087 struct hdcp_caps { 1088 union hdcp_rx_caps rx_caps; 1089 union hdcp_bcaps bcaps; 1090 }; 1091 1092 /* DP MST stream allocation (payload bandwidth number) */ 1093 struct link_mst_stream_allocation { 1094 /* DIG front */ 1095 const struct stream_encoder *stream_enc; 1096 /* HPO DP Stream Encoder */ 1097 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 1098 /* associate DRM payload table with DC stream encoder */ 1099 uint8_t vcp_id; 1100 /* number of slots required for the DP stream in transport packet */ 1101 uint8_t slot_count; 1102 }; 1103 1104 #define MAX_CONTROLLER_NUM 6 1105 1106 /* DP MST stream allocation table */ 1107 struct link_mst_stream_allocation_table { 1108 /* number of DP video streams */ 1109 int stream_count; 1110 /* array of stream allocations */ 1111 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1112 }; 1113 1114 /* PSR feature flags */ 1115 struct psr_settings { 1116 bool psr_feature_enabled; // PSR is supported by sink 1117 bool psr_allow_active; // PSR is currently active 1118 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1119 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1120 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1121 1122 /* These parameters are calculated in Driver, 1123 * based on display timing and Sink capabilities. 1124 * If VBLANK region is too small and Sink takes a long time 1125 * to set up RFB, it may take an extra frame to enter PSR state. 1126 */ 1127 bool psr_frame_capture_indication_req; 1128 unsigned int psr_sdp_transmit_line_num_deadline; 1129 uint8_t force_ffu_mode; 1130 unsigned int psr_power_opt; 1131 1132 /** 1133 * Some panels cannot handle idle pattern during PSR entry. 1134 * To power down phy before disable stream to avoid sending 1135 * idle pattern. 1136 */ 1137 uint8_t power_down_phy_before_disable_stream; 1138 }; 1139 1140 enum replay_coasting_vtotal_type { 1141 PR_COASTING_TYPE_NOM = 0, 1142 PR_COASTING_TYPE_STATIC, 1143 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1144 PR_COASTING_TYPE_TEST_HARNESS, 1145 PR_COASTING_TYPE_VIDEO_CONFERENCING_V2, 1146 PR_COASTING_TYPE_NUM, 1147 }; 1148 1149 enum replay_link_off_frame_count_level { 1150 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1151 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1152 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1153 }; 1154 1155 /* 1156 * This is general Interface for Replay to 1157 * set an 32 bit variable to dmub 1158 * The Message_type indicates which variable 1159 * passed to DMUB. 1160 */ 1161 enum replay_FW_Message_type { 1162 Replay_Msg_Not_Support = -1, 1163 Replay_Set_Timing_Sync_Supported, 1164 Replay_Set_Residency_Frameupdate_Timer, 1165 Replay_Set_Pseudo_VTotal, 1166 Replay_Disabled_Adaptive_Sync_SDP, 1167 Replay_Set_General_Cmd, 1168 }; 1169 1170 union replay_error_status { 1171 struct { 1172 unsigned int STATE_TRANSITION_ERROR :1; 1173 unsigned int LINK_CRC_ERROR :1; 1174 unsigned int DESYNC_ERROR :1; 1175 unsigned int RESERVED_3 :1; 1176 unsigned int LOW_RR_INCORRECT_VTOTAL :1; 1177 unsigned int NO_DOUBLED_RR :1; 1178 unsigned int RESERVED_6_7 :2; 1179 } bits; 1180 unsigned char raw; 1181 }; 1182 1183 union replay_low_refresh_rate_enable_options { 1184 struct { 1185 //BIT[0-3]: Replay Low Hz Support control 1186 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1187 unsigned int SKIP_ASIC_CHECK :1; 1188 unsigned int RESERVED_2_3 :2; 1189 //BIT[4-15]: Replay Low Hz Enable Scenarios 1190 unsigned int ENABLE_STATIC_SCREEN :1; 1191 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1192 unsigned int ENABLE_GENERAL_UI :1; 1193 unsigned int RESERVED_7_15 :9; 1194 //BIT[16-31]: Replay Low Hz Enable Check 1195 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1196 unsigned int RESERVED_17_31 :15; 1197 } bits; 1198 unsigned int raw; 1199 }; 1200 1201 union replay_optimization { 1202 struct { 1203 //BIT[0-1]: Replay Teams Optimization 1204 unsigned int TEAMS_OPTIMIZATION_VER_1 :1; 1205 unsigned int TEAMS_OPTIMIZATION_VER_2 :1; 1206 //BIT[2]: Replay Live Capture with CVT 1207 unsigned int LIVE_CAPTURE_WITH_CVT :1; 1208 unsigned int RESERVED_3 :1; 1209 } bits; 1210 1211 unsigned int raw; 1212 }; 1213 1214 struct replay_config { 1215 /* Replay version */ 1216 enum dc_replay_version replay_version; 1217 /* Replay feature is supported */ 1218 bool replay_supported; 1219 /* Replay caps support DPCD & EDID caps*/ 1220 bool replay_cap_support; 1221 /* Power opt flags that are supported */ 1222 unsigned int replay_power_opt_supported; 1223 /* SMU optimization is supported */ 1224 bool replay_smu_opt_supported; 1225 /* Replay enablement option */ 1226 unsigned int replay_enable_option; 1227 /* Replay debug flags */ 1228 uint32_t debug_flags; 1229 /* Replay sync is supported */ 1230 bool replay_timing_sync_supported; 1231 /* Replay Disable desync error check. */ 1232 bool force_disable_desync_error_check; 1233 /* Replay Received Desync Error HPD. */ 1234 bool received_desync_error_hpd; 1235 /* Replay feature is supported long vblank */ 1236 bool replay_support_fast_resync_in_ultra_sleep_mode; 1237 /* Replay error status */ 1238 union replay_error_status replay_error_status; 1239 /* Replay Low Hz enable Options */ 1240 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1241 /* Replay coasting vtotal is within low refresh rate range. */ 1242 bool low_rr_activated; 1243 /* Replay low refresh rate supported*/ 1244 bool low_rr_supported; 1245 /* Replay Video Conferencing Optimization Enabled */ 1246 bool replay_video_conferencing_optimization_enabled; 1247 /* Replay alpm mode */ 1248 enum dc_alpm_mode alpm_mode; 1249 /* Replay full screen only */ 1250 bool os_request_force_ffu; 1251 /* Replay optimization */ 1252 union replay_optimization replay_optimization; 1253 /* Replay sub feature Frame Skipping is supported */ 1254 bool frame_skip_supported; 1255 /* Replay Received Frame Skipping Error HPD. */ 1256 bool received_frame_skipping_error_hpd; 1257 /* Live capture with CVT is activated */ 1258 bool live_capture_with_cvt_activated; 1259 }; 1260 1261 /* Replay feature flags*/ 1262 struct replay_settings { 1263 /* Replay configuration */ 1264 struct replay_config config; 1265 /* Replay feature is ready for activating */ 1266 bool replay_feature_enabled; 1267 /* Replay is currently active */ 1268 bool replay_allow_active; 1269 /* Replay is currently active */ 1270 bool replay_allow_long_vblank; 1271 /* Power opt flags that are activated currently */ 1272 unsigned int replay_power_opt_active; 1273 /* SMU optimization is enabled */ 1274 bool replay_smu_opt_enable; 1275 /* Current Coasting vtotal */ 1276 uint32_t coasting_vtotal; 1277 /* Coasting vtotal table */ 1278 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1279 /* Defer Update Coasting vtotal table */ 1280 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1281 /* Skip frame number table */ 1282 uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1283 /* Defer skip frame number table */ 1284 uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1285 /* Maximum link off frame count */ 1286 uint32_t link_off_frame_count; 1287 /* Replay pseudo vtotal for low refresh rate*/ 1288 uint16_t low_rr_full_screen_video_pseudo_vtotal; 1289 /* Replay last pseudo vtotal set to DMUB */ 1290 uint16_t last_pseudo_vtotal; 1291 /* Replay desync error */ 1292 uint32_t replay_desync_error_fail_count; 1293 /* The frame skip number dal send to DMUB */ 1294 uint16_t frame_skip_number; 1295 /* Current Panel Replay events */ 1296 uint32_t replay_events; 1297 }; 1298 1299 /* To split out "global" and "per-panel" config settings. 1300 * Add a struct dc_panel_config under dc_link 1301 */ 1302 struct dc_panel_config { 1303 /* extra panel power sequence parameters */ 1304 struct pps { 1305 unsigned int extra_t3_ms; 1306 unsigned int extra_t7_ms; 1307 unsigned int extra_delay_backlight_off; 1308 unsigned int extra_post_t7_ms; 1309 unsigned int extra_pre_t11_ms; 1310 unsigned int extra_t12_ms; 1311 unsigned int extra_post_OUI_ms; 1312 } pps; 1313 /* nit brightness */ 1314 struct nits_brightness { 1315 unsigned int peak; /* nits */ 1316 unsigned int max_avg; /* nits */ 1317 unsigned int min; /* 1/10000 nits */ 1318 unsigned int max_nonboost_brightness_millinits; 1319 unsigned int min_brightness_millinits; 1320 } nits_brightness; 1321 /* PSR/Replay */ 1322 struct psr { 1323 bool disable_psr; 1324 bool disallow_psrsu; 1325 bool disallow_replay; 1326 bool rc_disable; 1327 bool rc_allow_static_screen; 1328 bool rc_allow_fullscreen_VPB; 1329 bool read_psrcap_again; 1330 unsigned int replay_enable_option; 1331 bool enable_frame_skipping; 1332 bool enable_teams_optimization; 1333 } psr; 1334 /* ABM */ 1335 struct varib { 1336 unsigned int varibright_feature_enable; 1337 unsigned int def_varibright_level; 1338 unsigned int abm_config_setting; 1339 } varib; 1340 /* edp DSC */ 1341 struct dsc { 1342 bool disable_dsc_edp; 1343 unsigned int force_dsc_edp_policy; 1344 } dsc; 1345 /* eDP ILR */ 1346 struct ilr { 1347 bool optimize_edp_link_rate; /* eDP ILR */ 1348 } ilr; 1349 /* Adaptive VariBright*/ 1350 struct adaptive_vb { 1351 bool disable_adaptive_vb; 1352 unsigned int default_abm_vb_levels; // default value = 0xDCAA6414 1353 unsigned int default_cacp_vb_levels; 1354 unsigned int default_abm_vb_hdr_levels; // default value = 0xB4805A40 1355 unsigned int default_cacp_vb_hdr_levels; 1356 unsigned int abm_scaling_factors; // default value = 0x23210012 1357 unsigned int cacp_scaling_factors; 1358 unsigned int battery_life_configures; // default value = 0x0A141E 1359 unsigned int abm_backlight_adaptive_pwl_1; // default value = 0x6A4F7244 1360 unsigned int abm_backlight_adaptive_pwl_2; // default value = 0x4C615659 1361 unsigned int abm_backlight_adaptive_pwl_3; // default value = 0x0064 1362 unsigned int cacp_backlight_adaptive_pwl_1; 1363 unsigned int cacp_backlight_adaptive_pwl_2; 1364 unsigned int cacp_backlight_adaptive_pwl_3; 1365 } adaptive_vb; 1366 /* Ramless Idle Opt*/ 1367 struct rio { 1368 bool disable_rio; 1369 } rio; 1370 }; 1371 1372 struct mccs_caps { 1373 bool freesync_supported; 1374 }; 1375 1376 #define MAX_SINKS_PER_LINK 4 1377 1378 /* 1379 * USB4 DPIA BW ALLOCATION STRUCTS 1380 */ 1381 struct dc_dpia_bw_alloc { 1382 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1383 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1384 int link_max_bw; // The Max BW that link can require/support 1385 int allocated_bw; // The Actual Allocated BW for this DPIA 1386 int estimated_bw; // The estimated available BW for this DPIA 1387 int bw_granularity; // BW Granularity 1388 int dp_overhead; // DP overhead in dp tunneling 1389 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1390 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1391 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1392 }; 1393 1394 enum dc_hpd_enable_select { 1395 HPD_EN_FOR_ALL_EDP = 0, 1396 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1397 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1398 }; 1399 1400 enum dc_cm2_shaper_3dlut_setting { 1401 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1402 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1403 /* Bypassing Shaper will always bypass 3DLUT */ 1404 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1405 }; 1406 1407 enum dc_cm2_gpu_mem_layout { 1408 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1409 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1410 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1411 }; 1412 1413 enum dc_cm2_gpu_mem_pixel_component_order { 1414 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1415 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA 1416 }; 1417 1418 enum dc_cm2_gpu_mem_format { 1419 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1420 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1421 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1422 }; 1423 1424 struct dc_cm2_gpu_mem_format_parameters { 1425 enum dc_cm2_gpu_mem_format format; 1426 union { 1427 struct { 1428 /* bias & scale for float only */ 1429 uint16_t bias; 1430 uint16_t scale; 1431 } float_params; 1432 }; 1433 }; 1434 1435 enum dc_cm2_gpu_mem_size { 1436 DC_CM2_GPU_MEM_SIZE_171717, 1437 DC_CM2_GPU_MEM_SIZE_333333, 1438 DC_CM2_GPU_MEM_SIZE_454545, 1439 DC_CM2_GPU_MEM_SIZE_656565, 1440 DC_CM2_GPU_MEM_SIZE_TRANSFORMED, 1441 }; 1442 1443 struct dc_cm2_gpu_mem_parameters { 1444 struct dc_plane_address addr; 1445 enum dc_cm2_gpu_mem_layout layout; 1446 struct dc_cm2_gpu_mem_format_parameters format_params; 1447 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1448 enum dc_cm2_gpu_mem_size size; 1449 uint16_t bit_depth; 1450 }; 1451 1452 enum dc_cm2_transfer_func_source { 1453 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1454 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1455 }; 1456 1457 struct dc_cm2_component_settings { 1458 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1459 bool lut1d_enable; 1460 }; 1461 1462 /* 1463 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1464 */ 1465 struct dc_cm2_func_luts { 1466 const struct dc_transfer_func *shaper; 1467 struct { 1468 enum dc_cm2_transfer_func_source lut3d_src; 1469 union { 1470 const struct dc_3dlut *lut3d_func; 1471 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1472 }; 1473 bool rmcm_3dlut_shaper_select; 1474 bool mpc_3dlut_enable; 1475 bool rmcm_3dlut_enable; 1476 bool mpc_mcm_post_blend; 1477 uint8_t rmcm_tmz; 1478 } lut3d_data; 1479 const struct dc_transfer_func *lut1d_func; 1480 }; 1481 1482 struct dc_cm2_parameters { 1483 struct dc_cm2_component_settings component_settings; 1484 struct dc_cm2_func_luts cm2_luts; 1485 }; 1486 1487 enum mall_stream_type { 1488 SUBVP_NONE, // subvp not in use 1489 SUBVP_MAIN, // subvp in use, this stream is main stream 1490 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1491 }; 1492 1493 enum dc_power_source_type { 1494 DC_POWER_SOURCE_AC, // wall power 1495 DC_POWER_SOURCE_DC, // battery power 1496 }; 1497 1498 struct dc_state_create_params { 1499 enum dc_power_source_type power_source; 1500 }; 1501 1502 struct dc_commit_streams_params { 1503 struct dc_stream_state **streams; 1504 uint8_t stream_count; 1505 enum dc_power_source_type power_source; 1506 }; 1507 1508 struct set_backlight_level_params { 1509 /* backlight in pwm */ 1510 uint32_t backlight_pwm_u16_16; 1511 /* brightness ramping */ 1512 uint32_t frame_ramp; 1513 /* backlight control type 1514 * 0: PWM backlight control 1515 * 1: VESA AUX backlight control 1516 * 2: AMD AUX backlight control 1517 */ 1518 enum backlight_control_type control_type; 1519 /* backlight in millinits */ 1520 uint32_t backlight_millinits; 1521 /* transition time in ms */ 1522 uint32_t transition_time_in_ms; 1523 /* minimum luminance in nits */ 1524 uint32_t min_luminance; 1525 /* maximum luminance in nits */ 1526 uint32_t max_luminance; 1527 /* minimum backlight in pwm */ 1528 uint32_t min_backlight_pwm; 1529 /* maximum backlight in pwm */ 1530 uint32_t max_backlight_pwm; 1531 /* AUX HW instance */ 1532 uint8_t aux_inst; 1533 }; 1534 1535 enum dc_validate_mode { 1536 /* validate the mode and program HW */ 1537 DC_VALIDATE_MODE_AND_PROGRAMMING = 0, 1538 /* only validate the mode */ 1539 DC_VALIDATE_MODE_ONLY = 1, 1540 /* validate the mode and get the max state (voltage level) */ 1541 DC_VALIDATE_MODE_AND_STATE_INDEX = 2, 1542 }; 1543 1544 struct dc_validation_dpia_set { 1545 const struct dc_link *link; 1546 const struct dc_tunnel_settings *tunnel_settings; 1547 uint32_t required_bw; 1548 }; 1549 1550 #endif /* DC_TYPES_H_ */ 1551