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Searched refs:KHz (Results 1 – 25 of 94) sorted by relevance

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/linux/drivers/cpufreq/
H A Dcppc_cpufreq.c411 unsigned long *power, unsigned long *KHz) in cppc_get_cpu_power() argument
415 unsigned long prev_freq = *KHz; in cppc_get_cpu_power()
433 perf_prev = cppc_khz_to_perf(perf_caps, *KHz); in cppc_get_cpu_power()
453 *KHz = cppc_perf_to_khz(perf_caps, perf); in cppc_get_cpu_power()
454 perf_check = cppc_khz_to_perf(perf_caps, *KHz); in cppc_get_cpu_power()
462 while ((*KHz == prev_freq) || (step_check != step)) { in cppc_get_cpu_power()
464 *KHz = cppc_perf_to_khz(perf_caps, perf); in cppc_get_cpu_power()
465 perf_check = cppc_khz_to_perf(perf_caps, *KHz); in cppc_get_cpu_power()
479 static int cppc_get_cpu_cost(struct device *cpu_dev, unsigned long KHz, in cppc_get_cpu_cost() argument
494 perf_prev = cppc_khz_to_perf(perf_caps, KHz); in cppc_get_cpu_cost()
H A Dscmi-cpufreq.c122 unsigned long *KHz) in scmi_get_cpu_power() argument
133 Hz = *KHz * 1000; in scmi_get_cpu_power()
143 *KHz = Hz / 1000; in scmi_get_cpu_power()
H A Dmediatek-cpufreq-hw.c57 unsigned long *KHz) in mtk_cpufreq_get_cpu_power() argument
70 if (data->table[i].frequency < *KHz) in mtk_cpufreq_get_cpu_power()
75 *KHz = data->table[i].frequency; in mtk_cpufreq_get_cpu_power()
/linux/Documentation/translations/zh_CN/power/
H A Denergy-model.rst171 02 unsigned long *KHz)
176 07 freq = foo_get_freq_ceil(dev, *KHz);
187 18 *KHz = freq;
/linux/Documentation/ABI/testing/
H A Dsysfs-class-rtc-rtc0-device-rtc_calibration7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
/linux/arch/arm/mach-omap1/
H A DKconfig66 bool "Use 32KHz timer"
70 Select this option if you want to enable the OMAP 32KHz timer.
72 support for no tick during idle. The 32KHz timer provides less
73 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
86 timer provides more intra-tick resolution than the 32KHz timer,
/linux/Documentation/devicetree/bindings/clock/
H A Dclk-palmas-clk32kg-clocks.txt1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
H A Dvf610-clock.txt16 - sxosc (external crystal oscillator 32KHz, recommended)
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c376 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1411_set_if_freq() argument
380 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1411_set_if_freq()
382 switch (KHz) { in s5h1411_set_if_freq()
400 __func__, KHz); in s5h1411_set_if_freq()
410 state->if_freq = KHz; in s5h1411_set_if_freq()
H A Ds5h1409.c353 static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1409_set_if_freq() argument
357 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1409_set_if_freq()
359 switch (KHz) { in s5h1409_set_if_freq()
373 state->if_freq = KHz; in s5h1409_set_if_freq()
/linux/Documentation/devicetree/bindings/mfd/
H A Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
H A Dsun8i-reference-design-tablet.dtsi67 * The gsl1680 is rated at 400KHz and it will not work reliable at
68 * 100KHz, this has been confirmed on multiple different q8 tablets.
/linux/drivers/clk/pxa/
H A Dclk-pxa27x.c21 #define KHz 1000 macro
100 return (unsigned int)clks[0] / KHz; in pxa27x_get_clk_frequency_khz()
294 32768 * KHz)); in pxa27x_register_plls()
H A Dclk-pxa25x.c25 #define KHz 1000 macro
97 return (unsigned int)clks[0] / KHz; in pxa25x_get_clk_frequency_khz()
H A Dclk-pxa3xx.c24 #define KHz 1000 macro
157 return (unsigned int)clks[0] / KHz; in pxa3xx_get_clk_frequency_khz()
/linux/Documentation/devicetree/bindings/media/
H A Dimg-ir-rev1.txt16 1st: Core clock (defaults to 32.768KHz if omitted).
/linux/drivers/gpu/drm/i915/
H A Di915_utils.h336 #define KHz(x) (1000 * (x)) macro
337 #define MHz(x) KHz(1000 * (x))
/linux/Documentation/userspace-api/media/dvb/
H A Dfe-diseqc-send-burst.rst13 FE_DISEQC_SEND_BURST - Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection.
/linux/Documentation/misc-devices/
H A Dics932s401.rst27 All frequencies are reported in KHz.
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull.dtsi25 /* KHz uV */
/linux/Documentation/i2c/busses/
H A Di2c-sis630.rst25 high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
/linux/drivers/gpu/drm/i915/display/
H A Dintel_backlight.c1014 return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), in cnp_hz_to_pwm()
1023 return DIV_ROUND_CLOSEST(KHz(19200), pwm_freq_hz); in bxt_hz_to_pwm()
1076 return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), in pch_hz_to_pwm()
1094 clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); in i9xx_hz_to_pwm()
1096 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1112 clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); in i965_hz_to_pwm()
1114 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
1131 clock = KHz(19200); in vlv_hz_to_pwm()
1136 clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); in vlv_hz_to_pwm()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-nanopc-t4.dts59 * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Delf_hwcaps.rst71 通用計時器頻率配置爲大約100KHz以生成事件。

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