xref: /linux/drivers/crypto/caam/regs.h (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * CAAM hardware register-level view
4  *
5  * Copyright 2008-2011 Freescale Semiconductor, Inc.
6  * Copyright 2018, 2023 NXP
7  */
8 
9 #ifndef REGS_H
10 #define REGS_H
11 
12 #include <linux/types.h>
13 #include <linux/bitops.h>
14 #include <linux/io.h>
15 #include <linux/io-64-nonatomic-hi-lo.h>
16 
17 /*
18  * Architecture-specific register access methods
19  *
20  * CAAM's bus-addressable registers are 64 bits internally.
21  * They have been wired to be safely accessible on 32-bit
22  * architectures, however. Registers were organized such
23  * that (a) they can be contained in 32 bits, (b) if not, then they
24  * can be treated as two 32-bit entities, or finally (c) if they
25  * must be treated as a single 64-bit value, then this can safely
26  * be done with two 32-bit cycles.
27  *
28  * For 32-bit operations on 64-bit values, CAAM follows the same
29  * 64-bit register access conventions as it's predecessors, in that
30  * writes are "triggered" by a write to the register at the numerically
31  * higher address, thus, a full 64-bit write cycle requires a write
32  * to the lower address, followed by a write to the higher address,
33  * which will latch/execute the write cycle.
34  *
35  * For example, let's assume a SW reset of CAAM through the master
36  * configuration register.
37  * - SWRST is in bit 31 of MCFG.
38  * - MCFG begins at base+0x0000.
39  * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
40  * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
41  *
42  * (and on Power, the convention is 0-31, 32-63, I know...)
43  *
44  * Assuming a 64-bit write to this MCFG to perform a software reset
45  * would then require a write of 0 to base+0x0000, followed by a
46  * write of 0x80000000 to base+0x0004, which would "execute" the
47  * reset.
48  *
49  * Of course, since MCFG 63-32 is all zero, we could cheat and simply
50  * write 0x8000000 to base+0x0004, and the reset would work fine.
51  * However, since CAAM does contain some write-and-read-intended
52  * 64-bit registers, this code defines 64-bit access methods for
53  * the sake of internal consistency and simplicity, and so that a
54  * clean transition to 64-bit is possible when it becomes necessary.
55  *
56  * There are limitations to this that the developer must recognize.
57  * 32-bit architectures cannot enforce an atomic-64 operation,
58  * Therefore:
59  *
60  * - On writes, since the HW is assumed to latch the cycle on the
61  *   write of the higher-numeric-address word, then ordered
62  *   writes work OK.
63  *
64  * - For reads, where a register contains a relevant value of more
65  *   that 32 bits, the hardware employs logic to latch the other
66  *   "half" of the data until read, ensuring an accurate value.
67  *   This is of particular relevance when dealing with CAAM's
68  *   performance counters.
69  *
70  */
71 
72 extern bool caam_little_end;
73 extern bool caam_imx;
74 extern size_t caam_ptr_sz;
75 
76 #define caam_to_cpu(len)						\
77 static inline u##len caam##len ## _to_cpu(u##len val)			\
78 {									\
79 	if (caam_little_end)						\
80 		return le##len ## _to_cpu((__force __le##len)val);	\
81 	else								\
82 		return be##len ## _to_cpu((__force __be##len)val);	\
83 }
84 
85 #define cpu_to_caam(len)					\
86 static inline u##len cpu_to_caam##len(u##len val)		\
87 {								\
88 	if (caam_little_end)					\
89 		return (__force u##len)cpu_to_le##len(val);	\
90 	else							\
91 		return (__force u##len)cpu_to_be##len(val);	\
92 }
93 
94 caam_to_cpu(16)
95 caam_to_cpu(32)
96 caam_to_cpu(64)
97 cpu_to_caam(16)
98 cpu_to_caam(32)
99 cpu_to_caam(64)
100 
wr_reg32(void __iomem * reg,u32 data)101 static inline void wr_reg32(void __iomem *reg, u32 data)
102 {
103 	if (caam_little_end)
104 		iowrite32(data, reg);
105 	else
106 		iowrite32be(data, reg);
107 }
108 
rd_reg32(void __iomem * reg)109 static inline u32 rd_reg32(void __iomem *reg)
110 {
111 	if (caam_little_end)
112 		return ioread32(reg);
113 
114 	return ioread32be(reg);
115 }
116 
clrsetbits_32(void __iomem * reg,u32 clear,u32 set)117 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
118 {
119 	if (caam_little_end)
120 		iowrite32((ioread32(reg) & ~clear) | set, reg);
121 	else
122 		iowrite32be((ioread32be(reg) & ~clear) | set, reg);
123 }
124 
125 /*
126  * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
127  * The DMA address registers in the JR are handled differently depending on
128  * platform:
129  *
130  * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
131  *
132  *    base + 0x0000 : most-significant 32 bits
133  *    base + 0x0004 : least-significant 32 bits
134  *
135  * The 32-bit version of this core therefore has to write to base + 0x0004
136  * to set the 32-bit wide DMA address.
137  *
138  * 2. All other LE CAAM platforms (LS1021A etc.)
139  *    base + 0x0000 : least-significant 32 bits
140  *    base + 0x0004 : most-significant 32 bits
141  */
wr_reg64(void __iomem * reg,u64 data)142 static inline void wr_reg64(void __iomem *reg, u64 data)
143 {
144 	if (caam_little_end) {
145 		if (caam_imx) {
146 			iowrite32(data >> 32, (u32 __iomem *)(reg));
147 			iowrite32(data, (u32 __iomem *)(reg) + 1);
148 		} else {
149 			iowrite64(data, reg);
150 		}
151 	} else {
152 		iowrite64be(data, reg);
153 	}
154 }
155 
rd_reg64(void __iomem * reg)156 static inline u64 rd_reg64(void __iomem *reg)
157 {
158 	if (caam_little_end) {
159 		if (caam_imx) {
160 			u32 low, high;
161 
162 			high = ioread32(reg);
163 			low  = ioread32(reg + sizeof(u32));
164 
165 			return low + ((u64)high << 32);
166 		} else {
167 			return ioread64(reg);
168 		}
169 	} else {
170 		return ioread64be(reg);
171 	}
172 }
173 
cpu_to_caam_dma64(dma_addr_t value)174 static inline u64 cpu_to_caam_dma64(dma_addr_t value)
175 {
176 	if (caam_imx) {
177 		u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32;
178 
179 		if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
180 			ret_val |= (u64)cpu_to_caam32(upper_32_bits(value));
181 
182 		return ret_val;
183 	}
184 
185 	return cpu_to_caam64(value);
186 }
187 
caam_dma64_to_cpu(u64 value)188 static inline u64 caam_dma64_to_cpu(u64 value)
189 {
190 	if (caam_imx)
191 		return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
192 			 (u64)caam32_to_cpu(upper_32_bits(value)));
193 
194 	return caam64_to_cpu(value);
195 }
196 
cpu_to_caam_dma(u64 value)197 static inline u64 cpu_to_caam_dma(u64 value)
198 {
199 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
200 	    caam_ptr_sz == sizeof(u64))
201 		return cpu_to_caam_dma64(value);
202 	else
203 		return cpu_to_caam32(value);
204 }
205 
caam_dma_to_cpu(u64 value)206 static inline u64 caam_dma_to_cpu(u64 value)
207 {
208 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
209 	    caam_ptr_sz == sizeof(u64))
210 		return caam_dma64_to_cpu(value);
211 	else
212 		return caam32_to_cpu(value);
213 }
214 
215 /*
216  * jr_outentry
217  * Represents each entry in a JobR output ring
218  */
219 
jr_outentry_get(void * outring,int hw_idx,dma_addr_t * desc,u32 * jrstatus)220 static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
221 				   u32 *jrstatus)
222 {
223 
224 	if (caam_ptr_sz == sizeof(u32)) {
225 		struct {
226 			u32 desc;
227 			u32 jrstatus;
228 		} __packed *outentry = outring;
229 
230 		*desc = outentry[hw_idx].desc;
231 		*jrstatus = outentry[hw_idx].jrstatus;
232 	} else {
233 		struct {
234 			dma_addr_t desc;/* Pointer to completed descriptor */
235 			u32 jrstatus;	/* Status for completed descriptor */
236 		} __packed *outentry = outring;
237 
238 		*desc = outentry[hw_idx].desc;
239 		*jrstatus = outentry[hw_idx].jrstatus;
240 	}
241 }
242 
243 #define SIZEOF_JR_OUTENTRY	(caam_ptr_sz + sizeof(u32))
244 
jr_outentry_desc(void * outring,int hw_idx)245 static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx)
246 {
247 	dma_addr_t desc;
248 	u32 unused;
249 
250 	jr_outentry_get(outring, hw_idx, &desc, &unused);
251 
252 	return desc;
253 }
254 
jr_outentry_jrstatus(void * outring,int hw_idx)255 static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
256 {
257 	dma_addr_t unused;
258 	u32 jrstatus;
259 
260 	jr_outentry_get(outring, hw_idx, &unused, &jrstatus);
261 
262 	return jrstatus;
263 }
264 
jr_inpentry_set(void * inpring,int hw_idx,dma_addr_t val)265 static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
266 {
267 	if (caam_ptr_sz == sizeof(u32)) {
268 		u32 *inpentry = inpring;
269 
270 		inpentry[hw_idx] = val;
271 	} else {
272 		dma_addr_t *inpentry = inpring;
273 
274 		inpentry[hw_idx] = val;
275 	}
276 }
277 
278 #define SIZEOF_JR_INPENTRY	caam_ptr_sz
279 
280 
281 /* Version registers (Era 10+)	e80-eff */
282 struct version_regs {
283 	u32 crca;	/* CRCA_VERSION */
284 	u32 afha;	/* AFHA_VERSION */
285 	u32 kfha;	/* KFHA_VERSION */
286 	u32 pkha;	/* PKHA_VERSION */
287 	u32 aesa;	/* AESA_VERSION */
288 	u32 mdha;	/* MDHA_VERSION */
289 	u32 desa;	/* DESA_VERSION */
290 	u32 snw8a;	/* SNW8A_VERSION */
291 	u32 snw9a;	/* SNW9A_VERSION */
292 	u32 zuce;	/* ZUCE_VERSION */
293 	u32 zuca;	/* ZUCA_VERSION */
294 	u32 ccha;	/* CCHA_VERSION */
295 	u32 ptha;	/* PTHA_VERSION */
296 	u32 rng;	/* RNG_VERSION */
297 	u32 trng;	/* TRNG_VERSION */
298 	u32 aaha;	/* AAHA_VERSION */
299 	u32 rsvd[10];
300 	u32 sr;		/* SR_VERSION */
301 	u32 dma;	/* DMA_VERSION */
302 	u32 ai;		/* AI_VERSION */
303 	u32 qi;		/* QI_VERSION */
304 	u32 jr;		/* JR_VERSION */
305 	u32 deco;	/* DECO_VERSION */
306 };
307 
308 /* Version registers bitfields */
309 
310 /* Number of CHAs instantiated */
311 #define CHA_VER_NUM_MASK	0xffull
312 /* CHA Miscellaneous Information */
313 #define CHA_VER_MISC_SHIFT	8
314 #define CHA_VER_MISC_MASK	(0xffull << CHA_VER_MISC_SHIFT)
315 /* CHA Revision Number */
316 #define CHA_VER_REV_SHIFT	16
317 #define CHA_VER_REV_MASK	(0xffull << CHA_VER_REV_SHIFT)
318 /* CHA Version ID */
319 #define CHA_VER_VID_SHIFT	24
320 #define CHA_VER_VID_MASK	(0xffull << CHA_VER_VID_SHIFT)
321 
322 /* CHA Miscellaneous Information - AESA_MISC specific */
323 #define CHA_VER_MISC_AES_NUM_MASK	GENMASK(7, 0)
324 #define CHA_VER_MISC_AES_GCM		BIT(1 + CHA_VER_MISC_SHIFT)
325 
326 /* CHA Miscellaneous Information - PKHA_MISC specific */
327 #define CHA_VER_MISC_PKHA_NO_CRYPT	BIT(7 + CHA_VER_MISC_SHIFT)
328 
329 /*
330  * caam_perfmon - Performance Monitor/Secure Memory Status/
331  *                CAAM Global Status/Component Version IDs
332  *
333  * Spans f00-fff wherever instantiated
334  */
335 
336 /* Number of DECOs */
337 #define CHA_NUM_MS_DECONUM_SHIFT	24
338 #define CHA_NUM_MS_DECONUM_MASK	(0xfull << CHA_NUM_MS_DECONUM_SHIFT)
339 
340 /*
341  * CHA version IDs / instantiation bitfields (< Era 10)
342  * Defined for use with the cha_id fields in perfmon, but the same shift/mask
343  * selectors can be used to pull out the number of instantiated blocks within
344  * cha_num fields in perfmon because the locations are the same.
345  */
346 #define CHA_ID_LS_AES_SHIFT	0
347 #define CHA_ID_LS_AES_MASK	(0xfull << CHA_ID_LS_AES_SHIFT)
348 
349 #define CHA_ID_LS_DES_SHIFT	4
350 #define CHA_ID_LS_DES_MASK	(0xfull << CHA_ID_LS_DES_SHIFT)
351 
352 #define CHA_ID_LS_ARC4_SHIFT	8
353 #define CHA_ID_LS_ARC4_MASK	(0xfull << CHA_ID_LS_ARC4_SHIFT)
354 
355 #define CHA_ID_LS_MD_SHIFT	12
356 #define CHA_ID_LS_MD_MASK	(0xfull << CHA_ID_LS_MD_SHIFT)
357 
358 #define CHA_ID_LS_RNG_SHIFT	16
359 #define CHA_ID_LS_RNG_MASK	(0xfull << CHA_ID_LS_RNG_SHIFT)
360 
361 #define CHA_ID_LS_SNW8_SHIFT	20
362 #define CHA_ID_LS_SNW8_MASK	(0xfull << CHA_ID_LS_SNW8_SHIFT)
363 
364 #define CHA_ID_LS_KAS_SHIFT	24
365 #define CHA_ID_LS_KAS_MASK	(0xfull << CHA_ID_LS_KAS_SHIFT)
366 
367 #define CHA_ID_LS_PK_SHIFT	28
368 #define CHA_ID_LS_PK_MASK	(0xfull << CHA_ID_LS_PK_SHIFT)
369 
370 #define CHA_ID_MS_CRC_SHIFT	0
371 #define CHA_ID_MS_CRC_MASK	(0xfull << CHA_ID_MS_CRC_SHIFT)
372 
373 #define CHA_ID_MS_SNW9_SHIFT	4
374 #define CHA_ID_MS_SNW9_MASK	(0xfull << CHA_ID_MS_SNW9_SHIFT)
375 
376 #define CHA_ID_MS_DECO_SHIFT	24
377 #define CHA_ID_MS_DECO_MASK	(0xfull << CHA_ID_MS_DECO_SHIFT)
378 
379 #define CHA_ID_MS_JR_SHIFT	28
380 #define CHA_ID_MS_JR_MASK	(0xfull << CHA_ID_MS_JR_SHIFT)
381 
382 /* Specific CHA version IDs */
383 #define CHA_VER_VID_AES_LP	0x3ull
384 #define CHA_VER_VID_AES_HP	0x4ull
385 #define CHA_VER_VID_MD_LP256	0x0ull
386 #define CHA_VER_VID_MD_LP512	0x1ull
387 #define CHA_VER_VID_MD_HP	0x2ull
388 
389 struct sec_vid {
390 	u16 ip_id;
391 	u8 maj_rev;
392 	u8 min_rev;
393 };
394 
395 struct caam_perfmon {
396 	/* Performance Monitor Registers			f00-f9f */
397 	u64 req_dequeued;	/* PC_REQ_DEQ - Dequeued Requests	     */
398 	u64 ob_enc_req;	/* PC_OB_ENC_REQ - Outbound Encrypt Requests */
399 	u64 ib_dec_req;	/* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
400 	u64 ob_enc_bytes;	/* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
401 	u64 ob_prot_bytes;	/* PC_OB_PROTECT - Outbound Bytes Protected  */
402 	u64 ib_dec_bytes;	/* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
403 	u64 ib_valid_bytes;	/* PC_IB_VALIDATED Inbound Bytes Validated   */
404 	u64 rsvd[13];
405 
406 	/* CAAM Hardware Instantiation Parameters		fa0-fbf */
407 	u32 cha_rev_ms;		/* CRNR - CHA Rev No. Most significant half*/
408 	u32 cha_rev_ls;		/* CRNR - CHA Rev No. Least significant half*/
409 #define CTPR_MS_QI_SHIFT	25
410 #define CTPR_MS_QI_MASK		(0x1ull << CTPR_MS_QI_SHIFT)
411 #define CTPR_MS_PS		BIT(17)
412 #define CTPR_MS_DPAA2		BIT(13)
413 #define CTPR_MS_VIRT_EN_INCL	0x00000001
414 #define CTPR_MS_VIRT_EN_POR	0x00000002
415 #define CTPR_MS_PG_SZ_MASK	0x10
416 #define CTPR_MS_PG_SZ_SHIFT	4
417 	u32 comp_parms_ms;	/* CTPR - Compile Parameters Register	*/
418 #define CTPR_LS_BLOB           BIT(1)
419 	u32 comp_parms_ls;	/* CTPR - Compile Parameters Register	*/
420 	u64 rsvd1[2];
421 
422 	/* CAAM Global Status					fc0-fdf */
423 	u64 faultaddr;	/* FAR  - Fault Address		*/
424 	u32 faultliodn;	/* FALR - Fault Address LIODN	*/
425 	u32 faultdetail;	/* FADR - Fault Addr Detail	*/
426 	u32 rsvd2;
427 #define CSTA_PLEND		BIT(10)
428 #define CSTA_ALT_PLEND		BIT(18)
429 #define CSTA_MOO		GENMASK(9, 8)
430 #define CSTA_MOO_SECURE	1
431 #define CSTA_MOO_TRUSTED	2
432 	u32 status;		/* CSTA - CAAM Status */
433 	u64 rsvd3;
434 
435 	/* Component Instantiation Parameters			fe0-fff */
436 	u32 rtic_id;		/* RVID - RTIC Version ID	*/
437 #define CCBVID_ERA_MASK		0xff000000
438 #define CCBVID_ERA_SHIFT	24
439 	u32 ccb_id;		/* CCBVID - CCB Version ID	*/
440 	u32 cha_id_ms;		/* CHAVID - CHA Version ID Most Significant*/
441 	u32 cha_id_ls;		/* CHAVID - CHA Version ID Least Significant*/
442 	u32 cha_num_ms;		/* CHANUM - CHA Number Most Significant	*/
443 	u32 cha_num_ls;		/* CHANUM - CHA Number Least Significant*/
444 #define SECVID_MS_IPID_MASK	0xffff0000
445 #define SECVID_MS_IPID_SHIFT	16
446 #define SECVID_MS_MAJ_REV_MASK	0x0000ff00
447 #define SECVID_MS_MAJ_REV_SHIFT	8
448 	u32 caam_id_ms;		/* CAAMVID - CAAM Version ID MS	*/
449 	u32 caam_id_ls;		/* CAAMVID - CAAM Version ID LS	*/
450 };
451 
452 /* LIODN programming for DMA configuration */
453 #define MSTRID_LOCK_LIODN	0x80000000
454 #define MSTRID_LOCK_MAKETRUSTED	0x00010000	/* only for JR masterid */
455 
456 #define MSTRID_LIODN_MASK	0x0fff
457 struct masterid {
458 	u32 liodn_ms;	/* lock and make-trusted control bits */
459 	u32 liodn_ls;	/* LIODN for non-sequence and seq access */
460 };
461 
462 /* RNGB test mode (replicated twice in some configurations) */
463 /* Padded out to 0x100 */
464 struct rngtst {
465 	u32 mode;		/* RTSTMODEx - Test mode */
466 	u32 rsvd1[3];
467 	u32 reset;		/* RTSTRESETx - Test reset control */
468 	u32 rsvd2[3];
469 	u32 status;		/* RTSTSSTATUSx - Test status */
470 	u32 rsvd3;
471 	u32 errstat;		/* RTSTERRSTATx - Test error status */
472 	u32 rsvd4;
473 	u32 errctl;		/* RTSTERRCTLx - Test error control */
474 	u32 rsvd5;
475 	u32 entropy;		/* RTSTENTROPYx - Test entropy */
476 	u32 rsvd6[15];
477 	u32 verifctl;	/* RTSTVERIFCTLx - Test verification control */
478 	u32 rsvd7;
479 	u32 verifstat;	/* RTSTVERIFSTATx - Test verification status */
480 	u32 rsvd8;
481 	u32 verifdata;	/* RTSTVERIFDx - Test verification data */
482 	u32 rsvd9;
483 	u32 xkey;		/* RTSTXKEYx - Test XKEY */
484 	u32 rsvd10;
485 	u32 oscctctl;	/* RTSTOSCCTCTLx - Test osc. counter control */
486 	u32 rsvd11;
487 	u32 oscct;		/* RTSTOSCCTx - Test oscillator counter */
488 	u32 rsvd12;
489 	u32 oscctstat;	/* RTSTODCCTSTATx - Test osc counter status */
490 	u32 rsvd13[2];
491 	u32 ofifo[4];	/* RTSTOFIFOx - Test output FIFO */
492 	u32 rsvd14[15];
493 };
494 
495 /* RNG4 TRNG test registers */
496 struct rng4tst {
497 #define RTMCTL_ACC  BIT(5)  /* TRNG access mode */
498 #define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */
499 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC	0 /* use von Neumann data in
500 						     both entropy shifter and
501 						     statistical checker */
502 #define RTMCTL_SAMP_MODE_RAW_ES_SC		1 /* use raw data in both
503 						     entropy shifter and
504 						     statistical checker */
505 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC	2 /* use von Neumann data in
506 						     entropy shifter, raw data
507 						     in statistical checker */
508 #define RTMCTL_SAMP_MODE_INVALID		3 /* invalid combination */
509 	u32 rtmctl;		/* misc. control register */
510 	u32 rtscmisc;		/* statistical check misc. register */
511 	u32 rtpkrrng;		/* poker range register */
512 	union {
513 		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
514 		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
515 	};
516 #define RTSDCTL_ENT_DLY_SHIFT 16
517 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
518 #define RTSDCTL_ENT_DLY_MIN 3200
519 #define RTSDCTL_ENT_DLY_MAX 12800
520 #define RTSDCTL_SAMP_SIZE_MASK 0xffff
521 #define RTSDCTL_SAMP_SIZE_VAL 512
522 	u32 rtsdctl;		/* seed control register */
523 	union {
524 		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
525 		u32 rttotsam;	/* PRGM=0: total samples register */
526 	};
527 	u32 rtfrqmin;		/* frequency count min. limit register */
528 #define RTFRQMAX_DISABLE	(1 << 20)
529 	union {
530 		u32 rtfrqmax;	/* PRGM=1: freq. count max. limit register */
531 		u32 rtfrqcnt;	/* PRGM=0: freq. count register */
532 	};
533 	union {
534 		u32 rtscmc;	/* statistical check run monobit count */
535 		u32 rtscml;	/* statistical check run monobit limit */
536 	};
537 	union {
538 		u32 rtscrc[6];	/* statistical check run length count */
539 		u32 rtscrl[6];	/* statistical check run length limit */
540 	};
541 	u32 rsvd1[33];
542 #define RDSTA_SKVT 0x80000000
543 #define RDSTA_SKVN 0x40000000
544 #define RDSTA_PR0 BIT(4)
545 #define RDSTA_PR1 BIT(5)
546 #define RDSTA_IF0 0x00000001
547 #define RDSTA_IF1 0x00000002
548 #define RDSTA_MASK (RDSTA_PR1 | RDSTA_PR0 | RDSTA_IF1 | RDSTA_IF0)
549 	u32 rdsta;
550 	u32 rsvd2[15];
551 };
552 
553 /*
554  * caam_ctrl - basic core configuration
555  * starts base + 0x0000 padded out to 0x1000
556  */
557 
558 #define KEK_KEY_SIZE		8
559 #define TKEK_KEY_SIZE		8
560 #define TDSK_KEY_SIZE		8
561 
562 #define DECO_RESET	1	/* Use with DECO reset/availability regs */
563 #define DECO_RESET_0	(DECO_RESET << 0)
564 #define DECO_RESET_1	(DECO_RESET << 1)
565 #define DECO_RESET_2	(DECO_RESET << 2)
566 #define DECO_RESET_3	(DECO_RESET << 3)
567 #define DECO_RESET_4	(DECO_RESET << 4)
568 
569 struct caam_ctrl {
570 	/* Basic Configuration Section				000-01f */
571 	/* Read/Writable					        */
572 	u32 rsvd1;
573 	u32 mcr;		/* MCFG      Master Config Register  */
574 	u32 rsvd2;
575 	u32 scfgr;		/* SCFGR, Security Config Register */
576 
577 	/* Bus Access Configuration Section			010-11f */
578 	/* Read/Writable                                                */
579 	struct masterid jr_mid[4];	/* JRxLIODNR - JobR LIODN setup */
580 	u32 rsvd3[11];
581 	u32 jrstart;			/* JRSTART - Job Ring Start Register */
582 	struct masterid rtic_mid[4];	/* RTICxLIODNR - RTIC LIODN setup */
583 	u32 rsvd4[5];
584 	u32 deco_rsr;			/* DECORSR - Deco Request Source */
585 	u32 rsvd11;
586 	u32 deco_rq;			/* DECORR - DECO Request */
587 	struct masterid deco_mid[16];	/* DECOxLIODNR - 1 per DECO */
588 
589 	/* DECO Availability/Reset Section			120-3ff */
590 	u32 deco_avail;		/* DAR - DECO availability */
591 	u32 deco_reset;		/* DRR - DECO reset */
592 	u32 rsvd6[182];
593 
594 	/* Key Encryption/Decryption Configuration              400-5ff */
595 	/* Read/Writable only while in Non-secure mode                  */
596 	u32 kek[KEK_KEY_SIZE];	/* JDKEKR - Key Encryption Key */
597 	u32 tkek[TKEK_KEY_SIZE];	/* TDKEKR - Trusted Desc KEK */
598 	u32 tdsk[TDSK_KEY_SIZE];	/* TDSKR - Trusted Desc Signing Key */
599 	u32 rsvd7[32];
600 	u64 sknonce;			/* SKNR - Secure Key Nonce */
601 	u32 rsvd8[70];
602 
603 	/* RNG Test/Verification/Debug Access                   600-7ff */
604 	/* (Useful in Test/Debug modes only...)                         */
605 	union {
606 		struct rngtst rtst[2];
607 		struct rng4tst r4tst[2];
608 	};
609 
610 	u32 rsvd9[416];
611 
612 	/* Version registers - introduced with era 10		e80-eff */
613 	struct version_regs vreg;
614 	/* Performance Monitor                                  f00-fff */
615 	struct caam_perfmon perfmon;
616 };
617 
618 /*
619  * Controller master config register defs
620  */
621 #define MCFGR_SWRESET		0x80000000 /* software reset */
622 #define MCFGR_WDENABLE		0x40000000 /* DECO watchdog enable */
623 #define MCFGR_WDFAIL		0x20000000 /* DECO watchdog force-fail */
624 #define MCFGR_DMA_RESET		0x10000000
625 #define MCFGR_LONG_PTR		0x00010000 /* Use >32-bit desc addressing */
626 #define SCFGR_RDBENABLE		0x00000400
627 #define SCFGR_VIRT_EN		0x00008000
628 #define DECORR_RQD0ENABLE	0x00000001 /* Enable DECO0 for direct access */
629 #define DECORSR_JR0		0x00000001 /* JR to supply TZ, SDID, ICID */
630 #define DECORSR_VALID		0x80000000
631 #define DECORR_DEN0		0x00010000 /* DECO0 available for access*/
632 
633 /* AXI read cache control */
634 #define MCFGR_ARCACHE_SHIFT	12
635 #define MCFGR_ARCACHE_MASK	(0xf << MCFGR_ARCACHE_SHIFT)
636 #define MCFGR_ARCACHE_BUFF	(0x1 << MCFGR_ARCACHE_SHIFT)
637 #define MCFGR_ARCACHE_CACH	(0x2 << MCFGR_ARCACHE_SHIFT)
638 #define MCFGR_ARCACHE_RALL	(0x4 << MCFGR_ARCACHE_SHIFT)
639 
640 /* AXI write cache control */
641 #define MCFGR_AWCACHE_SHIFT	8
642 #define MCFGR_AWCACHE_MASK	(0xf << MCFGR_AWCACHE_SHIFT)
643 #define MCFGR_AWCACHE_BUFF	(0x1 << MCFGR_AWCACHE_SHIFT)
644 #define MCFGR_AWCACHE_CACH	(0x2 << MCFGR_AWCACHE_SHIFT)
645 #define MCFGR_AWCACHE_WALL	(0x8 << MCFGR_AWCACHE_SHIFT)
646 
647 /* AXI pipeline depth */
648 #define MCFGR_AXIPIPE_SHIFT	4
649 #define MCFGR_AXIPIPE_MASK	(0xf << MCFGR_AXIPIPE_SHIFT)
650 
651 #define MCFGR_AXIPRI		0x00000008 /* Assert AXI priority sideband */
652 #define MCFGR_LARGE_BURST	0x00000004 /* 128/256-byte burst size */
653 #define MCFGR_BURST_64		0x00000001 /* 64-byte burst size */
654 
655 /* JRSTART register offsets */
656 #define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
657 #define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
658 #define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
659 #define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
660 
661 /*
662  * caam_job_ring - direct job ring setup
663  * 1-4 possible per instantiation, base + 1000/2000/3000/4000
664  * Padded out to 0x1000
665  */
666 struct caam_job_ring {
667 	/* Input ring */
668 	u64 inpring_base;	/* IRBAx -  Input desc ring baseaddr */
669 	u32 rsvd1;
670 	u32 inpring_size;	/* IRSx - Input ring size */
671 	u32 rsvd2;
672 	u32 inpring_avail;	/* IRSAx - Input ring room remaining */
673 	u32 rsvd3;
674 	u32 inpring_jobadd;	/* IRJAx - Input ring jobs added */
675 
676 	/* Output Ring */
677 	u64 outring_base;	/* ORBAx - Output status ring base addr */
678 	u32 rsvd4;
679 	u32 outring_size;	/* ORSx - Output ring size */
680 	u32 rsvd5;
681 	u32 outring_rmvd;	/* ORJRx - Output ring jobs removed */
682 	u32 rsvd6;
683 	u32 outring_used;	/* ORSFx - Output ring slots full */
684 
685 	/* Status/Configuration */
686 	u32 rsvd7;
687 	u32 jroutstatus;	/* JRSTAx - JobR output status */
688 	u32 rsvd8;
689 	u32 jrintstatus;	/* JRINTx - JobR interrupt status */
690 	u32 rconfig_hi;	/* JRxCFG - Ring configuration */
691 	u32 rconfig_lo;
692 
693 	/* Indices. CAAM maintains as "heads" of each queue */
694 	u32 rsvd9;
695 	u32 inp_rdidx;	/* IRRIx - Input ring read index */
696 	u32 rsvd10;
697 	u32 out_wtidx;	/* ORWIx - Output ring write index */
698 
699 	/* Command/control */
700 	u32 rsvd11;
701 	u32 jrcommand;	/* JRCRx - JobR command */
702 
703 	u32 rsvd12[900];
704 
705 	/* Version registers - introduced with era 10           e80-eff */
706 	struct version_regs vreg;
707 	/* Performance Monitor                                  f00-fff */
708 	struct caam_perfmon perfmon;
709 };
710 
711 #define JR_RINGSIZE_MASK	0x03ff
712 /*
713  * jrstatus - Job Ring Output Status
714  * All values in lo word
715  * Also note, same values written out as status through QI
716  * in the command/status field of a frame descriptor
717  */
718 #define JRSTA_SSRC_SHIFT            28
719 #define JRSTA_SSRC_MASK             0xf0000000
720 
721 #define JRSTA_SSRC_NONE             0x00000000
722 #define JRSTA_SSRC_CCB_ERROR        0x20000000
723 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
724 #define JRSTA_SSRC_DECO             0x40000000
725 #define JRSTA_SSRC_QI               0x50000000
726 #define JRSTA_SSRC_JRERROR          0x60000000
727 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
728 
729 #define JRSTA_DECOERR_JUMP          0x08000000
730 #define JRSTA_DECOERR_INDEX_SHIFT   8
731 #define JRSTA_DECOERR_INDEX_MASK    0xff00
732 #define JRSTA_DECOERR_ERROR_MASK    0x00ff
733 
734 #define JRSTA_DECOERR_NONE          0x00
735 #define JRSTA_DECOERR_LINKLEN       0x01
736 #define JRSTA_DECOERR_LINKPTR       0x02
737 #define JRSTA_DECOERR_JRCTRL        0x03
738 #define JRSTA_DECOERR_DESCCMD       0x04
739 #define JRSTA_DECOERR_ORDER         0x05
740 #define JRSTA_DECOERR_KEYCMD        0x06
741 #define JRSTA_DECOERR_LOADCMD       0x07
742 #define JRSTA_DECOERR_STORECMD      0x08
743 #define JRSTA_DECOERR_OPCMD         0x09
744 #define JRSTA_DECOERR_FIFOLDCMD     0x0a
745 #define JRSTA_DECOERR_FIFOSTCMD     0x0b
746 #define JRSTA_DECOERR_MOVECMD       0x0c
747 #define JRSTA_DECOERR_JUMPCMD       0x0d
748 #define JRSTA_DECOERR_MATHCMD       0x0e
749 #define JRSTA_DECOERR_SHASHCMD      0x0f
750 #define JRSTA_DECOERR_SEQCMD        0x10
751 #define JRSTA_DECOERR_DECOINTERNAL  0x11
752 #define JRSTA_DECOERR_SHDESCHDR     0x12
753 #define JRSTA_DECOERR_HDRLEN        0x13
754 #define JRSTA_DECOERR_BURSTER       0x14
755 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
756 #define JRSTA_DECOERR_DMA           0x16
757 #define JRSTA_DECOERR_BURSTFIFO     0x17
758 #define JRSTA_DECOERR_JRRESET       0x1a
759 #define JRSTA_DECOERR_JOBFAIL       0x1b
760 #define JRSTA_DECOERR_DNRERR        0x80
761 #define JRSTA_DECOERR_UNDEFPCL      0x81
762 #define JRSTA_DECOERR_PDBERR        0x82
763 #define JRSTA_DECOERR_ANRPLY_LATE   0x83
764 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
765 #define JRSTA_DECOERR_SEQOVF        0x85
766 #define JRSTA_DECOERR_INVSIGN       0x86
767 #define JRSTA_DECOERR_DSASIGN       0x87
768 
769 #define JRSTA_QIERR_ERROR_MASK      0x00ff
770 
771 #define JRSTA_CCBERR_JUMP           0x08000000
772 #define JRSTA_CCBERR_INDEX_MASK     0xff00
773 #define JRSTA_CCBERR_INDEX_SHIFT    8
774 #define JRSTA_CCBERR_CHAID_MASK     0x00f0
775 #define JRSTA_CCBERR_CHAID_SHIFT    4
776 #define JRSTA_CCBERR_ERRID_MASK     0x000f
777 
778 #define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
779 #define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
780 #define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
781 #define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
782 #define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
783 #define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
784 #define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
785 #define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
786 #define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
787 
788 #define JRSTA_CCBERR_ERRID_NONE     0x00
789 #define JRSTA_CCBERR_ERRID_MODE     0x01
790 #define JRSTA_CCBERR_ERRID_DATASIZ  0x02
791 #define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
792 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
793 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
794 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
795 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
796 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
797 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
798 #define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
799 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
800 #define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
801 #define JRSTA_CCBERR_ERRID_INVCHA   0x0f
802 
803 #define JRINT_ERR_INDEX_MASK        0x3fff0000
804 #define JRINT_ERR_INDEX_SHIFT       16
805 #define JRINT_ERR_TYPE_MASK         0xf00
806 #define JRINT_ERR_TYPE_SHIFT        8
807 #define JRINT_ERR_HALT_MASK         0xc
808 #define JRINT_ERR_HALT_SHIFT        2
809 #define JRINT_ERR_HALT_INPROGRESS   0x4
810 #define JRINT_ERR_HALT_COMPLETE     0x8
811 #define JRINT_JR_ERROR              0x02
812 #define JRINT_JR_INT                0x01
813 
814 #define JRINT_ERR_TYPE_WRITE        1
815 #define JRINT_ERR_TYPE_BAD_INPADDR  3
816 #define JRINT_ERR_TYPE_BAD_OUTADDR  4
817 #define JRINT_ERR_TYPE_INV_INPWRT   5
818 #define JRINT_ERR_TYPE_INV_OUTWRT   6
819 #define JRINT_ERR_TYPE_RESET        7
820 #define JRINT_ERR_TYPE_REMOVE_OFL   8
821 #define JRINT_ERR_TYPE_ADD_OFL      9
822 
823 #define JRCFG_SOE		0x04
824 #define JRCFG_ICEN		0x02
825 #define JRCFG_IMSK		0x01
826 #define JRCFG_ICDCT_SHIFT	8
827 #define JRCFG_ICTT_SHIFT	16
828 
829 #define JRCR_RESET                  0x01
830 
831 /*
832  * caam_assurance - Assurance Controller View
833  * base + 0x6000 padded out to 0x1000
834  */
835 
836 struct rtic_element {
837 	u64 address;
838 	u32 rsvd;
839 	u32 length;
840 };
841 
842 struct rtic_block {
843 	struct rtic_element element[2];
844 };
845 
846 struct rtic_memhash {
847 	u32 memhash_be[32];
848 	u32 memhash_le[32];
849 };
850 
851 struct caam_assurance {
852     /* Status/Command/Watchdog */
853 	u32 rsvd1;
854 	u32 status;		/* RSTA - Status */
855 	u32 rsvd2;
856 	u32 cmd;		/* RCMD - Command */
857 	u32 rsvd3;
858 	u32 ctrl;		/* RCTL - Control */
859 	u32 rsvd4;
860 	u32 throttle;	/* RTHR - Throttle */
861 	u32 rsvd5[2];
862 	u64 watchdog;	/* RWDOG - Watchdog Timer */
863 	u32 rsvd6;
864 	u32 rend;		/* REND - Endian corrections */
865 	u32 rsvd7[50];
866 
867 	/* Block access/configuration @ 100/110/120/130 */
868 	struct rtic_block memblk[4];	/* Memory Blocks A-D */
869 	u32 rsvd8[32];
870 
871 	/* Block hashes @ 200/300/400/500 */
872 	struct rtic_memhash hash[4];	/* Block hash values A-D */
873 	u32 rsvd_3[640];
874 };
875 
876 /*
877  * caam_queue_if - QI configuration and control
878  * starts base + 0x7000, padded out to 0x1000 long
879  */
880 
881 struct caam_queue_if {
882 	u32 qi_control_hi;	/* QICTL  - QI Control */
883 	u32 qi_control_lo;
884 	u32 rsvd1;
885 	u32 qi_status;	/* QISTA  - QI Status */
886 	u32 qi_deq_cfg_hi;	/* QIDQC  - QI Dequeue Configuration */
887 	u32 qi_deq_cfg_lo;
888 	u32 qi_enq_cfg_hi;	/* QISEQC - QI Enqueue Command     */
889 	u32 qi_enq_cfg_lo;
890 	u32 rsvd2[1016];
891 };
892 
893 /* QI control bits - low word */
894 #define QICTL_DQEN      0x01              /* Enable frame pop          */
895 #define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
896 #define QICTL_SOE       0x04              /* Stop on error             */
897 
898 /* QI control bits - high word */
899 #define QICTL_MBSI	0x01
900 #define QICTL_MHWSI	0x02
901 #define QICTL_MWSI	0x04
902 #define QICTL_MDWSI	0x08
903 #define QICTL_CBSI	0x10		/* CtrlDataByteSwapInput     */
904 #define QICTL_CHWSI	0x20		/* CtrlDataHalfSwapInput     */
905 #define QICTL_CWSI	0x40		/* CtrlDataWordSwapInput     */
906 #define QICTL_CDWSI	0x80		/* CtrlDataDWordSwapInput    */
907 #define QICTL_MBSO	0x0100
908 #define QICTL_MHWSO	0x0200
909 #define QICTL_MWSO	0x0400
910 #define QICTL_MDWSO	0x0800
911 #define QICTL_CBSO	0x1000		/* CtrlDataByteSwapOutput    */
912 #define QICTL_CHWSO	0x2000		/* CtrlDataHalfSwapOutput    */
913 #define QICTL_CWSO	0x4000		/* CtrlDataWordSwapOutput    */
914 #define QICTL_CDWSO     0x8000		/* CtrlDataDWordSwapOutput   */
915 #define QICTL_DMBS	0x010000
916 #define QICTL_EPO	0x020000
917 
918 /* QI status bits */
919 #define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
920 #define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
921 #define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
922 #define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
923 #define QISTA_BTSERR    0x10              /* Buffer Undersize          */
924 #define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
925 #define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
926 
927 /* deco_sg_table - DECO view of scatter/gather table */
928 struct deco_sg_table {
929 	u64 addr;		/* Segment Address */
930 	u32 elen;		/* E, F bits + 30-bit length */
931 	u32 bpid_offset;	/* Buffer Pool ID + 16-bit length */
932 };
933 
934 /*
935  * caam_deco - descriptor controller - CHA cluster block
936  *
937  * Only accessible when direct DECO access is turned on
938  * (done in DECORR, via MID programmed in DECOxMID
939  *
940  * 5 typical, base + 0x8000/9000/a000/b000
941  * Padded out to 0x1000 long
942  */
943 struct caam_deco {
944 	u32 rsvd1;
945 	u32 cls1_mode;	/* CxC1MR -  Class 1 Mode */
946 	u32 rsvd2;
947 	u32 cls1_keysize;	/* CxC1KSR - Class 1 Key Size */
948 	u32 cls1_datasize_hi;	/* CxC1DSR - Class 1 Data Size */
949 	u32 cls1_datasize_lo;
950 	u32 rsvd3;
951 	u32 cls1_icvsize;	/* CxC1ICVSR - Class 1 ICV size */
952 	u32 rsvd4[5];
953 	u32 cha_ctrl;	/* CCTLR - CHA control */
954 	u32 rsvd5;
955 	u32 irq_crtl;	/* CxCIRQ - CCB interrupt done/error/clear */
956 	u32 rsvd6;
957 	u32 clr_written;	/* CxCWR - Clear-Written */
958 	u32 ccb_status_hi;	/* CxCSTA - CCB Status/Error */
959 	u32 ccb_status_lo;
960 	u32 rsvd7[3];
961 	u32 aad_size;	/* CxAADSZR - Current AAD Size */
962 	u32 rsvd8;
963 	u32 cls1_iv_size;	/* CxC1IVSZR - Current Class 1 IV Size */
964 	u32 rsvd9[7];
965 	u32 pkha_a_size;	/* PKASZRx - Size of PKHA A */
966 	u32 rsvd10;
967 	u32 pkha_b_size;	/* PKBSZRx - Size of PKHA B */
968 	u32 rsvd11;
969 	u32 pkha_n_size;	/* PKNSZRx - Size of PKHA N */
970 	u32 rsvd12;
971 	u32 pkha_e_size;	/* PKESZRx - Size of PKHA E */
972 	u32 rsvd13[24];
973 	u32 cls1_ctx[16];	/* CxC1CTXR - Class 1 Context @100 */
974 	u32 rsvd14[48];
975 	u32 cls1_key[8];	/* CxC1KEYR - Class 1 Key @200 */
976 	u32 rsvd15[121];
977 	u32 cls2_mode;	/* CxC2MR - Class 2 Mode */
978 	u32 rsvd16;
979 	u32 cls2_keysize;	/* CxX2KSR - Class 2 Key Size */
980 	u32 cls2_datasize_hi;	/* CxC2DSR - Class 2 Data Size */
981 	u32 cls2_datasize_lo;
982 	u32 rsvd17;
983 	u32 cls2_icvsize;	/* CxC2ICVSZR - Class 2 ICV Size */
984 	u32 rsvd18[56];
985 	u32 cls2_ctx[18];	/* CxC2CTXR - Class 2 Context @500 */
986 	u32 rsvd19[46];
987 	u32 cls2_key[32];	/* CxC2KEYR - Class2 Key @600 */
988 	u32 rsvd20[84];
989 	u32 inp_infofifo_hi;	/* CxIFIFO - Input Info FIFO @7d0 */
990 	u32 inp_infofifo_lo;
991 	u32 rsvd21[2];
992 	u64 inp_datafifo;	/* CxDFIFO - Input Data FIFO */
993 	u32 rsvd22[2];
994 	u64 out_datafifo;	/* CxOFIFO - Output Data FIFO */
995 	u32 rsvd23[2];
996 	u32 jr_ctl_hi;	/* CxJRR - JobR Control Register      @800 */
997 	u32 jr_ctl_lo;
998 	u64 jr_descaddr;	/* CxDADR - JobR Descriptor Address */
999 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
1000 	u32 op_status_hi;	/* DxOPSTA - DECO Operation Status */
1001 	u32 op_status_lo;
1002 	u32 rsvd24[2];
1003 	u32 liodn;		/* DxLSR - DECO LIODN Status - non-seq */
1004 	u32 td_liodn;	/* DxLSR - DECO LIODN Status - trustdesc */
1005 	u32 rsvd26[6];
1006 	u64 math[4];		/* DxMTH - Math register */
1007 	u32 rsvd27[8];
1008 	struct deco_sg_table gthr_tbl[4];	/* DxGTR - Gather Tables */
1009 	u32 rsvd28[16];
1010 	struct deco_sg_table sctr_tbl[4];	/* DxSTR - Scatter Tables */
1011 	u32 rsvd29[48];
1012 	u32 descbuf[64];	/* DxDESB - Descriptor buffer */
1013 	u32 rscvd30[193];
1014 #define DESC_DBG_DECO_STAT_VALID	0x80000000
1015 #define DESC_DBG_DECO_STAT_MASK		0x00F00000
1016 #define DESC_DBG_DECO_STAT_SHIFT	20
1017 	u32 desc_dbg;		/* DxDDR - DECO Debug Register */
1018 	u32 rsvd31[13];
1019 #define DESC_DER_DECO_STAT_MASK		0x000F0000
1020 #define DESC_DER_DECO_STAT_SHIFT	16
1021 	u32 dbg_exec;		/* DxDER - DECO Debug Exec Register */
1022 	u32 rsvd32[112];
1023 };
1024 
1025 #define DECO_STAT_HOST_ERR	0xD
1026 
1027 #define DECO_JQCR_WHL		0x20000000
1028 #define DECO_JQCR_FOUR		0x10000000
1029 
1030 #define JR_BLOCK_NUMBER		1
1031 #define ASSURE_BLOCK_NUMBER	6
1032 #define QI_BLOCK_NUMBER		7
1033 #define DECO_BLOCK_NUMBER	8
1034 #define PG_SIZE_4K		0x1000
1035 #define PG_SIZE_64K		0x10000
1036 #endif /* REGS_H */
1037