xref: /linux/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #ifndef _DCB_82598_CONFIG_H_
5 #define _DCB_82598_CONFIG_H_
6 
7 /* DCB register definitions */
8 
9 #define IXGBE_DPMCS_MTSOS_SHIFT 16
10 #define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
11 #define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
12 #define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
13 #define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
14 
15 #define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
16 
17 #define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
18 #define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
19 
20 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores (RSS) enable */
22 
23 #define IXGBE_TDTQ2TCCR_MCL_SHIFT   12
24 #define IXGBE_TDTQ2TCCR_BWG_SHIFT   9
25 #define IXGBE_TDTQ2TCCR_GSP     0x40000000
26 #define IXGBE_TDTQ2TCCR_LSP     0x80000000
27 
28 #define IXGBE_TDPT2TCCR_MCL_SHIFT   12
29 #define IXGBE_TDPT2TCCR_BWG_SHIFT   9
30 #define IXGBE_TDPT2TCCR_GSP     0x40000000
31 #define IXGBE_TDPT2TCCR_LSP     0x80000000
32 
33 #define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
34 #define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
35 #define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
36 
37 #define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
38 
39 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
40 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
41 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
42 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
43 
44 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
45 
46 /* DCB hardware-specific driver APIs */
47 
48 /* DCB PFC functions */
49 int ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
50 
51 /* DCB hw initialization */
52 int ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
53 				      u16 *max, u8 *prio_type);
54 
55 int ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
56 					   u16 *max, u8 *bwg_id, u8 *prio_type);
57 
58 int ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
59 					   u16 *max, u8 *bwg_id, u8 *prio_type);
60 
61 int ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
62 			      u16 *max, u8 *bwg_id, u8 *prio_type);
63 
64 #endif /* _DCB_82598_CONFIG_H */
65