xref: /linux/drivers/net/ethernet/renesas/ravb.h (revision 2b240cfc6de4a6ca7779323e0f1ffdf0d7f99add) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet AVB device driver
3  *
4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
5  * Copyright (C) 2015 Renesas Solutions Corp.
6  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * Based on the SuperH Ethernet driver
9  */
10 
11 #ifndef __RAVB_H__
12 #define __RAVB_H__
13 
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <net/page_pool/types.h>
23 
24 #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
25 #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
26 #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
27 #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
28 #define BE_TX_RING_MIN	64
29 #define BE_RX_RING_MIN	64
30 #define BE_TX_RING_MAX	1024
31 #define BE_RX_RING_MAX	2048
32 
33 #define PKT_BUF_SZ	1538
34 
35 /* Driver's parameters */
36 #define RAVB_ALIGN	128
37 
38 enum ravb_reg {
39 	/* AVB-DMAC registers */
40 	CCC	= 0x0000,
41 	DBAT	= 0x0004,
42 	DLR	= 0x0008,
43 	CSR	= 0x000C,
44 	CDAR0	= 0x0010,
45 	CDAR1	= 0x0014,
46 	CDAR2	= 0x0018,
47 	CDAR3	= 0x001C,
48 	CDAR4	= 0x0020,
49 	CDAR5	= 0x0024,
50 	CDAR6	= 0x0028,
51 	CDAR7	= 0x002C,
52 	CDAR8	= 0x0030,
53 	CDAR9	= 0x0034,
54 	CDAR10	= 0x0038,
55 	CDAR11	= 0x003C,
56 	CDAR12	= 0x0040,
57 	CDAR13	= 0x0044,
58 	CDAR14	= 0x0048,
59 	CDAR15	= 0x004C,
60 	CDAR16	= 0x0050,
61 	CDAR17	= 0x0054,
62 	CDAR18	= 0x0058,
63 	CDAR19	= 0x005C,
64 	CDAR20	= 0x0060,
65 	CDAR21	= 0x0064,
66 	ESR	= 0x0088,
67 	APSR	= 0x008C,	/* R-Car Gen3 only */
68 	RCR	= 0x0090,
69 	RQC0	= 0x0094,
70 	RQC1	= 0x0098,
71 	RQC2	= 0x009C,
72 	RQC3	= 0x00A0,
73 	RQC4	= 0x00A4,
74 	RPC	= 0x00B0,
75 	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
76 	UFCW	= 0x00BC,
77 	UFCS	= 0x00C0,
78 	UFCV0	= 0x00C4,
79 	UFCV1	= 0x00C8,
80 	UFCV2	= 0x00CC,
81 	UFCV3	= 0x00D0,
82 	UFCV4	= 0x00D4,
83 	UFCD0	= 0x00E0,
84 	UFCD1	= 0x00E4,
85 	UFCD2	= 0x00E8,
86 	UFCD3	= 0x00EC,
87 	UFCD4	= 0x00F0,
88 	SFO	= 0x00FC,
89 	SFP0	= 0x0100,
90 	SFP1	= 0x0104,
91 	SFP2	= 0x0108,
92 	SFP3	= 0x010C,
93 	SFP4	= 0x0110,
94 	SFP5	= 0x0114,
95 	SFP6	= 0x0118,
96 	SFP7	= 0x011C,
97 	SFP8	= 0x0120,
98 	SFP9	= 0x0124,
99 	SFP10	= 0x0128,
100 	SFP11	= 0x012C,
101 	SFP12	= 0x0130,
102 	SFP13	= 0x0134,
103 	SFP14	= 0x0138,
104 	SFP15	= 0x013C,
105 	SFP16	= 0x0140,
106 	SFP17	= 0x0144,
107 	SFP18	= 0x0148,
108 	SFP19	= 0x014C,
109 	SFP20	= 0x0150,
110 	SFP21	= 0x0154,
111 	SFP22	= 0x0158,
112 	SFP23	= 0x015C,
113 	SFP24	= 0x0160,
114 	SFP25	= 0x0164,
115 	SFP26	= 0x0168,
116 	SFP27	= 0x016C,
117 	SFP28	= 0x0170,
118 	SFP29	= 0x0174,
119 	SFP30	= 0x0178,
120 	SFP31	= 0x017C,
121 	SFM0	= 0x01C0,
122 	SFM1	= 0x01C4,
123 	TGC	= 0x0300,
124 	TCCR	= 0x0304,
125 	TSR	= 0x0308,
126 	TFA0	= 0x0310,
127 	TFA1	= 0x0314,
128 	TFA2	= 0x0318,
129 	CIVR0	= 0x0320,
130 	CIVR1	= 0x0324,
131 	CDVR0	= 0x0328,
132 	CDVR1	= 0x032C,
133 	CUL0	= 0x0330,
134 	CUL1	= 0x0334,
135 	CLL0	= 0x0338,
136 	CLL1	= 0x033C,
137 	DIC	= 0x0350,
138 	DIS	= 0x0354,
139 	EIC	= 0x0358,
140 	EIS	= 0x035C,
141 	RIC0	= 0x0360,
142 	RIS0	= 0x0364,
143 	RIC1	= 0x0368,
144 	RIS1	= 0x036C,
145 	RIC2	= 0x0370,
146 	RIS2	= 0x0374,
147 	TIC	= 0x0378,
148 	TIS	= 0x037C,
149 	ISS	= 0x0380,
150 	CIE	= 0x0384,	/* R-Car Gen3 only */
151 	GCCR	= 0x0390,
152 	GMTT	= 0x0394,
153 	GPTC	= 0x0398,
154 	GTI	= 0x039C,
155 	GTO0	= 0x03A0,
156 	GTO1	= 0x03A4,
157 	GTO2	= 0x03A8,
158 	GIC	= 0x03AC,
159 	GIS	= 0x03B0,
160 	GCPT	= 0x03B4,	/* Documented for R-Car Gen3 only */
161 	GCT0	= 0x03B8,
162 	GCT1	= 0x03BC,
163 	GCT2	= 0x03C0,
164 	GIE	= 0x03CC,	/* R-Car Gen3 only */
165 	GID	= 0x03D0,	/* R-Car Gen3 only */
166 	DIL	= 0x0440,	/* R-Car Gen3 only */
167 	RIE0	= 0x0460,	/* R-Car Gen3 only */
168 	RID0	= 0x0464,	/* R-Car Gen3 only */
169 	RIE2	= 0x0470,	/* R-Car Gen3 only */
170 	RID2	= 0x0474,	/* R-Car Gen3 only */
171 	TIE	= 0x0478,	/* R-Car Gen3 only */
172 	TID	= 0x047c,	/* R-Car Gen3 only */
173 
174 	/* E-MAC registers */
175 	ECMR	= 0x0500,
176 	RFLR	= 0x0508,
177 	ECSR	= 0x0510,
178 	ECSIPR	= 0x0518,
179 	PIR	= 0x0520,
180 	PSR	= 0x0528,
181 	PIPR	= 0x052c,
182 	CXR31	= 0x0530,	/* RZ/G2L only */
183 	CXR35	= 0x0540,	/* RZ/G2L only */
184 	MPR	= 0x0558,
185 	PFTCR	= 0x055c,
186 	PFRCR	= 0x0560,
187 	GECMR	= 0x05b0,
188 	MAHR	= 0x05c0,
189 	MALR	= 0x05c8,
190 	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
191 	CXR41	= 0x0708,	/* RZ/G2L only */
192 	CXR42	= 0x0710,	/* RZ/G2L only */
193 	CEFCR	= 0x0740,
194 	FRECR	= 0x0748,
195 	TSFRCR	= 0x0750,
196 	TLFRCR	= 0x0758,
197 	RFCR	= 0x0760,
198 	MAFCR	= 0x0778,
199 
200 	/* TOE registers (RZ/G2L only) */
201 	CSR0    = 0x0800,
202 	CSR1    = 0x0804,
203 	CSR2    = 0x0808,
204 };
205 
206 
207 /* Register bits of the Ethernet AVB */
208 /* CCC */
209 enum CCC_BIT {
210 	CCC_OPC		= 0x00000003,
211 	CCC_OPC_RESET	= 0x00000000,
212 	CCC_OPC_CONFIG	= 0x00000001,
213 	CCC_OPC_OPERATION = 0x00000002,
214 	CCC_GAC		= 0x00000080,
215 	CCC_DTSR	= 0x00000100,
216 	CCC_CSEL	= 0x00030000,
217 	CCC_CSEL_HPB	= 0x00010000,
218 	CCC_CSEL_ETH_TX	= 0x00020000,
219 	CCC_CSEL_GMII_REF = 0x00030000,
220 	CCC_LBME	= 0x01000000,
221 };
222 
223 /* CSR */
224 enum CSR_BIT {
225 	CSR_OPS		= 0x0000000F,
226 	CSR_OPS_RESET	= 0x00000001,
227 	CSR_OPS_CONFIG	= 0x00000002,
228 	CSR_OPS_OPERATION = 0x00000004,
229 	CSR_OPS_STANDBY	= 0x00000008,	/* Documented for R-Car Gen3 only */
230 	CSR_DTS		= 0x00000100,
231 	CSR_TPO0	= 0x00010000,
232 	CSR_TPO1	= 0x00020000,
233 	CSR_TPO2	= 0x00040000,
234 	CSR_TPO3	= 0x00080000,
235 	CSR_RPO		= 0x00100000,
236 };
237 
238 /* ESR */
239 enum ESR_BIT {
240 	ESR_EQN		= 0x0000001F,
241 	ESR_ET		= 0x00000F00,
242 	ESR_EIL		= 0x00001000,
243 };
244 
245 /* APSR (R-Car Gen3 only) */
246 enum APSR_BIT {
247 	APSR_MEMS	= 0x00000002,	/* Undocumented */
248 	APSR_CMSW	= 0x00000010,
249 	APSR_RDM	= 0x00002000,
250 	APSR_TDM	= 0x00004000,
251 	APSR_MIISELECT	= 0x01000000,	/* R-Car V4M only */
252 	APSR_GPTPTIMER_SOURCE = BIT(25), /* Gen4 */
253 	APSR_GPTPCLOCK	= BIT(29),	/* Gen4 */
254 };
255 
256 /* RCR */
257 enum RCR_BIT {
258 	RCR_EFFS	= 0x00000001,
259 	RCR_ENCF	= 0x00000002,
260 	RCR_ESF		= 0x0000000C,
261 	RCR_ETS0	= 0x00000010,
262 	RCR_ETS2	= 0x00000020,
263 	RCR_RFCL	= 0x1FFF0000,
264 };
265 
266 /* RQC0/1/2/3/4 */
267 enum RQC_BIT {
268 	RQC_RSM0	= 0x00000003,
269 	RQC_UFCC0	= 0x00000030,
270 	RQC_RSM1	= 0x00000300,
271 	RQC_UFCC1	= 0x00003000,
272 	RQC_RSM2	= 0x00030000,
273 	RQC_UFCC2	= 0x00300000,
274 	RQC_RSM3	= 0x03000000,
275 	RQC_UFCC3	= 0x30000000,
276 };
277 
278 /* RPC */
279 enum RPC_BIT {
280 	RPC_PCNT	= 0x00000700,
281 	RPC_DCNT	= 0x00FF0000,
282 };
283 
284 /* UFCW */
285 enum UFCW_BIT {
286 	UFCW_WL0	= 0x0000003F,
287 	UFCW_WL1	= 0x00003F00,
288 	UFCW_WL2	= 0x003F0000,
289 	UFCW_WL3	= 0x3F000000,
290 };
291 
292 /* UFCS */
293 enum UFCS_BIT {
294 	UFCS_SL0	= 0x0000003F,
295 	UFCS_SL1	= 0x00003F00,
296 	UFCS_SL2	= 0x003F0000,
297 	UFCS_SL3	= 0x3F000000,
298 };
299 
300 /* UFCV0/1/2/3/4 */
301 enum UFCV_BIT {
302 	UFCV_CV0	= 0x0000003F,
303 	UFCV_CV1	= 0x00003F00,
304 	UFCV_CV2	= 0x003F0000,
305 	UFCV_CV3	= 0x3F000000,
306 };
307 
308 /* UFCD0/1/2/3/4 */
309 enum UFCD_BIT {
310 	UFCD_DV0	= 0x0000003F,
311 	UFCD_DV1	= 0x00003F00,
312 	UFCD_DV2	= 0x003F0000,
313 	UFCD_DV3	= 0x3F000000,
314 };
315 
316 /* SFO */
317 enum SFO_BIT {
318 	SFO_FBP		= 0x0000003F,
319 };
320 
321 /* RTC */
322 enum RTC_BIT {
323 	RTC_MFL0	= 0x00000FFF,
324 	RTC_MFL1	= 0x0FFF0000,
325 };
326 
327 /* TGC */
328 enum TGC_BIT {
329 	TGC_TSM0	= 0x00000001,
330 	TGC_TSM1	= 0x00000002,
331 	TGC_TSM2	= 0x00000004,
332 	TGC_TSM3	= 0x00000008,
333 	TGC_TQP		= 0x00000030,
334 	TGC_TQP_NONAVB	= 0x00000000,
335 	TGC_TQP_AVBMODE1 = 0x00000010,
336 	TGC_TQP_AVBMODE2 = 0x00000030,
337 	TGC_TBD0	= 0x00000300,
338 	TGC_TBD1	= 0x00003000,
339 	TGC_TBD2	= 0x00030000,
340 	TGC_TBD3	= 0x00300000,
341 };
342 
343 /* TCCR */
344 enum TCCR_BIT {
345 	TCCR_TSRQ0	= 0x00000001,
346 	TCCR_TSRQ1	= 0x00000002,
347 	TCCR_TSRQ2	= 0x00000004,
348 	TCCR_TSRQ3	= 0x00000008,
349 	TCCR_TFEN	= 0x00000100,
350 	TCCR_TFR	= 0x00000200,
351 };
352 
353 /* TSR */
354 enum TSR_BIT {
355 	TSR_CCS0	= 0x00000003,
356 	TSR_CCS1	= 0x0000000C,
357 	TSR_TFFL	= 0x00000700,
358 };
359 
360 /* TFA2 */
361 enum TFA2_BIT {
362 	TFA2_TSV	= 0x0000FFFF,
363 	TFA2_TST	= 0x03FF0000,
364 };
365 
366 /* DIC */
367 enum DIC_BIT {
368 	DIC_DPE1	= 0x00000002,
369 	DIC_DPE2	= 0x00000004,
370 	DIC_DPE3	= 0x00000008,
371 	DIC_DPE4	= 0x00000010,
372 	DIC_DPE5	= 0x00000020,
373 	DIC_DPE6	= 0x00000040,
374 	DIC_DPE7	= 0x00000080,
375 	DIC_DPE8	= 0x00000100,
376 	DIC_DPE9	= 0x00000200,
377 	DIC_DPE10	= 0x00000400,
378 	DIC_DPE11	= 0x00000800,
379 	DIC_DPE12	= 0x00001000,
380 	DIC_DPE13	= 0x00002000,
381 	DIC_DPE14	= 0x00004000,
382 	DIC_DPE15	= 0x00008000,
383 };
384 
385 /* DIS */
386 enum DIS_BIT {
387 	DIS_DPF1	= 0x00000002,
388 	DIS_DPF2	= 0x00000004,
389 	DIS_DPF3	= 0x00000008,
390 	DIS_DPF4	= 0x00000010,
391 	DIS_DPF5	= 0x00000020,
392 	DIS_DPF6	= 0x00000040,
393 	DIS_DPF7	= 0x00000080,
394 	DIS_DPF8	= 0x00000100,
395 	DIS_DPF9	= 0x00000200,
396 	DIS_DPF10	= 0x00000400,
397 	DIS_DPF11	= 0x00000800,
398 	DIS_DPF12	= 0x00001000,
399 	DIS_DPF13	= 0x00002000,
400 	DIS_DPF14	= 0x00004000,
401 	DIS_DPF15	= 0x00008000,
402 };
403 
404 /* EIC */
405 enum EIC_BIT {
406 	EIC_MREE	= 0x00000001,
407 	EIC_MTEE	= 0x00000002,
408 	EIC_QEE		= 0x00000004,
409 	EIC_SEE		= 0x00000008,
410 	EIC_CLLE0	= 0x00000010,
411 	EIC_CLLE1	= 0x00000020,
412 	EIC_CULE0	= 0x00000040,
413 	EIC_CULE1	= 0x00000080,
414 	EIC_TFFE	= 0x00000100,
415 };
416 
417 /* EIS */
418 enum EIS_BIT {
419 	EIS_MREF	= 0x00000001,
420 	EIS_MTEF	= 0x00000002,
421 	EIS_QEF		= 0x00000004,
422 	EIS_SEF		= 0x00000008,
423 	EIS_CLLF0	= 0x00000010,
424 	EIS_CLLF1	= 0x00000020,
425 	EIS_CULF0	= 0x00000040,
426 	EIS_CULF1	= 0x00000080,
427 	EIS_TFFF	= 0x00000100,
428 	EIS_QFS		= 0x00010000,
429 	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
430 };
431 
432 /* RIC0 */
433 enum RIC0_BIT {
434 	RIC0_FRE0	= 0x00000001,
435 	RIC0_FRE1	= 0x00000002,
436 	RIC0_FRE2	= 0x00000004,
437 	RIC0_FRE3	= 0x00000008,
438 	RIC0_FRE4	= 0x00000010,
439 	RIC0_FRE5	= 0x00000020,
440 	RIC0_FRE6	= 0x00000040,
441 	RIC0_FRE7	= 0x00000080,
442 	RIC0_FRE8	= 0x00000100,
443 	RIC0_FRE9	= 0x00000200,
444 	RIC0_FRE10	= 0x00000400,
445 	RIC0_FRE11	= 0x00000800,
446 	RIC0_FRE12	= 0x00001000,
447 	RIC0_FRE13	= 0x00002000,
448 	RIC0_FRE14	= 0x00004000,
449 	RIC0_FRE15	= 0x00008000,
450 	RIC0_FRE16	= 0x00010000,
451 	RIC0_FRE17	= 0x00020000,
452 };
453 
454 /* RIC0 */
455 enum RIS0_BIT {
456 	RIS0_FRF0	= 0x00000001,
457 	RIS0_FRF1	= 0x00000002,
458 	RIS0_FRF2	= 0x00000004,
459 	RIS0_FRF3	= 0x00000008,
460 	RIS0_FRF4	= 0x00000010,
461 	RIS0_FRF5	= 0x00000020,
462 	RIS0_FRF6	= 0x00000040,
463 	RIS0_FRF7	= 0x00000080,
464 	RIS0_FRF8	= 0x00000100,
465 	RIS0_FRF9	= 0x00000200,
466 	RIS0_FRF10	= 0x00000400,
467 	RIS0_FRF11	= 0x00000800,
468 	RIS0_FRF12	= 0x00001000,
469 	RIS0_FRF13	= 0x00002000,
470 	RIS0_FRF14	= 0x00004000,
471 	RIS0_FRF15	= 0x00008000,
472 	RIS0_FRF16	= 0x00010000,
473 	RIS0_FRF17	= 0x00020000,
474 	RIS0_RESERVED	= GENMASK(31, 18),
475 };
476 
477 /* RIC1 */
478 enum RIC1_BIT {
479 	RIC1_RFWE	= 0x80000000,
480 };
481 
482 /* RIS1 */
483 enum RIS1_BIT {
484 	RIS1_RFWF	= 0x80000000,
485 };
486 
487 /* RIC2 */
488 enum RIC2_BIT {
489 	RIC2_QFE0	= 0x00000001,
490 	RIC2_QFE1	= 0x00000002,
491 	RIC2_QFE2	= 0x00000004,
492 	RIC2_QFE3	= 0x00000008,
493 	RIC2_QFE4	= 0x00000010,
494 	RIC2_QFE5	= 0x00000020,
495 	RIC2_QFE6	= 0x00000040,
496 	RIC2_QFE7	= 0x00000080,
497 	RIC2_QFE8	= 0x00000100,
498 	RIC2_QFE9	= 0x00000200,
499 	RIC2_QFE10	= 0x00000400,
500 	RIC2_QFE11	= 0x00000800,
501 	RIC2_QFE12	= 0x00001000,
502 	RIC2_QFE13	= 0x00002000,
503 	RIC2_QFE14	= 0x00004000,
504 	RIC2_QFE15	= 0x00008000,
505 	RIC2_QFE16	= 0x00010000,
506 	RIC2_QFE17	= 0x00020000,
507 	RIC2_RFFE	= 0x80000000,
508 };
509 
510 /* RIS2 */
511 enum RIS2_BIT {
512 	RIS2_QFF0	= 0x00000001,
513 	RIS2_QFF1	= 0x00000002,
514 	RIS2_QFF2	= 0x00000004,
515 	RIS2_QFF3	= 0x00000008,
516 	RIS2_QFF4	= 0x00000010,
517 	RIS2_QFF5	= 0x00000020,
518 	RIS2_QFF6	= 0x00000040,
519 	RIS2_QFF7	= 0x00000080,
520 	RIS2_QFF8	= 0x00000100,
521 	RIS2_QFF9	= 0x00000200,
522 	RIS2_QFF10	= 0x00000400,
523 	RIS2_QFF11	= 0x00000800,
524 	RIS2_QFF12	= 0x00001000,
525 	RIS2_QFF13	= 0x00002000,
526 	RIS2_QFF14	= 0x00004000,
527 	RIS2_QFF15	= 0x00008000,
528 	RIS2_QFF16	= 0x00010000,
529 	RIS2_QFF17	= 0x00020000,
530 	RIS2_RFFF	= 0x80000000,
531 	RIS2_RESERVED	= GENMASK(30, 18),
532 };
533 
534 /* TIC */
535 enum TIC_BIT {
536 	TIC_FTE0	= 0x00000001,	/* Documented for R-Car Gen3 only */
537 	TIC_FTE1	= 0x00000002,	/* Documented for R-Car Gen3 only */
538 	TIC_TFUE	= 0x00000100,
539 	TIC_TFWE	= 0x00000200,
540 };
541 
542 /* TIS */
543 enum TIS_BIT {
544 	TIS_FTF0	= 0x00000001,	/* Documented for R-Car Gen3 only */
545 	TIS_FTF1	= 0x00000002,	/* Documented for R-Car Gen3 only */
546 	TIS_TFUF	= 0x00000100,
547 	TIS_TFWF	= 0x00000200,
548 	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
549 };
550 
551 /* ISS */
552 enum ISS_BIT {
553 	ISS_FRS		= 0x00000001,	/* Documented for R-Car Gen3 only */
554 	ISS_FTS		= 0x00000004,	/* Documented for R-Car Gen3 only */
555 	ISS_ES		= 0x00000040,
556 	ISS_MS		= 0x00000080,
557 	ISS_TFUS	= 0x00000100,
558 	ISS_TFWS	= 0x00000200,
559 	ISS_RFWS	= 0x00001000,
560 	ISS_CGIS	= 0x00002000,
561 	ISS_DPS1	= 0x00020000,
562 	ISS_DPS2	= 0x00040000,
563 	ISS_DPS3	= 0x00080000,
564 	ISS_DPS4	= 0x00100000,
565 	ISS_DPS5	= 0x00200000,
566 	ISS_DPS6	= 0x00400000,
567 	ISS_DPS7	= 0x00800000,
568 	ISS_DPS8	= 0x01000000,
569 	ISS_DPS9	= 0x02000000,
570 	ISS_DPS10	= 0x04000000,
571 	ISS_DPS11	= 0x08000000,
572 	ISS_DPS12	= 0x10000000,
573 	ISS_DPS13	= 0x20000000,
574 	ISS_DPS14	= 0x40000000,
575 	ISS_DPS15	= 0x80000000,
576 };
577 
578 /* CIE (R-Car Gen3 only) */
579 enum CIE_BIT {
580 	CIE_CRIE	= 0x00000001,
581 	CIE_CTIE	= 0x00000100,
582 	CIE_RQFM	= 0x00010000,
583 	CIE_CL0M	= 0x00020000,
584 	CIE_RFWL	= 0x00040000,
585 	CIE_RFFL	= 0x00080000,
586 };
587 
588 /* GCCR */
589 enum GCCR_BIT {
590 	GCCR_TCR	= 0x00000003,
591 	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
592 	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
593 	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
594 	GCCR_LTO	= 0x00000004,
595 	GCCR_LTI	= 0x00000008,
596 	GCCR_LPTC	= 0x00000010,
597 	GCCR_LMTT	= 0x00000020,
598 	GCCR_TCSS	= 0x00000300,
599 	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
600 	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
601 	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
602 };
603 
604 /* GTI */
605 enum GTI_BIT {
606 	GTI_TIV		= 0x0FFFFFFF,
607 };
608 
609 #define GTI_TIV_MAX	GTI_TIV
610 #define GTI_TIV_MIN	0x20
611 
612 /* GIC */
613 enum GIC_BIT {
614 	GIC_PTCE	= 0x00000001,	/* Documented for R-Car Gen3 only */
615 	GIC_PTME	= 0x00000004,
616 };
617 
618 /* GIS */
619 enum GIS_BIT {
620 	GIS_PTCF	= 0x00000001,	/* Documented for R-Car Gen3 only */
621 	GIS_PTMF	= 0x00000004,
622 	GIS_RESERVED	= GENMASK(15, 10),
623 };
624 
625 /* GIE (R-Car Gen3 only) */
626 enum GIE_BIT {
627 	GIE_PTCS	= 0x00000001,
628 	GIE_PTOS	= 0x00000002,
629 	GIE_PTMS0	= 0x00000004,
630 	GIE_PTMS1	= 0x00000008,
631 	GIE_PTMS2	= 0x00000010,
632 	GIE_PTMS3	= 0x00000020,
633 	GIE_PTMS4	= 0x00000040,
634 	GIE_PTMS5	= 0x00000080,
635 	GIE_PTMS6	= 0x00000100,
636 	GIE_PTMS7	= 0x00000200,
637 	GIE_ATCS0	= 0x00010000,
638 	GIE_ATCS1	= 0x00020000,
639 	GIE_ATCS2	= 0x00040000,
640 	GIE_ATCS3	= 0x00080000,
641 	GIE_ATCS4	= 0x00100000,
642 	GIE_ATCS5	= 0x00200000,
643 	GIE_ATCS6	= 0x00400000,
644 	GIE_ATCS7	= 0x00800000,
645 	GIE_ATCS8	= 0x01000000,
646 	GIE_ATCS9	= 0x02000000,
647 	GIE_ATCS10	= 0x04000000,
648 	GIE_ATCS11	= 0x08000000,
649 	GIE_ATCS12	= 0x10000000,
650 	GIE_ATCS13	= 0x20000000,
651 	GIE_ATCS14	= 0x40000000,
652 	GIE_ATCS15	= 0x80000000,
653 };
654 
655 /* GID (R-Car Gen3 only) */
656 enum GID_BIT {
657 	GID_PTCD	= 0x00000001,
658 	GID_PTOD	= 0x00000002,
659 	GID_PTMD0	= 0x00000004,
660 	GID_PTMD1	= 0x00000008,
661 	GID_PTMD2	= 0x00000010,
662 	GID_PTMD3	= 0x00000020,
663 	GID_PTMD4	= 0x00000040,
664 	GID_PTMD5	= 0x00000080,
665 	GID_PTMD6	= 0x00000100,
666 	GID_PTMD7	= 0x00000200,
667 	GID_ATCD0	= 0x00010000,
668 	GID_ATCD1	= 0x00020000,
669 	GID_ATCD2	= 0x00040000,
670 	GID_ATCD3	= 0x00080000,
671 	GID_ATCD4	= 0x00100000,
672 	GID_ATCD5	= 0x00200000,
673 	GID_ATCD6	= 0x00400000,
674 	GID_ATCD7	= 0x00800000,
675 	GID_ATCD8	= 0x01000000,
676 	GID_ATCD9	= 0x02000000,
677 	GID_ATCD10	= 0x04000000,
678 	GID_ATCD11	= 0x08000000,
679 	GID_ATCD12	= 0x10000000,
680 	GID_ATCD13	= 0x20000000,
681 	GID_ATCD14	= 0x40000000,
682 	GID_ATCD15	= 0x80000000,
683 };
684 
685 /* RIE0 (R-Car Gen3 only) */
686 enum RIE0_BIT {
687 	RIE0_FRS0	= 0x00000001,
688 	RIE0_FRS1	= 0x00000002,
689 	RIE0_FRS2	= 0x00000004,
690 	RIE0_FRS3	= 0x00000008,
691 	RIE0_FRS4	= 0x00000010,
692 	RIE0_FRS5	= 0x00000020,
693 	RIE0_FRS6	= 0x00000040,
694 	RIE0_FRS7	= 0x00000080,
695 	RIE0_FRS8	= 0x00000100,
696 	RIE0_FRS9	= 0x00000200,
697 	RIE0_FRS10	= 0x00000400,
698 	RIE0_FRS11	= 0x00000800,
699 	RIE0_FRS12	= 0x00001000,
700 	RIE0_FRS13	= 0x00002000,
701 	RIE0_FRS14	= 0x00004000,
702 	RIE0_FRS15	= 0x00008000,
703 	RIE0_FRS16	= 0x00010000,
704 	RIE0_FRS17	= 0x00020000,
705 };
706 
707 /* RID0 (R-Car Gen3 only) */
708 enum RID0_BIT {
709 	RID0_FRD0	= 0x00000001,
710 	RID0_FRD1	= 0x00000002,
711 	RID0_FRD2	= 0x00000004,
712 	RID0_FRD3	= 0x00000008,
713 	RID0_FRD4	= 0x00000010,
714 	RID0_FRD5	= 0x00000020,
715 	RID0_FRD6	= 0x00000040,
716 	RID0_FRD7	= 0x00000080,
717 	RID0_FRD8	= 0x00000100,
718 	RID0_FRD9	= 0x00000200,
719 	RID0_FRD10	= 0x00000400,
720 	RID0_FRD11	= 0x00000800,
721 	RID0_FRD12	= 0x00001000,
722 	RID0_FRD13	= 0x00002000,
723 	RID0_FRD14	= 0x00004000,
724 	RID0_FRD15	= 0x00008000,
725 	RID0_FRD16	= 0x00010000,
726 	RID0_FRD17	= 0x00020000,
727 };
728 
729 /* RIE2 (R-Car Gen3 only) */
730 enum RIE2_BIT {
731 	RIE2_QFS0	= 0x00000001,
732 	RIE2_QFS1	= 0x00000002,
733 	RIE2_QFS2	= 0x00000004,
734 	RIE2_QFS3	= 0x00000008,
735 	RIE2_QFS4	= 0x00000010,
736 	RIE2_QFS5	= 0x00000020,
737 	RIE2_QFS6	= 0x00000040,
738 	RIE2_QFS7	= 0x00000080,
739 	RIE2_QFS8	= 0x00000100,
740 	RIE2_QFS9	= 0x00000200,
741 	RIE2_QFS10	= 0x00000400,
742 	RIE2_QFS11	= 0x00000800,
743 	RIE2_QFS12	= 0x00001000,
744 	RIE2_QFS13	= 0x00002000,
745 	RIE2_QFS14	= 0x00004000,
746 	RIE2_QFS15	= 0x00008000,
747 	RIE2_QFS16	= 0x00010000,
748 	RIE2_QFS17	= 0x00020000,
749 	RIE2_RFFS	= 0x80000000,
750 };
751 
752 /* RID2 (R-Car Gen3 only) */
753 enum RID2_BIT {
754 	RID2_QFD0	= 0x00000001,
755 	RID2_QFD1	= 0x00000002,
756 	RID2_QFD2	= 0x00000004,
757 	RID2_QFD3	= 0x00000008,
758 	RID2_QFD4	= 0x00000010,
759 	RID2_QFD5	= 0x00000020,
760 	RID2_QFD6	= 0x00000040,
761 	RID2_QFD7	= 0x00000080,
762 	RID2_QFD8	= 0x00000100,
763 	RID2_QFD9	= 0x00000200,
764 	RID2_QFD10	= 0x00000400,
765 	RID2_QFD11	= 0x00000800,
766 	RID2_QFD12	= 0x00001000,
767 	RID2_QFD13	= 0x00002000,
768 	RID2_QFD14	= 0x00004000,
769 	RID2_QFD15	= 0x00008000,
770 	RID2_QFD16	= 0x00010000,
771 	RID2_QFD17	= 0x00020000,
772 	RID2_RFFD	= 0x80000000,
773 };
774 
775 /* TIE (R-Car Gen3 only) */
776 enum TIE_BIT {
777 	TIE_FTS0	= 0x00000001,
778 	TIE_FTS1	= 0x00000002,
779 	TIE_FTS2	= 0x00000004,
780 	TIE_FTS3	= 0x00000008,
781 	TIE_TFUS	= 0x00000100,
782 	TIE_TFWS	= 0x00000200,
783 	TIE_MFUS	= 0x00000400,
784 	TIE_MFWS	= 0x00000800,
785 	TIE_TDPS0	= 0x00010000,
786 	TIE_TDPS1	= 0x00020000,
787 	TIE_TDPS2	= 0x00040000,
788 	TIE_TDPS3	= 0x00080000,
789 };
790 
791 /* TID (R-Car Gen3 only) */
792 enum TID_BIT {
793 	TID_FTD0	= 0x00000001,
794 	TID_FTD1	= 0x00000002,
795 	TID_FTD2	= 0x00000004,
796 	TID_FTD3	= 0x00000008,
797 	TID_TFUD	= 0x00000100,
798 	TID_TFWD	= 0x00000200,
799 	TID_MFUD	= 0x00000400,
800 	TID_MFWD	= 0x00000800,
801 	TID_TDPD0	= 0x00010000,
802 	TID_TDPD1	= 0x00020000,
803 	TID_TDPD2	= 0x00040000,
804 	TID_TDPD3	= 0x00080000,
805 };
806 
807 /* ECMR */
808 enum ECMR_BIT {
809 	ECMR_PRM	= 0x00000001,
810 	ECMR_DM		= 0x00000002,
811 	ECMR_TE		= 0x00000020,
812 	ECMR_RE		= 0x00000040,
813 	ECMR_MPDE	= 0x00000200,
814 	ECMR_TXF	= 0x00010000,	/* Documented for R-Car Gen3 only */
815 	ECMR_RXF	= 0x00020000,
816 	ECMR_PFR	= 0x00040000,
817 	ECMR_ZPF	= 0x00080000,	/* Documented for R-Car Gen3 and RZ/G2L */
818 	ECMR_RZPF	= 0x00100000,
819 	ECMR_DPAD	= 0x00200000,
820 	ECMR_RCSC	= 0x00800000,
821 	ECMR_RCPT	= 0x02000000,	/* Documented for RZ/G2L only */
822 	ECMR_TRCCM	= 0x04000000,
823 };
824 
825 /* ECSR */
826 enum ECSR_BIT {
827 	ECSR_ICD	= 0x00000001,
828 	ECSR_MPD	= 0x00000002,
829 	ECSR_LCHNG	= 0x00000004,
830 	ECSR_PHYI	= 0x00000008,
831 	ECSR_PFRI	= 0x00000010,	/* Documented for R-Car Gen3 and RZ/G2L */
832 };
833 
834 /* ECSIPR */
835 enum ECSIPR_BIT {
836 	ECSIPR_ICDIP	= 0x00000001,
837 	ECSIPR_MPDIP	= 0x00000002,
838 	ECSIPR_LCHNGIP	= 0x00000004,
839 };
840 
841 /* PIR */
842 enum PIR_BIT {
843 	PIR_MDC		= 0x00000001,
844 	PIR_MMD		= 0x00000002,
845 	PIR_MDO		= 0x00000004,
846 	PIR_MDI		= 0x00000008,
847 };
848 
849 /* PSR */
850 enum PSR_BIT {
851 	PSR_LMON	= 0x00000001,
852 };
853 
854 /* PIPR */
855 enum PIPR_BIT {
856 	PIPR_PHYIP	= 0x00000001,
857 };
858 
859 /* MPR */
860 enum MPR_BIT {
861 	MPR_MP		= 0x0000ffff,
862 };
863 
864 /* GECMR */
865 enum GECMR_BIT {
866 	GECMR_SPEED		= 0x00000001,
867 	GECMR_SPEED_100		= 0x00000000,
868 	GECMR_SPEED_1000	= 0x00000001,
869 	GBETH_GECMR_SPEED	= 0x00000030,
870 	GBETH_GECMR_SPEED_10	= 0x00000000,
871 	GBETH_GECMR_SPEED_100	= 0x00000010,
872 	GBETH_GECMR_SPEED_1000	= 0x00000020,
873 };
874 
875 /* The Ethernet AVB descriptor definitions. */
876 struct ravb_desc {
877 	__le16 ds;	/* Descriptor size */
878 	u8 cc;		/* Content control MSBs (reserved) */
879 	u8 die_dt;	/* Descriptor interrupt enable and type */
880 	__le32 dptr;	/* Descriptor pointer */
881 };
882 
883 #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
884 
885 enum DIE_DT {
886 	/* Frame data */
887 	DT_FMID		= 0x40,
888 	DT_FSTART	= 0x50,
889 	DT_FEND		= 0x60,
890 	DT_FSINGLE	= 0x70,
891 	/* Chain control */
892 	DT_LINK		= 0x80,
893 	DT_LINKFIX	= 0x90,
894 	DT_EOS		= 0xa0,
895 	/* HW/SW arbitration */
896 	DT_FEMPTY	= 0xc0,
897 	DT_FEMPTY_IS	= 0xd0,
898 	DT_FEMPTY_IC	= 0xe0,
899 	DT_FEMPTY_ND	= 0xf0,
900 	DT_LEMPTY	= 0x20,
901 	DT_EEMPTY	= 0x30,
902 };
903 
904 struct ravb_rx_desc {
905 	__le16 ds_cc;	/* Descriptor size and content control LSBs */
906 	u8 msc;		/* MAC status code */
907 	u8 die_dt;	/* Descriptor interrupt enable and type */
908 	__le32 dptr;	/* Descpriptor pointer */
909 };
910 
911 struct ravb_ex_rx_desc {
912 	__le16 ds_cc;	/* Descriptor size and content control lower bits */
913 	u8 msc;		/* MAC status code */
914 	u8 die_dt;	/* Descriptor interrupt enable and type */
915 	__le32 dptr;	/* Descpriptor pointer */
916 	__le32 ts_n;	/* Timestampe nsec */
917 	__le32 ts_sl;	/* Timestamp low */
918 	__le16 ts_sh;	/* Timestamp high */
919 	__le16 res;	/* Reserved bits */
920 };
921 
922 enum RX_DS_CC_BIT {
923 	RX_DS		= 0x0fff, /* Data size */
924 	RX_TR		= 0x1000, /* Truncation indication */
925 	RX_EI		= 0x2000, /* Error indication */
926 	RX_PS		= 0xc000, /* Padding selection */
927 };
928 
929 /* E-MAC status code */
930 enum MSC_BIT {
931 	MSC_CRC		= 0x01, /* Frame CRC error */
932 	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
933 	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
934 	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
935 	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
936 	MSC_CRL		= 0x20, /* Carrier lost */
937 	MSC_CEEF	= 0x40, /* Carrier extension error */
938 	MSC_MC		= 0x80, /* Multicast frame reception */
939 };
940 
941 struct ravb_tx_desc {
942 	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
943 	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
944 	u8 die_dt;	/* Descriptor interrupt enable and type */
945 	__le32 dptr;	/* Descpriptor pointer */
946 };
947 
948 enum TX_DS_TAGL_BIT {
949 	TX_DS		= 0x0fff, /* Data size */
950 	TX_TAGL		= 0xf000, /* Frame tag LSBs */
951 };
952 
953 enum TX_TAGH_TSR_BIT {
954 	TX_TAGH		= 0x3f, /* Frame tag MSBs */
955 	TX_TSR		= 0x40, /* Timestamp storage request */
956 };
957 enum RAVB_QUEUE {
958 	RAVB_BE = 0,	/* Best Effort Queue */
959 	RAVB_NC,	/* Network Control Queue */
960 };
961 
962 enum CXR31_BIT {
963 	CXR31_SEL_LINK0	= 0x00000001,
964 	CXR31_SEL_LINK1	= 0x00000008,
965 };
966 
967 enum CXR35_BIT {
968 	CXR35_SEL_XMII		= 0x00000003,
969 	CXR35_SEL_XMII_RGMII	= 0x00000000,
970 	CXR35_SEL_XMII_MII	= 0x00000002,
971 	CXR35_HALFCYC_CLKSW	= 0xffff0000,
972 };
973 
974 enum CSR0_BIT {
975 	CSR0_TPE	= 0x00000010,
976 	CSR0_RPE	= 0x00000020,
977 };
978 
979 enum CSR1_BIT {
980 	CSR1_TIP4	= 0x00000001,
981 	CSR1_TTCP4	= 0x00000010,
982 	CSR1_TUDP4	= 0x00000020,
983 	CSR1_TICMP4	= 0x00000040,
984 	CSR1_TTCP6	= 0x00100000,
985 	CSR1_TUDP6	= 0x00200000,
986 	CSR1_TICMP6	= 0x00400000,
987 	CSR1_THOP	= 0x01000000,
988 	CSR1_TROUT	= 0x02000000,
989 	CSR1_TAHD	= 0x04000000,
990 	CSR1_TDHD	= 0x08000000,
991 };
992 
993 #define CSR1_CSUM_ENABLE (CSR1_TTCP4 | CSR1_TUDP4 | CSR1_TTCP6 | CSR1_TUDP6)
994 
995 enum CSR2_BIT {
996 	CSR2_RIP4	= 0x00000001,
997 	CSR2_RTCP4	= 0x00000010,
998 	CSR2_RUDP4	= 0x00000020,
999 	CSR2_RICMP4	= 0x00000040,
1000 	CSR2_RTCP6	= 0x00100000,
1001 	CSR2_RUDP6	= 0x00200000,
1002 	CSR2_RICMP6	= 0x00400000,
1003 	CSR2_RHOP	= 0x01000000,
1004 	CSR2_RROUT	= 0x02000000,
1005 	CSR2_RAHD	= 0x04000000,
1006 	CSR2_RDHD	= 0x08000000,
1007 };
1008 
1009 #define CSR2_CSUM_ENABLE (CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4 | \
1010 			  CSR2_RTCP6 | CSR2_RUDP6 | CSR2_RICMP6)
1011 
1012 #define RX_QUEUE_OFFSET	4
1013 #define NUM_RX_QUEUE	2
1014 #define NUM_TX_QUEUE	2
1015 
1016 struct ravb_tstamp_skb {
1017 	struct list_head list;
1018 	struct sk_buff *skb;
1019 	u16 tag;
1020 };
1021 
1022 struct ravb_ptp_perout {
1023 	u32 target;
1024 	u32 period;
1025 };
1026 
1027 #define N_EXT_TS	1
1028 #define N_PER_OUT	1
1029 
1030 struct ravb_ptp {
1031 	struct ptp_clock *clock;
1032 	struct ptp_clock_info info;
1033 	u32 default_addend;
1034 	u32 current_addend;
1035 	int extts[N_EXT_TS];
1036 	struct ravb_ptp_perout perout[N_PER_OUT];
1037 };
1038 
1039 /**
1040  * struct ravb_gptp_info - Platform specific gPTP behavior
1041  *
1042  * Each generation of RAVB have slightly different behaviors when interacting
1043  * with the gPTP clock. This struct provides the callbacks to be called at
1044  * critical points in the RAVB driver.
1045  *
1046  * @probe:		Probe the gPTP clock
1047  * @clock_index:	Get the PTP clock index, if any
1048  * @set_config_mode:	Enter config mode
1049  * @dmac_start:		Called when the DMAC starts
1050  * @dmac_stop:		Called when the DMAC stops
1051  * @ndev_open:		Called when the ndev is opened
1052  * @ndev_close:		Called when the ndev is closed
1053  */
1054 struct ravb_gptp_info {
1055 	int (*probe)(struct net_device *ndev);
1056 	int (*clock_index)(struct net_device *ndev);
1057 	int (*set_config_mode)(struct net_device *ndev);
1058 	int (*dmac_start)(struct net_device *ndev);
1059 	void (*dmac_stop)(struct net_device *ndev);
1060 	int (*ndev_open)(struct net_device *ndev);
1061 	void (*ndev_close)(struct net_device *ndev);
1062 };
1063 
1064 struct ravb_hw_info {
1065 	int (*receive)(struct net_device *ndev, int budget, int q);
1066 	void (*set_rate)(struct net_device *ndev);
1067 	int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1068 	int (*dmac_init)(struct net_device *ndev);
1069 	void (*emac_init)(struct net_device *ndev);
1070 	const char (*gstrings_stats)[ETH_GSTRING_LEN];
1071 	size_t gstrings_size;
1072 	netdev_features_t net_hw_features;
1073 	netdev_features_t net_features;
1074 	netdev_features_t vlan_features;
1075 	int stats_len;
1076 	u32 tccr_mask;
1077 	u32 tx_max_frame_size;
1078 	u32 rx_max_frame_size;
1079 	u32 rx_buffer_size;
1080 	u32 rx_desc_size;
1081 	u32 dbat_entry_num;
1082 	const struct ravb_gptp_info *ptp; /* Callbacks to handle gPTP interactions. */
1083 	unsigned aligned_tx: 1;
1084 	unsigned coalesce_irqs:1;	/* Needs software IRQ coalescing */
1085 
1086 	/* hardware features */
1087 	unsigned internal_delay:1;	/* AVB-DMAC has internal delays */
1088 	unsigned tx_counters:1;		/* E-MAC has TX counters */
1089 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
1090 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
1091 	unsigned irq_en_dis:1;		/* Has separate irq enable and disable regs */
1092 	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1093 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
1094 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
1095 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
1096 };
1097 
1098 struct ravb_rx_buffer {
1099 	struct page *page;
1100 	unsigned int offset;
1101 };
1102 
1103 struct ravb_private {
1104 	struct net_device *ndev;
1105 	struct platform_device *pdev;
1106 	void __iomem *addr;
1107 	struct clk *clk;
1108 	struct clk *refclk;
1109 	struct clk *gptp_clk;
1110 	struct mdiobb_ctrl mdiobb;
1111 	u32 num_rx_ring[NUM_RX_QUEUE];
1112 	u32 num_tx_ring[NUM_TX_QUEUE];
1113 	u32 desc_bat_size;
1114 	dma_addr_t desc_bat_dma;
1115 	struct ravb_desc *desc_bat;
1116 	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1117 	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1118 	union {
1119 		struct ravb_rx_desc *desc;
1120 		struct ravb_ex_rx_desc *ex_desc;
1121 		void *raw;
1122 	} rx_ring[NUM_RX_QUEUE];
1123 	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1124 	void *tx_align[NUM_TX_QUEUE];
1125 	struct sk_buff *rx_1st_skb;
1126 	struct page_pool *rx_pool[NUM_RX_QUEUE];
1127 	struct ravb_rx_buffer *rx_buffers[NUM_RX_QUEUE];
1128 	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1129 	u32 rx_over_errors;
1130 	u32 rx_fifo_errors;
1131 	struct net_device_stats stats[NUM_RX_QUEUE];
1132 	enum hwtstamp_tx_types tstamp_tx_ctrl;
1133 	enum hwtstamp_rx_filters tstamp_rx_ctrl;
1134 	struct list_head ts_skb_list;
1135 	u32 ts_skb_tag;
1136 	struct ravb_ptp ptp;
1137 	struct device_node *of_gptp;	/* Reference to external gPTP clock, if any. */
1138 	spinlock_t lock;		/* Register access lock */
1139 	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1140 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1141 	u32 cur_tx[NUM_TX_QUEUE];
1142 	u32 dirty_tx[NUM_TX_QUEUE];
1143 	struct napi_struct napi[NUM_RX_QUEUE];
1144 	struct work_struct work;
1145 	/* MII transceiver section. */
1146 	struct mii_bus *mii_bus;	/* MDIO bus control */
1147 	int link;
1148 	phy_interface_t phy_interface;
1149 	int msg_enable;
1150 	int speed;
1151 	int emac_irq;
1152 	int err_irq;
1153 	int mgmt_irq;
1154 
1155 	unsigned no_avb_link:1;
1156 	unsigned avb_link_active_low:1;
1157 	unsigned wol_enabled:1;
1158 	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
1159 	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
1160 	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
1161 	unsigned int num_tx_desc;	/* TX descriptors per packet */
1162 
1163 	int duplex;
1164 
1165 	const struct ravb_hw_info *info;
1166 	struct reset_control *rstc;
1167 
1168 	u32 gti_tiv;
1169 };
1170 
1171 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1172 {
1173 	struct ravb_private *priv = netdev_priv(ndev);
1174 
1175 	return ioread32(priv->addr + reg);
1176 }
1177 
1178 static inline void ravb_write(struct net_device *ndev, u32 data,
1179 			      enum ravb_reg reg)
1180 {
1181 	struct ravb_private *priv = netdev_priv(ndev);
1182 
1183 	iowrite32(data, priv->addr + reg);
1184 }
1185 
1186 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1187 		 u32 set);
1188 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1189 
1190 void ravb_ptp_interrupt(struct net_device *ndev);
1191 int ravb_ptp_init(struct net_device *ndev);
1192 void ravb_ptp_stop(struct net_device *ndev);
1193 
1194 #endif	/* #ifndef __RAVB_H__ */
1195