1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2026 Renesas Electronics Corp.
4 * Copyright (C) 2026 Ideas on Board Oy
5 * Copyright (C) 2026 Ragnatech AB
6 */
7
8 #include <linux/delay.h>
9 #include <linux/of_platform.h>
10 #include <linux/pm_runtime.h>
11
12 #include <media/v4l2-ioctl.h>
13 #include <media/videobuf2-dma-contig.h>
14 #include <media/vsp1.h>
15
16 #include "risp-core.h"
17
18 #define ISP_CS_STREAMER_MODE_REG 0x7000
19 #define ISP_CS_STREAMER_MODE_STREAMER_EN 0xf
20
21 #define ISP_CS_STREAMER_VBLANK_REG 0x7004
22 #define ISP_CS_STREAMER_HBLANK_REG 0x7008
23
24 #define ISP_CS_STREAMER_CONFIG_DMA_CONTROL_REG 0x7100
25 #define ISP_CS_STREAMER_CONFIG_DMA_REG_ADDRESS_UPPER_8BIT_MASK GENMASK(31, 24)
26 #define ISP_CS_STREAMER_CONFIG_DMA_ENABLE0 BIT(0)
27
28 #define ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_REG 0x2100
29 #define ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_ENABLE1 BIT(31)
30 #define ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_CONFIG_DATA_START_REG_ADDRESS_MASK GENMASK(15, 0)
31
32 #define ISP_CS_STREAMER_CONFIG_DMA_CONTROL2_REG 0x2104
33
34 #define ISP_CORE_ISPCORE_INT_STATUS 0x80000
35 #define ISP_CORE_ISPCORE_INT_ENABLE 0x80004
36 #define ISPCORE_DMA_IMAGE_FRAME_MODE(i, f) (0x84000 + 0x1000 * (i) + 0x100 * (f))
37 #define ISPCORE_DMA_IMAGE_FRAME_PIXEL_POSITION(i, f) (0x84004 + 0x1000 * (i) + 0x100 * (f))
38 #define ISPCORE_DMA_IMAGE_FRAME_PIXEL_BITWIDTH_MINUS1(i, f) (0x84008 + 0x1000 * (i) + 0x100 * (f))
39 #define ISPCORE_DMA_IMAGE_FRAME_PIXEL_BPP(i, f) (0x8400c + 0x1000 * (i) + 0x100 * (f))
40 #define ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP0(i, f) (0x84010 + 0x1000 * (i) + 0x100 * (f))
41 #define ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP1(i, f) (0x84014 + 0x1000 * (i) + 0x100 * (f))
42 #define ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP2(i, f) (0x84018 + 0x1000 * (i) + 0x100 * (f))
43 #define ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP3(i, f) (0x8401c + 0x1000 * (i) + 0x100 * (f))
44 #define ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP0(i, f) (0x84020 + 0x1000 * (i) + 0x100 * (f))
45 #define ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP1(i, f) (0x84024 + 0x1000 * (i) + 0x100 * (f))
46 #define ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP2(i, f) (0x84028 + 0x1000 * (i) + 0x100 * (f))
47 #define ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP3(i, f) (0x8402c + 0x1000 * (i) + 0x100 * (f))
48 #define ISPCORE_DMA_IMAGE_FRAME_AXI_ID(i, f) (0x84030 + 0x1000 * (i) + 0x100 * (f))
49
50 #define ISPCORE_DMA_IMAGE_FLUSH_OUT_REG(i) (0x84400 + 0x1000 * (i))
51 #define ISPCORE_DMA_IMAGE_FLUSH_OUT_PADDING_PIXEL_EOF_MASK GENMASK(31, 16)
52 #define ISPCORE_DMA_IMAGE_FLUSH_OUT_PADDING_PIXEL_EOF_SHIFT 16
53
54 #define ISPCORE_DMA_IMAGE_AXI_CONFIG_REG(i) (0x84800 + 0x1000 * (i))
55
risp_cs_write(struct rcar_isp_core * core,u32 offset,u32 value)56 static void risp_cs_write(struct rcar_isp_core *core, u32 offset, u32 value)
57 {
58 iowrite32(value, core->csbase + offset);
59 }
60
risp_cs_read(struct rcar_isp_core * core,u32 offset)61 static u32 risp_cs_read(struct rcar_isp_core *core, u32 offset)
62 {
63 return ioread32(core->csbase + offset);
64 }
65
risp_core_write(struct rcar_isp_core * core,u32 offset,u32 value)66 static void risp_core_write(struct rcar_isp_core *core, u32 offset, u32 value)
67 {
68 iowrite32(value, core->base + offset);
69 }
70
risp_core_read(struct rcar_isp_core * core,u32 offset)71 static u32 risp_core_read(struct rcar_isp_core *core, u32 offset)
72 {
73 return ioread32(core->base + offset);
74 }
75
risp_core_job_run_params(struct rcar_isp_core * core,struct vsp1_isp_job_desc * vspx_job,struct risp_buffer * buf)76 static void risp_core_job_run_params(struct rcar_isp_core *core,
77 struct vsp1_isp_job_desc *vspx_job,
78 struct risp_buffer *buf)
79 {
80 u32 *params_buf = (u32 *)buf->vsp_buffer.cpu_addr;
81 bool have_config = !!params_buf[0];
82 u32 ctrl0, ctrl1, ctrl2;
83
84 /*
85 * If we have a configuration but not asked the VSPX to program it,
86 * use MMIO to write the configuration. This might be needed to work
87 * around limitations of the VSPX ConfigDMA, see comment in
88 * risp_core_job_prepare().
89 */
90 if (have_config && !vspx_job->config.pairs) {
91 for (unsigned int i = 0; i < params_buf[0]; i++)
92 risp_core_write(core, params_buf[2 + i * 2] & 0xffff,
93 params_buf[3 + i * 2]);
94
95 /* Disable ConfigDMA. */
96 have_config = false;
97 }
98
99 ctrl0 = risp_cs_read(core, ISP_CS_STREAMER_CONFIG_DMA_CONTROL_REG) &
100 ~ISP_CS_STREAMER_CONFIG_DMA_ENABLE0;
101 ctrl1 = risp_cs_read(core, ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_REG) &
102 ~(ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_ENABLE1 | 0xffff);
103 ctrl2 = 0;
104
105 if (have_config) {
106 ctrl0 |= ISP_CS_STREAMER_CONFIG_DMA_ENABLE0;
107 ctrl1 |= ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_ENABLE1 |
108 (params_buf[2] & 0xffff);
109 ctrl2 = params_buf[3];
110 }
111
112 risp_cs_write(core, ISP_CS_STREAMER_CONFIG_DMA_CONTROL_REG, ctrl0);
113 risp_cs_write(core, ISP_CS_STREAMER_CONFIG_DMA_CONTROL1_REG, ctrl1);
114 risp_cs_write(core, ISP_CS_STREAMER_CONFIG_DMA_CONTROL2_REG, ctrl2);
115 }
116
risp_core_job_run_output(struct rcar_isp_core * core,struct risp_buffer * buf)117 static void risp_core_job_run_output(struct rcar_isp_core *core,
118 struct risp_buffer *buf)
119 {
120 const struct v4l2_format *fmt = &core->io[RISP_CORE_OUTPUT1].format;
121 dma_addr_t mem;
122 u32 reg;
123
124 for (unsigned int frame = 0; frame < 4; frame++) {
125 reg = ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP0(0, frame);
126 mem = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
127 risp_core_write(core, reg, mem);
128
129 /* Only NV16 uses 2 planes. */
130 if (fmt->fmt.pix_mp.pixelformat != V4L2_PIX_FMT_NV16M)
131 continue;
132
133 reg = ISPCORE_DMA_IMAGE_FRAME_BASE_ADDRESS_COMP1(0, frame);
134 mem = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 1);
135 risp_core_write(core, reg, mem);
136 }
137 }
138
risp_core_job_run(struct rcar_isp_core * core)139 static void risp_core_job_run(struct rcar_isp_core *core)
140 {
141 struct rcar_isp_job *job;
142
143 lockdep_assert_held(&core->lock);
144
145 /* ISP not yet started, nothing to do. */
146 if (!core->streaming)
147 return;
148
149 /* If we have active buffers in the ISP core, nothing to do. */
150 if (core->vspx.job)
151 return;
152
153 job = list_first_entry_or_null(&core->risp_jobs,
154 struct rcar_isp_job,
155 job_queue);
156 if (!job)
157 return;
158
159 list_del(&job->job_queue);
160
161 core->vspx.job = job;
162
163 /* Program the ISP register before kicking the VSPX. */
164 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
165 struct risp_buffer *buf = job->buffers[i];
166
167 switch (i) {
168 case RISP_CORE_PARAMS:
169 risp_core_job_run_params(core, &job->vspx_job, buf);
170 break;
171 case RISP_CORE_OUTPUT1:
172 risp_core_job_run_output(core, buf);
173 break;
174 }
175 }
176
177 if (vsp1_isp_job_run(core->vspx.dev, &job->vspx_job)) {
178 /*
179 * Release all buffers in this job if running on the VSPX
180 * failed. Userspace should recover from this, no new jobs are
181 * scheduled.
182 */
183 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
184 struct risp_buffer *buf = job->buffers[i];
185
186 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
187 }
188
189 vsp1_isp_job_release(core->vspx.dev, &job->vspx_job);
190 core->vspx.job = NULL;
191 kfree(job);
192
193 dev_err(core->dev, "Failed to run job");
194 }
195 }
196
risp_core_pixfmt_to_vspx(u32 pixfmt)197 static int risp_core_pixfmt_to_vspx(u32 pixfmt)
198 {
199 switch (pixfmt) {
200 case V4L2_PIX_FMT_SBGGR8:
201 case V4L2_PIX_FMT_SGBRG8:
202 case V4L2_PIX_FMT_SGRBG8:
203 case V4L2_PIX_FMT_SRGGB8:
204 return V4L2_PIX_FMT_GREY;
205 case V4L2_PIX_FMT_SBGGR10:
206 case V4L2_PIX_FMT_SGBRG10:
207 case V4L2_PIX_FMT_SGRBG10:
208 case V4L2_PIX_FMT_SRGGB10:
209 return V4L2_PIX_FMT_Y10;
210 case V4L2_PIX_FMT_SBGGR12:
211 case V4L2_PIX_FMT_SGBRG12:
212 case V4L2_PIX_FMT_SGRBG12:
213 case V4L2_PIX_FMT_SRGGB12:
214 return V4L2_PIX_FMT_Y12;
215 default:
216 return -EINVAL;
217 }
218 }
219
risp_core_job_prepare(struct rcar_isp_core * core)220 int risp_core_job_prepare(struct rcar_isp_core *core)
221 {
222 struct vsp1_isp_job_desc *vspx_job;
223 int vspx_pixfmt = -EINVAL;
224 struct rcar_isp_job *job;
225 int ret;
226
227 lockdep_assert_held(&core->io_lock);
228
229 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
230 if (list_empty(&core->io[i].buffers))
231 return 0;
232 }
233
234 /* Memory is released when the job is consumed. */
235 job = kzalloc_obj(*job);
236 if (!job)
237 return -ENOMEM;
238
239 vspx_job = &job->vspx_job;
240
241 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
242 struct risp_buffer *buf;
243
244 /*
245 * Extract buffer from the IO queue and save a reference in
246 * the job description. Buffers will be completed when the
247 * corresponding frame will be completed by the ISP.
248 */
249 buf = list_first_entry_or_null(&core->io[i].buffers,
250 struct risp_buffer, list);
251 /*
252 * This should not happen as we have checked there is buffers,
253 * with the lock held, but check the return value anyhow.
254 */
255 if (WARN_ON(!buf)) {
256 ret = -EINVAL;
257 goto error_return_buffers;
258 }
259
260 switch (i) {
261 case RISP_CORE_INPUT1: {
262 u32 isp_pixfmt = core->io[i].format.fmt.pix_mp.pixelformat;
263
264 vspx_pixfmt = risp_core_pixfmt_to_vspx(isp_pixfmt);
265
266 vspx_job->img.fmt = core->io[i].format.fmt.pix_mp;
267 vspx_job->img.fmt.pixelformat = vspx_pixfmt;
268 vspx_job->img.mem =
269 vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf,
270 0);
271 break;
272 }
273 case RISP_CORE_PARAMS: {
274 u32 *params_buf = (u32 *)buf->vsp_buffer.cpu_addr;
275 u32 pairs = params_buf[0];
276
277 /*
278 * Check config pairs not larger then buffer.
279 *
280 * Remove 8 byte header and each pair is 16 bytes.
281 */
282 if (pairs > (RISP_IO_PARAMS_BUF_SIZE - 8) / 16) {
283 ret = -EINVAL;
284 goto error_return_buffers;
285 }
286
287 /*
288 * Work around undocumented behavior of the ConfigDMA
289 * interface by using MMIO if 16 or less pairs are to
290 * be programmed.
291 *
292 * Programming 15 or less pairs corrupts the image data
293 * following the config buffer, programming exactly 16
294 * pairs freeze the whole VSPX.
295 */
296 if (pairs <= 16) {
297 vspx_job->config.pairs = 0;
298 } else {
299 vspx_job->config.pairs = pairs;
300 vspx_job->config.mem = buf->vsp_buffer.dma_addr;
301 }
302 break;
303 }
304 }
305
306 list_del(&buf->list);
307 job->buffers[i] = buf;
308 }
309
310 if (vspx_pixfmt < 0) {
311 ret = -EINVAL;
312 goto error_return_buffers;
313 }
314
315 ret = vsp1_isp_job_prepare(core->vspx.dev, vspx_job);
316 if (ret)
317 goto error_return_buffers;
318
319 scoped_guard(spinlock_irqsave, &core->lock) {
320 list_add_tail(&job->job_queue, &core->risp_jobs);
321 risp_core_job_run(core);
322 }
323
324 return 0;
325
326 error_return_buffers:
327 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
328 if (!job->buffers[i])
329 continue;
330
331 vb2_buffer_done(&job->buffers[i]->vb.vb2_buf,
332 VB2_BUF_STATE_ERROR);
333 }
334 kfree(job);
335 return ret;
336 }
337
risp_core_config_output(struct rcar_isp_core * core,unsigned int index,const struct v4l2_pix_format_mplane * pix)338 static int risp_core_config_output(struct rcar_isp_core *core,
339 unsigned int index,
340 const struct v4l2_pix_format_mplane *pix)
341 {
342 /* For all frame capture slots. */
343 for (unsigned int frame = 0; frame < 4; frame++) {
344 switch (pix->pixelformat) {
345 case V4L2_PIX_FMT_NV16M:
346 risp_core_write(core,
347 ISPCORE_DMA_IMAGE_FRAME_MODE(index, frame),
348 1);
349 risp_core_write(core,
350 ISPCORE_DMA_IMAGE_FRAME_PIXEL_POSITION(index, frame),
351 0 << 24 | 0 << 16 | 4 << 8 | 16 << 0);
352 risp_core_write(core,
353 ISPCORE_DMA_IMAGE_FRAME_PIXEL_BITWIDTH_MINUS1(index, frame),
354 0 << 24 | 0 << 16 | 7 << 8 | 7 << 0);
355 risp_core_write(core,
356 ISPCORE_DMA_IMAGE_FRAME_PIXEL_BPP(index, frame),
357 0 << 28 | 0 << 24 |
358 0 << 20 | 0 << 16 |
359 3 << 12 | 0 << 8 |
360 3 << 4 | 0 << 0);
361
362 risp_core_write(core,
363 ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP0(index, frame),
364 pix->plane_fmt[0].bytesperline);
365 risp_core_write(core,
366 ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP1(index, frame),
367 pix->plane_fmt[1].bytesperline);
368 break;
369 case V4L2_PIX_FMT_XBGR32:
370 risp_core_write(core,
371 ISPCORE_DMA_IMAGE_FRAME_MODE(index, frame),
372 0);
373 risp_core_write(core,
374 ISPCORE_DMA_IMAGE_FRAME_PIXEL_POSITION(index, frame),
375 0 << 24 | 0 << 16 | 0 << 8 | 0 << 0);
376 risp_core_write(core,
377 ISPCORE_DMA_IMAGE_FRAME_PIXEL_BITWIDTH_MINUS1(index, frame),
378 0 << 24 | 0 << 16 | 0 << 8 | 23 << 0);
379 risp_core_write(core,
380 ISPCORE_DMA_IMAGE_FRAME_PIXEL_BPP(index, frame),
381 0 << 28 | 0 << 24 |
382 0 << 20 | 0 << 16 |
383 0 << 12 | 0 << 8 |
384 3 << 4 | 2 << 0);
385
386 risp_core_write(core,
387 ISPCORE_DMA_IMAGE_FRAME_STRIDE_COMP0(index, frame),
388 pix->plane_fmt[0].bytesperline);
389 break;
390 default:
391 return -EINVAL;
392 }
393
394 risp_core_write(core,
395 ISPCORE_DMA_IMAGE_FRAME_AXI_ID(index, frame),
396 0);
397 }
398
399 /* Set image out flush EOF. */
400 risp_core_write(core, ISPCORE_DMA_IMAGE_FLUSH_OUT_REG(index),
401 pix->plane_fmt[0].bytesperline <<
402 ISPCORE_DMA_IMAGE_FLUSH_OUT_PADDING_PIXEL_EOF_SHIFT);
403
404 /* Enable DMA and set burst length. */
405 risp_core_write(core, ISPCORE_DMA_IMAGE_AXI_CONFIG_REG(index),
406 BIT(31) | 7);
407
408 return 0;
409 }
410
risp_core_pix2bus(const struct rcar_isp_core_io * io)411 static u32 risp_core_pix2bus(const struct rcar_isp_core_io *io)
412 {
413 switch (io->format.fmt.pix_mp.pixelformat) {
414 case V4L2_PIX_FMT_SBGGR8:
415 return MEDIA_BUS_FMT_SBGGR8_1X8;
416 case V4L2_PIX_FMT_SGBRG8:
417 return MEDIA_BUS_FMT_SGBRG8_1X8;
418 case V4L2_PIX_FMT_SGRBG8:
419 return MEDIA_BUS_FMT_SGRBG8_1X8;
420 case V4L2_PIX_FMT_SRGGB8:
421 return MEDIA_BUS_FMT_SRGGB8_1X8;
422 case V4L2_PIX_FMT_SBGGR10:
423 return MEDIA_BUS_FMT_SBGGR10_1X10;
424 case V4L2_PIX_FMT_SGBRG10:
425 return MEDIA_BUS_FMT_SGBRG10_1X10;
426 case V4L2_PIX_FMT_SGRBG10:
427 return MEDIA_BUS_FMT_SGRBG10_1X10;
428 case V4L2_PIX_FMT_SRGGB10:
429 return MEDIA_BUS_FMT_SRGGB10_1X10;
430 case V4L2_PIX_FMT_SBGGR12:
431 return MEDIA_BUS_FMT_SBGGR12_1X12;
432 case V4L2_PIX_FMT_SGBRG12:
433 return MEDIA_BUS_FMT_SGBRG12_1X12;
434 case V4L2_PIX_FMT_SGRBG12:
435 return MEDIA_BUS_FMT_SGRBG12_1X12;
436 case V4L2_PIX_FMT_SRGGB12:
437 return MEDIA_BUS_FMT_SRGGB12_1X12;
438 case V4L2_PIX_FMT_XBGR32:
439 return MEDIA_BUS_FMT_RGB888_1X24;
440 case V4L2_PIX_FMT_NV16M:
441 return MEDIA_BUS_FMT_YUYV12_1X24;
442 default:
443 return 0;
444 }
445 }
446
risp_core_try_next_job(struct rcar_isp_core * core)447 static void risp_core_try_next_job(struct rcar_isp_core *core)
448 {
449 lockdep_assert_held(&core->lock);
450
451 struct rcar_isp_job *job = core->vspx.job;
452
453 /* If the ISP or the VSPX is not done with the job, wait. */
454 if (!job || !job->done_isp || !job->done_vspx)
455 return;
456
457 core->vspx.job = NULL;
458 kfree(job);
459
460 core->sequence++;
461
462 /* Kickoff processing of next frame (if any). */
463 risp_core_job_run(core);
464 }
465
risp_core_vspx_frame_end(void * data)466 static void risp_core_vspx_frame_end(void *data)
467 {
468 struct rcar_isp_core *core = data;
469
470 guard(spinlock_irqsave)(&core->lock);
471
472 /*
473 * In tear-down the ISP may report a frame end event but we have already
474 * freed the job. It is safe to ignore the end of frame event.
475 */
476 if (!core->vspx.job)
477 return;
478
479 core->vspx.job->done_vspx = true;
480 risp_core_try_next_job(core);
481 }
482
risp_core_power_on(struct rcar_isp_core * core)483 static int risp_core_power_on(struct rcar_isp_core *core)
484 {
485 int ret;
486
487 ret = pm_runtime_resume_and_get(core->dev);
488 if (ret < 0)
489 return ret;
490
491 ret = reset_control_deassert(core->csrstc);
492 if (ret)
493 goto err_pm;
494
495 ret = clk_prepare_enable(core->clk);
496 if (ret)
497 goto err_csrstc;
498
499 return 0;
500
501 err_csrstc:
502 reset_control_assert(core->csrstc);
503 err_pm:
504 pm_runtime_put(core->dev);
505
506 return ret;
507 }
508
risp_core_power_off(struct rcar_isp_core * core)509 static void risp_core_power_off(struct rcar_isp_core *core)
510 {
511 clk_disable_unprepare(core->clk);
512
513 reset_control_assert(core->csrstc);
514
515 pm_runtime_put(core->dev);
516 }
517
risp_core_start_streaming(struct rcar_isp_core * core)518 int risp_core_start_streaming(struct rcar_isp_core *core)
519 {
520 struct vsp1_vspx_frame_end vspx_fe = {
521 .vspx_frame_end = risp_core_vspx_frame_end,
522 .frame_end_data = core,
523 };
524
525 struct v4l2_mbus_framefmt inputfmt = {
526 .width = core->io[RISP_CORE_INPUT1].format.fmt.pix_mp.width,
527 .height = core->io[RISP_CORE_INPUT1].format.fmt.pix_mp.height,
528 .code = risp_core_pix2bus(&core->io[RISP_CORE_INPUT1]),
529 .field = V4L2_FIELD_NONE,
530 .colorspace = V4L2_COLORSPACE_RAW,
531 .ycbcr_enc = V4L2_YCBCR_ENC_601,
532 .quantization = V4L2_QUANTIZATION_FULL_RANGE,
533 .xfer_func = V4L2_XFER_FUNC_NONE,
534 };
535
536 struct v4l2_mbus_framefmt hvout = {
537 .width = core->io[RISP_CORE_OUTPUT1].format.fmt.pix_mp.width,
538 .height = core->io[RISP_CORE_OUTPUT1].format.fmt.pix_mp.height,
539 .code = risp_core_pix2bus(&core->io[RISP_CORE_OUTPUT1]),
540 .field = V4L2_FIELD_NONE,
541 .colorspace = V4L2_COLORSPACE_SRGB,
542 .ycbcr_enc = V4L2_YCBCR_ENC_601,
543 .quantization =
544 core->io[RISP_CORE_OUTPUT1].format.fmt.pix_mp.pixelformat ==
545 V4L2_PIX_FMT_XBGR32 ?
546 V4L2_QUANTIZATION_FULL_RANGE :
547 V4L2_QUANTIZATION_LIM_RANGE,
548 .xfer_func = V4L2_XFER_FUNC_SRGB,
549 };
550 int ret;
551
552 scoped_guard(mutex, &core->io_lock) {
553 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
554 if (!core->io[i].streaming)
555 return 0;
556 }
557
558 /*
559 * The state core->streaming is protected by core->lock, which
560 * is not held yet. It is however safe to read it here since
561 * core->io_lock is held both in risp_core_stop_streaming() and
562 * here, the only two places the variable is modified.
563 *
564 * With this small implied dependency on the two locks for write
565 * access, the interrupt handler can safely depend sole on the
566 * spinlock core->lock for read access to core->streaming.
567 *
568 * The gain is an interrupt handler which can hold the spinlock
569 * and a start/stop procedure which can reset the ISP using the
570 * reset_control_reset() API, The later which can not be called
571 * from a context that may sleep.
572 *
573 * All other locations core->streaming is read and _all_
574 * locations where it is written core->lock is held.
575 */
576 if (core->streaming)
577 return 0;
578
579 ret = risp_core_power_on(core);
580 if (ret)
581 return ret;
582
583 /* Reset and wait for ISP core to initialize itself. */
584 reset_control_reset(core->rstc);
585 usleep_range(2000, 4000);
586
587 scoped_guard(spinlock_irqsave, &core->lock) {
588 risp_core_write(core, ISP_CORE_ISPCORE_INT_ENABLE, 1);
589
590 /* Configure output DMA */
591 risp_core_config_output(core, 0,
592 &core->io[RISP_CORE_OUTPUT1].format.fmt.pix_mp);
593
594 risp_cs_write(core, ISP_CS_STREAMER_VBLANK_REG, inputfmt.width * 25);
595 risp_cs_write(core, ISP_CS_STREAMER_HBLANK_REG, 64);
596
597 /* Enable ISP Streaming bridge. */
598 risp_cs_write(core, ISP_CS_STREAMER_MODE_REG,
599 ISP_CS_STREAMER_MODE_STREAMER_EN);
600
601 /* Start RPP ISP */
602 ret = rppx1_start(core->rpp, &inputfmt, &hvout, NULL);
603 if (ret) {
604 risp_core_power_off(core);
605 return ret;
606 }
607
608 core->vspx.job = NULL;
609 core->sequence = 0;
610 core->streaming = true;
611 }
612
613 /* Start VSPX */
614 vsp1_isp_start_streaming(core->vspx.dev, &vspx_fe);
615
616 scoped_guard(spinlock_irqsave, &core->lock) {
617 risp_core_job_run(core);
618 }
619 }
620
621 return 0;
622 }
623
risp_core_stop_streaming(struct rcar_isp_core * core)624 void risp_core_stop_streaming(struct rcar_isp_core *core)
625 {
626 struct rcar_isp_job *job, *tmp;
627
628 /*
629 * This function releases buffers and jobs: make sure the queues mutex
630 * is held.
631 */
632 lockdep_assert_held(&core->io_lock);
633
634 scoped_guard(spinlock_irqsave, &core->lock) {
635 /* Stop is called by each vdev, only act on the first call. */
636 if (!core->streaming)
637 return;
638
639 /* Stop queueing jobs to VSPX. */
640 core->streaming = false;
641 }
642
643 /* Wait for active VSPX job to finish. */
644 for (unsigned int retry = 0; retry <= 10; retry++) {
645 if (!core->vspx.job)
646 break;
647
648 usleep_range(2000, 4000);
649 }
650
651 if (core->vspx.job)
652 dev_err(core->dev, "Failed to complete running job");
653
654 /* Free all buffers and switch off the hardware. */
655 scoped_guard(spinlock_irqsave, &core->lock) {
656 /* Free all jobs and buffers. */
657 list_for_each_entry_safe(job, tmp, &core->risp_jobs, job_queue) {
658 vsp1_isp_job_release(core->vspx.dev, &job->vspx_job);
659
660 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
661 struct risp_buffer *buf = job->buffers[i];
662
663 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
664 }
665
666 list_del(&job->job_queue);
667 kfree(job);
668 }
669
670 rppx1_stop(core->rpp);
671 risp_cs_write(core, ISP_CS_STREAMER_MODE_REG, 0);
672 risp_core_write(core, ISP_CORE_ISPCORE_INT_ENABLE, 0);
673 }
674
675 vsp1_isp_stop_streaming(core->vspx.dev);
676
677 risp_core_power_off(core);
678 }
679
risp_core_irq(int irq,void * data)680 static irqreturn_t risp_core_irq(int irq, void *data)
681 {
682 struct rcar_isp_core *core = data;
683 struct rcar_isp_job *job;
684 u32 status;
685
686 status = risp_core_read(core, ISP_CORE_ISPCORE_INT_STATUS);
687 if (!(status & BIT(0)))
688 return IRQ_NONE;
689
690 if (!rppx1_interrupt(core->rpp, &status))
691 return IRQ_HANDLED;
692
693 guard(spinlock_irqsave)(&core->lock);
694
695 job = core->vspx.job;
696 if (!job)
697 return IRQ_HANDLED;
698
699 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
700 struct risp_buffer *buf;
701
702 buf = job->buffers[i];
703
704 switch (i) {
705 case RISP_CORE_STATS:
706 rppx1_stats_fill_isr(core->rpp, status,
707 vb2_plane_vaddr(&buf->vb.vb2_buf, 0));
708 fallthrough;
709 case RISP_CORE_OUTPUT1:
710 case RISP_CORE_INPUT1:
711 buf->vb.sequence = core->sequence;
712 buf->vb.vb2_buf.timestamp = ktime_get_ns();
713 fallthrough;
714 case RISP_CORE_PARAMS:
715 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
716 break;
717 }
718 }
719
720 core->vspx.job->done_isp = true;
721 risp_core_try_next_job(core);
722
723 return IRQ_HANDLED;
724 }
725
726 static const struct v4l2_subdev_ops risp_core_subdev_ops = {
727 };
728
risp_core_create_subdev(struct rcar_isp_core * core)729 static int risp_core_create_subdev(struct rcar_isp_core *core)
730 {
731 struct v4l2_subdev *subdev = &core->subdev;
732 int ret;
733
734 subdev->owner = THIS_MODULE;
735 subdev->dev = core->dev;
736 v4l2_subdev_init(subdev, &risp_core_subdev_ops);
737 v4l2_set_subdevdata(subdev, core->dev);
738 snprintf(subdev->name, sizeof(subdev->name), "%s %s core",
739 KBUILD_MODNAME, dev_name(core->dev));
740 subdev->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
741
742 subdev->entity.function = MEDIA_ENT_F_VID_MUX;
743
744 core->pads[RISP_CORE_INPUT1].flags = MEDIA_PAD_FL_SINK;
745 core->pads[RISP_CORE_PARAMS].flags = MEDIA_PAD_FL_SINK;
746 core->pads[RISP_CORE_STATS].flags = MEDIA_PAD_FL_SOURCE;
747 core->pads[RISP_CORE_OUTPUT1].flags = MEDIA_PAD_FL_SOURCE;
748
749 ret = media_entity_pads_init(&subdev->entity, RISP_CORE_NUM_PADS,
750 core->pads);
751 if (ret)
752 return ret;
753
754 return 0;
755 }
756
risp_core_registered(struct rcar_isp_core * core,struct v4l2_subdev * sd)757 int risp_core_registered(struct rcar_isp_core *core, struct v4l2_subdev *sd)
758 {
759 int ret;
760
761 core->v4l2_dev.mdev = sd->v4l2_dev->mdev;
762
763 /* Register ISP Core subdevice. */
764 ret = v4l2_device_register_subdev(&core->v4l2_dev, &core->subdev);
765 if (ret)
766 return ret;
767
768 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++) {
769 ret = risp_core_io_create(core->dev, core, &core->io[i], i);
770 if (ret) {
771 /* It is safe to destroy io node that is not created. */
772 for (unsigned int n = 0; n < RISP_CORE_NUM_PADS; n++)
773 risp_core_io_destroy(&core->io[n]);
774
775 v4l2_device_unregister_subdev(&core->subdev);
776
777 return ret;
778 }
779 }
780
781 return 0;
782 }
783
risp_core_probe_resources(struct rcar_isp_core * core,struct platform_device * pdev)784 static int risp_core_probe_resources(struct rcar_isp_core *core,
785 struct platform_device *pdev)
786 {
787 struct platform_device *vspx;
788 struct device_node *of_vspx;
789 struct resource *res;
790 int ret;
791
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
793 if (!res)
794 return -ENODEV;
795
796 core->rppaddr = res->start;
797 core->base = devm_ioremap_resource(&pdev->dev, res);
798 if (IS_ERR(core->base))
799 return PTR_ERR(core->base);
800
801 ret = platform_get_irq_byname(pdev, "core");
802 if (ret < 0)
803 return -ENODEV;
804
805 ret = devm_request_irq(&pdev->dev, ret, risp_core_irq, IRQF_SHARED,
806 KBUILD_MODNAME, core);
807 if (ret)
808 return ret;
809
810 core->clk = devm_clk_get(&pdev->dev, "core");
811 if (IS_ERR(core->clk))
812 return -ENODEV;
813
814 core->rstc = devm_reset_control_get(&pdev->dev, "core");
815 if (IS_ERR(core->rstc))
816 return -ENODEV;
817
818 of_vspx = of_parse_phandle(pdev->dev.of_node, "renesas,vspx", 0);
819 if (!of_vspx)
820 return -ENODEV;
821
822 vspx = of_find_device_by_node(of_vspx);
823 of_node_put(of_vspx);
824 if (!vspx)
825 return -ENODEV;
826
827 /* Attach to VSP-X */
828 core->vspx.dev = &vspx->dev;
829
830 ret = vsp1_isp_init(&vspx->dev);
831 if (ret < 0)
832 goto err_put_vspx;
833
834 /* Attach to the RPP library
835 *
836 * 1. Start and wait for the ISP to startup.
837 * 2. Attach the RPP library and talk with the RPP ISP.
838 * 3. Turn off ISP.
839 * 4. Fail if the RPP is unhappy with the hardware.
840 */
841 ret = clk_prepare_enable(core->clk);
842 if (ret)
843 goto err_put_vspx;
844
845 usleep_range(2000, 4000);
846
847 core->rpp = rppx1_create(core->base, &pdev->dev);
848
849 clk_disable_unprepare(core->clk);
850
851 if (!core->rpp) {
852 ret = -ENODEV;
853 goto err_put_vspx;
854 }
855
856 return 0;
857
858 err_put_vspx:
859 put_device(&vspx->dev);
860 return ret;
861 }
862
risp_core_probe(struct rcar_isp_core * core,struct platform_device * pdev,void __iomem * csbase,struct reset_control * csrstc)863 int risp_core_probe(struct rcar_isp_core *core, struct platform_device *pdev,
864 void __iomem *csbase, struct reset_control *csrstc)
865 {
866 int ret;
867
868 core->dev = &pdev->dev;
869 core->csrstc = csrstc;
870 core->csbase = csbase;
871
872 ret = risp_core_probe_resources(core, pdev);
873 if (ret) {
874 core->base = NULL;
875 return ret;
876 }
877
878 ret = v4l2_device_register(core->dev, &core->v4l2_dev);
879 if (ret)
880 goto err_destroy_rpp;
881
882 ret = risp_core_create_subdev(core);
883 if (ret)
884 goto err_unregister_v4l2;
885
886 mutex_init(&core->io_lock);
887 spin_lock_init(&core->lock);
888 INIT_LIST_HEAD(&core->risp_jobs);
889
890 return 0;
891
892 err_unregister_v4l2:
893 v4l2_device_unregister(&core->v4l2_dev);
894 err_destroy_rpp:
895 rppx1_destroy(core->rpp);
896 put_device(core->vspx.dev);
897 return ret;
898 }
899
risp_core_remove(struct rcar_isp_core * core)900 void risp_core_remove(struct rcar_isp_core *core)
901 {
902 /* If we did not probe the ISP core, nothing to do. */
903 if (!core->base)
904 return;
905
906 dev_info(core->dev, "Remove ISP Core\n");
907
908 for (unsigned int i = 0; i < RISP_CORE_NUM_PADS; i++)
909 risp_core_io_destroy(&core->io[i]);
910
911 v4l2_device_unregister(&core->v4l2_dev);
912
913 mutex_destroy(&core->io_lock);
914 rppx1_destroy(core->rpp);
915 put_device(core->vspx.dev);
916 }
917