1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/acpi.h> 15 #include <linux/arm-smccc.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/clkdev.h> 19 #include <linux/clk/clk-conf.h> 20 #include <linux/clk/tegra.h> 21 #include <linux/debugfs.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/err.h> 25 #include <linux/export.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/iopoll.h> 30 #include <linux/irqdomain.h> 31 #include <linux/irq.h> 32 #include <linux/irq_work.h> 33 #include <linux/kernel.h> 34 #include <linux/of_address.h> 35 #include <linux/of_clk.h> 36 #include <linux/of.h> 37 #include <linux/of_irq.h> 38 #include <linux/of_platform.h> 39 #include <linux/pinctrl/pinconf-generic.h> 40 #include <linux/pinctrl/pinconf.h> 41 #include <linux/pinctrl/pinctrl.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_domain.h> 44 #include <linux/pm_opp.h> 45 #include <linux/power_supply.h> 46 #include <linux/reboot.h> 47 #include <linux/regmap.h> 48 #include <linux/reset.h> 49 #include <linux/seq_file.h> 50 #include <linux/slab.h> 51 #include <linux/spinlock.h> 52 #include <linux/string_choices.h> 53 #include <linux/syscore_ops.h> 54 55 #include <soc/tegra/common.h> 56 #include <soc/tegra/fuse.h> 57 #include <soc/tegra/pmc.h> 58 59 #include <dt-bindings/interrupt-controller/arm-gic.h> 60 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 61 #include <dt-bindings/gpio/tegra186-gpio.h> 62 #include <dt-bindings/gpio/tegra194-gpio.h> 63 #include <dt-bindings/gpio/tegra234-gpio.h> 64 #include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 65 #include <dt-bindings/soc/tegra-pmc.h> 66 67 #define PMC_CNTRL 0x0 68 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 69 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 70 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 71 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 72 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 73 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 74 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 75 #define PMC_CNTRL_BLINK_EN 7 76 #define PMC_CNTRL_MAIN_RST BIT(4) 77 78 #define PMC_WAKE_MASK 0x0c 79 #define PMC_WAKE_LEVEL 0x10 80 #define PMC_WAKE_STATUS 0x14 81 #define PMC_SW_WAKE_STATUS 0x18 82 #define PMC_DPD_PADS_ORIDE 0x1c 83 #define PMC_DPD_PADS_ORIDE_BLINK 20 84 85 #define DPD_SAMPLE 0x020 86 #define DPD_SAMPLE_ENABLE BIT(0) 87 #define DPD_SAMPLE_DISABLE (0 << 0) 88 89 #define PWRGATE_TOGGLE 0x30 90 #define PWRGATE_TOGGLE_START BIT(8) 91 92 #define REMOVE_CLAMPING 0x34 93 94 #define PWRGATE_STATUS 0x38 95 96 #define PMC_BLINK_TIMER 0x40 97 #define PMC_IMPL_E_33V_PWR 0x40 98 99 #define PMC_PWR_DET 0x48 100 101 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 102 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 103 #define PMC_SCRATCH0_MODE_RCM BIT(1) 104 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 105 PMC_SCRATCH0_MODE_BOOTLOADER | \ 106 PMC_SCRATCH0_MODE_RCM) 107 108 #define PMC_CPUPWRGOOD_TIMER 0xc8 109 #define PMC_CPUPWROFF_TIMER 0xcc 110 #define PMC_COREPWRGOOD_TIMER 0x3c 111 #define PMC_COREPWROFF_TIMER 0xe0 112 113 #define PMC_PWR_DET_VALUE 0xe4 114 115 #define PMC_USB_DEBOUNCE_DEL 0xec 116 #define PMC_USB_AO 0xf0 117 118 #define PMC_SCRATCH37 0x130 119 #define PMC_SCRATCH41 0x140 120 121 #define PMC_WAKE2_MASK 0x160 122 #define PMC_WAKE2_LEVEL 0x164 123 #define PMC_WAKE2_STATUS 0x168 124 #define PMC_SW_WAKE2_STATUS 0x16c 125 126 #define PMC_CLK_OUT_CNTRL 0x1a8 127 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 128 #define PMC_SENSOR_CTRL 0x1b0 129 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 130 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 131 132 #define PMC_RST_STATUS_POR 0 133 #define PMC_RST_STATUS_WATCHDOG 1 134 #define PMC_RST_STATUS_SENSOR 2 135 #define PMC_RST_STATUS_SW_MAIN 3 136 #define PMC_RST_STATUS_LP0 4 137 #define PMC_RST_STATUS_AOTAG 5 138 139 #define IO_DPD_REQ 0x1b8 140 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 141 #define IO_DPD_REQ_CODE_OFF (1U << 30) 142 #define IO_DPD_REQ_CODE_ON (2U << 30) 143 #define IO_DPD_REQ_CODE_MASK (3U << 30) 144 145 #define IO_DPD_STATUS 0x1bc 146 #define IO_DPD2_REQ 0x1c0 147 #define IO_DPD2_STATUS 0x1c4 148 #define SEL_DPD_TIM 0x1c8 149 150 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 151 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 152 153 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 154 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 155 #define PMC_UTMIP_UHSIC_FAKE 0x218 156 157 #define PMC_SCRATCH54 0x258 158 #define PMC_SCRATCH54_DATA_SHIFT 8 159 #define PMC_SCRATCH54_ADDR_SHIFT 0 160 161 #define PMC_SCRATCH55 0x25c 162 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 163 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 164 #define PMC_SCRATCH55_PINMUX_SHIFT 24 165 #define PMC_SCRATCH55_16BITOP BIT(15) 166 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 167 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 168 169 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 170 171 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 172 #define PMC_UTMIP_MASTER_CONFIG 0x274 173 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 174 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 175 176 #define GPU_RG_CNTRL 0x2d4 177 178 #define PMC_UTMIP_PAD_CFG0 0x4c0 179 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 180 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 181 /* Tegra186 and later */ 182 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 183 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 184 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 185 #define WAKE_AOWAKE_MASK_W(_pmc, x) \ 186 ((_pmc)->soc->regs->aowake_mask_w + ((x) << 2)) 187 #define WAKE_AOWAKE_STATUS_W(_pmc, x) \ 188 ((_pmc)->soc->regs->aowake_status_w + ((x) << 2)) 189 #define WAKE_AOWAKE_STATUS_R(_pmc, x) \ 190 ((_pmc)->soc->regs->aowake_status_r + ((x) << 2)) 191 #define WAKE_AOWAKE_TIER2_ROUTING(_pmc, x) \ 192 ((_pmc)->soc->regs->aowake_tier2_routing + ((x) << 2)) 193 #define WAKE_AOWAKE_SW_STATUS(_pmc, x) \ 194 ((_pmc)->soc->regs->aowake_sw_status + ((x) << 2)) 195 196 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 197 198 #define SW_WAKE_ID 83 /* wake83 */ 199 200 /* for secure PMC */ 201 #define TEGRA_SMC_PMC 0xc2fffe00 202 #define TEGRA_SMC_PMC_READ 0xaa 203 #define TEGRA_SMC_PMC_WRITE 0xbb 204 205 /* Tegra264 and later */ 206 #define PMC_IMPL_SDMMC1_HV_PADCTL_0 0x41004 207 208 struct pmc_clk { 209 struct clk_hw hw; 210 struct tegra_pmc *pmc; 211 unsigned long offs; 212 u32 mux_shift; 213 u32 force_en_shift; 214 }; 215 216 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 217 218 struct pmc_clk_gate { 219 struct clk_hw hw; 220 struct tegra_pmc *pmc; 221 unsigned long offs; 222 u32 shift; 223 }; 224 225 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 226 227 struct pmc_clk_init_data { 228 char *name; 229 const char *const *parents; 230 int num_parents; 231 int clk_id; 232 u8 mux_shift; 233 u8 force_en_shift; 234 }; 235 236 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 237 "osc_div4", "extern1", 238 }; 239 240 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 241 "osc_div4", "extern2", 242 }; 243 244 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 245 "osc_div4", "extern3", 246 }; 247 248 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 249 { 250 .name = "pmc_clk_out_1", 251 .parents = clk_out1_parents, 252 .num_parents = ARRAY_SIZE(clk_out1_parents), 253 .clk_id = TEGRA_PMC_CLK_OUT_1, 254 .mux_shift = 6, 255 .force_en_shift = 2, 256 }, 257 { 258 .name = "pmc_clk_out_2", 259 .parents = clk_out2_parents, 260 .num_parents = ARRAY_SIZE(clk_out2_parents), 261 .clk_id = TEGRA_PMC_CLK_OUT_2, 262 .mux_shift = 14, 263 .force_en_shift = 10, 264 }, 265 { 266 .name = "pmc_clk_out_3", 267 .parents = clk_out3_parents, 268 .num_parents = ARRAY_SIZE(clk_out3_parents), 269 .clk_id = TEGRA_PMC_CLK_OUT_3, 270 .mux_shift = 22, 271 .force_en_shift = 18, 272 }, 273 }; 274 275 struct tegra_pmc_core_pd { 276 struct generic_pm_domain genpd; 277 struct tegra_pmc *pmc; 278 }; 279 280 static inline struct tegra_pmc_core_pd * 281 to_core_pd(struct generic_pm_domain *genpd) 282 { 283 return container_of(genpd, struct tegra_pmc_core_pd, genpd); 284 } 285 286 struct tegra_powergate { 287 struct generic_pm_domain genpd; 288 struct tegra_pmc *pmc; 289 unsigned int id; 290 struct clk **clks; 291 unsigned int num_clks; 292 unsigned long *clk_rates; 293 struct reset_control *reset; 294 }; 295 296 struct tegra_io_pad_soc { 297 enum tegra_io_pad id; 298 unsigned int dpd; 299 unsigned int request; 300 unsigned int status; 301 const char *name; 302 }; 303 304 struct tegra_io_pad_vctrl { 305 enum tegra_io_pad id; 306 unsigned int offset; 307 unsigned int ena_3v3; 308 unsigned int ena_1v8; 309 }; 310 311 struct tegra_pmc_regs { 312 unsigned int scratch0; 313 unsigned int rst_status; 314 unsigned int rst_source_shift; 315 unsigned int rst_source_mask; 316 unsigned int rst_level_shift; 317 unsigned int rst_level_mask; 318 unsigned int aowake_mask_w; 319 unsigned int aowake_status_w; 320 unsigned int aowake_status_r; 321 unsigned int aowake_tier2_routing; 322 unsigned int aowake_sw_status_w; 323 unsigned int aowake_sw_status; 324 unsigned int aowake_latch_sw; 325 unsigned int aowake_ctrl; 326 }; 327 328 struct tegra_wake_event { 329 const char *name; 330 unsigned int id; 331 unsigned int irq; 332 struct { 333 unsigned int instance; 334 unsigned int pin; 335 } gpio; 336 }; 337 338 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 339 { \ 340 .name = _name, \ 341 .id = _id, \ 342 .irq = 0, \ 343 .gpio = { \ 344 .instance = UINT_MAX, \ 345 .pin = UINT_MAX, \ 346 }, \ 347 } 348 349 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 350 { \ 351 .name = _name, \ 352 .id = _id, \ 353 .irq = _irq, \ 354 .gpio = { \ 355 .instance = UINT_MAX, \ 356 .pin = UINT_MAX, \ 357 }, \ 358 } 359 360 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 361 { \ 362 .name = _name, \ 363 .id = _id, \ 364 .irq = 0, \ 365 .gpio = { \ 366 .instance = _instance, \ 367 .pin = _pin, \ 368 }, \ 369 } 370 371 struct tegra_pmc_soc { 372 unsigned int num_powergates; 373 const char *const *powergates; 374 unsigned int num_cpu_powergates; 375 const u8 *cpu_powergates; 376 377 bool has_tsense_reset; 378 bool has_gpu_clamps; 379 bool needs_mbist_war; 380 bool has_io_pad_wren; 381 bool maybe_tz_only; 382 383 const struct tegra_io_pad_soc *io_pads; 384 unsigned int num_io_pads; 385 const struct tegra_io_pad_vctrl *io_pad_vctrls; 386 unsigned int num_io_pad_vctrls; 387 388 const struct pinctrl_pin_desc *pin_descs; 389 unsigned int num_pin_descs; 390 391 const struct tegra_pmc_regs *regs; 392 void (*init)(struct tegra_pmc *pmc); 393 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 394 struct device_node *np); 395 void (*set_wake_filters)(struct tegra_pmc *pmc); 396 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 397 int (*irq_set_type)(struct irq_data *data, unsigned int type); 398 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 399 bool new_state); 400 401 const char * const *reset_sources; 402 unsigned int num_reset_sources; 403 const char * const *reset_levels; 404 unsigned int num_reset_levels; 405 406 /* 407 * These describe events that can wake the system from sleep (i.e. 408 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 409 * are dealt with in the LIC. 410 */ 411 const struct tegra_wake_event *wake_events; 412 unsigned int num_wake_events; 413 unsigned int max_wake_events; 414 unsigned int max_wake_vectors; 415 416 const struct pmc_clk_init_data *pmc_clks_data; 417 unsigned int num_pmc_clks; 418 bool has_blink_output; 419 bool has_usb_sleepwalk; 420 bool supports_core_domain; 421 bool has_single_mmio_aperture; 422 }; 423 424 /** 425 * struct tegra_pmc - NVIDIA Tegra PMC 426 * @dev: pointer to PMC device structure 427 * @base: pointer to I/O remapped register region 428 * @wake: pointer to I/O remapped region for WAKE registers 429 * @aotag: pointer to I/O remapped region for AOTAG registers 430 * @scratch: pointer to I/O remapped region for scratch registers 431 * @clk: pointer to pclk clock 432 * @soc: pointer to SoC data structure 433 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 434 * @rate: currently configured rate of pclk 435 * @suspend_mode: lowest suspend mode available 436 * @cpu_good_time: CPU power good time (in microseconds) 437 * @cpu_off_time: CPU power off time (in microsecends) 438 * @core_osc_time: core power good OSC time (in microseconds) 439 * @core_pmu_time: core power good PMU time (in microseconds) 440 * @core_off_time: core power off time (in microseconds) 441 * @corereq_high: core power request is active-high 442 * @sysclkreq_high: system clock request is active-high 443 * @combined_req: combined power request for CPU & core 444 * @cpu_pwr_good_en: CPU power good signal is enabled 445 * @lp0_vec_phys: physical base address of the LP0 warm boot code 446 * @lp0_vec_size: size of the LP0 warm boot code 447 * @invert_irq: polarity of the PMU IRQ is inverted 448 * @powergates_available: Bitmap of available power gates 449 * @powergates_lock: mutex for power gate register access 450 * @pctl_dev: pin controller exposed by the PMC 451 * @domain: IRQ domain provided by the PMC 452 * @irq: chip implementation for the IRQ domain 453 * @clk_nb: pclk clock changes handler 454 * @core_domain_state_synced: flag marking the core domain's state as synced 455 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 456 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 457 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 458 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 459 * cntrl register associated with each wake during system suspend. 460 * @reboot_notifier: PMC reboot notifier handler 461 * @syscore: syscore suspend/resume callbacks 462 * @wake_work: IRQ work handler for processing wake-up events. 463 * @wake_status: Status of wake-up events. 464 */ 465 struct tegra_pmc { 466 struct device *dev; 467 void __iomem *base; 468 void __iomem *wake; 469 void __iomem *aotag; 470 void __iomem *scratch; 471 struct clk *clk; 472 473 const struct tegra_pmc_soc *soc; 474 bool tz_only; 475 476 unsigned long rate; 477 478 enum tegra_suspend_mode suspend_mode; 479 u32 cpu_good_time; 480 u32 cpu_off_time; 481 u32 core_osc_time; 482 u32 core_pmu_time; 483 u32 core_off_time; 484 bool corereq_high; 485 bool sysclkreq_high; 486 bool combined_req; 487 bool cpu_pwr_good_en; 488 u32 lp0_vec_phys; 489 u32 lp0_vec_size; 490 bool invert_irq; 491 492 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 493 494 struct mutex powergates_lock; 495 496 struct pinctrl_dev *pctl_dev; 497 498 struct irq_domain *domain; 499 struct irq_chip irq; 500 501 struct notifier_block clk_nb; 502 503 bool core_domain_state_synced; 504 505 unsigned long *wake_type_level_map; 506 unsigned long *wake_type_dual_edge_map; 507 unsigned long *wake_sw_status_map; 508 unsigned long *wake_cntrl_level_map; 509 510 struct notifier_block reboot_notifier; 511 struct syscore syscore; 512 513 /* Pending wake IRQ processing */ 514 struct irq_work wake_work; 515 u32 *wake_status; 516 }; 517 518 #if defined(CONFIG_ARM) 519 static struct tegra_pmc *early_pmc = &(struct tegra_pmc) { 520 .base = NULL, 521 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 522 }; 523 #endif 524 525 static inline struct tegra_powergate * 526 to_powergate(struct generic_pm_domain *domain) 527 { 528 return container_of(domain, struct tegra_powergate, genpd); 529 } 530 531 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 532 { 533 struct arm_smccc_res res; 534 535 if (pmc->tz_only) { 536 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 537 0, 0, 0, &res); 538 if (res.a0) { 539 if (pmc->dev) 540 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 541 __func__, res.a0); 542 else 543 pr_warn("%s(): SMC failed: %lu\n", __func__, 544 res.a0); 545 } 546 547 return res.a1; 548 } 549 550 return readl(pmc->base + offset); 551 } 552 553 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 554 unsigned long offset) 555 { 556 struct arm_smccc_res res; 557 558 if (pmc->tz_only) { 559 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 560 value, 0, 0, 0, 0, &res); 561 if (res.a0) { 562 if (pmc->dev) 563 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 564 __func__, res.a0); 565 else 566 pr_warn("%s(): SMC failed: %lu\n", __func__, 567 res.a0); 568 } 569 } else { 570 writel(value, pmc->base + offset); 571 } 572 } 573 574 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 575 { 576 if (pmc->tz_only) 577 return tegra_pmc_readl(pmc, offset); 578 579 return readl(pmc->scratch + offset); 580 } 581 582 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 583 unsigned long offset) 584 { 585 if (pmc->tz_only) 586 tegra_pmc_writel(pmc, value, offset); 587 else 588 writel(value, pmc->scratch + offset); 589 } 590 591 static inline bool tegra_powergate_state(struct tegra_pmc *pmc, int id) 592 { 593 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 594 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 595 else 596 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 597 } 598 599 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 600 { 601 return (pmc->soc && pmc->soc->powergates[id]); 602 } 603 604 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 605 { 606 return test_bit(id, pmc->powergates_available); 607 } 608 609 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 610 { 611 unsigned int i; 612 613 if (!pmc || !pmc->soc || !name) 614 return -EINVAL; 615 616 for (i = 0; i < pmc->soc->num_powergates; i++) { 617 if (!tegra_powergate_is_valid(pmc, i)) 618 continue; 619 620 if (!strcmp(name, pmc->soc->powergates[i])) 621 return i; 622 } 623 624 return -ENODEV; 625 } 626 627 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 628 bool new_state) 629 { 630 unsigned int retries = 100; 631 bool status; 632 int ret; 633 634 /* 635 * As per TRM documentation, the toggle command will be dropped by PMC 636 * if there is contention with a HW-initiated toggling (i.e. CPU core 637 * power-gated), the command should be retried in that case. 638 */ 639 do { 640 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 641 642 /* wait for PMC to execute the command */ 643 ret = read_poll_timeout(tegra_powergate_state, status, 644 status == new_state, 1, 10, false, 645 pmc, id); 646 } while (ret == -ETIMEDOUT && retries--); 647 648 return ret; 649 } 650 651 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 652 { 653 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 654 } 655 656 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 657 bool new_state) 658 { 659 bool status; 660 int err; 661 662 /* wait while PMC power gating is contended */ 663 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 664 status == true, 1, 100); 665 if (err) 666 return err; 667 668 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 669 670 /* wait for PMC to accept the command */ 671 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 672 status == true, 1, 100); 673 if (err) 674 return err; 675 676 /* wait for PMC to execute the command */ 677 err = read_poll_timeout(tegra_powergate_state, status, 678 status == new_state, 10, 100000, false, 679 pmc, id); 680 if (err) 681 return err; 682 683 return 0; 684 } 685 686 /** 687 * tegra_powergate_set() - set the state of a partition 688 * @pmc: power management controller 689 * @id: partition ID 690 * @new_state: new state of the partition 691 */ 692 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 693 bool new_state) 694 { 695 int err; 696 697 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 698 return -EINVAL; 699 700 mutex_lock(&pmc->powergates_lock); 701 702 if (tegra_powergate_state(pmc, id) == new_state) { 703 mutex_unlock(&pmc->powergates_lock); 704 return 0; 705 } 706 707 err = pmc->soc->powergate_set(pmc, id, new_state); 708 709 mutex_unlock(&pmc->powergates_lock); 710 711 return err; 712 } 713 714 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 715 unsigned int id) 716 { 717 u32 mask; 718 719 mutex_lock(&pmc->powergates_lock); 720 721 /* 722 * On Tegra124 and later, the clamps for the GPU are controlled by a 723 * separate register (with different semantics). 724 */ 725 if (id == TEGRA_POWERGATE_3D) { 726 if (pmc->soc->has_gpu_clamps) { 727 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 728 goto out; 729 } 730 } 731 732 /* 733 * Tegra 2 has a bug where PCIE and VDE clamping masks are 734 * swapped relatively to the partition ids 735 */ 736 if (id == TEGRA_POWERGATE_VDEC) 737 mask = (1 << TEGRA_POWERGATE_PCIE); 738 else if (id == TEGRA_POWERGATE_PCIE) 739 mask = (1 << TEGRA_POWERGATE_VDEC); 740 else 741 mask = (1 << id); 742 743 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 744 745 out: 746 mutex_unlock(&pmc->powergates_lock); 747 748 return 0; 749 } 750 751 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 752 { 753 unsigned long safe_rate = 100 * 1000 * 1000; 754 unsigned int i; 755 int err; 756 757 for (i = 0; i < pg->num_clks; i++) { 758 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 759 760 if (!pg->clk_rates[i]) { 761 err = -EINVAL; 762 goto out; 763 } 764 765 if (pg->clk_rates[i] <= safe_rate) 766 continue; 767 768 /* 769 * We don't know whether voltage state is okay for the 770 * current clock rate, hence it's better to temporally 771 * switch clock to a safe rate which is suitable for 772 * all voltages, before enabling the clock. 773 */ 774 err = clk_set_rate(pg->clks[i], safe_rate); 775 if (err) 776 goto out; 777 } 778 779 return 0; 780 781 out: 782 while (i--) 783 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 784 785 return err; 786 } 787 788 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 789 { 790 unsigned int i; 791 int err; 792 793 for (i = 0; i < pg->num_clks; i++) { 794 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 795 if (err) 796 return err; 797 } 798 799 return 0; 800 } 801 802 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 803 { 804 unsigned int i; 805 806 for (i = 0; i < pg->num_clks; i++) 807 clk_disable_unprepare(pg->clks[i]); 808 } 809 810 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 811 { 812 unsigned int i; 813 int err; 814 815 for (i = 0; i < pg->num_clks; i++) { 816 err = clk_prepare_enable(pg->clks[i]); 817 if (err) 818 goto out; 819 } 820 821 return 0; 822 823 out: 824 while (i--) 825 clk_disable_unprepare(pg->clks[i]); 826 827 return err; 828 } 829 830 static int tegra_powergate_power_up(struct tegra_powergate *pg, 831 bool disable_clocks) 832 { 833 int err; 834 835 err = reset_control_assert(pg->reset); 836 if (err) 837 return err; 838 839 usleep_range(10, 20); 840 841 err = tegra_powergate_set(pg->pmc, pg->id, true); 842 if (err < 0) 843 return err; 844 845 usleep_range(10, 20); 846 847 err = tegra_powergate_prepare_clocks(pg); 848 if (err) 849 goto powergate_off; 850 851 err = tegra_powergate_enable_clocks(pg); 852 if (err) 853 goto unprepare_clks; 854 855 usleep_range(10, 20); 856 857 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 858 if (err) 859 goto disable_clks; 860 861 usleep_range(10, 20); 862 863 err = reset_control_deassert(pg->reset); 864 if (err) 865 goto disable_clks; 866 867 usleep_range(10, 20); 868 869 if (pg->pmc->soc->needs_mbist_war) 870 err = tegra210_clk_handle_mbist_war(pg->id); 871 if (err) 872 goto disable_clks; 873 874 if (disable_clocks) 875 tegra_powergate_disable_clocks(pg); 876 877 err = tegra_powergate_unprepare_clocks(pg); 878 if (err) 879 return err; 880 881 return 0; 882 883 disable_clks: 884 tegra_powergate_disable_clocks(pg); 885 usleep_range(10, 20); 886 887 unprepare_clks: 888 tegra_powergate_unprepare_clocks(pg); 889 890 powergate_off: 891 tegra_powergate_set(pg->pmc, pg->id, false); 892 893 return err; 894 } 895 896 static int tegra_powergate_power_down(struct tegra_powergate *pg) 897 { 898 int err; 899 900 err = tegra_powergate_prepare_clocks(pg); 901 if (err) 902 return err; 903 904 err = tegra_powergate_enable_clocks(pg); 905 if (err) 906 goto unprepare_clks; 907 908 usleep_range(10, 20); 909 910 err = reset_control_assert(pg->reset); 911 if (err) 912 goto disable_clks; 913 914 usleep_range(10, 20); 915 916 tegra_powergate_disable_clocks(pg); 917 918 usleep_range(10, 20); 919 920 err = tegra_powergate_set(pg->pmc, pg->id, false); 921 if (err) 922 goto assert_resets; 923 924 err = tegra_powergate_unprepare_clocks(pg); 925 if (err) 926 return err; 927 928 return 0; 929 930 assert_resets: 931 tegra_powergate_enable_clocks(pg); 932 usleep_range(10, 20); 933 reset_control_deassert(pg->reset); 934 usleep_range(10, 20); 935 936 disable_clks: 937 tegra_powergate_disable_clocks(pg); 938 939 unprepare_clks: 940 tegra_powergate_unprepare_clocks(pg); 941 942 return err; 943 } 944 945 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 946 { 947 struct tegra_powergate *pg = to_powergate(domain); 948 struct device *dev = pg->pmc->dev; 949 int err; 950 951 err = tegra_powergate_power_up(pg, true); 952 if (err) { 953 dev_err(dev, "failed to turn on PM domain %s: %d\n", 954 pg->genpd.name, err); 955 goto out; 956 } 957 958 reset_control_release(pg->reset); 959 960 out: 961 return err; 962 } 963 964 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 965 { 966 struct tegra_powergate *pg = to_powergate(domain); 967 struct device *dev = pg->pmc->dev; 968 int err; 969 970 err = reset_control_acquire(pg->reset); 971 if (err < 0) { 972 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 973 pg->genpd.name, err); 974 return err; 975 } 976 977 err = tegra_powergate_power_down(pg); 978 if (err) { 979 dev_err(dev, "failed to turn off PM domain %s: %d\n", 980 pg->genpd.name, err); 981 reset_control_release(pg->reset); 982 } 983 984 return err; 985 } 986 987 static void tegra_pmc_put_device(void *data) 988 { 989 struct tegra_pmc *pmc = data; 990 991 put_device(pmc->dev); 992 } 993 994 static const struct of_device_id tegra_pmc_match[]; 995 996 static struct tegra_pmc *tegra_pmc_get(struct device *dev) 997 { 998 struct platform_device *pdev; 999 struct device_node *np; 1000 struct tegra_pmc *pmc; 1001 1002 np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0); 1003 if (!np) { 1004 struct device_node *parent = of_node_get(dev->of_node); 1005 1006 while ((parent = of_get_next_parent(parent)) != NULL) { 1007 np = of_find_matching_node(parent, tegra_pmc_match); 1008 if (np) 1009 break; 1010 } 1011 1012 of_node_put(parent); 1013 1014 if (!np) 1015 return ERR_PTR(-ENODEV); 1016 } 1017 1018 pdev = of_find_device_by_node(np); 1019 of_node_put(np); 1020 1021 if (!pdev) 1022 return ERR_PTR(-ENODEV); 1023 1024 pmc = platform_get_drvdata(pdev); 1025 if (!pmc) { 1026 put_device(&pdev->dev); 1027 return ERR_PTR(-EPROBE_DEFER); 1028 } 1029 1030 return pmc; 1031 } 1032 1033 /** 1034 * devm_tegra_pmc_get() - find the PMC for a given device 1035 * @dev: device for which to find the PMC 1036 * 1037 * Returns a pointer to the PMC on success or an ERR_PTR()-encoded error code 1038 * otherwise. 1039 */ 1040 struct tegra_pmc *devm_tegra_pmc_get(struct device *dev) 1041 { 1042 struct tegra_pmc *pmc; 1043 int err; 1044 1045 pmc = tegra_pmc_get(dev); 1046 if (IS_ERR(pmc)) 1047 return pmc; 1048 1049 err = devm_add_action_or_reset(dev, tegra_pmc_put_device, pmc); 1050 if (err < 0) 1051 return ERR_PTR(err); 1052 1053 return pmc; 1054 } 1055 EXPORT_SYMBOL(devm_tegra_pmc_get); 1056 1057 /** 1058 * tegra_pmc_powergate_power_on() - power on partition 1059 * @pmc: power management controller 1060 * @id: partition ID 1061 */ 1062 int tegra_pmc_powergate_power_on(struct tegra_pmc *pmc, unsigned int id) 1063 { 1064 if (!tegra_powergate_is_available(pmc, id)) 1065 return -EINVAL; 1066 1067 return tegra_powergate_set(pmc, id, true); 1068 } 1069 EXPORT_SYMBOL(tegra_pmc_powergate_power_on); 1070 1071 /** 1072 * tegra_pmc_powergate_power_off() - power off partition 1073 * @pmc: power management controller 1074 * @id: partition ID 1075 */ 1076 int tegra_pmc_powergate_power_off(struct tegra_pmc *pmc, unsigned int id) 1077 { 1078 if (!tegra_powergate_is_available(pmc, id)) 1079 return -EINVAL; 1080 1081 return tegra_powergate_set(pmc, id, false); 1082 } 1083 EXPORT_SYMBOL(tegra_pmc_powergate_power_off); 1084 1085 /** 1086 * tegra_powergate_is_powered() - check if partition is powered 1087 * @pmc: power management controller 1088 * @id: partition ID 1089 */ 1090 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 1091 { 1092 if (!tegra_powergate_is_valid(pmc, id)) 1093 return -EINVAL; 1094 1095 return tegra_powergate_state(pmc, id); 1096 } 1097 1098 /** 1099 * tegra_pmc_powergate_remove_clamping() - remove power clamps for partition 1100 * @pmc: power management controller 1101 * @id: partition ID 1102 */ 1103 int tegra_pmc_powergate_remove_clamping(struct tegra_pmc *pmc, unsigned int id) 1104 { 1105 if (!tegra_powergate_is_available(pmc, id)) 1106 return -EINVAL; 1107 1108 return __tegra_powergate_remove_clamping(pmc, id); 1109 } 1110 EXPORT_SYMBOL(tegra_pmc_powergate_remove_clamping); 1111 1112 /** 1113 * tegra_pmc_powergate_sequence_power_up() - power up partition 1114 * @pmc: power management controller 1115 * @id: partition ID 1116 * @clk: clock for partition 1117 * @rst: reset for partition 1118 * 1119 * Must be called with clk disabled, and returns with clk enabled. 1120 */ 1121 int tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc, 1122 unsigned int id, struct clk *clk, 1123 struct reset_control *rst) 1124 { 1125 struct tegra_powergate *pg; 1126 int err; 1127 1128 if (!tegra_powergate_is_available(pmc, id)) 1129 return -EINVAL; 1130 1131 pg = kzalloc_obj(*pg); 1132 if (!pg) 1133 return -ENOMEM; 1134 1135 pg->clk_rates = kzalloc_obj(*pg->clk_rates); 1136 if (!pg->clk_rates) { 1137 kfree(pg->clks); 1138 return -ENOMEM; 1139 } 1140 1141 pg->id = id; 1142 pg->clks = &clk; 1143 pg->num_clks = 1; 1144 pg->reset = rst; 1145 pg->pmc = pmc; 1146 1147 err = tegra_powergate_power_up(pg, false); 1148 if (err) 1149 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1150 err); 1151 1152 kfree(pg->clk_rates); 1153 kfree(pg); 1154 1155 return err; 1156 } 1157 EXPORT_SYMBOL(tegra_pmc_powergate_sequence_power_up); 1158 1159 static void tegra_pmc_program_reboot_reason(struct tegra_pmc *pmc, 1160 const char *cmd) 1161 { 1162 u32 value; 1163 1164 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1165 value &= ~PMC_SCRATCH0_MODE_MASK; 1166 1167 if (cmd) { 1168 if (strcmp(cmd, "recovery") == 0) 1169 value |= PMC_SCRATCH0_MODE_RECOVERY; 1170 1171 if (strcmp(cmd, "bootloader") == 0) 1172 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1173 1174 if (strcmp(cmd, "forced-recovery") == 0) 1175 value |= PMC_SCRATCH0_MODE_RCM; 1176 } 1177 1178 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1179 } 1180 1181 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1182 unsigned long action, void *data) 1183 { 1184 struct tegra_pmc *pmc = container_of(this, struct tegra_pmc, 1185 reboot_notifier); 1186 if (action == SYS_RESTART) 1187 tegra_pmc_program_reboot_reason(pmc, data); 1188 1189 return NOTIFY_DONE; 1190 } 1191 1192 static void tegra_pmc_restart(struct tegra_pmc *pmc) 1193 { 1194 u32 value; 1195 1196 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1197 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1198 value |= PMC_CNTRL_MAIN_RST; 1199 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1200 } 1201 1202 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1203 { 1204 struct tegra_pmc *pmc = data->cb_data; 1205 1206 tegra_pmc_restart(pmc); 1207 1208 return NOTIFY_DONE; 1209 } 1210 1211 static int tegra_pmc_grouper_power_off_handler(struct sys_off_data *data) 1212 { 1213 struct tegra_pmc *pmc = data->cb_data; 1214 1215 /* 1216 * Reboot Nexus 7 into special bootloader mode if USB cable is 1217 * connected in order to display battery status and power off. 1218 */ 1219 if (power_supply_is_system_supplied()) { 1220 const u32 go_to_charger_mode = 0xa5a55a5a; 1221 1222 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1223 tegra_pmc_restart(pmc); 1224 } 1225 1226 return NOTIFY_DONE; 1227 } 1228 1229 static int powergate_show(struct seq_file *s, void *data) 1230 { 1231 struct tegra_pmc *pmc = data; 1232 unsigned int i; 1233 int status; 1234 1235 seq_printf(s, " powergate powered\n"); 1236 seq_printf(s, "------------------\n"); 1237 1238 for (i = 0; i < pmc->soc->num_powergates; i++) { 1239 status = tegra_powergate_is_powered(pmc, i); 1240 if (status < 0) 1241 continue; 1242 1243 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1244 str_yes_no(status)); 1245 } 1246 1247 return 0; 1248 } 1249 1250 DEFINE_SHOW_ATTRIBUTE(powergate); 1251 1252 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1253 struct device_node *np) 1254 { 1255 struct clk *clk; 1256 unsigned int i, count; 1257 int err; 1258 1259 count = of_clk_get_parent_count(np); 1260 if (count == 0) 1261 return -ENODEV; 1262 1263 pg->clks = kzalloc_objs(clk, count); 1264 if (!pg->clks) 1265 return -ENOMEM; 1266 1267 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1268 if (!pg->clk_rates) { 1269 kfree(pg->clks); 1270 return -ENOMEM; 1271 } 1272 1273 for (i = 0; i < count; i++) { 1274 pg->clks[i] = of_clk_get(np, i); 1275 if (IS_ERR(pg->clks[i])) { 1276 err = PTR_ERR(pg->clks[i]); 1277 goto err; 1278 } 1279 } 1280 1281 pg->num_clks = count; 1282 1283 return 0; 1284 1285 err: 1286 while (i--) 1287 clk_put(pg->clks[i]); 1288 1289 kfree(pg->clk_rates); 1290 kfree(pg->clks); 1291 1292 return err; 1293 } 1294 1295 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1296 struct device_node *np) 1297 { 1298 struct device *dev = pg->pmc->dev; 1299 int err; 1300 1301 pg->reset = of_reset_control_array_get_exclusive_released(np); 1302 if (IS_ERR(pg->reset)) { 1303 err = PTR_ERR(pg->reset); 1304 dev_err(dev, "failed to get device resets: %d\n", err); 1305 return err; 1306 } 1307 1308 err = reset_control_acquire(pg->reset); 1309 if (err < 0) { 1310 pr_err("failed to acquire resets: %d\n", err); 1311 reset_control_put(pg->reset); 1312 } 1313 1314 return err; 1315 } 1316 1317 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1318 { 1319 struct device *dev = pmc->dev; 1320 struct tegra_powergate *pg; 1321 int id, err = 0; 1322 bool off; 1323 1324 pg = kzalloc_obj(*pg); 1325 if (!pg) 1326 return -ENOMEM; 1327 1328 id = tegra_powergate_lookup(pmc, np->name); 1329 if (id < 0) { 1330 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1331 err = -ENODEV; 1332 goto free_mem; 1333 } 1334 1335 /* 1336 * Clear the bit for this powergate so it cannot be managed 1337 * directly via the legacy APIs for controlling powergates. 1338 */ 1339 clear_bit(id, pmc->powergates_available); 1340 1341 pg->id = id; 1342 pg->genpd.name = np->name; 1343 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1344 pg->genpd.power_off = tegra_genpd_power_off; 1345 pg->genpd.power_on = tegra_genpd_power_on; 1346 pg->pmc = pmc; 1347 1348 off = !tegra_powergate_is_powered(pmc, pg->id); 1349 1350 err = tegra_powergate_of_get_clks(pg, np); 1351 if (err < 0) { 1352 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1353 goto set_available; 1354 } 1355 1356 err = tegra_powergate_of_get_resets(pg, np); 1357 if (err < 0) { 1358 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1359 goto remove_clks; 1360 } 1361 1362 /* 1363 * If the power-domain is off, then ensure the resets are asserted. 1364 * If the power-domain is on, then power down to ensure that when is 1365 * it turned on the power-domain, clocks and resets are all in the 1366 * expected state. 1367 */ 1368 if (off) { 1369 err = reset_control_assert(pg->reset); 1370 if (err) { 1371 pr_err("failed to assert resets: %d\n", err); 1372 goto remove_resets; 1373 } 1374 } else { 1375 err = tegra_powergate_power_down(pg); 1376 if (err) { 1377 dev_err(dev, "failed to turn off PM domain %s: %d\n", 1378 pg->genpd.name, err); 1379 goto remove_resets; 1380 } 1381 } 1382 1383 /* 1384 * If PM_GENERIC_DOMAINS is not enabled, power-on 1385 * the domain and skip the genpd registration. 1386 */ 1387 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1388 WARN_ON(tegra_powergate_power_up(pg, true)); 1389 goto remove_resets; 1390 } 1391 1392 err = pm_genpd_init(&pg->genpd, NULL, true); 1393 if (err < 0) { 1394 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1395 err); 1396 goto remove_resets; 1397 } 1398 1399 err = of_genpd_add_provider_simple(np, &pg->genpd); 1400 if (err < 0) { 1401 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1402 np, err); 1403 goto remove_genpd; 1404 } 1405 1406 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1407 1408 return 0; 1409 1410 remove_genpd: 1411 pm_genpd_remove(&pg->genpd); 1412 1413 remove_resets: 1414 reset_control_put(pg->reset); 1415 1416 remove_clks: 1417 while (pg->num_clks--) 1418 clk_put(pg->clks[pg->num_clks]); 1419 1420 kfree(pg->clks); 1421 1422 set_available: 1423 set_bit(id, pmc->powergates_available); 1424 1425 free_mem: 1426 kfree(pg); 1427 1428 return err; 1429 } 1430 1431 static int 1432 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1433 unsigned int level) 1434 { 1435 struct tegra_pmc_core_pd *pd = to_core_pd(genpd); 1436 struct tegra_pmc *pmc = pd->pmc; 1437 struct dev_pm_opp *opp; 1438 int err; 1439 1440 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1441 if (IS_ERR(opp)) { 1442 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1443 level, opp); 1444 return PTR_ERR(opp); 1445 } 1446 1447 mutex_lock(&pmc->powergates_lock); 1448 err = dev_pm_opp_set_opp(pmc->dev, opp); 1449 mutex_unlock(&pmc->powergates_lock); 1450 1451 dev_pm_opp_put(opp); 1452 1453 if (err) { 1454 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1455 level, err); 1456 return err; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1463 { 1464 const char *rname[] = { "core", NULL}; 1465 struct tegra_pmc_core_pd *pd; 1466 int err; 1467 1468 pd = devm_kzalloc(pmc->dev, sizeof(*pd), GFP_KERNEL); 1469 if (!pd) 1470 return -ENOMEM; 1471 1472 pd->genpd.name = "core"; 1473 pd->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1474 pd->genpd.set_performance_state = tegra_pmc_core_pd_set_performance_state; 1475 pd->pmc = pmc; 1476 1477 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1478 if (err) 1479 return dev_err_probe(pmc->dev, err, 1480 "failed to set core OPP regulator\n"); 1481 1482 err = pm_genpd_init(&pd->genpd, NULL, false); 1483 if (err) { 1484 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1485 return err; 1486 } 1487 1488 err = of_genpd_add_provider_simple(np, &pd->genpd); 1489 if (err) { 1490 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1491 goto remove_genpd; 1492 } 1493 1494 return 0; 1495 1496 remove_genpd: 1497 pm_genpd_remove(&pd->genpd); 1498 1499 return err; 1500 } 1501 1502 static int tegra_powergate_init(struct tegra_pmc *pmc, 1503 struct device_node *parent) 1504 { 1505 struct of_phandle_args child_args, parent_args; 1506 struct device_node *np; 1507 int err = 0; 1508 1509 /* 1510 * Core power domain is the parent of powergate domains, hence it 1511 * should be registered first. 1512 */ 1513 np = of_get_child_by_name(parent, "core-domain"); 1514 if (np) { 1515 err = tegra_pmc_core_pd_add(pmc, np); 1516 of_node_put(np); 1517 if (err) 1518 return err; 1519 } 1520 1521 np = of_get_child_by_name(parent, "powergates"); 1522 if (!np) 1523 return 0; 1524 1525 for_each_child_of_node_scoped(np, child) { 1526 err = tegra_powergate_add(pmc, child); 1527 if (err < 0) 1528 break; 1529 1530 if (of_parse_phandle_with_args(child, "power-domains", 1531 "#power-domain-cells", 1532 0, &parent_args)) 1533 continue; 1534 1535 child_args.np = child; 1536 child_args.args_count = 0; 1537 1538 err = of_genpd_add_subdomain(&parent_args, &child_args); 1539 of_node_put(parent_args.np); 1540 if (err) 1541 break; 1542 } 1543 1544 of_node_put(np); 1545 1546 return err; 1547 } 1548 1549 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1550 { 1551 struct tegra_powergate *pg = to_powergate(genpd); 1552 1553 reset_control_put(pg->reset); 1554 1555 while (pg->num_clks--) 1556 clk_put(pg->clks[pg->num_clks]); 1557 1558 kfree(pg->clks); 1559 1560 set_bit(pg->id, pg->pmc->powergates_available); 1561 1562 kfree(pg); 1563 } 1564 1565 static void tegra_powergate_remove_all(struct device_node *parent) 1566 { 1567 struct generic_pm_domain *genpd; 1568 struct device_node *np, *child; 1569 1570 np = of_get_child_by_name(parent, "powergates"); 1571 if (!np) 1572 return; 1573 1574 for_each_child_of_node(np, child) { 1575 of_genpd_del_provider(child); 1576 1577 genpd = of_genpd_remove_last(child); 1578 if (IS_ERR(genpd)) 1579 continue; 1580 1581 tegra_powergate_remove(genpd); 1582 } 1583 1584 of_node_put(np); 1585 1586 np = of_get_child_by_name(parent, "core-domain"); 1587 if (np) { 1588 of_genpd_del_provider(np); 1589 of_genpd_remove_last(np); 1590 } 1591 } 1592 1593 static const struct tegra_io_pad_soc * 1594 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1595 { 1596 unsigned int i; 1597 1598 for (i = 0; i < pmc->soc->num_io_pads; i++) 1599 if (pmc->soc->io_pads[i].id == id) 1600 return &pmc->soc->io_pads[i]; 1601 1602 return NULL; 1603 } 1604 1605 static const struct tegra_io_pad_vctrl * 1606 tegra_io_pad_vctrl_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1607 { 1608 unsigned int i; 1609 1610 for (i = 0; i < pmc->soc->num_io_pad_vctrls; i++) 1611 if (pmc->soc->io_pad_vctrls[i].id == id) 1612 return &pmc->soc->io_pad_vctrls[i]; 1613 1614 return NULL; 1615 } 1616 1617 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1618 const struct tegra_io_pad_soc *pad, 1619 unsigned long *request, 1620 unsigned long *status, 1621 u32 *mask) 1622 { 1623 unsigned long rate, value; 1624 1625 if (pad->dpd == UINT_MAX) 1626 return -EINVAL; 1627 1628 *request = pad->request; 1629 *status = pad->status; 1630 *mask = BIT(pad->dpd); 1631 1632 if (pmc->clk) { 1633 rate = pmc->rate; 1634 if (!rate) { 1635 dev_err(pmc->dev, "failed to get clock rate\n"); 1636 return -ENODEV; 1637 } 1638 1639 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1640 1641 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1642 value = DIV_ROUND_UP(1000000000, rate); 1643 value = DIV_ROUND_UP(200, value); 1644 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1651 u32 mask, u32 val, unsigned long timeout) 1652 { 1653 u32 value; 1654 1655 timeout = jiffies + msecs_to_jiffies(timeout); 1656 1657 while (time_after(timeout, jiffies)) { 1658 value = tegra_pmc_readl(pmc, offset); 1659 if ((value & mask) == val) 1660 return 0; 1661 1662 usleep_range(250, 1000); 1663 } 1664 1665 return -ETIMEDOUT; 1666 } 1667 1668 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1669 { 1670 if (pmc->clk) 1671 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1672 } 1673 1674 /** 1675 * tegra_pmc_io_pad_power_enable() - enable power to I/O pad 1676 * @pmc: power management controller 1677 * @id: Tegra I/O pad ID for which to enable power 1678 * 1679 * Returns: 0 on success or a negative error code on failure. 1680 */ 1681 int tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1682 { 1683 const struct tegra_io_pad_soc *pad; 1684 unsigned long request, status; 1685 u32 mask; 1686 int err; 1687 1688 pad = tegra_io_pad_find(pmc, id); 1689 if (!pad) { 1690 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1691 return -ENOENT; 1692 } 1693 1694 mutex_lock(&pmc->powergates_lock); 1695 1696 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1697 if (err < 0) { 1698 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1699 goto unlock; 1700 } 1701 1702 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1703 1704 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1705 if (err < 0) { 1706 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1707 goto unlock; 1708 } 1709 1710 tegra_io_pad_unprepare(pmc); 1711 1712 unlock: 1713 mutex_unlock(&pmc->powergates_lock); 1714 return err; 1715 } 1716 EXPORT_SYMBOL(tegra_pmc_io_pad_power_enable); 1717 1718 /** 1719 * tegra_pmc_io_pad_power_disable() - disable power to I/O pad 1720 * @pmc: power management controller 1721 * @id: Tegra I/O pad ID for which to disable power 1722 * 1723 * Returns: 0 on success or a negative error code on failure. 1724 */ 1725 int tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id) 1726 { 1727 const struct tegra_io_pad_soc *pad; 1728 unsigned long request, status; 1729 u32 mask; 1730 int err; 1731 1732 pad = tegra_io_pad_find(pmc, id); 1733 if (!pad) { 1734 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1735 return -ENOENT; 1736 } 1737 1738 mutex_lock(&pmc->powergates_lock); 1739 1740 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1741 if (err < 0) { 1742 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1743 goto unlock; 1744 } 1745 1746 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1747 1748 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1749 if (err < 0) { 1750 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1751 goto unlock; 1752 } 1753 1754 tegra_io_pad_unprepare(pmc); 1755 1756 unlock: 1757 mutex_unlock(&pmc->powergates_lock); 1758 return err; 1759 } 1760 EXPORT_SYMBOL(tegra_pmc_io_pad_power_disable); 1761 1762 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1763 { 1764 const struct tegra_io_pad_soc *pad; 1765 unsigned long status; 1766 u32 mask, value; 1767 1768 pad = tegra_io_pad_find(pmc, id); 1769 if (!pad) { 1770 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1771 return -ENOENT; 1772 } 1773 1774 if (pad->dpd == UINT_MAX) 1775 return -EINVAL; 1776 1777 status = pad->status; 1778 mask = BIT(pad->dpd); 1779 1780 value = tegra_pmc_readl(pmc, status); 1781 1782 return !(value & mask); 1783 } 1784 1785 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1786 int voltage) 1787 { 1788 const struct tegra_io_pad_vctrl *pad; 1789 u32 value; 1790 1791 pad = tegra_io_pad_vctrl_find(pmc, id); 1792 if (!pad) 1793 return -ENOENT; 1794 1795 mutex_lock(&pmc->powergates_lock); 1796 1797 if (pmc->soc->has_io_pad_wren) { 1798 /* write-enable PMC_PWR_DET_VALUE[pad->ena_3v3] */ 1799 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1800 value |= BIT(pad->ena_3v3); 1801 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1802 } 1803 1804 value = tegra_pmc_readl(pmc, pad->offset); 1805 1806 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) { 1807 value &= ~BIT(pad->ena_3v3); 1808 1809 if (pad->ena_1v8) 1810 value |= pad->ena_1v8; 1811 } else { 1812 value |= BIT(pad->ena_3v3); 1813 1814 if (pad->ena_1v8) 1815 value &= ~pad->ena_1v8; 1816 } 1817 1818 tegra_pmc_writel(pmc, value, pad->offset); 1819 1820 mutex_unlock(&pmc->powergates_lock); 1821 1822 usleep_range(100, 250); 1823 1824 return 0; 1825 } 1826 1827 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1828 { 1829 const struct tegra_io_pad_vctrl *pad; 1830 u32 value; 1831 1832 pad = tegra_io_pad_vctrl_find(pmc, id); 1833 if (!pad) 1834 return -ENOENT; 1835 1836 value = tegra_pmc_readl(pmc, pad->offset); 1837 1838 if ((value & BIT(pad->ena_3v3)) == 0) 1839 return TEGRA_IO_PAD_VOLTAGE_1V8; 1840 1841 return TEGRA_IO_PAD_VOLTAGE_3V3; 1842 } 1843 1844 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1845 { 1846 u32 value, values[2]; 1847 1848 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1849 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1850 } else { 1851 switch (value) { 1852 case 0: 1853 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1854 break; 1855 1856 case 1: 1857 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1858 break; 1859 1860 case 2: 1861 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1862 break; 1863 1864 default: 1865 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1866 break; 1867 } 1868 } 1869 1870 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1871 1872 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1873 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1874 1875 pmc->cpu_good_time = value; 1876 1877 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1878 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1879 1880 pmc->cpu_off_time = value; 1881 1882 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1883 values, ARRAY_SIZE(values))) 1884 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1885 1886 pmc->core_osc_time = values[0]; 1887 pmc->core_pmu_time = values[1]; 1888 1889 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1890 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1891 1892 pmc->core_off_time = value; 1893 1894 pmc->corereq_high = of_property_read_bool(np, 1895 "nvidia,core-power-req-active-high"); 1896 1897 pmc->sysclkreq_high = of_property_read_bool(np, 1898 "nvidia,sys-clock-req-active-high"); 1899 1900 pmc->combined_req = of_property_read_bool(np, 1901 "nvidia,combined-power-req"); 1902 1903 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1904 "nvidia,cpu-pwr-good-en"); 1905 1906 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1907 ARRAY_SIZE(values))) 1908 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1909 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1910 1911 pmc->lp0_vec_phys = values[0]; 1912 pmc->lp0_vec_size = values[1]; 1913 1914 pmc->invert_irq = of_property_read_bool(np, "nvidia,invert-interrupt"); 1915 1916 return 0; 1917 } 1918 1919 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 1920 static void tegra186_pmc_wake_handler(struct irq_work *work) 1921 { 1922 struct tegra_pmc *pmc = container_of(work, struct tegra_pmc, wake_work); 1923 unsigned int i, wake; 1924 1925 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 1926 unsigned long status = pmc->wake_status[i]; 1927 1928 for_each_set_bit(wake, &status, 32) { 1929 irq_hw_number_t hwirq = wake + (i * 32); 1930 struct irq_desc *desc; 1931 unsigned int irq; 1932 1933 irq = irq_find_mapping(pmc->domain, hwirq); 1934 if (!irq) { 1935 dev_warn(pmc->dev, 1936 "No IRQ found for WAKE#%lu!\n", 1937 hwirq); 1938 continue; 1939 } 1940 1941 dev_dbg(pmc->dev, 1942 "Resume caused by WAKE#%lu mapped to IRQ#%u\n", 1943 hwirq, irq); 1944 1945 desc = irq_to_desc(irq); 1946 if (!desc) { 1947 dev_warn(pmc->dev, 1948 "No descriptor found for IRQ#%u\n", 1949 irq); 1950 continue; 1951 } 1952 1953 if (!desc->action || !desc->action->name) 1954 continue; 1955 1956 generic_handle_irq(irq); 1957 } 1958 1959 pmc->wake_status[i] = 0; 1960 } 1961 } 1962 1963 static int tegra_pmc_init(struct tegra_pmc *pmc) 1964 { 1965 if (pmc->soc->max_wake_events > 0) { 1966 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1967 if (!pmc->wake_type_level_map) 1968 return -ENOMEM; 1969 1970 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1971 if (!pmc->wake_type_dual_edge_map) 1972 return -ENOMEM; 1973 1974 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1975 if (!pmc->wake_sw_status_map) 1976 return -ENOMEM; 1977 1978 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1979 if (!pmc->wake_cntrl_level_map) 1980 return -ENOMEM; 1981 1982 pmc->wake_status = kcalloc(pmc->soc->max_wake_vectors, sizeof(u32), GFP_KERNEL); 1983 if (!pmc->wake_status) 1984 return -ENOMEM; 1985 1986 /* 1987 * Initialize IRQ work for processing wake IRQs. Must use 1988 * HARD_IRQ variant to run in hard IRQ context on PREEMPT_RT 1989 * because we call generic_handle_irq() which requires hard 1990 * IRQ context. 1991 */ 1992 pmc->wake_work = IRQ_WORK_INIT_HARD(tegra186_pmc_wake_handler); 1993 } 1994 1995 if (pmc->soc->init) 1996 pmc->soc->init(pmc); 1997 1998 return 0; 1999 } 2000 2001 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 2002 { 2003 static const char disabled[] = "emergency thermal reset disabled"; 2004 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 2005 struct device *dev = pmc->dev; 2006 struct device_node *np; 2007 u32 value, checksum; 2008 2009 if (!pmc->soc->has_tsense_reset) 2010 return; 2011 2012 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 2013 if (!np) { 2014 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 2015 return; 2016 } 2017 2018 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 2019 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 2020 goto out; 2021 } 2022 2023 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 2024 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 2025 goto out; 2026 } 2027 2028 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 2029 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 2030 goto out; 2031 } 2032 2033 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 2034 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 2035 goto out; 2036 } 2037 2038 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 2039 pinmux = 0; 2040 2041 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2042 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 2043 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2044 2045 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 2046 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 2047 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 2048 2049 value = PMC_SCRATCH55_RESET_TEGRA; 2050 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 2051 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 2052 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 2053 2054 /* 2055 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 2056 * contain the checksum and are currently zero, so they are not added. 2057 */ 2058 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 2059 + ((value >> 24) & 0xff); 2060 checksum &= 0xff; 2061 checksum = 0x100 - checksum; 2062 2063 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 2064 2065 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 2066 2067 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2068 value |= PMC_SENSOR_CTRL_ENABLE_RST; 2069 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2070 2071 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2072 2073 out: 2074 of_node_put(np); 2075 } 2076 2077 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2078 { 2079 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2080 2081 return pmc->soc->num_io_pads; 2082 } 2083 2084 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2085 unsigned int group) 2086 { 2087 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2088 2089 return pmc->soc->io_pads[group].name; 2090 } 2091 2092 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2093 unsigned int group, 2094 const unsigned int **pins, 2095 unsigned int *num_pins) 2096 { 2097 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2098 2099 *pins = &pmc->soc->io_pads[group].id; 2100 *num_pins = 1; 2101 2102 return 0; 2103 } 2104 2105 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2106 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2107 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2108 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2109 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2110 .dt_free_map = pinconf_generic_dt_free_map, 2111 }; 2112 2113 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2114 unsigned int pin, unsigned long *config) 2115 { 2116 enum pin_config_param param = pinconf_to_config_param(*config); 2117 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2118 const struct tegra_io_pad_soc *pad; 2119 int ret; 2120 u32 arg; 2121 2122 pad = tegra_io_pad_find(pmc, pin); 2123 if (!pad) 2124 return -EINVAL; 2125 2126 switch (param) { 2127 case PIN_CONFIG_POWER_SOURCE: 2128 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2129 if (ret < 0) 2130 return ret; 2131 2132 arg = ret; 2133 break; 2134 2135 case PIN_CONFIG_MODE_LOW_POWER: 2136 ret = tegra_io_pad_is_powered(pmc, pad->id); 2137 if (ret < 0) 2138 return ret; 2139 2140 arg = !ret; 2141 break; 2142 2143 default: 2144 return -EINVAL; 2145 } 2146 2147 *config = pinconf_to_config_packed(param, arg); 2148 2149 return 0; 2150 } 2151 2152 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2153 unsigned int pin, unsigned long *configs, 2154 unsigned int num_configs) 2155 { 2156 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2157 const struct tegra_io_pad_soc *pad; 2158 enum pin_config_param param; 2159 unsigned int i; 2160 int err; 2161 u32 arg; 2162 2163 pad = tegra_io_pad_find(pmc, pin); 2164 if (!pad) 2165 return -EINVAL; 2166 2167 for (i = 0; i < num_configs; ++i) { 2168 param = pinconf_to_config_param(configs[i]); 2169 arg = pinconf_to_config_argument(configs[i]); 2170 2171 switch (param) { 2172 case PIN_CONFIG_MODE_LOW_POWER: 2173 if (arg) 2174 err = tegra_pmc_io_pad_power_disable(pmc, pad->id); 2175 else 2176 err = tegra_pmc_io_pad_power_enable(pmc, pad->id); 2177 if (err) 2178 return err; 2179 break; 2180 case PIN_CONFIG_POWER_SOURCE: 2181 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2182 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2183 return -EINVAL; 2184 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2185 if (err) 2186 return err; 2187 break; 2188 default: 2189 return -EINVAL; 2190 } 2191 } 2192 2193 return 0; 2194 } 2195 2196 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2197 .pin_config_get = tegra_io_pad_pinconf_get, 2198 .pin_config_set = tegra_io_pad_pinconf_set, 2199 .is_generic = true, 2200 }; 2201 2202 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2203 .pctlops = &tegra_io_pad_pinctrl_ops, 2204 .confops = &tegra_io_pad_pinconf_ops, 2205 }; 2206 2207 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2208 { 2209 int err; 2210 2211 if (!pmc->soc->num_pin_descs) 2212 return 0; 2213 2214 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2215 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2216 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2217 2218 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2219 pmc); 2220 if (IS_ERR(pmc->pctl_dev)) { 2221 err = PTR_ERR(pmc->pctl_dev); 2222 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2223 err); 2224 return err; 2225 } 2226 2227 return 0; 2228 } 2229 2230 static ssize_t reset_reason_show(struct device *dev, 2231 struct device_attribute *attr, char *buf) 2232 { 2233 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2234 u32 value; 2235 2236 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2237 value &= pmc->soc->regs->rst_source_mask; 2238 value >>= pmc->soc->regs->rst_source_shift; 2239 2240 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2241 return sprintf(buf, "%s\n", "UNKNOWN"); 2242 2243 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2244 } 2245 2246 static DEVICE_ATTR_RO(reset_reason); 2247 2248 static ssize_t reset_level_show(struct device *dev, 2249 struct device_attribute *attr, char *buf) 2250 { 2251 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2252 u32 value; 2253 2254 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2255 value &= pmc->soc->regs->rst_level_mask; 2256 value >>= pmc->soc->regs->rst_level_shift; 2257 2258 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2259 return sprintf(buf, "%s\n", "UNKNOWN"); 2260 2261 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2262 } 2263 2264 static DEVICE_ATTR_RO(reset_level); 2265 2266 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2267 { 2268 struct device *dev = pmc->dev; 2269 int err = 0; 2270 2271 if (pmc->soc->reset_sources) { 2272 err = device_create_file(dev, &dev_attr_reset_reason); 2273 if (err < 0) 2274 dev_warn(dev, 2275 "failed to create attr \"reset_reason\": %d\n", 2276 err); 2277 } 2278 2279 if (pmc->soc->reset_levels) { 2280 err = device_create_file(dev, &dev_attr_reset_level); 2281 if (err < 0) 2282 dev_warn(dev, 2283 "failed to create attr \"reset_level\": %d\n", 2284 err); 2285 } 2286 } 2287 2288 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2289 struct irq_fwspec *fwspec, 2290 unsigned long *hwirq, 2291 unsigned int *type) 2292 { 2293 if (WARN_ON(fwspec->param_count < 2)) 2294 return -EINVAL; 2295 2296 *hwirq = fwspec->param[0]; 2297 *type = fwspec->param[1]; 2298 2299 return 0; 2300 } 2301 2302 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2303 unsigned int num_irqs, void *data) 2304 { 2305 struct tegra_pmc *pmc = domain->host_data; 2306 const struct tegra_pmc_soc *soc = pmc->soc; 2307 struct irq_fwspec *fwspec = data; 2308 unsigned int i; 2309 int err = 0; 2310 2311 if (WARN_ON(num_irqs > 1)) 2312 return -EINVAL; 2313 2314 for (i = 0; i < soc->num_wake_events; i++) { 2315 const struct tegra_wake_event *event = &soc->wake_events[i]; 2316 2317 /* IRQ and simple wake events */ 2318 if (fwspec->param_count == 2) { 2319 struct irq_fwspec spec; 2320 2321 if (event->id != fwspec->param[0]) 2322 continue; 2323 2324 err = irq_domain_set_hwirq_and_chip(domain, virq, 2325 event->id, 2326 &pmc->irq, pmc); 2327 if (err < 0) 2328 break; 2329 2330 /* simple hierarchies stop at the PMC level */ 2331 if (event->irq == 0) { 2332 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2333 break; 2334 } 2335 2336 spec.fwnode = &pmc->dev->of_node->fwnode; 2337 spec.param_count = 3; 2338 spec.param[0] = GIC_SPI; 2339 spec.param[1] = event->irq; 2340 spec.param[2] = fwspec->param[1]; 2341 2342 err = irq_domain_alloc_irqs_parent(domain, virq, 2343 num_irqs, &spec); 2344 2345 break; 2346 } 2347 2348 /* GPIO wake events */ 2349 if (fwspec->param_count == 3) { 2350 if (event->gpio.instance != fwspec->param[0] || 2351 event->gpio.pin != fwspec->param[1]) 2352 continue; 2353 2354 err = irq_domain_set_hwirq_and_chip(domain, virq, 2355 event->id, 2356 &pmc->irq, pmc); 2357 2358 /* GPIO hierarchies stop at the PMC level */ 2359 if (!err && domain->parent) 2360 err = irq_domain_disconnect_hierarchy(domain->parent, 2361 virq); 2362 break; 2363 } 2364 } 2365 2366 /* If there is no wake-up event, there is no PMC mapping */ 2367 if (i == soc->num_wake_events) 2368 err = irq_domain_disconnect_hierarchy(domain, virq); 2369 2370 return err; 2371 } 2372 2373 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2374 .translate = tegra_pmc_irq_translate, 2375 .alloc = tegra_pmc_irq_alloc, 2376 }; 2377 2378 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2379 { 2380 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2381 unsigned int offset, bit; 2382 u32 value; 2383 2384 offset = data->hwirq / 32; 2385 bit = data->hwirq % 32; 2386 2387 /* clear wake status */ 2388 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2389 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2390 2391 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2392 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2393 2394 /* enable PMC wake */ 2395 if (data->hwirq >= 32) 2396 offset = PMC_WAKE2_MASK; 2397 else 2398 offset = PMC_WAKE_MASK; 2399 2400 value = tegra_pmc_readl(pmc, offset); 2401 2402 if (on) 2403 value |= BIT(bit); 2404 else 2405 value &= ~BIT(bit); 2406 2407 tegra_pmc_writel(pmc, value, offset); 2408 2409 return 0; 2410 } 2411 2412 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2413 { 2414 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2415 unsigned int offset, bit; 2416 u32 value; 2417 2418 offset = data->hwirq / 32; 2419 bit = data->hwirq % 32; 2420 2421 if (data->hwirq >= 32) 2422 offset = PMC_WAKE2_LEVEL; 2423 else 2424 offset = PMC_WAKE_LEVEL; 2425 2426 value = tegra_pmc_readl(pmc, offset); 2427 2428 switch (type) { 2429 case IRQ_TYPE_EDGE_RISING: 2430 case IRQ_TYPE_LEVEL_HIGH: 2431 value |= BIT(bit); 2432 break; 2433 2434 case IRQ_TYPE_EDGE_FALLING: 2435 case IRQ_TYPE_LEVEL_LOW: 2436 value &= ~BIT(bit); 2437 break; 2438 2439 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2440 value ^= BIT(bit); 2441 break; 2442 2443 default: 2444 return -EINVAL; 2445 } 2446 2447 tegra_pmc_writel(pmc, value, offset); 2448 2449 return 0; 2450 } 2451 2452 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2453 { 2454 u32 value; 2455 2456 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2457 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2458 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2459 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2460 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2461 } 2462 2463 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2464 { 2465 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2466 unsigned int offset, bit; 2467 u32 value; 2468 2469 offset = data->hwirq / 32; 2470 bit = data->hwirq % 32; 2471 2472 /* clear wake status */ 2473 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(pmc, data->hwirq)); 2474 2475 /* route wake to tier 2 */ 2476 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset)); 2477 2478 if (!on) 2479 value &= ~(1 << bit); 2480 else 2481 value |= 1 << bit; 2482 2483 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset)); 2484 2485 /* enable wakeup event */ 2486 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(pmc, data->hwirq)); 2487 2488 return 0; 2489 } 2490 2491 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2492 { 2493 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2494 u32 value; 2495 2496 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2497 2498 switch (type) { 2499 case IRQ_TYPE_EDGE_RISING: 2500 case IRQ_TYPE_LEVEL_HIGH: 2501 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2502 set_bit(data->hwirq, pmc->wake_type_level_map); 2503 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2504 break; 2505 2506 case IRQ_TYPE_EDGE_FALLING: 2507 case IRQ_TYPE_LEVEL_LOW: 2508 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2509 clear_bit(data->hwirq, pmc->wake_type_level_map); 2510 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2511 break; 2512 2513 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2514 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2515 clear_bit(data->hwirq, pmc->wake_type_level_map); 2516 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2517 break; 2518 2519 default: 2520 return -EINVAL; 2521 } 2522 2523 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2524 2525 return 0; 2526 } 2527 2528 static void tegra_irq_mask_parent(struct irq_data *data) 2529 { 2530 if (data->parent_data) 2531 irq_chip_mask_parent(data); 2532 } 2533 2534 static void tegra_irq_unmask_parent(struct irq_data *data) 2535 { 2536 if (data->parent_data) 2537 irq_chip_unmask_parent(data); 2538 } 2539 2540 static void tegra_irq_eoi_parent(struct irq_data *data) 2541 { 2542 if (data->parent_data) 2543 irq_chip_eoi_parent(data); 2544 } 2545 2546 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2547 const struct cpumask *dest, 2548 bool force) 2549 { 2550 if (data->parent_data) 2551 return irq_chip_set_affinity_parent(data, dest, force); 2552 2553 return -EINVAL; 2554 } 2555 2556 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2557 { 2558 struct irq_domain *parent = NULL; 2559 struct device_node *np; 2560 2561 np = of_irq_find_parent(pmc->dev->of_node); 2562 if (np) { 2563 parent = irq_find_host(np); 2564 of_node_put(np); 2565 } 2566 2567 if (!parent) 2568 return 0; 2569 2570 pmc->irq.name = dev_name(pmc->dev); 2571 pmc->irq.irq_mask = tegra_irq_mask_parent; 2572 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2573 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2574 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2575 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2576 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2577 2578 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, dev_fwnode(pmc->dev), 2579 &tegra_pmc_irq_domain_ops, pmc); 2580 if (!pmc->domain) { 2581 dev_err(pmc->dev, "failed to allocate domain\n"); 2582 return -ENOMEM; 2583 } 2584 2585 return 0; 2586 } 2587 2588 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2589 unsigned long action, void *ptr) 2590 { 2591 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2592 struct clk_notifier_data *data = ptr; 2593 2594 switch (action) { 2595 case PRE_RATE_CHANGE: 2596 mutex_lock(&pmc->powergates_lock); 2597 break; 2598 2599 case POST_RATE_CHANGE: 2600 pmc->rate = data->new_rate; 2601 fallthrough; 2602 2603 case ABORT_RATE_CHANGE: 2604 mutex_unlock(&pmc->powergates_lock); 2605 break; 2606 2607 default: 2608 WARN_ON_ONCE(1); 2609 return notifier_from_errno(-EINVAL); 2610 } 2611 2612 return NOTIFY_OK; 2613 } 2614 2615 static void pmc_clk_fence_udelay(struct tegra_pmc *pmc, u32 offset) 2616 { 2617 tegra_pmc_readl(pmc, offset); 2618 /* pmc clk propagation delay 2 us */ 2619 udelay(2); 2620 } 2621 2622 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2623 { 2624 struct pmc_clk *clk = to_pmc_clk(hw); 2625 u32 val; 2626 2627 val = tegra_pmc_readl(clk->pmc, clk->offs) >> clk->mux_shift; 2628 val &= PMC_CLK_OUT_MUX_MASK; 2629 2630 return val; 2631 } 2632 2633 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2634 { 2635 struct pmc_clk *clk = to_pmc_clk(hw); 2636 u32 val; 2637 2638 val = tegra_pmc_readl(clk->pmc, clk->offs); 2639 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2640 val |= index << clk->mux_shift; 2641 tegra_pmc_writel(clk->pmc, val, clk->offs); 2642 pmc_clk_fence_udelay(clk->pmc, clk->offs); 2643 2644 return 0; 2645 } 2646 2647 static int pmc_clk_is_enabled(struct clk_hw *hw) 2648 { 2649 struct pmc_clk *clk = to_pmc_clk(hw); 2650 u32 val; 2651 2652 val = tegra_pmc_readl(clk->pmc, clk->offs) & BIT(clk->force_en_shift); 2653 2654 return val ? 1 : 0; 2655 } 2656 2657 static void pmc_clk_set_state(struct tegra_pmc *pmc, unsigned long offs, 2658 u32 shift, int state) 2659 { 2660 u32 val; 2661 2662 val = tegra_pmc_readl(pmc, offs); 2663 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2664 tegra_pmc_writel(pmc, val, offs); 2665 pmc_clk_fence_udelay(pmc, offs); 2666 } 2667 2668 static int pmc_clk_enable(struct clk_hw *hw) 2669 { 2670 struct pmc_clk *clk = to_pmc_clk(hw); 2671 2672 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 1); 2673 2674 return 0; 2675 } 2676 2677 static void pmc_clk_disable(struct clk_hw *hw) 2678 { 2679 struct pmc_clk *clk = to_pmc_clk(hw); 2680 2681 pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 0); 2682 } 2683 2684 static const struct clk_ops pmc_clk_ops = { 2685 .get_parent = pmc_clk_mux_get_parent, 2686 .set_parent = pmc_clk_mux_set_parent, 2687 .determine_rate = __clk_mux_determine_rate, 2688 .is_enabled = pmc_clk_is_enabled, 2689 .enable = pmc_clk_enable, 2690 .disable = pmc_clk_disable, 2691 }; 2692 2693 static struct clk * 2694 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2695 const struct pmc_clk_init_data *data, 2696 unsigned long offset) 2697 { 2698 struct clk_init_data init = {}; 2699 struct pmc_clk *pmc_clk; 2700 2701 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2702 if (!pmc_clk) 2703 return ERR_PTR(-ENOMEM); 2704 2705 init.name = data->name; 2706 init.ops = &pmc_clk_ops; 2707 init.parent_names = data->parents; 2708 init.num_parents = data->num_parents; 2709 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2710 CLK_SET_PARENT_GATE; 2711 2712 pmc_clk->hw.init = &init; 2713 pmc_clk->pmc = pmc; 2714 pmc_clk->offs = offset; 2715 pmc_clk->mux_shift = data->mux_shift; 2716 pmc_clk->force_en_shift = data->force_en_shift; 2717 2718 return clk_register(NULL, &pmc_clk->hw); 2719 } 2720 2721 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2722 { 2723 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2724 u32 value = tegra_pmc_readl(gate->pmc, gate->offs); 2725 2726 return value & BIT(gate->shift) ? 1 : 0; 2727 } 2728 2729 static int pmc_clk_gate_enable(struct clk_hw *hw) 2730 { 2731 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2732 2733 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 1); 2734 2735 return 0; 2736 } 2737 2738 static void pmc_clk_gate_disable(struct clk_hw *hw) 2739 { 2740 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2741 2742 pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 0); 2743 } 2744 2745 static const struct clk_ops pmc_clk_gate_ops = { 2746 .is_enabled = pmc_clk_gate_is_enabled, 2747 .enable = pmc_clk_gate_enable, 2748 .disable = pmc_clk_gate_disable, 2749 }; 2750 2751 static struct clk * 2752 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2753 const char *parent_name, unsigned long offset, 2754 u32 shift) 2755 { 2756 struct clk_init_data init = {}; 2757 struct pmc_clk_gate *gate; 2758 2759 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2760 if (!gate) 2761 return ERR_PTR(-ENOMEM); 2762 2763 init.name = name; 2764 init.ops = &pmc_clk_gate_ops; 2765 init.parent_names = &parent_name; 2766 init.num_parents = 1; 2767 init.flags = 0; 2768 2769 gate->hw.init = &init; 2770 gate->pmc = pmc; 2771 gate->offs = offset; 2772 gate->shift = shift; 2773 2774 return clk_register(NULL, &gate->hw); 2775 } 2776 2777 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2778 struct device_node *np) 2779 { 2780 struct clk *clk; 2781 struct clk_onecell_data *clk_data; 2782 unsigned int num_clks; 2783 int i, err; 2784 2785 num_clks = pmc->soc->num_pmc_clks; 2786 if (pmc->soc->has_blink_output) 2787 num_clks += 1; 2788 2789 if (!num_clks) 2790 return; 2791 2792 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2793 if (!clk_data) 2794 return; 2795 2796 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2797 sizeof(*clk_data->clks), GFP_KERNEL); 2798 if (!clk_data->clks) 2799 return; 2800 2801 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2802 2803 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2804 clk_data->clks[i] = ERR_PTR(-ENOENT); 2805 2806 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2807 const struct pmc_clk_init_data *data; 2808 2809 data = pmc->soc->pmc_clks_data + i; 2810 2811 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2812 if (IS_ERR(clk)) { 2813 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2814 data->name, PTR_ERR_OR_ZERO(clk)); 2815 return; 2816 } 2817 2818 err = clk_register_clkdev(clk, data->name, NULL); 2819 if (err) { 2820 dev_warn(pmc->dev, 2821 "unable to register %s clock lookup: %d\n", 2822 data->name, err); 2823 return; 2824 } 2825 2826 clk_data->clks[data->clk_id] = clk; 2827 } 2828 2829 if (pmc->soc->has_blink_output) { 2830 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2831 clk = tegra_pmc_clk_gate_register(pmc, 2832 "pmc_blink_override", 2833 "clk_32k", 2834 PMC_DPD_PADS_ORIDE, 2835 PMC_DPD_PADS_ORIDE_BLINK); 2836 if (IS_ERR(clk)) { 2837 dev_warn(pmc->dev, 2838 "unable to register pmc_blink_override: %d\n", 2839 PTR_ERR_OR_ZERO(clk)); 2840 return; 2841 } 2842 2843 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2844 "pmc_blink_override", 2845 PMC_CNTRL, 2846 PMC_CNTRL_BLINK_EN); 2847 if (IS_ERR(clk)) { 2848 dev_warn(pmc->dev, 2849 "unable to register pmc_blink: %d\n", 2850 PTR_ERR_OR_ZERO(clk)); 2851 return; 2852 } 2853 2854 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2855 if (err) { 2856 dev_warn(pmc->dev, 2857 "unable to register pmc_blink lookup: %d\n", 2858 err); 2859 return; 2860 } 2861 2862 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2863 } 2864 2865 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2866 if (err) 2867 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2868 err); 2869 } 2870 2871 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2872 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2873 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2874 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2875 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2876 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2877 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2878 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2879 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2880 }; 2881 2882 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2883 .yes_ranges = pmc_usb_sleepwalk_ranges, 2884 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2885 }; 2886 2887 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2888 { 2889 struct tegra_pmc *pmc = context; 2890 2891 *value = tegra_pmc_readl(pmc, offset); 2892 return 0; 2893 } 2894 2895 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2896 { 2897 struct tegra_pmc *pmc = context; 2898 2899 tegra_pmc_writel(pmc, value, offset); 2900 return 0; 2901 } 2902 2903 static const struct regmap_config usb_sleepwalk_regmap_config = { 2904 .name = "usb_sleepwalk", 2905 .reg_bits = 32, 2906 .val_bits = 32, 2907 .reg_stride = 4, 2908 .fast_io = true, 2909 .rd_table = &pmc_usb_sleepwalk_table, 2910 .wr_table = &pmc_usb_sleepwalk_table, 2911 .reg_read = tegra_pmc_regmap_readl, 2912 .reg_write = tegra_pmc_regmap_writel, 2913 }; 2914 2915 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2916 { 2917 struct regmap *regmap; 2918 int err; 2919 2920 if (pmc->soc->has_usb_sleepwalk) { 2921 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2922 if (IS_ERR(regmap)) { 2923 err = PTR_ERR(regmap); 2924 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2925 return err; 2926 } 2927 } 2928 2929 return 0; 2930 } 2931 2932 static bool tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 2933 { 2934 u32 value, saved; 2935 2936 saved = readl(pmc->base + pmc->soc->regs->scratch0); 2937 value = saved ^ 0xffffffff; 2938 2939 if (value == 0xffffffff) 2940 value = 0xdeadbeef; 2941 2942 /* write pattern and read it back */ 2943 writel(value, pmc->base + pmc->soc->regs->scratch0); 2944 value = readl(pmc->base + pmc->soc->regs->scratch0); 2945 2946 /* if we read all-zeroes, access is restricted to TZ only */ 2947 if (value == 0) { 2948 pr_info("access to PMC is restricted to TZ\n"); 2949 return true; 2950 } 2951 2952 /* restore original value */ 2953 writel(saved, pmc->base + pmc->soc->regs->scratch0); 2954 2955 return false; 2956 } 2957 2958 static void tegra_pmc_init_common(struct tegra_pmc *pmc, struct device_node *np) 2959 { 2960 unsigned int i; 2961 2962 if (pmc->soc->maybe_tz_only) 2963 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 2964 2965 /* Create a bitmap of the available and valid partitions */ 2966 for (i = 0; i < pmc->soc->num_powergates; i++) 2967 if (pmc->soc->powergates[i]) 2968 set_bit(i, pmc->powergates_available); 2969 2970 /* 2971 * Invert the interrupt polarity if a PMC device tree node exists and 2972 * contains the nvidia,invert-interrupt property. 2973 */ 2974 pmc->soc->setup_irq_polarity(pmc, np); 2975 } 2976 2977 static void tegra_pmc_reset_suspend_mode(void *data) 2978 { 2979 struct tegra_pmc *pmc = data; 2980 2981 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2982 } 2983 2984 static int tegra_pmc_acpi_probe(struct platform_device *pdev, struct tegra_pmc *pmc) 2985 { 2986 pmc->base = devm_platform_ioremap_resource(pdev, 0); 2987 if (IS_ERR(pmc->base)) 2988 return PTR_ERR(pmc->base); 2989 2990 tegra_pmc_reset_sysfs_init(pmc); 2991 platform_set_drvdata(pdev, pmc); 2992 2993 return 0; 2994 } 2995 2996 static int tegra_pmc_probe(struct platform_device *pdev) 2997 { 2998 struct tegra_pmc *pmc; 2999 struct resource *res; 3000 int err; 3001 3002 #if defined(CONFIG_ARM) 3003 /* 3004 * Early initialisation should have configured an initial 3005 * register mapping and setup the soc data pointer. If these 3006 * are not valid then something went badly wrong! 3007 */ 3008 if (WARN_ON(!early_pmc->base || !early_pmc->soc)) 3009 return -ENODEV; 3010 #endif 3011 3012 pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL); 3013 if (!pmc) 3014 return -ENOMEM; 3015 3016 pmc->soc = device_get_match_data(&pdev->dev); 3017 mutex_init(&pmc->powergates_lock); 3018 pmc->dev = &pdev->dev; 3019 3020 if (is_acpi_node(dev_fwnode(&pdev->dev))) 3021 return tegra_pmc_acpi_probe(pdev, pmc); 3022 3023 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 3024 if (err < 0) 3025 return dev_err_probe(&pdev->dev, err, "failed to parse DT\n"); 3026 3027 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 3028 pmc); 3029 if (err) 3030 return err; 3031 3032 /* take over the memory region from the early initialization */ 3033 pmc->base = devm_platform_ioremap_resource(pdev, 0); 3034 if (IS_ERR(pmc->base)) 3035 return PTR_ERR(pmc->base); 3036 3037 if (pmc->soc->has_single_mmio_aperture) { 3038 pmc->wake = pmc->base; 3039 pmc->aotag = pmc->base; 3040 pmc->scratch = pmc->base; 3041 } else { 3042 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 3043 if (IS_ERR(pmc->wake)) 3044 return PTR_ERR(pmc->wake); 3045 3046 /* "aotag" is an optional aperture */ 3047 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3048 "aotag"); 3049 if (res) { 3050 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 3051 if (IS_ERR(pmc->aotag)) 3052 return PTR_ERR(pmc->aotag); 3053 } else { 3054 pmc->aotag = NULL; 3055 } 3056 3057 /* "scratch" is an optional aperture */ 3058 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 3059 "scratch"); 3060 if (res) { 3061 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 3062 if (IS_ERR(pmc->scratch)) 3063 return PTR_ERR(pmc->scratch); 3064 } else { 3065 pmc->scratch = NULL; 3066 } 3067 } 3068 3069 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 3070 if (IS_ERR(pmc->clk)) 3071 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 3072 "failed to get pclk\n"); 3073 3074 tegra_pmc_init_common(pmc, pdev->dev.of_node); 3075 3076 /* 3077 * PMC should be last resort for restarting since it soft-resets 3078 * CPU without resetting everything else. 3079 */ 3080 if (pmc->scratch) { 3081 pmc->reboot_notifier.notifier_call = tegra_pmc_reboot_notify; 3082 3083 err = devm_register_reboot_notifier(&pdev->dev, 3084 &pmc->reboot_notifier); 3085 if (err) { 3086 dev_err(&pdev->dev, 3087 "unable to register reboot notifier, %d\n", 3088 err); 3089 return err; 3090 } 3091 } 3092 3093 if (dev_to_node(&pdev->dev) == NUMA_NO_NODE) { 3094 err = devm_register_sys_off_handler(&pdev->dev, 3095 SYS_OFF_MODE_RESTART, 3096 SYS_OFF_PRIO_LOW, 3097 tegra_pmc_restart_handler, 3098 pmc); 3099 if (err) { 3100 dev_err(&pdev->dev, 3101 "failed to register sys-off handler: %d\n", 3102 err); 3103 return err; 3104 } 3105 } 3106 3107 /* 3108 * PMC should be primary power-off method on Grouper if it soft-resets 3109 * CPU, asking bootloader to shutdown hardware. 3110 */ 3111 if (of_machine_is_compatible("asus,grouper")) { 3112 err = devm_register_sys_off_handler(&pdev->dev, 3113 SYS_OFF_MODE_POWER_OFF, 3114 SYS_OFF_PRIO_FIRMWARE, 3115 tegra_pmc_grouper_power_off_handler, 3116 pmc); 3117 if (err) { 3118 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3119 err); 3120 return err; 3121 } 3122 } 3123 3124 /* 3125 * PCLK clock rate can't be retrieved using CLK API because it 3126 * causes lockup if CPU enters LP2 idle state from some other 3127 * CLK notifier, hence we're caching the rate's value locally. 3128 */ 3129 if (pmc->clk) { 3130 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 3131 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 3132 &pmc->clk_nb); 3133 if (err) { 3134 dev_err(&pdev->dev, 3135 "failed to register clk notifier\n"); 3136 return err; 3137 } 3138 3139 pmc->rate = clk_get_rate(pmc->clk); 3140 } 3141 3142 err = tegra_pmc_init(pmc); 3143 if (err < 0) { 3144 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 3145 return err; 3146 } 3147 3148 tegra_pmc_init_tsense_reset(pmc); 3149 3150 tegra_pmc_reset_sysfs_init(pmc); 3151 3152 err = tegra_pmc_pinctrl_init(pmc); 3153 if (err) 3154 goto cleanup_sysfs; 3155 3156 err = tegra_pmc_regmap_init(pmc); 3157 if (err < 0) 3158 goto cleanup_sysfs; 3159 3160 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3161 if (err < 0) 3162 goto cleanup_powergates; 3163 3164 err = tegra_pmc_irq_init(pmc); 3165 if (err < 0) 3166 goto cleanup_powergates; 3167 3168 #if defined(CONFIG_ARM) 3169 mutex_lock(&early_pmc->powergates_lock); 3170 early_pmc->rate = pmc->rate; 3171 iounmap(early_pmc->base); 3172 early_pmc->base = pmc->base; 3173 mutex_unlock(&early_pmc->powergates_lock); 3174 #endif 3175 3176 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3177 platform_set_drvdata(pdev, pmc); 3178 tegra_pm_init_suspend(); 3179 3180 /* Some wakes require specific filter configuration */ 3181 if (pmc->soc->set_wake_filters) 3182 pmc->soc->set_wake_filters(pmc); 3183 3184 if (pmc->soc->num_powergates) 3185 debugfs_create_file("powergate", 0444, NULL, pmc, &powergate_fops); 3186 3187 return 0; 3188 3189 cleanup_powergates: 3190 tegra_powergate_remove_all(pdev->dev.of_node); 3191 cleanup_sysfs: 3192 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3193 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3194 3195 return err; 3196 } 3197 3198 /* 3199 * Ensures that sufficient time is passed for a register write to 3200 * serialize into the 32KHz domain. 3201 */ 3202 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3203 { 3204 writel(value, pmc->wake + offset); 3205 udelay(130); 3206 } 3207 3208 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3209 { 3210 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3211 u32 value; 3212 3213 value = readl(pmc->wake + offset); 3214 if (level) 3215 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3216 else 3217 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3218 3219 writel(value, pmc->wake + offset); 3220 } 3221 3222 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3223 { 3224 unsigned int i; 3225 3226 for (i = 0; i < pmc->soc->max_wake_events; i++) 3227 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3228 } 3229 3230 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3231 { 3232 wke_32kwritel(pmc, 1, pmc->soc->regs->aowake_sw_status_w); 3233 } 3234 3235 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3236 { 3237 unsigned long status; 3238 unsigned int wake, i; 3239 3240 for (i = 0; i < pmc->soc->max_wake_events; i++) 3241 wke_write_wake_level(pmc, i, 0); 3242 3243 wke_clear_sw_wake_status(pmc); 3244 3245 wke_32kwritel(pmc, 1, pmc->soc->regs->aowake_latch_sw); 3246 3247 /* 3248 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3249 * obtain the current status of the input wake signals, change 3250 * the polarity of the wake level from 0->1 while latching to force 3251 * a positive edge if the sampled signal is '1'. 3252 */ 3253 for (i = 0; i < pmc->soc->max_wake_events; i++) 3254 wke_write_wake_level(pmc, i, 1); 3255 3256 /* 3257 * Wait for the update to be synced into the 32kHz domain, 3258 * and let enough time lapse, so that the wake signals have time to 3259 * be sampled. 3260 */ 3261 udelay(300); 3262 3263 wke_32kwritel(pmc, 0, pmc->soc->regs->aowake_latch_sw); 3264 3265 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3266 3267 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3268 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(pmc, i)); 3269 3270 for_each_set_bit(wake, &status, 32) 3271 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3272 } 3273 } 3274 3275 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3276 { 3277 unsigned long status; 3278 unsigned int i, wake; 3279 u32 mask; 3280 3281 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3282 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i)); 3283 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(pmc, i)) & mask; 3284 3285 for_each_set_bit(wake, &status, 32) 3286 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W(pmc, 3287 (i * 32) + wake)); 3288 } 3289 } 3290 3291 static void tegra186_pmc_wake_syscore_resume(void *data) 3292 { 3293 struct tegra_pmc *pmc = data; 3294 unsigned int i; 3295 u32 mask; 3296 3297 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3298 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i)); 3299 pmc->wake_status[i] = readl(pmc->wake + 3300 WAKE_AOWAKE_STATUS_R(pmc, i)) & mask; 3301 } 3302 3303 /* Schedule IRQ work to process wake IRQs (if any) */ 3304 irq_work_queue(&pmc->wake_work); 3305 } 3306 3307 static int tegra186_pmc_wake_syscore_suspend(void *data) 3308 { 3309 struct tegra_pmc *pmc = data; 3310 unsigned int i; 3311 3312 /* Check if there are unhandled wake IRQs */ 3313 for (i = 0; i < pmc->soc->max_wake_vectors; i++) 3314 if (pmc->wake_status[i]) 3315 dev_warn(pmc->dev, 3316 "Unhandled wake IRQs pending vector[%u]: 0x%x\n", 3317 i, pmc->wake_status[i]); 3318 3319 wke_read_sw_wake_status(pmc); 3320 3321 /* flip the wakeup trigger for dual-edge triggered pads 3322 * which are currently asserting as wakeups 3323 */ 3324 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3325 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3326 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3327 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3328 3329 /* Clear PMC Wake Status registers while going to suspend */ 3330 wke_clear_wake_status(pmc); 3331 wke_write_wake_levels(pmc); 3332 3333 return 0; 3334 } 3335 3336 static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { 3337 .suspend = tegra186_pmc_wake_syscore_suspend, 3338 .resume = tegra186_pmc_wake_syscore_resume, 3339 }; 3340 3341 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3342 static int tegra_pmc_suspend(struct device *dev) 3343 { 3344 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3345 3346 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3347 3348 return 0; 3349 } 3350 3351 static int tegra_pmc_resume(struct device *dev) 3352 { 3353 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3354 3355 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3356 3357 return 0; 3358 } 3359 3360 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3361 3362 #endif 3363 3364 static const char * const tegra20_powergates[] = { 3365 [TEGRA_POWERGATE_CPU] = "cpu", 3366 [TEGRA_POWERGATE_3D] = "td", 3367 [TEGRA_POWERGATE_VENC] = "venc", 3368 [TEGRA_POWERGATE_VDEC] = "vdec", 3369 [TEGRA_POWERGATE_PCIE] = "pcie", 3370 [TEGRA_POWERGATE_L2] = "l2", 3371 [TEGRA_POWERGATE_MPE] = "mpe", 3372 }; 3373 3374 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3375 .scratch0 = 0x50, 3376 .rst_status = 0x1b4, 3377 .rst_source_shift = 0x0, 3378 .rst_source_mask = 0x7, 3379 .rst_level_shift = 0x0, 3380 .rst_level_mask = 0x0, 3381 }; 3382 3383 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3384 { 3385 u32 value, osc, pmu, off; 3386 3387 /* Always enable CPU power request */ 3388 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3389 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3390 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3391 3392 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3393 3394 if (pmc->sysclkreq_high) 3395 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3396 else 3397 value |= PMC_CNTRL_SYSCLK_POLARITY; 3398 3399 if (pmc->corereq_high) 3400 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3401 else 3402 value |= PMC_CNTRL_PWRREQ_POLARITY; 3403 3404 /* configure the output polarity while the request is tristated */ 3405 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3406 3407 /* now enable the request */ 3408 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3409 value |= PMC_CNTRL_SYSCLK_OE; 3410 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3411 3412 /* program core timings which are applicable only for suspend state */ 3413 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3414 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3415 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3416 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3417 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3418 PMC_COREPWRGOOD_TIMER); 3419 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3420 } 3421 } 3422 3423 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3424 struct device_node *np) 3425 { 3426 u32 value; 3427 3428 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3429 3430 if (pmc->invert_irq) 3431 value |= PMC_CNTRL_INTR_POLARITY; 3432 else 3433 value &= ~PMC_CNTRL_INTR_POLARITY; 3434 3435 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3436 } 3437 3438 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3439 .supports_core_domain = true, 3440 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3441 .powergates = tegra20_powergates, 3442 .num_cpu_powergates = 0, 3443 .cpu_powergates = NULL, 3444 .has_tsense_reset = false, 3445 .has_gpu_clamps = false, 3446 .needs_mbist_war = false, 3447 .has_io_pad_wren = true, 3448 .maybe_tz_only = false, 3449 .num_io_pads = 0, 3450 .io_pads = NULL, 3451 .num_pin_descs = 0, 3452 .pin_descs = NULL, 3453 .regs = &tegra20_pmc_regs, 3454 .init = tegra20_pmc_init, 3455 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3456 .powergate_set = tegra20_powergate_set, 3457 .reset_sources = NULL, 3458 .num_reset_sources = 0, 3459 .reset_levels = NULL, 3460 .num_reset_levels = 0, 3461 .pmc_clks_data = NULL, 3462 .num_pmc_clks = 0, 3463 .has_blink_output = true, 3464 .has_usb_sleepwalk = true, 3465 .has_single_mmio_aperture = true, 3466 }; 3467 3468 static const char * const tegra30_powergates[] = { 3469 [TEGRA_POWERGATE_CPU] = "cpu0", 3470 [TEGRA_POWERGATE_3D] = "td", 3471 [TEGRA_POWERGATE_VENC] = "venc", 3472 [TEGRA_POWERGATE_VDEC] = "vdec", 3473 [TEGRA_POWERGATE_PCIE] = "pcie", 3474 [TEGRA_POWERGATE_L2] = "l2", 3475 [TEGRA_POWERGATE_MPE] = "mpe", 3476 [TEGRA_POWERGATE_HEG] = "heg", 3477 [TEGRA_POWERGATE_SATA] = "sata", 3478 [TEGRA_POWERGATE_CPU1] = "cpu1", 3479 [TEGRA_POWERGATE_CPU2] = "cpu2", 3480 [TEGRA_POWERGATE_CPU3] = "cpu3", 3481 [TEGRA_POWERGATE_CELP] = "celp", 3482 [TEGRA_POWERGATE_3D1] = "td2", 3483 }; 3484 3485 static const u8 tegra30_cpu_powergates[] = { 3486 TEGRA_POWERGATE_CPU, 3487 TEGRA_POWERGATE_CPU1, 3488 TEGRA_POWERGATE_CPU2, 3489 TEGRA_POWERGATE_CPU3, 3490 }; 3491 3492 static const char * const tegra30_reset_sources[] = { 3493 "POWER_ON_RESET", 3494 "WATCHDOG", 3495 "SENSOR", 3496 "SW_MAIN", 3497 "LP0" 3498 }; 3499 3500 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3501 .supports_core_domain = true, 3502 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3503 .powergates = tegra30_powergates, 3504 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3505 .cpu_powergates = tegra30_cpu_powergates, 3506 .has_tsense_reset = true, 3507 .has_gpu_clamps = false, 3508 .needs_mbist_war = false, 3509 .has_io_pad_wren = true, 3510 .maybe_tz_only = false, 3511 .num_io_pads = 0, 3512 .io_pads = NULL, 3513 .num_pin_descs = 0, 3514 .pin_descs = NULL, 3515 .regs = &tegra20_pmc_regs, 3516 .init = tegra20_pmc_init, 3517 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3518 .powergate_set = tegra20_powergate_set, 3519 .reset_sources = tegra30_reset_sources, 3520 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3521 .reset_levels = NULL, 3522 .num_reset_levels = 0, 3523 .pmc_clks_data = tegra_pmc_clks_data, 3524 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3525 .has_blink_output = true, 3526 .has_usb_sleepwalk = true, 3527 .has_single_mmio_aperture = true, 3528 }; 3529 3530 static const char * const tegra114_powergates[] = { 3531 [TEGRA_POWERGATE_CPU] = "crail", 3532 [TEGRA_POWERGATE_3D] = "td", 3533 [TEGRA_POWERGATE_VENC] = "venc", 3534 [TEGRA_POWERGATE_VDEC] = "vdec", 3535 [TEGRA_POWERGATE_MPE] = "mpe", 3536 [TEGRA_POWERGATE_HEG] = "heg", 3537 [TEGRA_POWERGATE_CPU1] = "cpu1", 3538 [TEGRA_POWERGATE_CPU2] = "cpu2", 3539 [TEGRA_POWERGATE_CPU3] = "cpu3", 3540 [TEGRA_POWERGATE_CELP] = "celp", 3541 [TEGRA_POWERGATE_CPU0] = "cpu0", 3542 [TEGRA_POWERGATE_C0NC] = "c0nc", 3543 [TEGRA_POWERGATE_C1NC] = "c1nc", 3544 [TEGRA_POWERGATE_DIS] = "dis", 3545 [TEGRA_POWERGATE_DISB] = "disb", 3546 [TEGRA_POWERGATE_XUSBA] = "xusba", 3547 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3548 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3549 }; 3550 3551 static const u8 tegra114_cpu_powergates[] = { 3552 TEGRA_POWERGATE_CPU0, 3553 TEGRA_POWERGATE_CPU1, 3554 TEGRA_POWERGATE_CPU2, 3555 TEGRA_POWERGATE_CPU3, 3556 }; 3557 3558 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3559 .supports_core_domain = true, 3560 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3561 .powergates = tegra114_powergates, 3562 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3563 .cpu_powergates = tegra114_cpu_powergates, 3564 .has_tsense_reset = true, 3565 .has_gpu_clamps = false, 3566 .needs_mbist_war = false, 3567 .has_io_pad_wren = true, 3568 .maybe_tz_only = false, 3569 .num_io_pads = 0, 3570 .io_pads = NULL, 3571 .num_pin_descs = 0, 3572 .pin_descs = NULL, 3573 .regs = &tegra20_pmc_regs, 3574 .init = tegra20_pmc_init, 3575 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3576 .powergate_set = tegra114_powergate_set, 3577 .reset_sources = tegra30_reset_sources, 3578 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3579 .reset_levels = NULL, 3580 .num_reset_levels = 0, 3581 .pmc_clks_data = tegra_pmc_clks_data, 3582 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3583 .has_blink_output = true, 3584 .has_usb_sleepwalk = true, 3585 .has_single_mmio_aperture = true, 3586 }; 3587 3588 static const char * const tegra124_powergates[] = { 3589 [TEGRA_POWERGATE_CPU] = "crail", 3590 [TEGRA_POWERGATE_3D] = "3d", 3591 [TEGRA_POWERGATE_VENC] = "venc", 3592 [TEGRA_POWERGATE_PCIE] = "pcie", 3593 [TEGRA_POWERGATE_VDEC] = "vdec", 3594 [TEGRA_POWERGATE_MPE] = "mpe", 3595 [TEGRA_POWERGATE_HEG] = "heg", 3596 [TEGRA_POWERGATE_SATA] = "sata", 3597 [TEGRA_POWERGATE_CPU1] = "cpu1", 3598 [TEGRA_POWERGATE_CPU2] = "cpu2", 3599 [TEGRA_POWERGATE_CPU3] = "cpu3", 3600 [TEGRA_POWERGATE_CELP] = "celp", 3601 [TEGRA_POWERGATE_CPU0] = "cpu0", 3602 [TEGRA_POWERGATE_C0NC] = "c0nc", 3603 [TEGRA_POWERGATE_C1NC] = "c1nc", 3604 [TEGRA_POWERGATE_SOR] = "sor", 3605 [TEGRA_POWERGATE_DIS] = "dis", 3606 [TEGRA_POWERGATE_DISB] = "disb", 3607 [TEGRA_POWERGATE_XUSBA] = "xusba", 3608 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3609 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3610 [TEGRA_POWERGATE_VIC] = "vic", 3611 [TEGRA_POWERGATE_IRAM] = "iram", 3612 }; 3613 3614 static const u8 tegra124_cpu_powergates[] = { 3615 TEGRA_POWERGATE_CPU0, 3616 TEGRA_POWERGATE_CPU1, 3617 TEGRA_POWERGATE_CPU2, 3618 TEGRA_POWERGATE_CPU3, 3619 }; 3620 3621 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _name) \ 3622 ((struct tegra_io_pad_soc) { \ 3623 .id = (_id), \ 3624 .dpd = (_dpd), \ 3625 .request = (_request), \ 3626 .status = (_status), \ 3627 .name = (_name), \ 3628 }) 3629 3630 #define TEGRA_IO_PAD_VCTRL(_id, _offset, _ena_3v3) \ 3631 ((struct tegra_io_pad_vctrl) { \ 3632 .id = (_id), \ 3633 .offset = (_offset), \ 3634 .ena_3v3 = (_ena_3v3), \ 3635 .ena_1v8 = 0, \ 3636 }) 3637 3638 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3639 ((struct pinctrl_pin_desc) { \ 3640 .number = (_id), \ 3641 .name = (_name), \ 3642 }) 3643 3644 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3645 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, "audio"), 3646 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, "bb"), 3647 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, "cam"), 3648 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, "comp"), 3649 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, "csia"), 3650 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, "csib"), 3651 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, "csie"), 3652 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, "dsi"), 3653 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, "dsib"), 3654 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, "dsic"), 3655 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, "dsid"), 3656 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, "hdmi"), 3657 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, "hsic"), 3658 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, "hv"), 3659 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, "lvds"), 3660 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, "mipi-bias"), 3661 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, "nand"), 3662 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, "pex-bias"), 3663 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, "pex-clk1"), 3664 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, "pex-clk2"), 3665 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, "pex-cntrl"), 3666 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, "sdmmc1"), 3667 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, "sdmmc3"), 3668 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, "sdmmc4"), 3669 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, "sys_ddc"), 3670 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, "uart"), 3671 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, "usb0"), 3672 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, "usb1"), 3673 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, "usb2"), 3674 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, "usb_bias"), 3675 }; 3676 3677 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3691 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3692 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3693 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3694 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3695 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3696 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3697 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3698 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3699 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3700 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3701 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3702 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3703 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3704 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3705 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3706 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3707 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3708 }; 3709 3710 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3711 .supports_core_domain = false, 3712 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3713 .powergates = tegra124_powergates, 3714 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3715 .cpu_powergates = tegra124_cpu_powergates, 3716 .has_tsense_reset = true, 3717 .has_gpu_clamps = true, 3718 .needs_mbist_war = false, 3719 .has_io_pad_wren = true, 3720 .maybe_tz_only = false, 3721 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3722 .io_pads = tegra124_io_pads, 3723 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3724 .pin_descs = tegra124_pin_descs, 3725 .regs = &tegra20_pmc_regs, 3726 .init = tegra20_pmc_init, 3727 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3728 .powergate_set = tegra114_powergate_set, 3729 .reset_sources = tegra30_reset_sources, 3730 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3731 .reset_levels = NULL, 3732 .num_reset_levels = 0, 3733 .pmc_clks_data = tegra_pmc_clks_data, 3734 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3735 .has_blink_output = true, 3736 .has_usb_sleepwalk = true, 3737 .has_single_mmio_aperture = true, 3738 }; 3739 3740 static const char * const tegra210_powergates[] = { 3741 [TEGRA_POWERGATE_CPU] = "crail", 3742 [TEGRA_POWERGATE_3D] = "3d", 3743 [TEGRA_POWERGATE_VENC] = "venc", 3744 [TEGRA_POWERGATE_PCIE] = "pcie", 3745 [TEGRA_POWERGATE_MPE] = "mpe", 3746 [TEGRA_POWERGATE_SATA] = "sata", 3747 [TEGRA_POWERGATE_CPU1] = "cpu1", 3748 [TEGRA_POWERGATE_CPU2] = "cpu2", 3749 [TEGRA_POWERGATE_CPU3] = "cpu3", 3750 [TEGRA_POWERGATE_CPU0] = "cpu0", 3751 [TEGRA_POWERGATE_C0NC] = "c0nc", 3752 [TEGRA_POWERGATE_SOR] = "sor", 3753 [TEGRA_POWERGATE_DIS] = "dis", 3754 [TEGRA_POWERGATE_DISB] = "disb", 3755 [TEGRA_POWERGATE_XUSBA] = "xusba", 3756 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3757 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3758 [TEGRA_POWERGATE_VIC] = "vic", 3759 [TEGRA_POWERGATE_IRAM] = "iram", 3760 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3761 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3762 [TEGRA_POWERGATE_AUD] = "aud", 3763 [TEGRA_POWERGATE_DFD] = "dfd", 3764 [TEGRA_POWERGATE_VE2] = "ve2", 3765 }; 3766 3767 static const u8 tegra210_cpu_powergates[] = { 3768 TEGRA_POWERGATE_CPU0, 3769 TEGRA_POWERGATE_CPU1, 3770 TEGRA_POWERGATE_CPU2, 3771 TEGRA_POWERGATE_CPU3, 3772 }; 3773 3774 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3775 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, "audio"), 3776 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, "audio-hv"), 3777 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, "cam"), 3778 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, "csia"), 3779 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, "csib"), 3780 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, "csic"), 3781 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, "csid"), 3782 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, "csie"), 3783 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, "csif"), 3784 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, "dbg"), 3785 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, "debug-nonao"), 3786 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, "dmic"), 3787 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, "dp"), 3788 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, "dsi"), 3789 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, "dsib"), 3790 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, "dsic"), 3791 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, "dsid"), 3792 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, "emmc"), 3793 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, "emmc2"), 3794 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, "gpio"), 3795 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, "hdmi"), 3796 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, "hsic"), 3797 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, "lvds"), 3798 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, "mipi-bias"), 3799 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, "pex-bias"), 3800 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, "pex-clk1"), 3801 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, "pex-clk2"), 3802 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, "pex-cntrl"), 3803 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, "sdmmc1"), 3804 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, "sdmmc3"), 3805 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, "spi"), 3806 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, "spi-hv"), 3807 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, "uart"), 3808 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, "usb0"), 3809 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, "usb1"), 3810 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, "usb2"), 3811 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, "usb3"), 3812 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, "usb-bias"), 3813 }; 3814 3815 static const struct tegra_io_pad_vctrl tegra210_io_pad_vctrls[] = { 3816 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO, PMC_PWR_DET_VALUE, 5), 3817 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_PWR_DET_VALUE, 18), 3818 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_CAM, PMC_PWR_DET_VALUE, 10), 3819 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DBG, PMC_PWR_DET_VALUE, 19), 3820 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC, PMC_PWR_DET_VALUE, 20), 3821 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_GPIO, PMC_PWR_DET_VALUE, 21), 3822 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_PEX_CNTRL, PMC_PWR_DET_VALUE, 11), 3823 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1, PMC_PWR_DET_VALUE, 12), 3824 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3, PMC_PWR_DET_VALUE, 13), 3825 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI, PMC_PWR_DET_VALUE, 22), 3826 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI_HV, PMC_PWR_DET_VALUE, 23), 3827 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_UART, PMC_PWR_DET_VALUE, 2), 3828 }; 3829 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3830 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3831 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3832 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3833 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3834 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3835 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3836 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3837 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3838 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3839 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3840 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3841 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3842 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3843 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3844 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3845 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3846 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3847 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3848 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3849 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3850 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3851 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3852 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3853 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3854 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3855 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3856 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3857 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3858 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3859 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3860 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3861 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3862 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3863 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3864 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3865 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3866 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3867 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3868 }; 3869 3870 static const char * const tegra210_reset_sources[] = { 3871 "POWER_ON_RESET", 3872 "WATCHDOG", 3873 "SENSOR", 3874 "SW_MAIN", 3875 "LP0", 3876 "AOTAG" 3877 }; 3878 3879 static const struct tegra_wake_event tegra210_wake_events[] = { 3880 TEGRA_WAKE_IRQ("rtc", 16, 2), 3881 TEGRA_WAKE_IRQ("pmu", 51, 86), 3882 }; 3883 3884 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3885 .supports_core_domain = false, 3886 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3887 .powergates = tegra210_powergates, 3888 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3889 .cpu_powergates = tegra210_cpu_powergates, 3890 .has_tsense_reset = true, 3891 .has_gpu_clamps = true, 3892 .needs_mbist_war = true, 3893 .has_io_pad_wren = true, 3894 .maybe_tz_only = true, 3895 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3896 .io_pads = tegra210_io_pads, 3897 .num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls), 3898 .io_pad_vctrls = tegra210_io_pad_vctrls, 3899 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3900 .pin_descs = tegra210_pin_descs, 3901 .regs = &tegra20_pmc_regs, 3902 .init = tegra20_pmc_init, 3903 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3904 .powergate_set = tegra114_powergate_set, 3905 .irq_set_wake = tegra210_pmc_irq_set_wake, 3906 .irq_set_type = tegra210_pmc_irq_set_type, 3907 .reset_sources = tegra210_reset_sources, 3908 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3909 .reset_levels = NULL, 3910 .num_reset_levels = 0, 3911 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3912 .wake_events = tegra210_wake_events, 3913 .pmc_clks_data = tegra_pmc_clks_data, 3914 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3915 .has_blink_output = true, 3916 .has_usb_sleepwalk = true, 3917 .has_single_mmio_aperture = true, 3918 }; 3919 3920 static const char * const tegra210b01_powergates[] = { 3921 [TEGRA_POWERGATE_CPU] = "crail", 3922 [TEGRA_POWERGATE_3D] = "3d", 3923 [TEGRA_POWERGATE_VENC] = "venc", 3924 [TEGRA_POWERGATE_PCIE] = "pcie", 3925 [TEGRA_POWERGATE_MPE] = "mpe", 3926 [TEGRA_POWERGATE_CPU1] = "cpu1", 3927 [TEGRA_POWERGATE_CPU2] = "cpu2", 3928 [TEGRA_POWERGATE_CPU3] = "cpu3", 3929 [TEGRA_POWERGATE_CPU0] = "cpu0", 3930 [TEGRA_POWERGATE_C0NC] = "c0nc", 3931 [TEGRA_POWERGATE_SOR] = "sor", 3932 [TEGRA_POWERGATE_DIS] = "dis", 3933 [TEGRA_POWERGATE_DISB] = "disb", 3934 [TEGRA_POWERGATE_XUSBA] = "xusba", 3935 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3936 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3937 [TEGRA_POWERGATE_VIC] = "vic", 3938 [TEGRA_POWERGATE_IRAM] = "iram", 3939 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3940 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3941 [TEGRA_POWERGATE_AUD] = "aud", 3942 [TEGRA_POWERGATE_DFD] = "dfd", 3943 }; 3944 3945 static const struct tegra_pmc_soc tegra210b01_pmc_soc = { 3946 .supports_core_domain = false, 3947 .num_powergates = ARRAY_SIZE(tegra210b01_powergates), 3948 .powergates = tegra210b01_powergates, 3949 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3950 .cpu_powergates = tegra210_cpu_powergates, 3951 .has_tsense_reset = true, 3952 .has_gpu_clamps = true, 3953 .needs_mbist_war = false, 3954 .has_io_pad_wren = true, 3955 .maybe_tz_only = true, 3956 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3957 .io_pads = tegra210_io_pads, 3958 .num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls), 3959 .io_pad_vctrls = tegra210_io_pad_vctrls, 3960 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3961 .pin_descs = tegra210_pin_descs, 3962 .regs = &tegra20_pmc_regs, 3963 .init = tegra20_pmc_init, 3964 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3965 .powergate_set = tegra114_powergate_set, 3966 .irq_set_wake = tegra210_pmc_irq_set_wake, 3967 .irq_set_type = tegra210_pmc_irq_set_type, 3968 .reset_sources = tegra210_reset_sources, 3969 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3970 .reset_levels = NULL, 3971 .num_reset_levels = 0, 3972 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3973 .wake_events = tegra210_wake_events, 3974 .pmc_clks_data = tegra_pmc_clks_data, 3975 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3976 .has_blink_output = true, 3977 .has_usb_sleepwalk = true, 3978 .has_single_mmio_aperture = true, 3979 }; 3980 3981 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3982 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"), 3983 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"), 3984 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, "dsi"), 3985 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, "mipi-bias"), 3986 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, "pex-clk-bias"), 3987 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, "pex-clk3"), 3988 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, "pex-clk2"), 3989 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, "pex-clk1"), 3990 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, "usb0"), 3991 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, "usb1"), 3992 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, "usb2"), 3993 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, "usb-bias"), 3994 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, "uart"), 3995 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, "audio"), 3996 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, "hsic"), 3997 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, "dbg"), 3998 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, "hdmi-dp0"), 3999 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, "hdmi-dp1"), 4000 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, "pex-cntrl"), 4001 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, "sdmmc2-hv"), 4002 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, "sdmmc4"), 4003 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, "cam"), 4004 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, "dsib"), 4005 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, "dsic"), 4006 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, "dsid"), 4007 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, "csic"), 4008 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, "csid"), 4009 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, "csie"), 4010 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, "csif"), 4011 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, "spi"), 4012 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, "ufs"), 4013 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, "dmic-hv"), 4014 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, "edp"), 4015 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, "sdmmc1-hv"), 4016 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, "sdmmc3-hv"), 4017 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, "conn"), 4018 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, "audio-hv"), 4019 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4020 }; 4021 4022 static const struct tegra_io_pad_vctrl tegra186_io_pad_vctrls[] = { 4023 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC2_HV, PMC_IMPL_E_33V_PWR, 5), 4024 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC_HV, PMC_IMPL_E_33V_PWR, 2), 4025 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4026 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4027 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4028 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4029 }; 4030 4031 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 4041 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 4042 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 4043 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 4044 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4050 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4053 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4054 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 4055 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 4056 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 4057 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4058 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4059 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4060 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4061 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4062 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4063 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 4064 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4065 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4066 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4067 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4068 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4069 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4070 }; 4071 4072 static const struct tegra_pmc_regs tegra186_pmc_regs = { 4073 .scratch0 = 0x2000, 4074 .rst_status = 0x70, 4075 .rst_source_shift = 0x2, 4076 .rst_source_mask = 0x3c, 4077 .rst_level_shift = 0x0, 4078 .rst_level_mask = 0x3, 4079 .aowake_mask_w = 0x180, 4080 .aowake_status_w = 0x30c, 4081 .aowake_status_r = 0x48c, 4082 .aowake_tier2_routing = 0x4cc, 4083 .aowake_sw_status_w = 0x49c, 4084 .aowake_sw_status = 0x4a0, 4085 .aowake_latch_sw = 0x498, 4086 .aowake_ctrl = 0x4f4, 4087 }; 4088 4089 static void tegra186_pmc_init(struct tegra_pmc *pmc) 4090 { 4091 pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; 4092 pmc->syscore.data = pmc; 4093 register_syscore(&pmc->syscore); 4094 } 4095 4096 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 4097 struct device_node *np) 4098 { 4099 struct resource regs; 4100 void __iomem *wake; 4101 u32 value; 4102 int index; 4103 4104 index = of_property_match_string(np, "reg-names", "wake"); 4105 if (index < 0) { 4106 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 4107 return; 4108 } 4109 4110 of_address_to_resource(np, index, ®s); 4111 4112 wake = ioremap(regs.start, resource_size(®s)); 4113 if (!wake) { 4114 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 4115 return; 4116 } 4117 4118 value = readl(wake + pmc->soc->regs->aowake_ctrl); 4119 4120 if (pmc->invert_irq) 4121 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 4122 else 4123 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 4124 4125 writel(value, wake + pmc->soc->regs->aowake_ctrl); 4126 4127 iounmap(wake); 4128 } 4129 4130 static const char * const tegra186_reset_sources[] = { 4131 "SYS_RESET", 4132 "AOWDT", 4133 "MCCPLEXWDT", 4134 "BPMPWDT", 4135 "SCEWDT", 4136 "SPEWDT", 4137 "APEWDT", 4138 "BCCPLEXWDT", 4139 "SENSOR", 4140 "AOTAG", 4141 "VFSENSOR", 4142 "SWREST", 4143 "SC7", 4144 "HSM", 4145 "CORESIGHT" 4146 }; 4147 4148 static const char * const tegra186_reset_levels[] = { 4149 "L0", "L1", "L2", "WARM" 4150 }; 4151 4152 static const struct tegra_wake_event tegra186_wake_events[] = { 4153 TEGRA_WAKE_IRQ("pmu", 24, 209), 4154 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 4155 TEGRA_WAKE_IRQ("rtc", 73, 10), 4156 }; 4157 4158 static const struct tegra_pmc_soc tegra186_pmc_soc = { 4159 .supports_core_domain = false, 4160 .num_powergates = 0, 4161 .powergates = NULL, 4162 .num_cpu_powergates = 0, 4163 .cpu_powergates = NULL, 4164 .has_tsense_reset = false, 4165 .has_gpu_clamps = false, 4166 .needs_mbist_war = false, 4167 .has_io_pad_wren = false, 4168 .maybe_tz_only = false, 4169 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 4170 .io_pads = tegra186_io_pads, 4171 .num_io_pad_vctrls = ARRAY_SIZE(tegra186_io_pad_vctrls), 4172 .io_pad_vctrls = tegra186_io_pad_vctrls, 4173 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 4174 .pin_descs = tegra186_pin_descs, 4175 .regs = &tegra186_pmc_regs, 4176 .init = tegra186_pmc_init, 4177 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4178 .set_wake_filters = tegra186_pmc_set_wake_filters, 4179 .irq_set_wake = tegra186_pmc_irq_set_wake, 4180 .irq_set_type = tegra186_pmc_irq_set_type, 4181 .reset_sources = tegra186_reset_sources, 4182 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 4183 .reset_levels = tegra186_reset_levels, 4184 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4185 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 4186 .wake_events = tegra186_wake_events, 4187 .max_wake_events = 96, 4188 .max_wake_vectors = 3, 4189 .pmc_clks_data = NULL, 4190 .num_pmc_clks = 0, 4191 .has_blink_output = false, 4192 .has_usb_sleepwalk = false, 4193 .has_single_mmio_aperture = false, 4194 }; 4195 4196 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 4197 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"), 4198 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"), 4199 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, "mipi-bias"), 4200 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, "pex-clk-bias"), 4201 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, "pex-clk3"), 4202 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, "pex-clk2"), 4203 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, "pex-clk1"), 4204 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, "eqos"), 4205 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, "pex-clk-2-bias"), 4206 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, "pex-clk-2"), 4207 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, "dap3"), 4208 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, "dap5"), 4209 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, "uart"), 4210 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, "pwr-ctl"), 4211 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, "soc-gpio53"), 4212 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, "audio"), 4213 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, "gp-pwm2"), 4214 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, "gp-pwm3"), 4215 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, "soc-gpio12"), 4216 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, "soc-gpio13"), 4217 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, "soc-gpio10"), 4218 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, "uart4"), 4219 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, "uart5"), 4220 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, "dbg"), 4221 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, "hdmi-dp3"), 4222 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, "hdmi-dp2"), 4223 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, "hdmi-dp0"), 4224 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, "hdmi-dp1"), 4225 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, "pex-cntrl"), 4226 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, "pex-ctl2"), 4227 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, "pex-l0-rst"), 4228 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, "pex-l1-rst"), 4229 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, "sdmmc4"), 4230 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, "pex-l5-rst"), 4231 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, "cam"), 4232 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, "csic"), 4233 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, "csid"), 4234 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, "csie"), 4235 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, "csif"), 4236 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, "spi"), 4237 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, "ufs"), 4238 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, "csig"), 4239 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, "csih"), 4240 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, "edp"), 4241 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, "sdmmc1-hv"), 4242 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, "sdmmc3-hv"), 4243 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, "conn"), 4244 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, "audio-hv"), 4245 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4246 }; 4247 4248 static const struct tegra_io_pad_vctrl tegra194_io_pad_vctrls[] = { 4249 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4250 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4251 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4252 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4253 }; 4254 4255 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 4256 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4257 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4258 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4259 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4260 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4261 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4262 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4263 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4264 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4265 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4266 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4267 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4268 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4269 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4270 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4271 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4272 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4273 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4274 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4275 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4276 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4277 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4278 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4279 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4280 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4281 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4282 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4283 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4284 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4285 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4286 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4287 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4288 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4289 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4290 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4291 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4292 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4293 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4294 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4295 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4296 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4297 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4298 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4299 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4300 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4301 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4302 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4303 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4304 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4305 }; 4306 4307 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4308 .scratch0 = 0x2000, 4309 .rst_status = 0x70, 4310 .rst_source_shift = 0x2, 4311 .rst_source_mask = 0x7c, 4312 .rst_level_shift = 0x0, 4313 .rst_level_mask = 0x3, 4314 .aowake_mask_w = 0x180, 4315 .aowake_status_w = 0x30c, 4316 .aowake_status_r = 0x48c, 4317 .aowake_tier2_routing = 0x4cc, 4318 .aowake_sw_status_w = 0x49c, 4319 .aowake_sw_status = 0x4a0, 4320 .aowake_latch_sw = 0x498, 4321 .aowake_ctrl = 0x4f4, 4322 }; 4323 4324 static const char * const tegra194_reset_sources[] = { 4325 "SYS_RESET_N", 4326 "AOWDT", 4327 "BCCPLEXWDT", 4328 "BPMPWDT", 4329 "SCEWDT", 4330 "SPEWDT", 4331 "APEWDT", 4332 "LCCPLEXWDT", 4333 "SENSOR", 4334 "AOTAG", 4335 "VFSENSOR", 4336 "MAINSWRST", 4337 "SC7", 4338 "HSM", 4339 "CSITE", 4340 "RCEWDT", 4341 "PVA0WDT", 4342 "PVA1WDT", 4343 "L1A_ASYNC", 4344 "BPMPBOOT", 4345 "FUSECRC", 4346 }; 4347 4348 static const struct tegra_wake_event tegra194_wake_events[] = { 4349 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4350 TEGRA_WAKE_IRQ("pmu", 24, 209), 4351 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4352 TEGRA_WAKE_IRQ("rtc", 73, 10), 4353 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4354 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4355 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4356 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4357 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4358 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4359 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4360 }; 4361 4362 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4363 .supports_core_domain = false, 4364 .num_powergates = 0, 4365 .powergates = NULL, 4366 .num_cpu_powergates = 0, 4367 .cpu_powergates = NULL, 4368 .has_tsense_reset = false, 4369 .has_gpu_clamps = false, 4370 .needs_mbist_war = false, 4371 .has_io_pad_wren = false, 4372 .maybe_tz_only = false, 4373 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4374 .io_pads = tegra194_io_pads, 4375 .num_io_pad_vctrls = ARRAY_SIZE(tegra194_io_pad_vctrls), 4376 .io_pad_vctrls = tegra194_io_pad_vctrls, 4377 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4378 .pin_descs = tegra194_pin_descs, 4379 .regs = &tegra194_pmc_regs, 4380 .init = tegra186_pmc_init, 4381 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4382 .set_wake_filters = tegra186_pmc_set_wake_filters, 4383 .irq_set_wake = tegra186_pmc_irq_set_wake, 4384 .irq_set_type = tegra186_pmc_irq_set_type, 4385 .reset_sources = tegra194_reset_sources, 4386 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4387 .reset_levels = tegra186_reset_levels, 4388 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4389 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4390 .wake_events = tegra194_wake_events, 4391 .max_wake_events = 96, 4392 .max_wake_vectors = 3, 4393 .pmc_clks_data = NULL, 4394 .num_pmc_clks = 0, 4395 .has_blink_output = false, 4396 .has_usb_sleepwalk = false, 4397 .has_single_mmio_aperture = false, 4398 }; 4399 4400 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4401 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, "csia"), 4402 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, "csib"), 4403 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, "hdmi-dp0"), 4404 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, "csic"), 4405 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, "csid"), 4406 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, "csie"), 4407 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, "csif"), 4408 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, "ufs"), 4409 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, "edp"), 4410 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, "sdmmc1-hv"), 4411 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc3-hv"), 4412 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "audio-hv"), 4413 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4414 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, "csig"), 4415 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, "csih"), 4416 }; 4417 4418 static const struct tegra_io_pad_vctrl tegra234_io_pad_vctrls[] = { 4419 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4420 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4421 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4422 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4423 }; 4424 4425 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4426 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4427 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4428 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4429 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4430 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4431 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4432 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4433 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4434 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4435 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4436 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4437 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4438 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4439 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4440 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4441 }; 4442 4443 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4444 .scratch0 = 0x2000, 4445 .rst_status = 0x70, 4446 .rst_source_shift = 0x2, 4447 .rst_source_mask = 0xfc, 4448 .rst_level_shift = 0x0, 4449 .rst_level_mask = 0x3, 4450 .aowake_mask_w = 0x180, 4451 .aowake_status_w = 0x30c, 4452 .aowake_status_r = 0x48c, 4453 .aowake_tier2_routing = 0x4cc, 4454 .aowake_sw_status_w = 0x49c, 4455 .aowake_sw_status = 0x4a0, 4456 .aowake_latch_sw = 0x498, 4457 .aowake_ctrl = 0x4f4, 4458 }; 4459 4460 static const char * const tegra234_reset_sources[] = { 4461 "SYS_RESET_N", /* 0x0 */ 4462 "AOWDT", 4463 "BCCPLEXWDT", 4464 "BPMPWDT", 4465 "SCEWDT", 4466 "SPEWDT", 4467 "APEWDT", 4468 "LCCPLEXWDT", 4469 "SENSOR", /* 0x8 */ 4470 NULL, 4471 NULL, 4472 "MAINSWRST", 4473 "SC7", 4474 "HSM", 4475 NULL, 4476 "RCEWDT", 4477 NULL, /* 0x10 */ 4478 NULL, 4479 NULL, 4480 "BPMPBOOT", 4481 "FUSECRC", 4482 "DCEWDT", 4483 "PSCWDT", 4484 "PSC", 4485 "CSITE_SW", /* 0x18 */ 4486 "POD", 4487 "SCPM", 4488 "VREFRO_POWERBAD", 4489 "VMON", 4490 "FMON", 4491 "FSI_R5WDT", 4492 "FSI_THERM", 4493 "FSI_R52C0WDT", /* 0x20 */ 4494 "FSI_R52C1WDT", 4495 "FSI_R52C2WDT", 4496 "FSI_R52C3WDT", 4497 "FSI_FMON", 4498 "FSI_VMON", /* 0x25 */ 4499 }; 4500 4501 static const struct tegra_wake_event tegra234_wake_events[] = { 4502 TEGRA_WAKE_GPIO("pcie-wake", 1, 0, TEGRA234_MAIN_GPIO(L, 2)), 4503 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4504 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4505 TEGRA_WAKE_IRQ("pmu", 24, 209), 4506 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4507 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4508 TEGRA_WAKE_IRQ("rtc", 73, 10), 4509 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4510 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4511 TEGRA_WAKE_IRQ("usb3-port-2-3", 78, 167), 4512 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4513 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4514 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4515 TEGRA_WAKE_IRQ("usb2-port-3", 82, 167), 4516 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4517 }; 4518 4519 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4520 .supports_core_domain = false, 4521 .num_powergates = 0, 4522 .powergates = NULL, 4523 .num_cpu_powergates = 0, 4524 .cpu_powergates = NULL, 4525 .has_tsense_reset = false, 4526 .has_gpu_clamps = false, 4527 .needs_mbist_war = false, 4528 .has_io_pad_wren = false, 4529 .maybe_tz_only = false, 4530 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4531 .io_pads = tegra234_io_pads, 4532 .num_io_pad_vctrls = ARRAY_SIZE(tegra234_io_pad_vctrls), 4533 .io_pad_vctrls = tegra234_io_pad_vctrls, 4534 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4535 .pin_descs = tegra234_pin_descs, 4536 .regs = &tegra234_pmc_regs, 4537 .init = tegra186_pmc_init, 4538 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4539 .set_wake_filters = tegra186_pmc_set_wake_filters, 4540 .irq_set_wake = tegra186_pmc_irq_set_wake, 4541 .irq_set_type = tegra186_pmc_irq_set_type, 4542 .reset_sources = tegra234_reset_sources, 4543 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4544 .reset_levels = tegra186_reset_levels, 4545 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4546 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4547 .wake_events = tegra234_wake_events, 4548 .max_wake_events = 96, 4549 .max_wake_vectors = 3, 4550 .pmc_clks_data = NULL, 4551 .num_pmc_clks = 0, 4552 .has_blink_output = false, 4553 .has_single_mmio_aperture = false, 4554 }; 4555 4556 static const struct tegra_io_pad_soc tegra238_io_pads[] = { 4557 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe028, 0xe02c, "hdmi-dp0"), 4558 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe06c, 0xe070, "ufs"), 4559 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 2, 0xe040, 0xe044, "edp"), 4560 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe058, 0xe05c, "sdmmc1-hv"), 4561 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc3-hv"), 4562 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "audio-hv"), 4563 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), 4564 }; 4565 4566 static const struct tegra_io_pad_vctrl tegra238_io_pad_vctrls[] = { 4567 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), 4568 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), 4569 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), 4570 TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), 4571 }; 4572 4573 static const struct pinctrl_pin_desc tegra238_pin_descs[] = { 4574 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4575 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4576 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4577 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4578 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4579 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4580 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4581 }; 4582 4583 static const struct tegra_pmc_regs tegra238_pmc_regs = { 4584 .scratch0 = 0x2000, 4585 .rst_status = 0x70, 4586 .rst_source_shift = 0x2, 4587 .rst_source_mask = 0xfc, 4588 .rst_level_shift = 0x0, 4589 .rst_level_mask = 0x3, 4590 .aowake_mask_w = 0x180, 4591 .aowake_status_w = 0x30c, 4592 .aowake_status_r = 0x48c, 4593 .aowake_tier2_routing = 0x4cc, 4594 .aowake_sw_status_w = 0x49c, 4595 .aowake_sw_status = 0x4a0, 4596 .aowake_latch_sw = 0x498, 4597 .aowake_ctrl = 0x4f4, 4598 }; 4599 4600 static const char * const tegra238_reset_sources[] = { 4601 "SYS_RESET_N", /* 0 */ 4602 "AOWDT", 4603 NULL, 4604 "BPMPWDT", 4605 NULL, 4606 "SPEWDT", /* 5 */ 4607 NULL, 4608 NULL, 4609 "SENSOR", 4610 NULL, 4611 NULL, /* 10 */ 4612 "MAINSWRST", 4613 "SC7", 4614 NULL, 4615 NULL, 4616 NULL, /* 15 */ 4617 NULL, 4618 NULL, 4619 "RTC_XTAL_CSDC", 4620 "BPMPBOOT", 4621 "FUSECRC", /* 20 */ 4622 NULL, 4623 "PSCWDT", 4624 "PSC_SW", 4625 "CSITE_SW", 4626 NULL, /* 25 */ 4627 NULL, 4628 "VREFRO_POWERBAD", 4629 NULL, 4630 NULL, 4631 NULL, /* 30 */ 4632 NULL, 4633 NULL, 4634 NULL, 4635 NULL, 4636 NULL, /* 35 */ 4637 NULL, 4638 NULL, 4639 "TOP0WDT", 4640 "TOP1WDT", 4641 "TOP2WDT", /* 40 */ 4642 "APE_C0WDT", 4643 "APE_C1WDT", 4644 "APE_C2WDT", 4645 "APE_C3WDT", 4646 "SCPM_SOC_XTAL", /* 45 */ 4647 "SCPM_RTC_XTAL", 4648 "SCPM_BPMP_CORE_CLK", 4649 "SCPM_PSC_SE_CLK", 4650 "FMON_32K", 4651 "FMON_OSC", /* 50 */ 4652 "VMON_SOC", 4653 "VMON_CPU0", 4654 NULL, 4655 "POD_CPU", 4656 "POD_GPU", /* 55 */ 4657 "POD_RTC", 4658 NULL, 4659 "POD_IO", 4660 "POD_PLUS_SOC", 4661 "POD_PLUS_IO_VMON", /* 60 */ 4662 "POD_PLUS_IO_PSCPLL", 4663 "VMON_PLUS_0", 4664 "VMON_PLUS_1", /* 63 */ 4665 }; 4666 4667 static const struct tegra_wake_event tegra238_wake_events[] = { 4668 TEGRA_WAKE_IRQ("rtc", 73, 10), 4669 TEGRA_WAKE_IRQ("pmu", 24, 209), 4670 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4671 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4672 TEGRA_WAKE_IRQ("usb3-port-2", 78, 167), 4673 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4674 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4675 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4676 }; 4677 4678 static const struct tegra_pmc_soc tegra238_pmc_soc = { 4679 .num_powergates = 0, 4680 .powergates = NULL, 4681 .num_cpu_powergates = 0, 4682 .cpu_powergates = NULL, 4683 .has_tsense_reset = false, 4684 .has_gpu_clamps = false, 4685 .needs_mbist_war = false, 4686 .has_io_pad_wren = false, 4687 .maybe_tz_only = false, 4688 .num_io_pads = ARRAY_SIZE(tegra238_io_pads), 4689 .io_pads = tegra238_io_pads, 4690 .num_io_pad_vctrls = ARRAY_SIZE(tegra238_io_pad_vctrls), 4691 .io_pad_vctrls = tegra238_io_pad_vctrls, 4692 .num_pin_descs = ARRAY_SIZE(tegra238_pin_descs), 4693 .pin_descs = tegra238_pin_descs, 4694 .regs = &tegra238_pmc_regs, 4695 .init = tegra186_pmc_init, 4696 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4697 .set_wake_filters = tegra186_pmc_set_wake_filters, 4698 .irq_set_wake = tegra186_pmc_irq_set_wake, 4699 .irq_set_type = tegra186_pmc_irq_set_type, 4700 .reset_sources = tegra238_reset_sources, 4701 .num_reset_sources = ARRAY_SIZE(tegra238_reset_sources), 4702 .reset_levels = tegra186_reset_levels, 4703 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4704 .num_wake_events = ARRAY_SIZE(tegra238_wake_events), 4705 .wake_events = tegra238_wake_events, 4706 .max_wake_events = 96, 4707 .max_wake_vectors = 3, 4708 .pmc_clks_data = NULL, 4709 .num_pmc_clks = 0, 4710 .has_blink_output = false, 4711 .has_single_mmio_aperture = false, 4712 }; 4713 4714 #define TEGRA264_IO_PAD_VCTRL(_id, _offset, _ena_3v3, _ena_1v8) \ 4715 ((struct tegra_io_pad_vctrl) { \ 4716 .id = (_id), \ 4717 .offset = (_offset), \ 4718 .ena_3v3 = (_ena_3v3), \ 4719 .ena_1v8 = (_ena_1v8), \ 4720 }) 4721 4722 static const struct tegra_io_pad_soc tegra264_io_pads[] = { 4723 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x41020, 0x41024, "csia"), 4724 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x41020, 0x41024, "csib"), 4725 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0x41050, 0x41054, "hdmi-dp0"), 4726 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0x41020, 0x41024, "csic"), 4727 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0x41020, 0x41024, "csid"), 4728 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0x41020, 0x41024, "csie"), 4729 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0x41020, 0x41024, "csif"), 4730 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 4, 0x41040, 0x41044, "ufs0"), 4731 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 0, 0x41028, 0x4102c, "edp"), 4732 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 0, 0x41090, 0x41094, "sdmmc1"), 4733 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc1-hv"), 4734 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0x41020, 0x41024, "csig"), 4735 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0x41020, 0x41024, "csih"), 4736 }; 4737 4738 static const struct tegra_io_pad_vctrl tegra264_io_pad_vctrls[] = { 4739 TEGRA264_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_SDMMC1_HV_PADCTL_0, 0, 0x6), 4740 }; 4741 4742 static const struct pinctrl_pin_desc tegra264_pin_descs[] = { 4743 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4744 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4745 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4746 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4747 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4748 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4749 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4750 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs0"), 4751 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4752 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 4753 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4754 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4755 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4756 }; 4757 4758 static const struct tegra_pmc_regs tegra264_pmc_regs = { 4759 .scratch0 = 0x684, 4760 .rst_status = 0x4, 4761 .rst_source_shift = 0x2, 4762 .rst_source_mask = 0x1fc, 4763 .rst_level_shift = 0x0, 4764 .rst_level_mask = 0x3, 4765 .aowake_mask_w = 0x200, 4766 .aowake_status_w = 0x410, 4767 .aowake_status_r = 0x610, 4768 .aowake_tier2_routing = 0x660, 4769 .aowake_sw_status_w = 0x624, 4770 .aowake_sw_status = 0x628, 4771 .aowake_latch_sw = 0x620, 4772 .aowake_ctrl = 0x68c, 4773 }; 4774 4775 static const char * const tegra264_reset_sources[] = { 4776 "SYS_RESET_N", /* 0x0 */ 4777 "CSDC_RTC_XTAL", 4778 "VREFRO_POWER_BAD", 4779 "SCPM_SOC_XTAL", 4780 "SCPM_RTC_XTAL", 4781 "FMON_32K", 4782 "FMON_OSC", 4783 "POD_RTC", 4784 "POD_IO", /* 0x8 */ 4785 "POD_PLUS_IO_SPLL", 4786 "POD_PLUS_SOC", 4787 "VMON_PLUS_UV", 4788 "VMON_PLUS_OV", 4789 "FUSECRC_FAULT", 4790 "OSC_FAULT", 4791 "BPMP_BOOT_FAULT", 4792 "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4793 "SCPM_PSC_SE_CLK", 4794 "VMON_SOC_MIN", 4795 "VMON_SOC_MAX", 4796 "VMON_MSS_MIN", 4797 "VMON_MSS_MAX", 4798 "POD_PLUS_IO_VMON", 4799 "NVJTAG_SEL_MONITOR", 4800 "NV_THERM_FAULT", /* 0x18 */ 4801 "FSI_THERM_FAULT", 4802 "PSC_SW", 4803 "SCPM_OESP_SE_CLK", 4804 "SCPM_SB_SE_CLK", 4805 "POD_CPU", 4806 "POD_GPU", 4807 "DCLS_GPU", 4808 "POD_MSS", /* 0x20 */ 4809 "FMON_FSI", 4810 "POD_FSI", 4811 "VMON_FSI_MIN", 4812 "VMON_FSI_MAX", 4813 "VMON_CPU0_MIN", 4814 "VMON_CPU0_MAX", 4815 "BPMP_FMON", 4816 "AO_WDT_POR", /* 0x28 */ 4817 "BPMP_WDT_POR", 4818 "AO_TKE_WDT_POR", 4819 "RCE0_WDT_POR", 4820 "RCE1_WDT_POR", 4821 "DCE_WDT_POR", 4822 "FSI_R5_WDT_POR", 4823 "FSI_R52_0_WDT_POR", 4824 "FSI_R52_1_WDT_POR", /* 0x30 */ 4825 "FSI_R52_2_WDT_POR", 4826 "FSI_R52_3_WDT_POR", 4827 "TOP_0_WDT_POR", 4828 "TOP_1_WDT_POR", 4829 "TOP_2_WDT_POR", 4830 "APE_C0_WDT_POR", 4831 "APE_C1_WDT_POR", 4832 "GPU_TKE_WDT_POR", /* 0x38 */ 4833 "PSC_WDT_POR", 4834 "OESP_WDT_POR", 4835 "SB_WDT_POR", 4836 "SW_MAIN", 4837 "L0L1_RST_OUT_N", 4838 "FSI_HSM", 4839 "CSITE_SW", 4840 "AO_WDT_DBG", /* 0x40 */ 4841 "BPMP_WDT_DBG", 4842 "AO_TKE_WDT_DBG", 4843 "RCE0_WDT_DBG", 4844 "RCE1_WDT_DBG", 4845 "DCE_WDT_DBG", 4846 "FSI_R5_WDT_DBG", 4847 "FSI_R52_0_WDT_DBG", 4848 "FSI_R52_1_WDT_DBG", /* 0x48 */ 4849 "FSI_R52_2_WDT_DBG", 4850 "FSI_R52_3_WDT_DBG", 4851 "TOP_0_WDT_DBG", 4852 "TOP_1_WDT_DBG", 4853 "TOP_2_WDT_DBG", 4854 "APE_C0_WDT_DBG", 4855 "APE_C1_WDT_DBG", 4856 "PSC_WDT_DBG", /* 0x50 */ 4857 "OESP_WDT_DBG", 4858 "SB_WDT_DBG", 4859 "TSC_0_WDT_DBG", 4860 "TSC_1_WDT_DBG", 4861 "L2_RST_OUT_N", 4862 "SC7" 4863 }; 4864 4865 static const struct tegra_wake_event tegra264_wake_events[] = { 4866 TEGRA_WAKE_IRQ("pmu", 0, 727), 4867 TEGRA_WAKE_GPIO("power", 5, 1, TEGRA264_AON_GPIO(AA, 5)), 4868 TEGRA_WAKE_IRQ("rtc", 65, 548), 4869 TEGRA_WAKE_IRQ("usb3-port-0", 79, 965), 4870 TEGRA_WAKE_IRQ("usb3-port-1", 80, 965), 4871 TEGRA_WAKE_IRQ("usb3-port-3", 82, 965), 4872 TEGRA_WAKE_IRQ("usb2-port-0", 83, 965), 4873 TEGRA_WAKE_IRQ("usb2-port-1", 84, 965), 4874 TEGRA_WAKE_IRQ("usb2-port-2", 85, 965), 4875 TEGRA_WAKE_IRQ("usb2-port-3", 86, 965), 4876 }; 4877 4878 static const struct tegra_pmc_soc tegra264_pmc_soc = { 4879 .has_io_pad_wren = false, 4880 .num_io_pads = ARRAY_SIZE(tegra264_io_pads), 4881 .io_pads = tegra264_io_pads, 4882 .num_io_pad_vctrls = ARRAY_SIZE(tegra264_io_pad_vctrls), 4883 .io_pad_vctrls = tegra264_io_pad_vctrls, 4884 .num_pin_descs = ARRAY_SIZE(tegra264_pin_descs), 4885 .pin_descs = tegra264_pin_descs, 4886 .regs = &tegra264_pmc_regs, 4887 .init = tegra186_pmc_init, 4888 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4889 .set_wake_filters = tegra186_pmc_set_wake_filters, 4890 .irq_set_wake = tegra186_pmc_irq_set_wake, 4891 .irq_set_type = tegra186_pmc_irq_set_type, 4892 .reset_sources = tegra264_reset_sources, 4893 .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4894 .reset_levels = tegra186_reset_levels, 4895 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4896 .wake_events = tegra264_wake_events, 4897 .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4898 .max_wake_events = 128, 4899 .max_wake_vectors = 4, 4900 }; 4901 4902 static const char * const tegra410_reset_sources[] = { 4903 "SYS_RESET_N", /* 0x0 */ 4904 "CSDC_RTC_XTAL", 4905 "VREFRO_POWER_BAD", 4906 "FMON_32K", 4907 "FMON_OSC", 4908 "POD_RTC", 4909 "POD_IO", 4910 "POD_PLUS_IO_SPLL", 4911 "POD_PLUS_IO_VMON", /* 0x8 */ 4912 "POD_PLUS_SOC", 4913 "VMON_PLUS_UV", 4914 "VMON_PLUS_OV", 4915 "FUSECRC_FAULT", 4916 "OSC_FAULT", 4917 "BPMP_BOOT_FAULT", 4918 "SCPM_BPMP_CORE_CLK", 4919 "SCPM_PSC_SE_CLK", /* 0x10 */ 4920 "VMON_SOC_MIN", 4921 "VMON_SOC_MAX", 4922 "NVJTAG_SEL_MONITOR", 4923 "L0_RST_REQ_N", 4924 "NV_THERM_FAULT", 4925 "PSC_SW", 4926 "POD_C2C_LPI_0", 4927 "POD_C2C_LPI_1", /* 0x18 */ 4928 "BPMP_FMON", 4929 "FMON_SPLL_OUT", 4930 "L1_RST_REQ_N", 4931 "OCP_RECOVERY", 4932 "AO_WDT_POR", 4933 "BPMP_WDT_POR", 4934 "RAS_WDT_POR", 4935 "TOP_0_WDT_POR", /* 0x20 */ 4936 "TOP_1_WDT_POR", 4937 "TOP_2_WDT_POR", 4938 "PSC_WDT_POR", 4939 "OOBHUB_WDT_POR", 4940 "MSS_SEQ_WDT_POR", 4941 "SW_MAIN", 4942 "L0L1_RST_OUT_N", 4943 "HSM", /* 0x28 */ 4944 "CSITE_SW", 4945 "AO_WDT_DBG", 4946 "BPMP_WDT_DBG", 4947 "RAS_WDT_DBG", 4948 "TOP_0_WDT_DBG", 4949 "TOP_1_WDT_DBG", 4950 "TOP_2_WDT_DBG", 4951 "PSC_WDT_DBG", /* 0x30 */ 4952 "TSC_0_WDT_DBG", 4953 "TSC_1_WDT_DBG", 4954 "OOBHUB_WDT_DBG", 4955 "MSS_SEQ_WDT_DBG", 4956 "L2_RST_REQ_N", 4957 "L2_RST_OUT_N", 4958 "SC7" 4959 }; 4960 4961 static const struct tegra_pmc_regs tegra410_pmc_regs = { 4962 .rst_status = 0x8, 4963 .rst_source_shift = 0x2, 4964 .rst_source_mask = 0xfc, 4965 .rst_level_shift = 0x0, 4966 .rst_level_mask = 0x3, 4967 }; 4968 4969 static const struct tegra_pmc_soc tegra410_pmc_soc = { 4970 .regs = &tegra410_pmc_regs, 4971 .reset_sources = tegra410_reset_sources, 4972 .num_reset_sources = ARRAY_SIZE(tegra410_reset_sources), 4973 .reset_levels = tegra186_reset_levels, 4974 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4975 }; 4976 4977 static const struct of_device_id tegra_pmc_match[] = { 4978 { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4979 { .compatible = "nvidia,tegra238-pmc", .data = &tegra238_pmc_soc }, 4980 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4981 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4982 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4983 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4984 { .compatible = "nvidia,tegra210b01-pmc", .data = &tegra210b01_pmc_soc }, 4985 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4986 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4987 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4988 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4989 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4990 { } 4991 }; 4992 4993 static const struct acpi_device_id tegra_pmc_acpi_match[] = { 4994 { .id = "NVDA2016", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc }, 4995 { } 4996 }; 4997 MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match); 4998 4999 static void tegra_pmc_sync_state(struct device *dev) 5000 { 5001 struct tegra_pmc *pmc = dev_get_drvdata(dev); 5002 struct device_node *np, *child; 5003 int err; 5004 5005 np = of_get_child_by_name(dev->of_node, "powergates"); 5006 if (!np) 5007 return; 5008 5009 for_each_child_of_node(np, child) 5010 of_genpd_sync_state(child); 5011 5012 of_node_put(np); 5013 5014 np = of_get_child_by_name(dev->of_node, "core-domain"); 5015 if (!np) 5016 return; 5017 5018 of_genpd_sync_state(np); 5019 of_node_put(np); 5020 5021 /* 5022 * Newer device-trees have power domains, but we need to prepare all 5023 * device drivers with runtime PM and OPP support first, otherwise 5024 * state syncing is unsafe. 5025 */ 5026 if (!pmc->soc->supports_core_domain) 5027 return; 5028 5029 /* 5030 * Older device-trees don't have core PD, and thus, there are 5031 * no dependencies that will block the state syncing. We shouldn't 5032 * mark the domain as synced in this case. 5033 */ 5034 pmc->core_domain_state_synced = true; 5035 5036 /* this is a no-op if core regulator isn't used */ 5037 mutex_lock(&pmc->powergates_lock); 5038 err = dev_pm_opp_sync_regulators(dev); 5039 mutex_unlock(&pmc->powergates_lock); 5040 5041 if (err) 5042 dev_err(dev, "failed to sync regulators: %d\n", err); 5043 } 5044 5045 static struct platform_driver tegra_pmc_driver = { 5046 .driver = { 5047 .name = "tegra-pmc", 5048 .suppress_bind_attrs = true, 5049 .of_match_table = tegra_pmc_match, 5050 .acpi_match_table = tegra_pmc_acpi_match, 5051 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 5052 .pm = &tegra_pmc_pm_ops, 5053 #endif 5054 .sync_state = tegra_pmc_sync_state, 5055 }, 5056 .probe = tegra_pmc_probe, 5057 }; 5058 builtin_platform_driver(tegra_pmc_driver); 5059 5060 #if defined(CONFIG_ARM) 5061 /** 5062 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 5063 * @pmc: power management controller 5064 * @cpuid: CPU partition ID 5065 * 5066 * Returns the partition ID corresponding to the CPU partition ID or a 5067 * negative error code on failure. 5068 */ 5069 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 5070 unsigned int cpuid) 5071 { 5072 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 5073 return pmc->soc->cpu_powergates[cpuid]; 5074 5075 return -EINVAL; 5076 } 5077 5078 /** 5079 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 5080 * @cpuid: CPU partition ID 5081 */ 5082 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 5083 { 5084 int id; 5085 5086 id = tegra_get_cpu_powergate_id(early_pmc, cpuid); 5087 if (id < 0) 5088 return false; 5089 5090 return tegra_powergate_is_powered(early_pmc, id); 5091 } 5092 5093 /** 5094 * tegra_pmc_cpu_power_on() - power on CPU partition 5095 * @cpuid: CPU partition ID 5096 */ 5097 int tegra_pmc_cpu_power_on(unsigned int cpuid) 5098 { 5099 int id; 5100 5101 id = tegra_get_cpu_powergate_id(early_pmc, cpuid); 5102 if (id < 0) 5103 return id; 5104 5105 return tegra_powergate_set(early_pmc, id, true); 5106 } 5107 5108 /** 5109 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 5110 * @cpuid: CPU partition ID 5111 */ 5112 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 5113 { 5114 int id; 5115 5116 id = tegra_get_cpu_powergate_id(early_pmc, cpuid); 5117 if (id < 0) 5118 return id; 5119 5120 return tegra_pmc_powergate_remove_clamping(early_pmc, id); 5121 } 5122 5123 bool tegra_pmc_core_domain_state_synced(void) 5124 { 5125 return early_pmc->core_domain_state_synced; 5126 } 5127 5128 #ifdef CONFIG_PM_SLEEP 5129 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 5130 { 5131 return early_pmc->suspend_mode; 5132 } 5133 5134 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 5135 { 5136 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 5137 return; 5138 5139 early_pmc->suspend_mode = mode; 5140 } 5141 5142 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 5143 { 5144 unsigned long long rate = 0; 5145 u64 ticks; 5146 u32 value; 5147 5148 switch (mode) { 5149 case TEGRA_SUSPEND_LP1: 5150 rate = 32768; 5151 break; 5152 5153 case TEGRA_SUSPEND_LP2: 5154 rate = early_pmc->rate; 5155 break; 5156 5157 default: 5158 break; 5159 } 5160 5161 if (WARN_ON_ONCE(rate == 0)) 5162 rate = 100000000; 5163 5164 ticks = early_pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 5165 do_div(ticks, USEC_PER_SEC); 5166 tegra_pmc_writel(early_pmc, ticks, PMC_CPUPWRGOOD_TIMER); 5167 5168 ticks = early_pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 5169 do_div(ticks, USEC_PER_SEC); 5170 tegra_pmc_writel(early_pmc, ticks, PMC_CPUPWROFF_TIMER); 5171 5172 value = tegra_pmc_readl(early_pmc, PMC_CNTRL); 5173 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 5174 value |= PMC_CNTRL_CPU_PWRREQ_OE; 5175 tegra_pmc_writel(early_pmc, value, PMC_CNTRL); 5176 } 5177 #endif /* CONFIG_PM_SLEEP */ 5178 5179 /* 5180 * Early initialization to allow access to registers in the very early boot 5181 * process. 5182 */ 5183 static int __init tegra_pmc_early_init(void) 5184 { 5185 const struct of_device_id *match; 5186 struct device_node *np; 5187 struct resource regs; 5188 int err; 5189 5190 mutex_init(&early_pmc->powergates_lock); 5191 5192 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 5193 if (!np) { 5194 /* 5195 * Fall back to legacy initialization for 32-bit ARM only. All 5196 * 64-bit ARM device tree files for Tegra are required to have 5197 * a PMC node. 5198 * 5199 * This is for backwards-compatibility with old device trees 5200 * that didn't contain a PMC node. Note that in this case the 5201 * SoC data can't be matched and therefore powergating is 5202 * disabled. 5203 */ 5204 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 5205 pr_warn("DT node not found, powergating disabled\n"); 5206 5207 regs.start = 0x7000e400; 5208 regs.end = 0x7000e7ff; 5209 regs.flags = IORESOURCE_MEM; 5210 5211 pr_warn("Using memory region %pR\n", ®s); 5212 } else { 5213 /* 5214 * At this point we're not running on Tegra, so play 5215 * nice with multi-platform kernels. 5216 */ 5217 return 0; 5218 } 5219 } else { 5220 /* 5221 * Extract information from the device tree if we've found a 5222 * matching node. 5223 */ 5224 if (of_address_to_resource(np, 0, ®s) < 0) { 5225 pr_err("failed to get PMC registers\n"); 5226 of_node_put(np); 5227 return -ENXIO; 5228 } 5229 } 5230 5231 early_pmc->base = ioremap(regs.start, resource_size(®s)); 5232 if (!early_pmc->base) { 5233 pr_err("failed to map PMC registers\n"); 5234 of_node_put(np); 5235 return -ENXIO; 5236 } 5237 5238 if (of_device_is_available(np)) { 5239 early_pmc->soc = match->data; 5240 5241 err = tegra_pmc_parse_dt(early_pmc, np); 5242 if (err < 0) { 5243 pr_err("failed to parse DT: %d\n", err); 5244 of_node_put(np); 5245 return err; 5246 } 5247 5248 tegra_pmc_init_common(early_pmc, np); 5249 5250 of_node_put(np); 5251 } 5252 5253 return 0; 5254 } 5255 early_initcall(tegra_pmc_early_init); 5256 #endif /* CONFIG_ARM */ 5257