1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel devices 5 * 6 * Copyright (C) 2015 Intel Corporation 7 */ 8 9 /* List of tlv type */ 10 enum { 11 INTEL_TLV_CNVI_TOP = 0x10, 12 INTEL_TLV_CNVR_TOP, 13 INTEL_TLV_CNVI_BT, 14 INTEL_TLV_CNVR_BT, 15 INTEL_TLV_CNVI_OTP, 16 INTEL_TLV_CNVR_OTP, 17 INTEL_TLV_DEV_REV_ID, 18 INTEL_TLV_USB_VENDOR_ID, 19 INTEL_TLV_USB_PRODUCT_ID, 20 INTEL_TLV_PCIE_VENDOR_ID, 21 INTEL_TLV_PCIE_DEVICE_ID, 22 INTEL_TLV_PCIE_SUBSYSTEM_ID, 23 INTEL_TLV_IMAGE_TYPE, 24 INTEL_TLV_TIME_STAMP, 25 INTEL_TLV_BUILD_TYPE, 26 INTEL_TLV_BUILD_NUM, 27 INTEL_TLV_FW_BUILD_PRODUCT, 28 INTEL_TLV_FW_BUILD_HW, 29 INTEL_TLV_FW_STEP, 30 INTEL_TLV_BT_SPEC, 31 INTEL_TLV_MFG_NAME, 32 INTEL_TLV_HCI_REV, 33 INTEL_TLV_LMP_SUBVER, 34 INTEL_TLV_OTP_PATCH_VER, 35 INTEL_TLV_SECURE_BOOT, 36 INTEL_TLV_KEY_FROM_HDR, 37 INTEL_TLV_OTP_LOCK, 38 INTEL_TLV_API_LOCK, 39 INTEL_TLV_DEBUG_LOCK, 40 INTEL_TLV_MIN_FW, 41 INTEL_TLV_LIMITED_CCE, 42 INTEL_TLV_SBE_TYPE, 43 INTEL_TLV_OTP_BDADDR, 44 INTEL_TLV_UNLOCKED_STATE, 45 INTEL_TLV_GIT_SHA1, 46 INTEL_TLV_UNLOCK_POLICY = 0x3c, 47 INTEL_TLV_PLATFORM_ID = 0x3d, 48 INTEL_TLV_FW_ID = 0x50 49 }; 50 51 struct intel_tlv { 52 u8 type; 53 u8 len; 54 u8 val[]; 55 } __packed; 56 57 #define BTINTEL_HCI_OP_RESET 0xfc01 58 #define BTINTEL_HCI_OP_DEBUG 0xfcd9 59 60 #define BTINTEL_CNVI_BLAZARI 0x900 /* BlazarI - Lunar Lake */ 61 #define BTINTEL_CNVI_BLAZARIW 0x901 /* BlazarIW - Wildcat Lake */ 62 #define BTINTEL_CNVI_GAP 0x910 /* Gale Peak2 - Meteor Lake */ 63 #define BTINTEL_CNVI_BLAZARU 0x930 /* BlazarU - Meteor Lake */ 64 #define BTINTEL_CNVI_SCP 0xA00 /* Scorpius Peak - Panther Lake */ 65 #define BTINTEL_CNVI_SCP2 0xA10 /* Scorpius Peak2 - Nova Lake */ 66 #define BTINTEL_CNVI_SCP2_C0 0xA11 /* Scorpius Peak2 C0 - Titan Lake */ 67 #define BTINTEL_CNVI_SCP2F 0xA20 /* Scorpius Peak2F - Nova Lake */ 68 #define BTINTEL_CNVI_DRACO 0xA30 /* Draco */ 69 70 /* CNVR */ 71 #define BTINTEL_CNVR_FMP2 0x910 72 #define BTINTEL_CNVR_WHP2 0xA10 /* Whale Peak2 - Panther Lake */ 73 74 #define BTINTEL_IMG_BOOTLOADER 0x01 /* Bootloader image */ 75 #define BTINTEL_IMG_IML 0x02 /* Intermediate image */ 76 #define BTINTEL_IMG_OP 0x03 /* Operational image */ 77 78 #define BTINTEL_FWID_MAXLEN 64 79 80 /* CNVi Hardware variant */ 81 #define BTINTEL_HWID_GAP 0x1c /* Gale Peak2 - Meteor Lake */ 82 #define BTINTEL_HWID_BZRI 0x1e /* BlazarI - Lunar Lake */ 83 #define BTINTEL_HWID_BZRU 0x1d /* BlazarU - Meteor Lake */ 84 #define BTINTEL_HWID_SCP 0x1f /* Scorpius Peak - Panther Lake */ 85 #define BTINTEL_HWID_SCP2 0x20 /* Scorpius Peak2 - Nova Lake */ 86 #define BTINTEL_HWID_SCP2F 0x21 /* Scorpius Peak2-F - Nova Lake */ 87 #define BTINTEL_HWID_BZRIW 0x22 /* BlazarIW - Wildcat Lake */ 88 89 extern const guid_t btintel_guid_dsm; 90 91 struct intel_version_tlv { 92 u32 cnvi_top; 93 u32 cnvr_top; 94 u32 cnvi_bt; 95 u32 cnvr_bt; 96 u16 dev_rev_id; 97 u8 img_type; 98 u16 timestamp; 99 u8 build_type; 100 u32 build_num; 101 u8 secure_boot; 102 u8 otp_lock; 103 u8 api_lock; 104 u8 debug_lock; 105 u8 min_fw_build_nn; 106 u8 min_fw_build_cw; 107 u8 min_fw_build_yy; 108 u8 limited_cce; 109 u8 sbe_type; 110 u32 git_sha1; 111 u8 fw_id[BTINTEL_FWID_MAXLEN]; 112 bdaddr_t otp_bd_addr; 113 u8 unlock_policy; 114 u8 platform_id[6]; 115 }; 116 117 struct intel_version { 118 u8 status; 119 u8 hw_platform; 120 u8 hw_variant; 121 u8 hw_revision; 122 u8 fw_variant; 123 u8 fw_revision; 124 u8 fw_build_num; 125 u8 fw_build_ww; 126 u8 fw_build_yy; 127 u8 fw_patch_num; 128 } __packed; 129 130 struct intel_boot_params { 131 __u8 status; 132 __u8 otp_format; 133 __u8 otp_content; 134 __u8 otp_patch; 135 __le16 dev_revid; 136 __u8 secure_boot; 137 __u8 key_from_hdr; 138 __u8 key_type; 139 __u8 otp_lock; 140 __u8 api_lock; 141 __u8 debug_lock; 142 bdaddr_t otp_bdaddr; 143 __u8 min_fw_build_nn; 144 __u8 min_fw_build_cw; 145 __u8 min_fw_build_yy; 146 __u8 limited_cce; 147 __u8 unlocked_state; 148 } __packed; 149 150 struct intel_bootup { 151 __u8 zero; 152 __u8 num_cmds; 153 __u8 source; 154 __u8 reset_type; 155 __u8 reset_reason; 156 __u8 ddc_status; 157 } __packed; 158 159 struct intel_secure_send_result { 160 __u8 result; 161 __le16 opcode; 162 __u8 status; 163 } __packed; 164 165 struct intel_reset { 166 __u8 reset_type; 167 __u8 patch_enable; 168 __u8 ddc_reload; 169 __u8 boot_option; 170 __le32 boot_param; 171 } __packed; 172 173 struct intel_debug_features { 174 __u8 page1[16]; 175 } __packed; 176 177 struct intel_offload_use_cases { 178 __u8 status; 179 __u8 preset[8]; 180 } __packed; 181 182 #define INTEL_OP_PPAG_CMD 0xFE0B 183 struct hci_ppag_enable_cmd { 184 __le32 ppag_enable_flags; 185 } __packed; 186 187 #define BTINTEL_GET_ROM_DEBUG_INFO 0xfcde 188 struct btintel_rp_get_rom_debug_info { 189 __u8 status; 190 __le32 debug_reg0; 191 __le32 debug_reg1; 192 __le32 debug_reg2; 193 __le32 debug_reg3; 194 } __packed; 195 196 #define INTEL_TLV_TYPE_ID 0x01 197 198 #define INTEL_TLV_SYSTEM_EXCEPTION 0x00 199 #define INTEL_TLV_FATAL_EXCEPTION 0x01 200 #define INTEL_TLV_DEBUG_EXCEPTION 0x02 201 #define INTEL_TLV_TEST_EXCEPTION 0xDE 202 203 struct btintel_cp_ddc_write { 204 u8 len; 205 __le16 id; 206 u8 data[]; 207 } __packed; 208 209 /* Bluetooth SAR feature (BRDS), Revision 1 */ 210 struct btintel_sar_inc_pwr { 211 u8 revision; 212 u32 bt_sar_bios; /* Mode of SAR control to be used, 1:enabled in bios */ 213 u32 inc_power_mode; /* Increased power mode */ 214 u8 sar_2400_chain_a; /* Sar power restriction LB */ 215 u8 br; 216 u8 edr2; 217 u8 edr3; 218 u8 le; 219 u8 le_2mhz; 220 u8 le_lr; 221 }; 222 223 /* Bluetooth SAR feature (BRDS), Revision 2 - per-chain sub-band power limits */ 224 struct btintel_sar_band_limits { 225 u8 subband_2g4; 226 u8 subband_5g2; 227 u8 subband_5g8_5g9; 228 u8 subband_6g1; 229 u8 subband_6g3; 230 }; 231 232 struct btintel_sar_rev2 { 233 u8 revision; 234 u32 bt_sar_bios; /* 1: BIOS-managed SAR enabled */ 235 u32 inc_power_mode; /* 0: supported, 1: disabled */ 236 struct btintel_sar_band_limits chain_a; 237 struct btintel_sar_band_limits chain_b; 238 }; 239 240 #define INTEL_HW_PLATFORM(cnvx_bt) ((u8)(((cnvx_bt) & 0x0000ff00) >> 8)) 241 #define INTEL_HW_VARIANT(cnvx_bt) ((u8)(((cnvx_bt) & 0x003f0000) >> 16)) 242 #define INTEL_CNVX_TOP_TYPE(cnvx_top) ((cnvx_top) & 0x00000fff) 243 #define INTEL_CNVX_TOP_DASH(cnvx_top) (((cnvx_top) & 0x00f00000) >> 20) 244 #define INTEL_CNVX_TOP_STEP(cnvx_top) (((cnvx_top) & 0x0f000000) >> 24) 245 #define INTEL_CNVX_TOP_FLAVOR(cnvx_top) (((cnvx_top) & 0xf0000000) >> 28) 246 #define INTEL_CNVX_TOP_PACK_SWAB(t, s) __swab16(((__u16)(((t) << 4) | (s)))) 247 248 enum { 249 INTEL_BOOTLOADER, 250 INTEL_DOWNLOADING, 251 INTEL_FIRMWARE_LOADED, 252 INTEL_FIRMWARE_FAILED, 253 INTEL_BOOTING, 254 INTEL_BROKEN_INITIAL_NCMD, 255 INTEL_BROKEN_SHUTDOWN_LED, 256 INTEL_ROM_LEGACY, 257 INTEL_ROM_LEGACY_NO_WBS_SUPPORT, 258 INTEL_ACPI_RESET_ACTIVE, 259 INTEL_WAIT_FOR_D0, 260 261 __INTEL_NUM_FLAGS, 262 }; 263 264 struct btintel_data { 265 DECLARE_BITMAP(flags, __INTEL_NUM_FLAGS); 266 int (*acpi_reset_method)(struct hci_dev *hdev); 267 u32 cnvi_bt; 268 bool unlocker; 269 }; 270 271 #define btintel_set_flag(hdev, nr) \ 272 do { \ 273 struct btintel_data *intel = hci_get_priv((hdev)); \ 274 set_bit((nr), intel->flags); \ 275 } while (0) 276 277 #define btintel_clear_flag(hdev, nr) \ 278 do { \ 279 struct btintel_data *intel = hci_get_priv((hdev)); \ 280 clear_bit((nr), intel->flags); \ 281 } while (0) 282 283 #define btintel_wake_up_flag(hdev, nr) \ 284 do { \ 285 struct btintel_data *intel = hci_get_priv((hdev)); \ 286 wake_up_bit(intel->flags, (nr)); \ 287 } while (0) 288 289 #define btintel_get_flag(hdev) \ 290 (((struct btintel_data *)hci_get_priv(hdev))->flags) 291 292 #define btintel_test_flag(hdev, nr) test_bit((nr), btintel_get_flag(hdev)) 293 #define btintel_test_and_clear_flag(hdev, nr) test_and_clear_bit((nr), btintel_get_flag(hdev)) 294 #define btintel_wait_on_flag_timeout(hdev, nr, m, to) \ 295 wait_on_bit_timeout(btintel_get_flag(hdev), (nr), m, to) 296 297 #if IS_ENABLED(CONFIG_BT_INTEL) || IS_ENABLED(CONFIG_BT_INTEL_PCIE) 298 299 int btintel_check_bdaddr(struct hci_dev *hdev); 300 int btintel_enter_mfg(struct hci_dev *hdev); 301 int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched); 302 int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); 303 int btintel_set_diag(struct hci_dev *hdev, bool enable); 304 305 int btintel_version_info(struct hci_dev *hdev, struct intel_version *ver); 306 int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name); 307 int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug); 308 int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver); 309 struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, 310 u16 opcode_write); 311 int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param); 312 int btintel_read_boot_params(struct hci_dev *hdev, 313 struct intel_boot_params *params); 314 int btintel_download_firmware(struct hci_dev *dev, struct intel_version *ver, 315 const struct firmware *fw, u32 *boot_param); 316 int btintel_configure_setup(struct hci_dev *hdev, const char *driver_name); 317 int btintel_recv_event(struct hci_dev *hdev, struct sk_buff *skb); 318 void btintel_bootup(struct hci_dev *hdev, const void *ptr, unsigned int len); 319 void btintel_secure_send_result(struct hci_dev *hdev, 320 const void *ptr, unsigned int len); 321 int btintel_set_quality_report(struct hci_dev *hdev, bool enable); 322 int btintel_version_info_tlv(struct hci_dev *hdev, 323 struct intel_version_tlv *version); 324 int btintel_parse_version_tlv(struct hci_dev *hdev, 325 struct intel_version_tlv *version, 326 struct sk_buff *skb); 327 void btintel_set_msft_opcode(struct hci_dev *hdev, u8 hw_variant); 328 int btintel_bootloader_setup_tlv(struct hci_dev *hdev, 329 struct intel_version_tlv *ver); 330 int btintel_shutdown_combined(struct hci_dev *hdev); 331 void btintel_hw_error(struct hci_dev *hdev, u8 code); 332 void btintel_print_fseq_info(struct hci_dev *hdev); 333 int btintel_acpi_reset_method(struct hci_dev *hdev); 334 #else 335 336 static inline int btintel_check_bdaddr(struct hci_dev *hdev) 337 { 338 return -EOPNOTSUPP; 339 } 340 341 static inline int btintel_enter_mfg(struct hci_dev *hdev) 342 { 343 return -EOPNOTSUPP; 344 } 345 346 static inline int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) 347 { 348 return -EOPNOTSUPP; 349 } 350 351 static inline int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) 352 { 353 return -EOPNOTSUPP; 354 } 355 356 static inline int btintel_set_diag(struct hci_dev *hdev, bool enable) 357 { 358 return -EOPNOTSUPP; 359 } 360 361 static inline int btintel_version_info(struct hci_dev *hdev, 362 struct intel_version *ver) 363 { 364 return -EOPNOTSUPP; 365 } 366 367 static inline int btintel_load_ddc_config(struct hci_dev *hdev, 368 const char *ddc_name) 369 { 370 return -EOPNOTSUPP; 371 } 372 373 static inline int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) 374 { 375 return -EOPNOTSUPP; 376 } 377 378 static inline int btintel_read_version(struct hci_dev *hdev, 379 struct intel_version *ver) 380 { 381 return -EOPNOTSUPP; 382 } 383 384 static inline struct regmap *btintel_regmap_init(struct hci_dev *hdev, 385 u16 opcode_read, 386 u16 opcode_write) 387 { 388 return ERR_PTR(-EINVAL); 389 } 390 391 static inline int btintel_send_intel_reset(struct hci_dev *hdev, 392 u32 reset_param) 393 { 394 return -EOPNOTSUPP; 395 } 396 397 static inline int btintel_read_boot_params(struct hci_dev *hdev, 398 struct intel_boot_params *params) 399 { 400 return -EOPNOTSUPP; 401 } 402 403 static inline int btintel_download_firmware(struct hci_dev *dev, 404 const struct firmware *fw, 405 u32 *boot_param) 406 { 407 return -EOPNOTSUPP; 408 } 409 410 static inline int btintel_configure_setup(struct hci_dev *hdev, 411 const char *driver_name) 412 { 413 return -ENODEV; 414 } 415 416 static inline void btintel_bootup(struct hci_dev *hdev, 417 const void *ptr, unsigned int len) 418 { 419 } 420 421 static inline void btintel_secure_send_result(struct hci_dev *hdev, 422 const void *ptr, unsigned int len) 423 { 424 } 425 426 static inline int btintel_set_quality_report(struct hci_dev *hdev, bool enable) 427 { 428 return -ENODEV; 429 } 430 431 static inline int btintel_version_info_tlv(struct hci_dev *hdev, 432 struct intel_version_tlv *version) 433 { 434 return -EOPNOTSUPP; 435 } 436 437 static inline int btintel_parse_version_tlv(struct hci_dev *hdev, 438 struct intel_version_tlv *version, 439 struct sk_buff *skb) 440 { 441 return -EOPNOTSUPP; 442 } 443 444 static inline void btintel_set_msft_opcode(struct hci_dev *hdev, u8 hw_variant) 445 446 { 447 } 448 449 static inline int btintel_bootloader_setup_tlv(struct hci_dev *hdev, 450 struct intel_version_tlv *ver) 451 { 452 return -ENODEV; 453 } 454 455 static inline int btintel_shutdown_combined(struct hci_dev *hdev) 456 { 457 return -ENODEV; 458 } 459 460 static inline void btintel_hw_error(struct hci_dev *hdev, u8 code) 461 { 462 } 463 464 static inline void btintel_print_fseq_info(struct hci_dev *hdev) 465 { 466 } 467 static inline int btintel_acpi_reset_method(struct hci_dev *hdev) 468 { 469 return -ENODEV; 470 } 471 #endif 472