Searched refs:INTEL_CX0_LANE0 (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cx0_phy.c | 28 #define INTEL_CX0_LANE0 BIT(0) macro
30 #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
67 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; in intel_cx0_get_owned_lane_mask()
484 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
2084 u8 lane = INTEL_CX0_LANE0; in intel_c10pll_readout_hw_state()
2120 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i), in intel_c10_pll_program()
2124 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2125 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2131 intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
2400 …cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_… in intel_c20pll_readout_hw_state()
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