1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /***************************************************************************
4 * Header for ines GPIB boards
5 * copyright : (C) 2002 by Frank Mori Hess
6 ***************************************************************************/
7
8 #ifndef _INES_GPIB_H
9 #define _INES_GPIB_H
10
11 #include "nec7210.h"
12 #include "gpibP.h"
13 #include "plx9050.h"
14 #include "amcc5920.h"
15 #include "quancom_pci.h"
16 #include <linux/interrupt.h>
17
18 enum ines_pci_chip {
19 PCI_CHIP_NONE,
20 PCI_CHIP_PLX9050,
21 PCI_CHIP_AMCC5920,
22 PCI_CHIP_QUANCOM,
23 PCI_CHIP_QUICKLOGIC5030,
24 };
25
26 struct ines_priv {
27 struct nec7210_priv nec7210_priv;
28 struct pci_dev *pci_device;
29 // base address for plx9052 pci chip
30 unsigned long plx_iobase;
31 // base address for amcc5920 pci chip
32 unsigned long amcc_iobase;
33 unsigned int irq;
34 enum ines_pci_chip pci_chip_type;
35 u8 extend_mode_bits;
36 };
37
38 // interfaces
39 extern gpib_interface_t ines_pci_interface;
40 extern gpib_interface_t ines_pci_accel_interface;
41 extern gpib_interface_t ines_pcmcia_interface;
42 extern gpib_interface_t ines_pcmcia_accel_interface;
43 extern gpib_interface_t ines_pcmcia_unaccel_interface;
44
45 // interface functions
46 int ines_read(gpib_board_t *board, uint8_t *buffer, size_t length, int *end, size_t *bytes_read);
47 int ines_write(gpib_board_t *board, uint8_t *buffer, size_t length,
48 int send_eoi, size_t *bytes_written);
49 int ines_accel_read(gpib_board_t *board, uint8_t *buffer, size_t length,
50 int *end, size_t *bytes_read);
51 int ines_accel_write(gpib_board_t *board, uint8_t *buffer, size_t length,
52 int send_eoi, size_t *bytes_written);
53 int ines_command(gpib_board_t *board, uint8_t *buffer, size_t length, size_t *bytes_written);
54 int ines_take_control(gpib_board_t *board, int synchronous);
55 int ines_go_to_standby(gpib_board_t *board);
56 void ines_request_system_control(gpib_board_t *board, int request_control);
57 void ines_interface_clear(gpib_board_t *board, int assert);
58 void ines_remote_enable(gpib_board_t *board, int enable);
59 int ines_enable_eos(gpib_board_t *board, uint8_t eos_byte, int compare_8_bits);
60 void ines_disable_eos(gpib_board_t *board);
61 unsigned int ines_update_status(gpib_board_t *board, unsigned int clear_mask);
62 int ines_primary_address(gpib_board_t *board, unsigned int address);
63 int ines_secondary_address(gpib_board_t *board, unsigned int address, int enable);
64 int ines_parallel_poll(gpib_board_t *board, uint8_t *result);
65 void ines_parallel_poll_configure(gpib_board_t *board, uint8_t config);
66 void ines_parallel_poll_response(gpib_board_t *board, int ist);
67 void ines_serial_poll_response(gpib_board_t *board, uint8_t status);
68 uint8_t ines_serial_poll_status(gpib_board_t *board);
69 int ines_line_status(const gpib_board_t *board);
70 unsigned int ines_t1_delay(gpib_board_t *board, unsigned int nano_sec);
71 void ines_return_to_local(gpib_board_t *board);
72
73 // interrupt service routines
74 irqreturn_t ines_pci_interrupt(int irq, void *arg);
75 irqreturn_t ines_interrupt(gpib_board_t *board);
76
77 // utility functions
78 void ines_free_private(gpib_board_t *board);
79 int ines_generic_attach(gpib_board_t *board);
80 void ines_online(struct ines_priv *priv, const gpib_board_t *board, int use_accel);
81 void ines_set_xfer_counter(struct ines_priv *priv, unsigned int count);
82
83 /* inb/outb wrappers */
ines_inb(struct ines_priv * priv,unsigned int register_number)84 static inline unsigned int ines_inb(struct ines_priv *priv, unsigned int register_number)
85 {
86 return inb(priv->nec7210_priv.iobase +
87 register_number * priv->nec7210_priv.offset);
88 }
89
ines_outb(struct ines_priv * priv,unsigned int value,unsigned int register_number)90 static inline void ines_outb(struct ines_priv *priv, unsigned int value,
91 unsigned int register_number)
92 {
93 outb(value, priv->nec7210_priv.iobase +
94 register_number * priv->nec7210_priv.offset);
95 }
96
97 // pcmcia init/cleanup
98
99 int ines_pcmcia_init_module(void);
100 void ines_pcmcia_cleanup_module(void);
101
102 enum ines_regs {
103 // read
104 FIFO_STATUS = 0x8,
105 ISR3 = 0x9,
106 ISR4 = 0xa,
107 IN_FIFO_COUNT = 0x10,
108 OUT_FIFO_COUNT = 0x11,
109 EXTEND_STATUS = 0xf,
110
111 // write
112 XDMA_CONTROL = 0x8,
113 IMR3 = ISR3,
114 IMR4 = ISR4,
115 IN_FIFO_WATERMARK = IN_FIFO_COUNT,
116 OUT_FIFO_WATERMARK = OUT_FIFO_COUNT,
117 EXTEND_MODE = 0xf,
118
119 // read-write
120 XFER_COUNT_LOWER = 0xb,
121 XFER_COUNT_UPPER = 0xc,
122 BUS_CONTROL_MONITOR = 0x13,
123 };
124
125 enum isr3_imr3_bits {
126 HW_TIMEOUT_BIT = 0x1,
127 XFER_COUNT_BIT = 0x2,
128 CMD_RECEIVED_BIT = 0x4,
129 TCT_RECEIVED_BIT = 0x8,
130 IFC_ACTIVE_BIT = 0x10,
131 ATN_ACTIVE_BIT = 0x20,
132 FIFO_ERROR_BIT = 0x40,
133 };
134
135 enum isr4_imr4_bits {
136 IN_FIFO_WATERMARK_BIT = 0x1,
137 OUT_FIFO_WATERMARK_BIT = 0x2,
138 IN_FIFO_FULL_BIT = 0x4,
139 OUT_FIFO_EMPTY_BIT = 0x8,
140 IN_FIFO_READY_BIT = 0x10,
141 OUT_FIFO_READY_BIT = 0x20,
142 IN_FIFO_EXIT_WATERMARK_BIT = 0x40,
143 OUT_FIFO_EXIT_WATERMARK_BIT = 0x80,
144 };
145
146 enum extend_mode_bits {
147 TR3_TRIG_ENABLE_BIT = 0x1, // enable generation of trigger pulse T/R3 pin
148 // clear message available status bit when chip writes byte with EOI true
149 MAV_ENABLE_BIT = 0x2,
150 EOS1_ENABLE_BIT = 0x4, // enable eos register 1
151 EOS2_ENABLE_BIT = 0x8, // enable eos register 2
152 EOIDIS_BIT = 0x10, // disable EOI interrupt when doing rfd holdoff on end?
153 XFER_COUNTER_ENABLE_BIT = 0x20,
154 XFER_COUNTER_OUTPUT_BIT = 0x40, // use counter for output, clear for input
155 // when xfer counter hits 0, assert EOI on write or RFD holdoff on read
156 LAST_BYTE_HANDLING_BIT = 0x80,
157 };
158
159 enum extend_status_bits {
160 OUTPUT_MESSAGE_IN_PROGRESS_BIT = 0x1,
161 SCSEL_BIT = 0x2, // statue of SCSEL pin
162 LISTEN_DISABLED = 0x4,
163 IN_FIFO_EMPTY_BIT = 0x8,
164 OUT_FIFO_FULL_BIT = 0x10,
165 };
166
167 // ines adds fifo enable bits to address mode register
168 enum ines_admr_bits {
169 IN_FIFO_ENABLE_BIT = 0x8,
170 OUT_FIFO_ENABLE_BIT = 0x4,
171 };
172
173 enum xdma_control_bits {
174 DMA_OUTPUT_BIT = 0x1, // use dma for output, clear for input
175 ENABLE_SYNC_DMA_BIT = 0x2,
176 DMA_ACCESS_EVERY_CYCLE = 0x4,// dma accesses fifo every cycle, clear for every other cycle
177 DMA_16BIT = 0x8, // clear for 8 bit transfers
178 };
179
180 enum bus_control_monitor_bits {
181 BCM_DAV_BIT = 0x1,
182 BCM_NRFD_BIT = 0x2,
183 BCM_NDAC_BIT = 0x4,
184 BCM_IFC_BIT = 0x8,
185 BCM_ATN_BIT = 0x10,
186 BCM_SRQ_BIT = 0x20,
187 BCM_REN_BIT = 0x40,
188 BCM_EOI_BIT = 0x80,
189 };
190
191 enum ines_aux_reg_bits {
192 INES_AUXD = 0x40,
193 };
194
195 enum ines_aux_cmds {
196 INES_RFD_HLD_IMMEDIATE = 0x4,
197 INES_AUX_CLR_OUT_FIFO = 0x5,
198 INES_AUX_CLR_IN_FIFO = 0x6,
199 INES_AUX_XMODE = 0xa,
200 };
201
202 enum ines_auxd_bits {
203 INES_FOLLOWING_T1_MASK = 0x3,
204 INES_FOLLOWING_T1_500ns = 0x0,
205 INES_FOLLOWING_T1_350ns = 0x1,
206 INES_FOLLOWING_T1_250ns = 0x2,
207 INES_INITIAL_TI_MASK = 0xc,
208 INES_INITIAL_T1_2000ns = 0x0,
209 INES_INITIAL_T1_1100ns = 0x4,
210 INES_INITIAL_T1_700ns = 0x8,
211 INES_T6_2us = 0x0,
212 INES_T6_50us = 0x10,
213 };
214
215 #endif // _INES_GPIB_H
216