xref: /linux/include/dt-bindings/clock/imx7ulp-clock.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  * Copyright 2017~2018 NXP
5  *
6  */
7 
8 #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
9 #define __DT_BINDINGS_CLOCK_IMX7ULP_H
10 
11 /* SCG1 */
12 
13 #define IMX7ULP_CLK_DUMMY		0
14 #define IMX7ULP_CLK_ROSC		1
15 #define IMX7ULP_CLK_SOSC		2
16 #define IMX7ULP_CLK_FIRC		3
17 #define IMX7ULP_CLK_SPLL_PRE_SEL	4
18 #define IMX7ULP_CLK_SPLL_PRE_DIV	5
19 #define IMX7ULP_CLK_SPLL		6
20 #define IMX7ULP_CLK_SPLL_POST_DIV1	7
21 #define IMX7ULP_CLK_SPLL_POST_DIV2	8
22 #define IMX7ULP_CLK_SPLL_PFD0		9
23 #define IMX7ULP_CLK_SPLL_PFD1		10
24 #define IMX7ULP_CLK_SPLL_PFD2		11
25 #define IMX7ULP_CLK_SPLL_PFD3		12
26 #define IMX7ULP_CLK_SPLL_PFD_SEL	13
27 #define IMX7ULP_CLK_SPLL_SEL		14
28 #define IMX7ULP_CLK_APLL_PRE_SEL	15
29 #define IMX7ULP_CLK_APLL_PRE_DIV	16
30 #define IMX7ULP_CLK_APLL		17
31 #define IMX7ULP_CLK_APLL_POST_DIV1	18
32 #define IMX7ULP_CLK_APLL_POST_DIV2	19
33 #define IMX7ULP_CLK_APLL_PFD0		20
34 #define IMX7ULP_CLK_APLL_PFD1		21
35 #define IMX7ULP_CLK_APLL_PFD2		22
36 #define IMX7ULP_CLK_APLL_PFD3		23
37 #define IMX7ULP_CLK_APLL_PFD_SEL	24
38 #define IMX7ULP_CLK_APLL_SEL		25
39 #define IMX7ULP_CLK_UPLL		26
40 #define IMX7ULP_CLK_SYS_SEL		27
41 #define IMX7ULP_CLK_CORE_DIV		28
42 #define IMX7ULP_CLK_BUS_DIV		29
43 #define IMX7ULP_CLK_PLAT_DIV		30
44 #define IMX7ULP_CLK_DDR_SEL		31
45 #define IMX7ULP_CLK_DDR_DIV		32
46 #define IMX7ULP_CLK_NIC_SEL		33
47 #define IMX7ULP_CLK_NIC0_DIV		34
48 #define IMX7ULP_CLK_GPU_DIV		35
49 #define IMX7ULP_CLK_NIC1_DIV		36
50 #define IMX7ULP_CLK_NIC1_BUS_DIV	37
51 #define IMX7ULP_CLK_NIC1_EXT_DIV	38
52 /* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
53 #define IMX7ULP_CLK_MIPI_PLL		39
54 #define IMX7ULP_CLK_SIRC		40
55 #define IMX7ULP_CLK_SOSC_BUS_CLK	41
56 #define IMX7ULP_CLK_FIRC_BUS_CLK	42
57 #define IMX7ULP_CLK_SPLL_BUS_CLK	43
58 #define IMX7ULP_CLK_HSRUN_SYS_SEL	44
59 #define IMX7ULP_CLK_HSRUN_CORE_DIV	45
60 
61 #define IMX7ULP_CLK_CORE		46
62 #define IMX7ULP_CLK_HSRUN_CORE		47
63 
64 #define IMX7ULP_CLK_SCG1_END		48
65 
66 /* PCC2 */
67 #define IMX7ULP_CLK_DMA1		0
68 #define IMX7ULP_CLK_RGPIO2P1		1
69 #define IMX7ULP_CLK_FLEXBUS		2
70 #define IMX7ULP_CLK_SEMA42_1		3
71 #define IMX7ULP_CLK_DMA_MUX1		4
72 #define IMX7ULP_CLK_CAAM		6
73 #define IMX7ULP_CLK_LPTPM4		7
74 #define IMX7ULP_CLK_LPTPM5		8
75 #define IMX7ULP_CLK_LPIT1		9
76 #define IMX7ULP_CLK_LPSPI2		10
77 #define IMX7ULP_CLK_LPSPI3		11
78 #define IMX7ULP_CLK_LPI2C4		12
79 #define IMX7ULP_CLK_LPI2C5		13
80 #define IMX7ULP_CLK_LPUART4		14
81 #define IMX7ULP_CLK_LPUART5		15
82 #define IMX7ULP_CLK_FLEXIO1		16
83 #define IMX7ULP_CLK_USB0		17
84 #define IMX7ULP_CLK_USB1		18
85 #define IMX7ULP_CLK_USB_PHY		19
86 #define IMX7ULP_CLK_USB_PL301		20
87 #define IMX7ULP_CLK_USDHC0		21
88 #define IMX7ULP_CLK_USDHC1		22
89 #define IMX7ULP_CLK_WDG1		23
90 #define IMX7ULP_CLK_WDG2		24
91 
92 #define IMX7ULP_CLK_PCC2_END		25
93 
94 /* PCC3 */
95 #define IMX7ULP_CLK_LPTPM6		0
96 #define IMX7ULP_CLK_LPTPM7		1
97 #define IMX7ULP_CLK_LPI2C6		2
98 #define IMX7ULP_CLK_LPI2C7		3
99 #define IMX7ULP_CLK_LPUART6		4
100 #define IMX7ULP_CLK_LPUART7		5
101 #define IMX7ULP_CLK_VIU			6
102 #define IMX7ULP_CLK_DSI			7
103 #define IMX7ULP_CLK_LCDIF		8
104 #define IMX7ULP_CLK_MMDC		9
105 #define IMX7ULP_CLK_PCTLC		10
106 #define IMX7ULP_CLK_PCTLD		11
107 #define IMX7ULP_CLK_PCTLE		12
108 #define IMX7ULP_CLK_PCTLF		13
109 #define IMX7ULP_CLK_GPU3D		14
110 #define IMX7ULP_CLK_GPU2D		15
111 
112 #define IMX7ULP_CLK_PCC3_END		16
113 
114 /* SMC1 */
115 #define IMX7ULP_CLK_ARM			0
116 
117 #define IMX7ULP_CLK_SMC1_END		1
118 
119 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
120