Searched refs:IMX27_CLK_SSI1_DIV (Results 1 – 2 of 2) sorted by relevance
31 #define IMX27_CLK_SSI1_DIV 22 macro
96 clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); in _mx27_clocks_init()