1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Texas Instruments ICSSG Ethernet driver
3 *
4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 */
7
8 #ifndef __NET_TI_ICSSG_PRUETH_H
9 #define __NET_TI_ICSSG_PRUETH_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/genalloc.h>
13 #include <linux/if_vlan.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/remoteproc/pruss.h>
27 #include <linux/pruss_driver.h>
28 #include <linux/ptp_clock_kernel.h>
29 #include <linux/remoteproc.h>
30
31 #include <linux/dma-mapping.h>
32 #include <linux/dma/ti-cppi5.h>
33 #include <linux/dma/k3-udma-glue.h>
34
35 #include <net/devlink.h>
36
37 #include "icssg_config.h"
38 #include "icss_iep.h"
39 #include "icssg_switch_map.h"
40
41 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN)
42 #define PRUETH_MIN_PKT_SIZE (VLAN_ETH_ZLEN)
43 #define PRUETH_MAX_PKT_SIZE (PRUETH_MAX_MTU + ETH_HLEN + ETH_FCS_LEN)
44
45 #define ICSS_SLICE0 0
46 #define ICSS_SLICE1 1
47
48 #define ICSS_FW_PRU 0
49 #define ICSS_FW_RTU 1
50
51 #define ICSSG_MAX_RFLOWS 8 /* per slice */
52
53 #define ICSSG_NUM_PA_STATS 4
54 #define ICSSG_NUM_MIIG_STATS 60
55 /* Number of ICSSG related stats */
56 #define ICSSG_NUM_STATS (ICSSG_NUM_MIIG_STATS + ICSSG_NUM_PA_STATS)
57 #define ICSSG_NUM_STANDARD_STATS 31
58 #define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS)
59
60 #define IEP_DEFAULT_CYCLE_TIME_NS 1000000 /* 1 ms */
61
62 #define PRUETH_UNDIRECTED_PKT_DST_TAG 0
63 #define PRUETH_UNDIRECTED_PKT_TAG_INS BIT(30)
64
65 /* Firmware status codes */
66 #define ICSS_HS_FW_READY 0x55555555
67 #define ICSS_HS_FW_DEAD 0xDEAD0000 /* lower 16 bits contain error code */
68
69 /* Firmware command codes */
70 #define ICSS_HS_CMD_BUSY 0x40000000
71 #define ICSS_HS_CMD_DONE 0x80000000
72 #define ICSS_HS_CMD_CANCEL 0x10000000
73
74 /* Firmware commands */
75 #define ICSS_CMD_SPAD 0x20
76 #define ICSS_CMD_RXTX 0x10
77 #define ICSS_CMD_ADD_FDB 0x1
78 #define ICSS_CMD_DEL_FDB 0x2
79 #define ICSS_CMD_SET_RUN 0x4
80 #define ICSS_CMD_GET_FDB_SLOT 0x5
81 #define ICSS_CMD_ENABLE_VLAN 0x5
82 #define ICSS_CMD_DISABLE_VLAN 0x6
83 #define ICSS_CMD_ADD_FILTER 0x7
84 #define ICSS_CMD_ADD_MAC 0x8
85
86 /* In switch mode there are 3 real ports i.e. 3 mac addrs.
87 * however Linux sees only the host side port. The other 2 ports
88 * are the switch ports.
89 * In emac mode there are 2 real ports i.e. 2 mac addrs.
90 * Linux sees both the ports.
91 */
92 enum prueth_port {
93 PRUETH_PORT_HOST = 0, /* host side port */
94 PRUETH_PORT_MII0, /* physical port RG/SG MII 0 */
95 PRUETH_PORT_MII1, /* physical port RG/SG MII 1 */
96 PRUETH_PORT_INVALID, /* Invalid prueth port */
97 };
98
99 enum prueth_mac {
100 PRUETH_MAC0 = 0,
101 PRUETH_MAC1,
102 PRUETH_NUM_MACS,
103 PRUETH_MAC_INVALID,
104 };
105
106 struct prueth_tx_chn {
107 struct device *dma_dev;
108 struct napi_struct napi_tx;
109 struct k3_cppi_desc_pool *desc_pool;
110 struct k3_udma_glue_tx_channel *tx_chn;
111 struct prueth_emac *emac;
112 u32 id;
113 u32 descs_num;
114 unsigned int irq;
115 char name[32];
116 struct hrtimer tx_hrtimer;
117 unsigned long tx_pace_timeout_ns;
118 };
119
120 struct prueth_rx_chn {
121 struct device *dev;
122 struct device *dma_dev;
123 struct k3_cppi_desc_pool *desc_pool;
124 struct k3_udma_glue_rx_channel *rx_chn;
125 u32 descs_num;
126 unsigned int irq[ICSSG_MAX_RFLOWS]; /* separate irq per flow */
127 char name[32];
128 };
129
130 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3)
131 * and lower three are lower priority channels or threads.
132 */
133 #define PRUETH_MAX_TX_QUEUES 4
134
135 #define PRUETH_MAX_TX_TS_REQUESTS 50 /* Max simultaneous TX_TS requests */
136
137 /* Minimum coalesce time in usecs for both Tx and Rx */
138 #define ICSSG_MIN_COALESCE_USECS 20
139
140 /* data for each emac port */
141 struct prueth_emac {
142 bool is_sr1;
143 bool fw_running;
144 struct prueth *prueth;
145 struct net_device *ndev;
146 u8 mac_addr[6];
147 struct napi_struct napi_rx;
148 u32 msg_enable;
149
150 int link;
151 int speed;
152 int duplex;
153
154 const char *phy_id;
155 struct device_node *phy_node;
156 phy_interface_t phy_if;
157 enum prueth_port port_id;
158 struct icss_iep *iep;
159 unsigned int rx_ts_enabled : 1;
160 unsigned int tx_ts_enabled : 1;
161 unsigned int half_duplex : 1;
162
163 /* DMA related */
164 struct prueth_tx_chn tx_chns[PRUETH_MAX_TX_QUEUES];
165 struct completion tdown_complete;
166 atomic_t tdown_cnt;
167 struct prueth_rx_chn rx_chns;
168 int rx_flow_id_base;
169 int tx_ch_num;
170
171 /* SR1.0 Management channel */
172 struct prueth_rx_chn rx_mgm_chn;
173 int rx_mgm_flow_id_base;
174
175 spinlock_t lock; /* serialize access */
176
177 /* TX HW Timestamping */
178 /* TX TS cookie will be index to the tx_ts_skb array */
179 struct sk_buff *tx_ts_skb[PRUETH_MAX_TX_TS_REQUESTS];
180 atomic_t tx_ts_pending;
181 int tx_ts_irq;
182
183 u8 cmd_seq;
184 /* shutdown related */
185 __le32 cmd_data[4];
186 struct completion cmd_complete;
187 /* Mutex to serialize access to firmware command interface */
188 struct mutex cmd_lock;
189 struct work_struct rx_mode_work;
190 struct workqueue_struct *cmd_wq;
191
192 struct pruss_mem_region dram;
193
194 bool offload_fwd_mark;
195 int port_vlan;
196
197 struct delayed_work stats_work;
198 u64 stats[ICSSG_NUM_MIIG_STATS];
199 u64 pa_stats[ICSSG_NUM_PA_STATS];
200
201 /* RX IRQ Coalescing Related */
202 struct hrtimer rx_hrtimer;
203 unsigned long rx_pace_timeout_ns;
204 };
205
206 /**
207 * struct prueth_pdata - PRUeth platform data
208 * @fdqring_mode: Free desc queue mode
209 * @quirk_10m_link_issue: 10M link detect errata
210 * @switch_mode: switch firmware support
211 */
212 struct prueth_pdata {
213 enum k3_ring_mode fdqring_mode;
214 u32 quirk_10m_link_issue:1;
215 u32 switch_mode:1;
216 };
217
218 struct icssg_firmwares {
219 char *pru;
220 char *rtu;
221 char *txpru;
222 };
223
224 /**
225 * struct prueth - PRUeth structure
226 * @dev: device
227 * @pruss: pruss handle
228 * @pru: rproc instances of PRUs
229 * @rtu: rproc instances of RTUs
230 * @txpru: rproc instances of TX_PRUs
231 * @shram: PRUSS shared RAM region
232 * @sram_pool: MSMC RAM pool for buffers
233 * @msmcram: MSMC RAM region
234 * @eth_node: DT node for the port
235 * @emac: private EMAC data structure
236 * @registered_netdevs: list of registered netdevs
237 * @miig_rt: regmap to mii_g_rt block
238 * @mii_rt: regmap to mii_rt block
239 * @pa_stats: regmap to pa_stats block
240 * @pru_id: ID for each of the PRUs
241 * @pdev: pointer to ICSSG platform device
242 * @pdata: pointer to platform data for ICSSG driver
243 * @icssg_hwcmdseq: seq counter or HWQ messages
244 * @emacs_initialized: num of EMACs/ext ports that are up/running
245 * @iep0: pointer to IEP0 device
246 * @iep1: pointer to IEP1 device
247 * @vlan_tbl: VLAN-FID table pointer
248 * @hw_bridge_dev: pointer to HW bridge net device
249 * @hsr_dev: pointer to the HSR net device
250 * @br_members: bitmask of bridge member ports
251 * @hsr_members: bitmask of hsr member ports
252 * @prueth_netdevice_nb: netdevice notifier block
253 * @prueth_switchdev_nb: switchdev notifier block
254 * @prueth_switchdev_bl_nb: switchdev blocking notifier block
255 * @is_switch_mode: flag to indicate if device is in Switch mode
256 * @is_hsr_offload_mode: flag to indicate if device is in hsr offload mode
257 * @is_switchmode_supported: indicates platform support for switch mode
258 * @switch_id: ID for mapping switch ports to bridge
259 * @default_vlan: Default VLAN for host
260 */
261 struct prueth {
262 struct device *dev;
263 struct pruss *pruss;
264 struct rproc *pru[PRUSS_NUM_PRUS];
265 struct rproc *rtu[PRUSS_NUM_PRUS];
266 struct rproc *txpru[PRUSS_NUM_PRUS];
267 struct pruss_mem_region shram;
268 struct gen_pool *sram_pool;
269 struct pruss_mem_region msmcram;
270
271 struct device_node *eth_node[PRUETH_NUM_MACS];
272 struct prueth_emac *emac[PRUETH_NUM_MACS];
273 struct net_device *registered_netdevs[PRUETH_NUM_MACS];
274 struct regmap *miig_rt;
275 struct regmap *mii_rt;
276 struct regmap *pa_stats;
277
278 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS];
279 struct platform_device *pdev;
280 struct prueth_pdata pdata;
281 u8 icssg_hwcmdseq;
282 int emacs_initialized;
283 struct icss_iep *iep0;
284 struct icss_iep *iep1;
285 struct prueth_vlan_tbl *vlan_tbl;
286
287 struct net_device *hw_bridge_dev;
288 struct net_device *hsr_dev;
289 u8 br_members;
290 u8 hsr_members;
291 struct notifier_block prueth_netdevice_nb;
292 struct notifier_block prueth_switchdev_nb;
293 struct notifier_block prueth_switchdev_bl_nb;
294 bool is_switch_mode;
295 bool is_hsr_offload_mode;
296 bool is_switchmode_supported;
297 unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
298 int default_vlan;
299 };
300
301 struct emac_tx_ts_response {
302 u32 reserved[2];
303 u32 cookie;
304 u32 lo_ts;
305 u32 hi_ts;
306 };
307
308 struct emac_tx_ts_response_sr1 {
309 __le32 lo_ts;
310 __le32 hi_ts;
311 __le32 reserved;
312 __le32 cookie;
313 };
314
315 /* get PRUSS SLICE number from prueth_emac */
prueth_emac_slice(struct prueth_emac * emac)316 static inline int prueth_emac_slice(struct prueth_emac *emac)
317 {
318 switch (emac->port_id) {
319 case PRUETH_PORT_MII0:
320 return ICSS_SLICE0;
321 case PRUETH_PORT_MII1:
322 return ICSS_SLICE1;
323 default:
324 return -EINVAL;
325 }
326 }
327
328 extern const struct ethtool_ops icssg_ethtool_ops;
329 extern const struct dev_pm_ops prueth_dev_pm_ops;
330
331 /* Classifier helpers */
332 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
333 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
334 void icssg_class_disable(struct regmap *miig_rt, int slice);
335 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
336 bool is_sr1);
337 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice);
338 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
339 struct net_device *ndev);
340 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
341
342 /* config helpers */
343 void icssg_config_ipg(struct prueth_emac *emac);
344 int icssg_config(struct prueth *prueth, struct prueth_emac *emac,
345 int slice);
346 int icssg_set_port_state(struct prueth_emac *emac,
347 enum icssg_port_state_cmd state);
348 void icssg_config_set_speed(struct prueth_emac *emac);
349 void icssg_config_half_duplex(struct prueth_emac *emac);
350
351 /* Buffer queue helpers */
352 int icssg_queue_pop(struct prueth *prueth, u8 queue);
353 void icssg_queue_push(struct prueth *prueth, int queue, u16 addr);
354 u32 icssg_queue_level(struct prueth *prueth, int queue);
355
356 int icssg_send_fdb_msg(struct prueth_emac *emac, struct mgmt_cmd *cmd,
357 struct mgmt_cmd_rsp *rsp);
358 int icssg_fdb_add_del(struct prueth_emac *emac, const unsigned char *addr,
359 u8 vid, u8 fid_c2, bool add);
360 int icssg_fdb_lookup(struct prueth_emac *emac, const unsigned char *addr,
361 u8 vid);
362 void icssg_vtbl_modify(struct prueth_emac *emac, u8 vid, u8 port_mask,
363 u8 untag_mask, bool add);
364 u16 icssg_get_pvid(struct prueth_emac *emac);
365 void icssg_set_pvid(struct prueth *prueth, u8 vid, u8 port);
366 #define prueth_napi_to_tx_chn(pnapi) \
367 container_of(pnapi, struct prueth_tx_chn, napi_tx)
368
369 void icssg_stats_work_handler(struct work_struct *work);
370 void emac_update_hardware_stats(struct prueth_emac *emac);
371 int emac_get_stat_by_name(struct prueth_emac *emac, char *stat_name);
372
373 /* Common functions */
374 void prueth_cleanup_rx_chns(struct prueth_emac *emac,
375 struct prueth_rx_chn *rx_chn,
376 int max_rflows);
377 void prueth_cleanup_tx_chns(struct prueth_emac *emac);
378 void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num);
379 void prueth_xmit_free(struct prueth_tx_chn *tx_chn,
380 struct cppi5_host_desc_t *desc);
381 int emac_tx_complete_packets(struct prueth_emac *emac, int chn,
382 int budget, bool *tdown);
383 int prueth_ndev_add_tx_napi(struct prueth_emac *emac);
384 int prueth_init_tx_chns(struct prueth_emac *emac);
385 int prueth_init_rx_chns(struct prueth_emac *emac,
386 struct prueth_rx_chn *rx_chn,
387 char *name, u32 max_rflows,
388 u32 max_desc_num);
389 int prueth_dma_rx_push(struct prueth_emac *emac,
390 struct sk_buff *skb,
391 struct prueth_rx_chn *rx_chn);
392 void emac_rx_timestamp(struct prueth_emac *emac,
393 struct sk_buff *skb, u32 *psdata);
394 enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev);
395 irqreturn_t prueth_rx_irq(int irq, void *dev_id);
396 void prueth_emac_stop(struct prueth_emac *emac);
397 void prueth_cleanup_tx_ts(struct prueth_emac *emac);
398 int icssg_napi_rx_poll(struct napi_struct *napi_rx, int budget);
399 int prueth_prepare_rx_chan(struct prueth_emac *emac,
400 struct prueth_rx_chn *chn,
401 int buf_size);
402 void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num,
403 bool free_skb);
404 void prueth_reset_rx_chan(struct prueth_rx_chn *chn,
405 int num_flows, bool disable);
406 void icssg_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
407 int icssg_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
408 void icssg_ndo_get_stats64(struct net_device *ndev,
409 struct rtnl_link_stats64 *stats);
410 int icssg_ndo_get_phys_port_name(struct net_device *ndev, char *name,
411 size_t len);
412 int prueth_node_port(struct device_node *eth_node);
413 int prueth_node_mac(struct device_node *eth_node);
414 void prueth_netdev_exit(struct prueth *prueth,
415 struct device_node *eth_node);
416 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1);
417 void prueth_put_cores(struct prueth *prueth, int slice);
418
419 /* Revision specific helper */
420 u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns);
421
422 #endif /* __NET_TI_ICSSG_PRUETH_H */
423