xref: /linux/drivers/mtd/chips/jedec_probe.c (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3    Common Flash Interface probe code.
4    (C) 2000 Red Hat.
5    See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
6    for the standard this probe goes back to.
7 
8    Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
9 */
10 
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <asm/io.h>
16 #include <asm/byteorder.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/interrupt.h>
20 
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/map.h>
23 #include <linux/mtd/cfi.h>
24 #include <linux/mtd/gen_probe.h>
25 
26 /* AMD */
27 #define AM29DL800BB	0x22CB
28 #define AM29DL800BT	0x224A
29 
30 #define AM29F800BB	0x2258
31 #define AM29F800BT	0x22D6
32 #define AM29LV400BB	0x22BA
33 #define AM29LV400BT	0x22B9
34 #define AM29LV800BB	0x225B
35 #define AM29LV800BT	0x22DA
36 #define AM29LV160DT	0x22C4
37 #define AM29LV160DB	0x2249
38 #define AM29F017D	0x003D
39 #define AM29F016D	0x00AD
40 #define AM29F080	0x00D5
41 #define AM29F040	0x00A4
42 #define AM29LV040B	0x004F
43 #define AM29F032B	0x0041
44 #define AM29F002T	0x00B0
45 #define AM29SL800DB	0x226B
46 #define AM29SL800DT	0x22EA
47 
48 /* Atmel */
49 #define AT49BV512	0x0003
50 #define AT29LV512	0x003d
51 #define AT49BV16X	0x00C0
52 #define AT49BV16XT	0x00C2
53 #define AT49BV32X	0x00C8
54 #define AT49BV32XT	0x00C9
55 
56 /* Eon */
57 #define EN29LV400AT	0x22B9
58 #define EN29LV400AB	0x22BA
59 #define EN29SL800BB	0x226B
60 #define EN29SL800BT	0x22EA
61 
62 /* Fujitsu */
63 #define MBM29F040C	0x00A4
64 #define MBM29F800BA	0x2258
65 #define MBM29LV650UE	0x22D7
66 #define MBM29LV320TE	0x22F6
67 #define MBM29LV320BE	0x22F9
68 #define MBM29LV160TE	0x22C4
69 #define MBM29LV160BE	0x2249
70 #define MBM29LV800BA	0x225B
71 #define MBM29LV800TA	0x22DA
72 #define MBM29LV400TC	0x22B9
73 #define MBM29LV400BC	0x22BA
74 
75 /* Hyundai */
76 #define HY29F002T	0x00B0
77 
78 /* Intel */
79 #define I28F004B3T	0x00d4
80 #define I28F004B3B	0x00d5
81 #define I28F400B3T	0x8894
82 #define I28F400B3B	0x8895
83 #define I28F008S5	0x00a6
84 #define I28F016S5	0x00a0
85 #define I28F008SA	0x00a2
86 #define I28F008B3T	0x00d2
87 #define I28F008B3B	0x00d3
88 #define I28F800B3T	0x8892
89 #define I28F800B3B	0x8893
90 #define I28F016S3	0x00aa
91 #define I28F016B3T	0x00d0
92 #define I28F016B3B	0x00d1
93 #define I28F160B3T	0x8890
94 #define I28F160B3B	0x8891
95 #define I28F320B3T	0x8896
96 #define I28F320B3B	0x8897
97 #define I28F640B3T	0x8898
98 #define I28F640B3B	0x8899
99 #define I28F640C3B	0x88CD
100 #define I28F160F3T	0x88F3
101 #define I28F160F3B	0x88F4
102 #define I28F160C3T	0x88C2
103 #define I28F160C3B	0x88C3
104 #define I82802AB	0x00ad
105 #define I82802AC	0x00ac
106 
107 /* Macronix */
108 #define MX29LV040C	0x004F
109 #define MX29LV160T	0x22C4
110 #define MX29LV160B	0x2249
111 #define MX29F040	0x00A4
112 #define MX29F016	0x00AD
113 #define MX29F002T	0x00B0
114 #define MX29F004T	0x0045
115 #define MX29F004B	0x0046
116 
117 /* NEC */
118 #define UPD29F064115	0x221C
119 
120 /* PMC */
121 #define PM49FL002	0x006D
122 #define PM49FL004	0x006E
123 #define PM49FL008	0x006A
124 
125 /* Sharp */
126 #define LH28F640BF	0x00B0
127 
128 /* ST - www.st.com */
129 #define M29F800AB	0x0058
130 #define M29W800DT	0x22D7
131 #define M29W800DB	0x225B
132 #define M29W400DT	0x00EE
133 #define M29W400DB	0x00EF
134 #define M29W160DT	0x22C4
135 #define M29W160DB	0x2249
136 #define M29W040B	0x00E3
137 #define M50FW040	0x002C
138 #define M50FW080	0x002D
139 #define M50FW016	0x002E
140 #define M50LPW080       0x002F
141 #define M50FLW080A	0x0080
142 #define M50FLW080B	0x0081
143 #define PSD4256G6V	0x00e9
144 
145 /* SST */
146 #define SST29EE020	0x0010
147 #define SST29LE020	0x0012
148 #define SST29EE512	0x005d
149 #define SST29LE512	0x003d
150 #define SST39LF800	0x2781
151 #define SST39LF160	0x2782
152 #define SST39VF1601	0x234b
153 #define SST39VF3201	0x235b
154 #define SST39WF1601	0x274b
155 #define SST39WF1602	0x274a
156 #define SST39LF512	0x00D4
157 #define SST39LF010	0x00D5
158 #define SST39LF020	0x00D6
159 #define SST39LF040	0x00D7
160 #define SST39SF010A	0x00B5
161 #define SST39SF020A	0x00B6
162 #define SST39SF040	0x00B7
163 #define SST49LF004B	0x0060
164 #define SST49LF040B	0x0050
165 #define SST49LF008A	0x005a
166 #define SST49LF030A	0x001C
167 #define SST49LF040A	0x0051
168 #define SST49LF080A	0x005B
169 #define SST36VF3203	0x7354
170 
171 /* Toshiba */
172 #define TC58FVT160	0x00C2
173 #define TC58FVB160	0x0043
174 #define TC58FVT321	0x009A
175 #define TC58FVB321	0x009C
176 #define TC58FVT641	0x0093
177 #define TC58FVB641	0x0095
178 
179 /* Winbond */
180 #define W49V002A	0x00b0
181 
182 
183 /*
184  * Unlock address sets for AMD command sets.
185  * Intel command sets use the MTD_UADDR_UNNECESSARY.
186  * Each identifier, except MTD_UADDR_UNNECESSARY, and
187  * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
188  * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
189  * initialization need not require initializing all of the
190  * unlock addresses for all bit widths.
191  */
192 enum uaddr {
193 	MTD_UADDR_NOT_SUPPORTED = 0,	/* data width not supported */
194 	MTD_UADDR_0x0555_0x02AA,
195 	MTD_UADDR_0x0555_0x0AAA,
196 	MTD_UADDR_0x5555_0x2AAA,
197 	MTD_UADDR_0x0AAA_0x0554,
198 	MTD_UADDR_0x0AAA_0x0555,
199 	MTD_UADDR_0xAAAA_0x5555,
200 	MTD_UADDR_DONT_CARE,		/* Requires an arbitrary address */
201 	MTD_UADDR_UNNECESSARY,		/* Does not require any address */
202 };
203 
204 
205 struct unlock_addr {
206 	uint32_t addr1;
207 	uint32_t addr2;
208 };
209 
210 
211 /*
212  * I don't like the fact that the first entry in unlock_addrs[]
213  * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
214  * should not be used.  The  problem is that structures with
215  * initializers have extra fields initialized to 0.  It is _very_
216  * desirable to have the unlock address entries for unsupported
217  * data widths automatically initialized - that means that
218  * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
219  * must go unused.
220  */
221 static const struct unlock_addr  unlock_addrs[] = {
222 	[MTD_UADDR_NOT_SUPPORTED] = {
223 		.addr1 = 0xffff,
224 		.addr2 = 0xffff
225 	},
226 
227 	[MTD_UADDR_0x0555_0x02AA] = {
228 		.addr1 = 0x0555,
229 		.addr2 = 0x02aa
230 	},
231 
232 	[MTD_UADDR_0x0555_0x0AAA] = {
233 		.addr1 = 0x0555,
234 		.addr2 = 0x0aaa
235 	},
236 
237 	[MTD_UADDR_0x5555_0x2AAA] = {
238 		.addr1 = 0x5555,
239 		.addr2 = 0x2aaa
240 	},
241 
242 	[MTD_UADDR_0x0AAA_0x0554] = {
243 		.addr1 = 0x0AAA,
244 		.addr2 = 0x0554
245 	},
246 
247 	[MTD_UADDR_0x0AAA_0x0555] = {
248 		.addr1 = 0x0AAA,
249 		.addr2 = 0x0555
250 	},
251 
252 	[MTD_UADDR_0xAAAA_0x5555] = {
253 		.addr1 = 0xaaaa,
254 		.addr2 = 0x5555
255 	},
256 
257 	[MTD_UADDR_DONT_CARE] = {
258 		.addr1 = 0x0000,      /* Doesn't matter which address */
259 		.addr2 = 0x0000       /* is used - must be last entry */
260 	},
261 
262 	[MTD_UADDR_UNNECESSARY] = {
263 		.addr1 = 0x0000,
264 		.addr2 = 0x0000
265 	}
266 };
267 
268 struct amd_flash_info {
269 	const char *name;
270 	const uint16_t mfr_id;
271 	const uint16_t dev_id;
272 	const uint8_t dev_size;
273 	const uint8_t nr_regions;
274 	const uint16_t cmd_set;
275 	const uint32_t regions[6];
276 	const uint8_t devtypes;		/* Bitmask for x8, x16 etc. */
277 	const uint8_t uaddr;		/* unlock addrs for 8, 16, 32, 64 */
278 };
279 
280 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
281 
282 #define SIZE_64KiB  16
283 #define SIZE_128KiB 17
284 #define SIZE_256KiB 18
285 #define SIZE_512KiB 19
286 #define SIZE_1MiB   20
287 #define SIZE_2MiB   21
288 #define SIZE_4MiB   22
289 #define SIZE_8MiB   23
290 
291 
292 /*
293  * Please keep this list ordered by manufacturer!
294  * Fortunately, the list isn't searched often and so a
295  * slow, linear search isn't so bad.
296  */
297 static const struct amd_flash_info jedec_table[] = {
298 	{
299 		.mfr_id		= CFI_MFR_AMD,
300 		.dev_id		= AM29F032B,
301 		.name		= "AMD AM29F032B",
302 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
303 		.devtypes	= CFI_DEVICETYPE_X8,
304 		.dev_size	= SIZE_4MiB,
305 		.cmd_set	= P_ID_AMD_STD,
306 		.nr_regions	= 1,
307 		.regions	= {
308 			ERASEINFO(0x10000,64)
309 		}
310 	}, {
311 		.mfr_id		= CFI_MFR_AMD,
312 		.dev_id		= AM29LV160DT,
313 		.name		= "AMD AM29LV160DT",
314 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
315 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
316 		.dev_size	= SIZE_2MiB,
317 		.cmd_set	= P_ID_AMD_STD,
318 		.nr_regions	= 4,
319 		.regions	= {
320 			ERASEINFO(0x10000,31),
321 			ERASEINFO(0x08000,1),
322 			ERASEINFO(0x02000,2),
323 			ERASEINFO(0x04000,1)
324 		}
325 	}, {
326 		.mfr_id		= CFI_MFR_AMD,
327 		.dev_id		= AM29LV160DB,
328 		.name		= "AMD AM29LV160DB",
329 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
330 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
331 		.dev_size	= SIZE_2MiB,
332 		.cmd_set	= P_ID_AMD_STD,
333 		.nr_regions	= 4,
334 		.regions	= {
335 			ERASEINFO(0x04000,1),
336 			ERASEINFO(0x02000,2),
337 			ERASEINFO(0x08000,1),
338 			ERASEINFO(0x10000,31)
339 		}
340 	}, {
341 		.mfr_id		= CFI_MFR_AMD,
342 		.dev_id		= AM29LV400BB,
343 		.name		= "AMD AM29LV400BB",
344 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
345 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
346 		.dev_size	= SIZE_512KiB,
347 		.cmd_set	= P_ID_AMD_STD,
348 		.nr_regions	= 4,
349 		.regions	= {
350 			ERASEINFO(0x04000,1),
351 			ERASEINFO(0x02000,2),
352 			ERASEINFO(0x08000,1),
353 			ERASEINFO(0x10000,7)
354 		}
355 	}, {
356 		.mfr_id		= CFI_MFR_AMD,
357 		.dev_id		= AM29LV400BT,
358 		.name		= "AMD AM29LV400BT",
359 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
360 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
361 		.dev_size	= SIZE_512KiB,
362 		.cmd_set	= P_ID_AMD_STD,
363 		.nr_regions	= 4,
364 		.regions	= {
365 			ERASEINFO(0x10000,7),
366 			ERASEINFO(0x08000,1),
367 			ERASEINFO(0x02000,2),
368 			ERASEINFO(0x04000,1)
369 		}
370 	}, {
371 		.mfr_id		= CFI_MFR_AMD,
372 		.dev_id		= AM29LV800BB,
373 		.name		= "AMD AM29LV800BB",
374 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
375 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
376 		.dev_size	= SIZE_1MiB,
377 		.cmd_set	= P_ID_AMD_STD,
378 		.nr_regions	= 4,
379 		.regions	= {
380 			ERASEINFO(0x04000,1),
381 			ERASEINFO(0x02000,2),
382 			ERASEINFO(0x08000,1),
383 			ERASEINFO(0x10000,15),
384 		}
385 	}, {
386 /* add DL */
387 		.mfr_id		= CFI_MFR_AMD,
388 		.dev_id		= AM29DL800BB,
389 		.name		= "AMD AM29DL800BB",
390 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
391 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
392 		.dev_size	= SIZE_1MiB,
393 		.cmd_set	= P_ID_AMD_STD,
394 		.nr_regions	= 6,
395 		.regions	= {
396 			ERASEINFO(0x04000,1),
397 			ERASEINFO(0x08000,1),
398 			ERASEINFO(0x02000,4),
399 			ERASEINFO(0x08000,1),
400 			ERASEINFO(0x04000,1),
401 			ERASEINFO(0x10000,14)
402 		}
403 	}, {
404 		.mfr_id		= CFI_MFR_AMD,
405 		.dev_id		= AM29DL800BT,
406 		.name		= "AMD AM29DL800BT",
407 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
408 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
409 		.dev_size	= SIZE_1MiB,
410 		.cmd_set	= P_ID_AMD_STD,
411 		.nr_regions	= 6,
412 		.regions	= {
413 			ERASEINFO(0x10000,14),
414 			ERASEINFO(0x04000,1),
415 			ERASEINFO(0x08000,1),
416 			ERASEINFO(0x02000,4),
417 			ERASEINFO(0x08000,1),
418 			ERASEINFO(0x04000,1)
419 		}
420 	}, {
421 		.mfr_id		= CFI_MFR_AMD,
422 		.dev_id		= AM29F800BB,
423 		.name		= "AMD AM29F800BB",
424 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
425 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
426 		.dev_size	= SIZE_1MiB,
427 		.cmd_set	= P_ID_AMD_STD,
428 		.nr_regions	= 4,
429 		.regions	= {
430 			ERASEINFO(0x04000,1),
431 			ERASEINFO(0x02000,2),
432 			ERASEINFO(0x08000,1),
433 			ERASEINFO(0x10000,15),
434 		}
435 	}, {
436 		.mfr_id		= CFI_MFR_AMD,
437 		.dev_id		= AM29LV800BT,
438 		.name		= "AMD AM29LV800BT",
439 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
440 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
441 		.dev_size	= SIZE_1MiB,
442 		.cmd_set	= P_ID_AMD_STD,
443 		.nr_regions	= 4,
444 		.regions	= {
445 			ERASEINFO(0x10000,15),
446 			ERASEINFO(0x08000,1),
447 			ERASEINFO(0x02000,2),
448 			ERASEINFO(0x04000,1)
449 		}
450 	}, {
451 		.mfr_id		= CFI_MFR_AMD,
452 		.dev_id		= AM29F800BT,
453 		.name		= "AMD AM29F800BT",
454 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
455 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
456 		.dev_size	= SIZE_1MiB,
457 		.cmd_set	= P_ID_AMD_STD,
458 		.nr_regions	= 4,
459 		.regions	= {
460 			ERASEINFO(0x10000,15),
461 			ERASEINFO(0x08000,1),
462 			ERASEINFO(0x02000,2),
463 			ERASEINFO(0x04000,1)
464 		}
465 	}, {
466 		.mfr_id		= CFI_MFR_AMD,
467 		.dev_id		= AM29F017D,
468 		.name		= "AMD AM29F017D",
469 		.devtypes	= CFI_DEVICETYPE_X8,
470 		.uaddr		= MTD_UADDR_DONT_CARE,
471 		.dev_size	= SIZE_2MiB,
472 		.cmd_set	= P_ID_AMD_STD,
473 		.nr_regions	= 1,
474 		.regions	= {
475 			ERASEINFO(0x10000,32),
476 		}
477 	}, {
478 		.mfr_id		= CFI_MFR_AMD,
479 		.dev_id		= AM29F016D,
480 		.name		= "AMD AM29F016D",
481 		.devtypes	= CFI_DEVICETYPE_X8,
482 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
483 		.dev_size	= SIZE_2MiB,
484 		.cmd_set	= P_ID_AMD_STD,
485 		.nr_regions	= 1,
486 		.regions	= {
487 			ERASEINFO(0x10000,32),
488 		}
489 	}, {
490 		.mfr_id		= CFI_MFR_AMD,
491 		.dev_id		= AM29F080,
492 		.name		= "AMD AM29F080",
493 		.devtypes	= CFI_DEVICETYPE_X8,
494 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
495 		.dev_size	= SIZE_1MiB,
496 		.cmd_set	= P_ID_AMD_STD,
497 		.nr_regions	= 1,
498 		.regions	= {
499 			ERASEINFO(0x10000,16),
500 		}
501 	}, {
502 		.mfr_id		= CFI_MFR_AMD,
503 		.dev_id		= AM29F040,
504 		.name		= "AMD AM29F040",
505 		.devtypes	= CFI_DEVICETYPE_X8,
506 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
507 		.dev_size	= SIZE_512KiB,
508 		.cmd_set	= P_ID_AMD_STD,
509 		.nr_regions	= 1,
510 		.regions	= {
511 			ERASEINFO(0x10000,8),
512 		}
513 	}, {
514 		.mfr_id		= CFI_MFR_AMD,
515 		.dev_id		= AM29LV040B,
516 		.name		= "AMD AM29LV040B",
517 		.devtypes	= CFI_DEVICETYPE_X8,
518 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
519 		.dev_size	= SIZE_512KiB,
520 		.cmd_set	= P_ID_AMD_STD,
521 		.nr_regions	= 1,
522 		.regions	= {
523 			ERASEINFO(0x10000,8),
524 		}
525 	}, {
526 		.mfr_id		= CFI_MFR_AMD,
527 		.dev_id		= AM29F002T,
528 		.name		= "AMD AM29F002T",
529 		.devtypes	= CFI_DEVICETYPE_X8,
530 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
531 		.dev_size	= SIZE_256KiB,
532 		.cmd_set	= P_ID_AMD_STD,
533 		.nr_regions	= 4,
534 		.regions	= {
535 			ERASEINFO(0x10000,3),
536 			ERASEINFO(0x08000,1),
537 			ERASEINFO(0x02000,2),
538 			ERASEINFO(0x04000,1),
539 		}
540 	}, {
541 		.mfr_id		= CFI_MFR_AMD,
542 		.dev_id		= AM29SL800DT,
543 		.name		= "AMD AM29SL800DT",
544 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
545 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
546 		.dev_size	= SIZE_1MiB,
547 		.cmd_set	= P_ID_AMD_STD,
548 		.nr_regions	= 4,
549 		.regions	= {
550 			ERASEINFO(0x10000,15),
551 			ERASEINFO(0x08000,1),
552 			ERASEINFO(0x02000,2),
553 			ERASEINFO(0x04000,1),
554 		}
555 	}, {
556 		.mfr_id		= CFI_MFR_AMD,
557 		.dev_id		= AM29SL800DB,
558 		.name		= "AMD AM29SL800DB",
559 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
560 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
561 		.dev_size	= SIZE_1MiB,
562 		.cmd_set	= P_ID_AMD_STD,
563 		.nr_regions	= 4,
564 		.regions	= {
565 			ERASEINFO(0x04000,1),
566 			ERASEINFO(0x02000,2),
567 			ERASEINFO(0x08000,1),
568 			ERASEINFO(0x10000,15),
569 		}
570 	}, {
571 		.mfr_id		= CFI_MFR_ATMEL,
572 		.dev_id		= AT49BV512,
573 		.name		= "Atmel AT49BV512",
574 		.devtypes	= CFI_DEVICETYPE_X8,
575 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
576 		.dev_size	= SIZE_64KiB,
577 		.cmd_set	= P_ID_AMD_STD,
578 		.nr_regions	= 1,
579 		.regions	= {
580 			ERASEINFO(0x10000,1)
581 		}
582 	}, {
583 		.mfr_id		= CFI_MFR_ATMEL,
584 		.dev_id		= AT29LV512,
585 		.name		= "Atmel AT29LV512",
586 		.devtypes	= CFI_DEVICETYPE_X8,
587 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
588 		.dev_size	= SIZE_64KiB,
589 		.cmd_set	= P_ID_AMD_STD,
590 		.nr_regions	= 1,
591 		.regions	= {
592 			ERASEINFO(0x80,256),
593 			ERASEINFO(0x80,256)
594 		}
595 	}, {
596 		.mfr_id		= CFI_MFR_ATMEL,
597 		.dev_id		= AT49BV16X,
598 		.name		= "Atmel AT49BV16X",
599 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
600 		.uaddr		= MTD_UADDR_0x0555_0x0AAA,	/* ???? */
601 		.dev_size	= SIZE_2MiB,
602 		.cmd_set	= P_ID_AMD_STD,
603 		.nr_regions	= 2,
604 		.regions	= {
605 			ERASEINFO(0x02000,8),
606 			ERASEINFO(0x10000,31)
607 		}
608 	}, {
609 		.mfr_id		= CFI_MFR_ATMEL,
610 		.dev_id		= AT49BV16XT,
611 		.name		= "Atmel AT49BV16XT",
612 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
613 		.uaddr		= MTD_UADDR_0x0555_0x0AAA,	/* ???? */
614 		.dev_size	= SIZE_2MiB,
615 		.cmd_set	= P_ID_AMD_STD,
616 		.nr_regions	= 2,
617 		.regions	= {
618 			ERASEINFO(0x10000,31),
619 			ERASEINFO(0x02000,8)
620 		}
621 	}, {
622 		.mfr_id		= CFI_MFR_ATMEL,
623 		.dev_id		= AT49BV32X,
624 		.name		= "Atmel AT49BV32X",
625 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
626 		.uaddr		= MTD_UADDR_0x0555_0x0AAA,	/* ???? */
627 		.dev_size	= SIZE_4MiB,
628 		.cmd_set	= P_ID_AMD_STD,
629 		.nr_regions	= 2,
630 		.regions	= {
631 			ERASEINFO(0x02000,8),
632 			ERASEINFO(0x10000,63)
633 		}
634 	}, {
635 		.mfr_id		= CFI_MFR_ATMEL,
636 		.dev_id		= AT49BV32XT,
637 		.name		= "Atmel AT49BV32XT",
638 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
639 		.uaddr		= MTD_UADDR_0x0555_0x0AAA,	/* ???? */
640 		.dev_size	= SIZE_4MiB,
641 		.cmd_set	= P_ID_AMD_STD,
642 		.nr_regions	= 2,
643 		.regions	= {
644 			ERASEINFO(0x10000,63),
645 			ERASEINFO(0x02000,8)
646 		}
647 	}, {
648 		.mfr_id		= CFI_MFR_EON,
649 		.dev_id		= EN29LV400AT,
650 		.name		= "Eon EN29LV400AT",
651 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
652 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
653 		.dev_size	= SIZE_512KiB,
654 		.cmd_set	= P_ID_AMD_STD,
655 		.nr_regions	= 4,
656 		.regions	= {
657 			ERASEINFO(0x10000,7),
658 			ERASEINFO(0x08000,1),
659 			ERASEINFO(0x02000,2),
660 			ERASEINFO(0x04000,1),
661 		}
662 	}, {
663 		.mfr_id		= CFI_MFR_EON,
664 		.dev_id		= EN29LV400AB,
665 		.name		= "Eon EN29LV400AB",
666 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
667 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
668 		.dev_size	= SIZE_512KiB,
669 		.cmd_set	= P_ID_AMD_STD,
670 		.nr_regions	= 4,
671 		.regions	= {
672 			ERASEINFO(0x04000,1),
673 			ERASEINFO(0x02000,2),
674 			ERASEINFO(0x08000,1),
675 			ERASEINFO(0x10000,7),
676 		}
677 	}, {
678 		.mfr_id		= CFI_MFR_EON,
679 		.dev_id		= EN29SL800BT,
680 		.name		= "Eon EN29SL800BT",
681 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
682 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
683 		.dev_size	= SIZE_1MiB,
684 		.cmd_set	= P_ID_AMD_STD,
685 		.nr_regions	= 4,
686 		.regions	= {
687 			ERASEINFO(0x10000,15),
688 			ERASEINFO(0x08000,1),
689 			ERASEINFO(0x02000,2),
690 			ERASEINFO(0x04000,1),
691 		}
692 	}, {
693 		.mfr_id		= CFI_MFR_EON,
694 		.dev_id		= EN29SL800BB,
695 		.name		= "Eon EN29SL800BB",
696 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
697 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
698 		.dev_size	= SIZE_1MiB,
699 		.cmd_set	= P_ID_AMD_STD,
700 		.nr_regions	= 4,
701 		.regions	= {
702 			ERASEINFO(0x04000,1),
703 			ERASEINFO(0x02000,2),
704 			ERASEINFO(0x08000,1),
705 			ERASEINFO(0x10000,15),
706 		}
707 	}, {
708 		.mfr_id		= CFI_MFR_FUJITSU,
709 		.dev_id		= MBM29F040C,
710 		.name		= "Fujitsu MBM29F040C",
711 		.devtypes	= CFI_DEVICETYPE_X8,
712 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
713 		.dev_size	= SIZE_512KiB,
714 		.cmd_set	= P_ID_AMD_STD,
715 		.nr_regions	= 1,
716 		.regions	= {
717 			ERASEINFO(0x10000,8)
718 		}
719 	}, {
720 		.mfr_id		= CFI_MFR_FUJITSU,
721 		.dev_id		= MBM29F800BA,
722 		.name		= "Fujitsu MBM29F800BA",
723 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
724 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
725 		.dev_size	= SIZE_1MiB,
726 		.cmd_set	= P_ID_AMD_STD,
727 		.nr_regions	= 4,
728 		.regions	= {
729 			ERASEINFO(0x04000,1),
730 			ERASEINFO(0x02000,2),
731 			ERASEINFO(0x08000,1),
732 			ERASEINFO(0x10000,15),
733 		}
734 	}, {
735 		.mfr_id		= CFI_MFR_FUJITSU,
736 		.dev_id		= MBM29LV650UE,
737 		.name		= "Fujitsu MBM29LV650UE",
738 		.devtypes	= CFI_DEVICETYPE_X8,
739 		.uaddr		= MTD_UADDR_DONT_CARE,
740 		.dev_size	= SIZE_8MiB,
741 		.cmd_set	= P_ID_AMD_STD,
742 		.nr_regions	= 1,
743 		.regions	= {
744 			ERASEINFO(0x10000,128)
745 		}
746 	}, {
747 		.mfr_id		= CFI_MFR_FUJITSU,
748 		.dev_id		= MBM29LV320TE,
749 		.name		= "Fujitsu MBM29LV320TE",
750 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
751 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
752 		.dev_size	= SIZE_4MiB,
753 		.cmd_set	= P_ID_AMD_STD,
754 		.nr_regions	= 2,
755 		.regions	= {
756 			ERASEINFO(0x10000,63),
757 			ERASEINFO(0x02000,8)
758 		}
759 	}, {
760 		.mfr_id		= CFI_MFR_FUJITSU,
761 		.dev_id		= MBM29LV320BE,
762 		.name		= "Fujitsu MBM29LV320BE",
763 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
764 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
765 		.dev_size	= SIZE_4MiB,
766 		.cmd_set	= P_ID_AMD_STD,
767 		.nr_regions	= 2,
768 		.regions	= {
769 			ERASEINFO(0x02000,8),
770 			ERASEINFO(0x10000,63)
771 		}
772 	}, {
773 		.mfr_id		= CFI_MFR_FUJITSU,
774 		.dev_id		= MBM29LV160TE,
775 		.name		= "Fujitsu MBM29LV160TE",
776 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
777 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
778 		.dev_size	= SIZE_2MiB,
779 		.cmd_set	= P_ID_AMD_STD,
780 		.nr_regions	= 4,
781 		.regions	= {
782 			ERASEINFO(0x10000,31),
783 			ERASEINFO(0x08000,1),
784 			ERASEINFO(0x02000,2),
785 			ERASEINFO(0x04000,1)
786 		}
787 	}, {
788 		.mfr_id		= CFI_MFR_FUJITSU,
789 		.dev_id		= MBM29LV160BE,
790 		.name		= "Fujitsu MBM29LV160BE",
791 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
792 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
793 		.dev_size	= SIZE_2MiB,
794 		.cmd_set	= P_ID_AMD_STD,
795 		.nr_regions	= 4,
796 		.regions	= {
797 			ERASEINFO(0x04000,1),
798 			ERASEINFO(0x02000,2),
799 			ERASEINFO(0x08000,1),
800 			ERASEINFO(0x10000,31)
801 		}
802 	}, {
803 		.mfr_id		= CFI_MFR_FUJITSU,
804 		.dev_id		= MBM29LV800BA,
805 		.name		= "Fujitsu MBM29LV800BA",
806 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
807 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
808 		.dev_size	= SIZE_1MiB,
809 		.cmd_set	= P_ID_AMD_STD,
810 		.nr_regions	= 4,
811 		.regions	= {
812 			ERASEINFO(0x04000,1),
813 			ERASEINFO(0x02000,2),
814 			ERASEINFO(0x08000,1),
815 			ERASEINFO(0x10000,15)
816 		}
817 	}, {
818 		.mfr_id		= CFI_MFR_FUJITSU,
819 		.dev_id		= MBM29LV800TA,
820 		.name		= "Fujitsu MBM29LV800TA",
821 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
822 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
823 		.dev_size	= SIZE_1MiB,
824 		.cmd_set	= P_ID_AMD_STD,
825 		.nr_regions	= 4,
826 		.regions	= {
827 			ERASEINFO(0x10000,15),
828 			ERASEINFO(0x08000,1),
829 			ERASEINFO(0x02000,2),
830 			ERASEINFO(0x04000,1)
831 		}
832 	}, {
833 		.mfr_id		= CFI_MFR_FUJITSU,
834 		.dev_id		= MBM29LV400BC,
835 		.name		= "Fujitsu MBM29LV400BC",
836 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
837 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
838 		.dev_size	= SIZE_512KiB,
839 		.cmd_set	= P_ID_AMD_STD,
840 		.nr_regions	= 4,
841 		.regions	= {
842 			ERASEINFO(0x04000,1),
843 			ERASEINFO(0x02000,2),
844 			ERASEINFO(0x08000,1),
845 			ERASEINFO(0x10000,7)
846 		}
847 	}, {
848 		.mfr_id		= CFI_MFR_FUJITSU,
849 		.dev_id		= MBM29LV400TC,
850 		.name		= "Fujitsu MBM29LV400TC",
851 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
852 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
853 		.dev_size	= SIZE_512KiB,
854 		.cmd_set	= P_ID_AMD_STD,
855 		.nr_regions	= 4,
856 		.regions	= {
857 			ERASEINFO(0x10000,7),
858 			ERASEINFO(0x08000,1),
859 			ERASEINFO(0x02000,2),
860 			ERASEINFO(0x04000,1)
861 		}
862 	}, {
863 		.mfr_id		= CFI_MFR_HYUNDAI,
864 		.dev_id		= HY29F002T,
865 		.name		= "Hyundai HY29F002T",
866 		.devtypes	= CFI_DEVICETYPE_X8,
867 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
868 		.dev_size	= SIZE_256KiB,
869 		.cmd_set	= P_ID_AMD_STD,
870 		.nr_regions	= 4,
871 		.regions	= {
872 			ERASEINFO(0x10000,3),
873 			ERASEINFO(0x08000,1),
874 			ERASEINFO(0x02000,2),
875 			ERASEINFO(0x04000,1),
876 		}
877 	}, {
878 		.mfr_id		= CFI_MFR_INTEL,
879 		.dev_id		= I28F004B3B,
880 		.name		= "Intel 28F004B3B",
881 		.devtypes	= CFI_DEVICETYPE_X8,
882 		.uaddr		= MTD_UADDR_UNNECESSARY,
883 		.dev_size	= SIZE_512KiB,
884 		.cmd_set	= P_ID_INTEL_STD,
885 		.nr_regions	= 2,
886 		.regions	= {
887 			ERASEINFO(0x02000, 8),
888 			ERASEINFO(0x10000, 7),
889 		}
890 	}, {
891 		.mfr_id		= CFI_MFR_INTEL,
892 		.dev_id		= I28F004B3T,
893 		.name		= "Intel 28F004B3T",
894 		.devtypes	= CFI_DEVICETYPE_X8,
895 		.uaddr		= MTD_UADDR_UNNECESSARY,
896 		.dev_size	= SIZE_512KiB,
897 		.cmd_set	= P_ID_INTEL_STD,
898 		.nr_regions	= 2,
899 		.regions	= {
900 			ERASEINFO(0x10000, 7),
901 			ERASEINFO(0x02000, 8),
902 		}
903 	}, {
904 		.mfr_id		= CFI_MFR_INTEL,
905 		.dev_id		= I28F400B3B,
906 		.name		= "Intel 28F400B3B",
907 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
908 		.uaddr		= MTD_UADDR_UNNECESSARY,
909 		.dev_size	= SIZE_512KiB,
910 		.cmd_set	= P_ID_INTEL_STD,
911 		.nr_regions	= 2,
912 		.regions	= {
913 			ERASEINFO(0x02000, 8),
914 			ERASEINFO(0x10000, 7),
915 		}
916 	}, {
917 		.mfr_id		= CFI_MFR_INTEL,
918 		.dev_id		= I28F400B3T,
919 		.name		= "Intel 28F400B3T",
920 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
921 		.uaddr		= MTD_UADDR_UNNECESSARY,
922 		.dev_size	= SIZE_512KiB,
923 		.cmd_set	= P_ID_INTEL_STD,
924 		.nr_regions	= 2,
925 		.regions	= {
926 			ERASEINFO(0x10000, 7),
927 			ERASEINFO(0x02000, 8),
928 		}
929 	}, {
930 		.mfr_id		= CFI_MFR_INTEL,
931 		.dev_id		= I28F008B3B,
932 		.name		= "Intel 28F008B3B",
933 		.devtypes	= CFI_DEVICETYPE_X8,
934 		.uaddr		= MTD_UADDR_UNNECESSARY,
935 		.dev_size	= SIZE_1MiB,
936 		.cmd_set	= P_ID_INTEL_STD,
937 		.nr_regions	= 2,
938 		.regions	= {
939 			ERASEINFO(0x02000, 8),
940 			ERASEINFO(0x10000, 15),
941 		}
942 	}, {
943 		.mfr_id		= CFI_MFR_INTEL,
944 		.dev_id		= I28F008B3T,
945 		.name		= "Intel 28F008B3T",
946 		.devtypes	= CFI_DEVICETYPE_X8,
947 		.uaddr		= MTD_UADDR_UNNECESSARY,
948 		.dev_size	= SIZE_1MiB,
949 		.cmd_set	= P_ID_INTEL_STD,
950 		.nr_regions	= 2,
951 		.regions	= {
952 			ERASEINFO(0x10000, 15),
953 			ERASEINFO(0x02000, 8),
954 		}
955 	}, {
956 		.mfr_id		= CFI_MFR_INTEL,
957 		.dev_id		= I28F008S5,
958 		.name		= "Intel 28F008S5",
959 		.devtypes	= CFI_DEVICETYPE_X8,
960 		.uaddr		= MTD_UADDR_UNNECESSARY,
961 		.dev_size	= SIZE_1MiB,
962 		.cmd_set	= P_ID_INTEL_EXT,
963 		.nr_regions	= 1,
964 		.regions	= {
965 			ERASEINFO(0x10000,16),
966 		}
967 	}, {
968 		.mfr_id		= CFI_MFR_INTEL,
969 		.dev_id		= I28F016S5,
970 		.name		= "Intel 28F016S5",
971 		.devtypes	= CFI_DEVICETYPE_X8,
972 		.uaddr		= MTD_UADDR_UNNECESSARY,
973 		.dev_size	= SIZE_2MiB,
974 		.cmd_set	= P_ID_INTEL_EXT,
975 		.nr_regions	= 1,
976 		.regions	= {
977 			ERASEINFO(0x10000,32),
978 		}
979 	}, {
980 		.mfr_id		= CFI_MFR_INTEL,
981 		.dev_id		= I28F008SA,
982 		.name		= "Intel 28F008SA",
983 		.devtypes	= CFI_DEVICETYPE_X8,
984 		.uaddr		= MTD_UADDR_UNNECESSARY,
985 		.dev_size	= SIZE_1MiB,
986 		.cmd_set	= P_ID_INTEL_STD,
987 		.nr_regions	= 1,
988 		.regions	= {
989 			ERASEINFO(0x10000, 16),
990 		}
991 	}, {
992 		.mfr_id		= CFI_MFR_INTEL,
993 		.dev_id		= I28F800B3B,
994 		.name		= "Intel 28F800B3B",
995 		.devtypes	= CFI_DEVICETYPE_X16,
996 		.uaddr		= MTD_UADDR_UNNECESSARY,
997 		.dev_size	= SIZE_1MiB,
998 		.cmd_set	= P_ID_INTEL_STD,
999 		.nr_regions	= 2,
1000 		.regions	= {
1001 			ERASEINFO(0x02000, 8),
1002 			ERASEINFO(0x10000, 15),
1003 		}
1004 	}, {
1005 		.mfr_id		= CFI_MFR_INTEL,
1006 		.dev_id		= I28F800B3T,
1007 		.name		= "Intel 28F800B3T",
1008 		.devtypes	= CFI_DEVICETYPE_X16,
1009 		.uaddr		= MTD_UADDR_UNNECESSARY,
1010 		.dev_size	= SIZE_1MiB,
1011 		.cmd_set	= P_ID_INTEL_STD,
1012 		.nr_regions	= 2,
1013 		.regions	= {
1014 			ERASEINFO(0x10000, 15),
1015 			ERASEINFO(0x02000, 8),
1016 		}
1017 	}, {
1018 		.mfr_id		= CFI_MFR_INTEL,
1019 		.dev_id		= I28F016B3B,
1020 		.name		= "Intel 28F016B3B",
1021 		.devtypes	= CFI_DEVICETYPE_X8,
1022 		.uaddr		= MTD_UADDR_UNNECESSARY,
1023 		.dev_size	= SIZE_2MiB,
1024 		.cmd_set	= P_ID_INTEL_STD,
1025 		.nr_regions	= 2,
1026 		.regions	= {
1027 			ERASEINFO(0x02000, 8),
1028 			ERASEINFO(0x10000, 31),
1029 		}
1030 	}, {
1031 		.mfr_id		= CFI_MFR_INTEL,
1032 		.dev_id		= I28F016S3,
1033 		.name		= "Intel I28F016S3",
1034 		.devtypes	= CFI_DEVICETYPE_X8,
1035 		.uaddr		= MTD_UADDR_UNNECESSARY,
1036 		.dev_size	= SIZE_2MiB,
1037 		.cmd_set	= P_ID_INTEL_STD,
1038 		.nr_regions	= 1,
1039 		.regions	= {
1040 			ERASEINFO(0x10000, 32),
1041 		}
1042 	}, {
1043 		.mfr_id		= CFI_MFR_INTEL,
1044 		.dev_id		= I28F016B3T,
1045 		.name		= "Intel 28F016B3T",
1046 		.devtypes	= CFI_DEVICETYPE_X8,
1047 		.uaddr		= MTD_UADDR_UNNECESSARY,
1048 		.dev_size	= SIZE_2MiB,
1049 		.cmd_set	= P_ID_INTEL_STD,
1050 		.nr_regions	= 2,
1051 		.regions	= {
1052 			ERASEINFO(0x10000, 31),
1053 			ERASEINFO(0x02000, 8),
1054 		}
1055 	}, {
1056 		.mfr_id		= CFI_MFR_INTEL,
1057 		.dev_id		= I28F160B3B,
1058 		.name		= "Intel 28F160B3B",
1059 		.devtypes	= CFI_DEVICETYPE_X16,
1060 		.uaddr		= MTD_UADDR_UNNECESSARY,
1061 		.dev_size	= SIZE_2MiB,
1062 		.cmd_set	= P_ID_INTEL_STD,
1063 		.nr_regions	= 2,
1064 		.regions	= {
1065 			ERASEINFO(0x02000, 8),
1066 			ERASEINFO(0x10000, 31),
1067 		}
1068 	}, {
1069 		.mfr_id		= CFI_MFR_INTEL,
1070 		.dev_id		= I28F160B3T,
1071 		.name		= "Intel 28F160B3T",
1072 		.devtypes	= CFI_DEVICETYPE_X16,
1073 		.uaddr		= MTD_UADDR_UNNECESSARY,
1074 		.dev_size	= SIZE_2MiB,
1075 		.cmd_set	= P_ID_INTEL_STD,
1076 		.nr_regions	= 2,
1077 		.regions	= {
1078 			ERASEINFO(0x10000, 31),
1079 			ERASEINFO(0x02000, 8),
1080 		}
1081 	}, {
1082 		.mfr_id		= CFI_MFR_INTEL,
1083 		.dev_id		= I28F320B3B,
1084 		.name		= "Intel 28F320B3B",
1085 		.devtypes	= CFI_DEVICETYPE_X16,
1086 		.uaddr		= MTD_UADDR_UNNECESSARY,
1087 		.dev_size	= SIZE_4MiB,
1088 		.cmd_set	= P_ID_INTEL_STD,
1089 		.nr_regions	= 2,
1090 		.regions	= {
1091 			ERASEINFO(0x02000, 8),
1092 			ERASEINFO(0x10000, 63),
1093 		}
1094 	}, {
1095 		.mfr_id		= CFI_MFR_INTEL,
1096 		.dev_id		= I28F320B3T,
1097 		.name		= "Intel 28F320B3T",
1098 		.devtypes	= CFI_DEVICETYPE_X16,
1099 		.uaddr		= MTD_UADDR_UNNECESSARY,
1100 		.dev_size	= SIZE_4MiB,
1101 		.cmd_set	= P_ID_INTEL_STD,
1102 		.nr_regions	= 2,
1103 		.regions	= {
1104 			ERASEINFO(0x10000, 63),
1105 			ERASEINFO(0x02000, 8),
1106 		}
1107 	}, {
1108 		.mfr_id		= CFI_MFR_INTEL,
1109 		.dev_id		= I28F640B3B,
1110 		.name		= "Intel 28F640B3B",
1111 		.devtypes	= CFI_DEVICETYPE_X16,
1112 		.uaddr		= MTD_UADDR_UNNECESSARY,
1113 		.dev_size	= SIZE_8MiB,
1114 		.cmd_set	= P_ID_INTEL_STD,
1115 		.nr_regions	= 2,
1116 		.regions	= {
1117 			ERASEINFO(0x02000, 8),
1118 			ERASEINFO(0x10000, 127),
1119 		}
1120 	}, {
1121 		.mfr_id		= CFI_MFR_INTEL,
1122 		.dev_id		= I28F640B3T,
1123 		.name		= "Intel 28F640B3T",
1124 		.devtypes	= CFI_DEVICETYPE_X16,
1125 		.uaddr		= MTD_UADDR_UNNECESSARY,
1126 		.dev_size	= SIZE_8MiB,
1127 		.cmd_set	= P_ID_INTEL_STD,
1128 		.nr_regions	= 2,
1129 		.regions	= {
1130 			ERASEINFO(0x10000, 127),
1131 			ERASEINFO(0x02000, 8),
1132 		}
1133 	}, {
1134 		.mfr_id		= CFI_MFR_INTEL,
1135 		.dev_id		= I28F640C3B,
1136 		.name		= "Intel 28F640C3B",
1137 		.devtypes	= CFI_DEVICETYPE_X16,
1138 		.uaddr		= MTD_UADDR_UNNECESSARY,
1139 		.dev_size	= SIZE_8MiB,
1140 		.cmd_set	= P_ID_INTEL_STD,
1141 		.nr_regions	= 2,
1142 		.regions	= {
1143 			ERASEINFO(0x02000, 8),
1144 			ERASEINFO(0x10000, 127),
1145 		}
1146 	}, {
1147 		.mfr_id		= CFI_MFR_INTEL,
1148 		.dev_id		= I82802AB,
1149 		.name		= "Intel 82802AB",
1150 		.devtypes	= CFI_DEVICETYPE_X8,
1151 		.uaddr		= MTD_UADDR_UNNECESSARY,
1152 		.dev_size	= SIZE_512KiB,
1153 		.cmd_set	= P_ID_INTEL_EXT,
1154 		.nr_regions	= 1,
1155 		.regions	= {
1156 			ERASEINFO(0x10000,8),
1157 		}
1158 	}, {
1159 		.mfr_id		= CFI_MFR_INTEL,
1160 		.dev_id		= I82802AC,
1161 		.name		= "Intel 82802AC",
1162 		.devtypes	= CFI_DEVICETYPE_X8,
1163 		.uaddr		= MTD_UADDR_UNNECESSARY,
1164 		.dev_size	= SIZE_1MiB,
1165 		.cmd_set	= P_ID_INTEL_EXT,
1166 		.nr_regions	= 1,
1167 		.regions	= {
1168 			ERASEINFO(0x10000,16),
1169 		}
1170 	}, {
1171 		.mfr_id		= CFI_MFR_MACRONIX,
1172 		.dev_id		= MX29LV040C,
1173 		.name		= "Macronix MX29LV040C",
1174 		.devtypes	= CFI_DEVICETYPE_X8,
1175 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1176 		.dev_size	= SIZE_512KiB,
1177 		.cmd_set	= P_ID_AMD_STD,
1178 		.nr_regions	= 1,
1179 		.regions	= {
1180 			ERASEINFO(0x10000,8),
1181 		}
1182 	}, {
1183 		.mfr_id		= CFI_MFR_MACRONIX,
1184 		.dev_id		= MX29LV160T,
1185 		.name		= "MXIC MX29LV160T",
1186 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1187 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1188 		.dev_size	= SIZE_2MiB,
1189 		.cmd_set	= P_ID_AMD_STD,
1190 		.nr_regions	= 4,
1191 		.regions	= {
1192 			ERASEINFO(0x10000,31),
1193 			ERASEINFO(0x08000,1),
1194 			ERASEINFO(0x02000,2),
1195 			ERASEINFO(0x04000,1)
1196 		}
1197 	}, {
1198 		.mfr_id		= CFI_MFR_NEC,
1199 		.dev_id		= UPD29F064115,
1200 		.name		= "NEC uPD29F064115",
1201 		.devtypes	= CFI_DEVICETYPE_X16,
1202 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1203 		.dev_size	= SIZE_8MiB,
1204 		.cmd_set	= P_ID_AMD_STD,
1205 		.nr_regions	= 3,
1206 		.regions	= {
1207 			ERASEINFO(0x2000,8),
1208 			ERASEINFO(0x10000,126),
1209 			ERASEINFO(0x2000,8),
1210 		}
1211 	}, {
1212 		.mfr_id		= CFI_MFR_MACRONIX,
1213 		.dev_id		= MX29LV160B,
1214 		.name		= "MXIC MX29LV160B",
1215 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1216 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1217 		.dev_size	= SIZE_2MiB,
1218 		.cmd_set	= P_ID_AMD_STD,
1219 		.nr_regions	= 4,
1220 		.regions	= {
1221 			ERASEINFO(0x04000,1),
1222 			ERASEINFO(0x02000,2),
1223 			ERASEINFO(0x08000,1),
1224 			ERASEINFO(0x10000,31)
1225 		}
1226 	}, {
1227 		.mfr_id		= CFI_MFR_MACRONIX,
1228 		.dev_id		= MX29F040,
1229 		.name		= "Macronix MX29F040",
1230 		.devtypes	= CFI_DEVICETYPE_X8,
1231 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1232 		.dev_size	= SIZE_512KiB,
1233 		.cmd_set	= P_ID_AMD_STD,
1234 		.nr_regions	= 1,
1235 		.regions	= {
1236 			ERASEINFO(0x10000,8),
1237 		}
1238 	}, {
1239 		.mfr_id		= CFI_MFR_MACRONIX,
1240 		.dev_id		= MX29F016,
1241 		.name		= "Macronix MX29F016",
1242 		.devtypes	= CFI_DEVICETYPE_X8,
1243 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1244 		.dev_size	= SIZE_2MiB,
1245 		.cmd_set	= P_ID_AMD_STD,
1246 		.nr_regions	= 1,
1247 		.regions	= {
1248 			ERASEINFO(0x10000,32),
1249 		}
1250 	}, {
1251 		.mfr_id		= CFI_MFR_MACRONIX,
1252 		.dev_id		= MX29F004T,
1253 		.name		= "Macronix MX29F004T",
1254 		.devtypes	= CFI_DEVICETYPE_X8,
1255 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1256 		.dev_size	= SIZE_512KiB,
1257 		.cmd_set	= P_ID_AMD_STD,
1258 		.nr_regions	= 4,
1259 		.regions	= {
1260 			ERASEINFO(0x10000,7),
1261 			ERASEINFO(0x08000,1),
1262 			ERASEINFO(0x02000,2),
1263 			ERASEINFO(0x04000,1),
1264 		}
1265 	}, {
1266 		.mfr_id		= CFI_MFR_MACRONIX,
1267 		.dev_id		= MX29F004B,
1268 		.name		= "Macronix MX29F004B",
1269 		.devtypes	= CFI_DEVICETYPE_X8,
1270 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1271 		.dev_size	= SIZE_512KiB,
1272 		.cmd_set	= P_ID_AMD_STD,
1273 		.nr_regions	= 4,
1274 		.regions	= {
1275 			ERASEINFO(0x04000,1),
1276 			ERASEINFO(0x02000,2),
1277 			ERASEINFO(0x08000,1),
1278 			ERASEINFO(0x10000,7),
1279 		}
1280 	}, {
1281 		.mfr_id		= CFI_MFR_MACRONIX,
1282 		.dev_id		= MX29F002T,
1283 		.name		= "Macronix MX29F002T",
1284 		.devtypes	= CFI_DEVICETYPE_X8,
1285 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1286 		.dev_size	= SIZE_256KiB,
1287 		.cmd_set	= P_ID_AMD_STD,
1288 		.nr_regions	= 4,
1289 		.regions	= {
1290 			ERASEINFO(0x10000,3),
1291 			ERASEINFO(0x08000,1),
1292 			ERASEINFO(0x02000,2),
1293 			ERASEINFO(0x04000,1),
1294 		}
1295 	}, {
1296 		.mfr_id		= CFI_MFR_PMC,
1297 		.dev_id		= PM49FL002,
1298 		.name		= "PMC Pm49FL002",
1299 		.devtypes	= CFI_DEVICETYPE_X8,
1300 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1301 		.dev_size	= SIZE_256KiB,
1302 		.cmd_set	= P_ID_AMD_STD,
1303 		.nr_regions	= 1,
1304 		.regions	= {
1305 			ERASEINFO( 0x01000, 64 )
1306 		}
1307 	}, {
1308 		.mfr_id		= CFI_MFR_PMC,
1309 		.dev_id		= PM49FL004,
1310 		.name		= "PMC Pm49FL004",
1311 		.devtypes	= CFI_DEVICETYPE_X8,
1312 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1313 		.dev_size	= SIZE_512KiB,
1314 		.cmd_set	= P_ID_AMD_STD,
1315 		.nr_regions	= 1,
1316 		.regions	= {
1317 			ERASEINFO( 0x01000, 128 )
1318 		}
1319 	}, {
1320 		.mfr_id		= CFI_MFR_PMC,
1321 		.dev_id		= PM49FL008,
1322 		.name		= "PMC Pm49FL008",
1323 		.devtypes	= CFI_DEVICETYPE_X8,
1324 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1325 		.dev_size	= SIZE_1MiB,
1326 		.cmd_set	= P_ID_AMD_STD,
1327 		.nr_regions	= 1,
1328 		.regions	= {
1329 			ERASEINFO( 0x01000, 256 )
1330 		}
1331 	}, {
1332 		.mfr_id		= CFI_MFR_SHARP,
1333 		.dev_id		= LH28F640BF,
1334 		.name		= "LH28F640BF",
1335 		.devtypes	= CFI_DEVICETYPE_X16,
1336 		.uaddr		= MTD_UADDR_UNNECESSARY,
1337 		.dev_size	= SIZE_8MiB,
1338 		.cmd_set	= P_ID_INTEL_EXT,
1339 		.nr_regions	= 2,
1340 		.regions	= {
1341 			ERASEINFO(0x10000, 127),
1342 			ERASEINFO(0x02000, 8),
1343 		}
1344 	}, {
1345 		.mfr_id		= CFI_MFR_SST,
1346 		.dev_id		= SST39LF512,
1347 		.name		= "SST 39LF512",
1348 		.devtypes	= CFI_DEVICETYPE_X8,
1349 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1350 		.dev_size	= SIZE_64KiB,
1351 		.cmd_set	= P_ID_AMD_STD,
1352 		.nr_regions	= 1,
1353 		.regions	= {
1354 			ERASEINFO(0x01000,16),
1355 		}
1356 	}, {
1357 		.mfr_id		= CFI_MFR_SST,
1358 		.dev_id		= SST39LF010,
1359 		.name		= "SST 39LF010",
1360 		.devtypes	= CFI_DEVICETYPE_X8,
1361 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1362 		.dev_size	= SIZE_128KiB,
1363 		.cmd_set	= P_ID_AMD_STD,
1364 		.nr_regions	= 1,
1365 		.regions	= {
1366 			ERASEINFO(0x01000,32),
1367 		}
1368 	}, {
1369 		.mfr_id		= CFI_MFR_SST,
1370 		.dev_id		= SST29EE020,
1371 		.name		= "SST 29EE020",
1372 		.devtypes	= CFI_DEVICETYPE_X8,
1373 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1374 		.dev_size	= SIZE_256KiB,
1375 		.cmd_set	= P_ID_SST_PAGE,
1376 		.nr_regions	= 1,
1377 		.regions = {ERASEINFO(0x01000,64),
1378 		}
1379 	}, {
1380 		.mfr_id		= CFI_MFR_SST,
1381 		.dev_id		= SST29LE020,
1382 		.name		= "SST 29LE020",
1383 		.devtypes	= CFI_DEVICETYPE_X8,
1384 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1385 		.dev_size	= SIZE_256KiB,
1386 		.cmd_set	= P_ID_SST_PAGE,
1387 		.nr_regions	= 1,
1388 		.regions = {ERASEINFO(0x01000,64),
1389 		}
1390 	}, {
1391 		.mfr_id		= CFI_MFR_SST,
1392 		.dev_id		= SST39LF020,
1393 		.name		= "SST 39LF020",
1394 		.devtypes	= CFI_DEVICETYPE_X8,
1395 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1396 		.dev_size	= SIZE_256KiB,
1397 		.cmd_set	= P_ID_AMD_STD,
1398 		.nr_regions	= 1,
1399 		.regions	= {
1400 			ERASEINFO(0x01000,64),
1401 		}
1402 	}, {
1403 		.mfr_id		= CFI_MFR_SST,
1404 		.dev_id		= SST39LF040,
1405 		.name		= "SST 39LF040",
1406 		.devtypes	= CFI_DEVICETYPE_X8,
1407 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1408 		.dev_size	= SIZE_512KiB,
1409 		.cmd_set	= P_ID_AMD_STD,
1410 		.nr_regions	= 1,
1411 		.regions	= {
1412 			ERASEINFO(0x01000,128),
1413 		}
1414 	}, {
1415 		.mfr_id		= CFI_MFR_SST,
1416 		.dev_id		= SST39SF010A,
1417 		.name		= "SST 39SF010A",
1418 		.devtypes	= CFI_DEVICETYPE_X8,
1419 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1420 		.dev_size	= SIZE_128KiB,
1421 		.cmd_set	= P_ID_AMD_STD,
1422 		.nr_regions	= 1,
1423 		.regions	= {
1424 			ERASEINFO(0x01000,32),
1425 		}
1426 	}, {
1427 		.mfr_id		= CFI_MFR_SST,
1428 		.dev_id		= SST39SF020A,
1429 		.name		= "SST 39SF020A",
1430 		.devtypes	= CFI_DEVICETYPE_X8,
1431 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1432 		.dev_size	= SIZE_256KiB,
1433 		.cmd_set	= P_ID_AMD_STD,
1434 		.nr_regions	= 1,
1435 		.regions	= {
1436 			ERASEINFO(0x01000,64),
1437 		}
1438 	}, {
1439 		.mfr_id		= CFI_MFR_SST,
1440 		.dev_id		= SST39SF040,
1441 		.name		= "SST 39SF040",
1442 		.devtypes	= CFI_DEVICETYPE_X8,
1443 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1444 		.dev_size	= SIZE_512KiB,
1445 		.cmd_set	= P_ID_AMD_STD,
1446 		.nr_regions	= 1,
1447 		.regions	= {
1448 			ERASEINFO(0x01000,128),
1449 		}
1450 	}, {
1451 		.mfr_id		= CFI_MFR_SST,
1452 		.dev_id		= SST49LF040B,
1453 		.name		= "SST 49LF040B",
1454 		.devtypes	= CFI_DEVICETYPE_X8,
1455 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1456 		.dev_size	= SIZE_512KiB,
1457 		.cmd_set	= P_ID_AMD_STD,
1458 		.nr_regions	= 1,
1459 		.regions	= {
1460 			ERASEINFO(0x01000,128),
1461 		}
1462 	}, {
1463 
1464 		.mfr_id		= CFI_MFR_SST,
1465 		.dev_id		= SST49LF004B,
1466 		.name		= "SST 49LF004B",
1467 		.devtypes	= CFI_DEVICETYPE_X8,
1468 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1469 		.dev_size	= SIZE_512KiB,
1470 		.cmd_set	= P_ID_AMD_STD,
1471 		.nr_regions	= 1,
1472 		.regions	= {
1473 			ERASEINFO(0x01000,128),
1474 		}
1475 	}, {
1476 		.mfr_id		= CFI_MFR_SST,
1477 		.dev_id		= SST49LF008A,
1478 		.name		= "SST 49LF008A",
1479 		.devtypes	= CFI_DEVICETYPE_X8,
1480 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1481 		.dev_size	= SIZE_1MiB,
1482 		.cmd_set	= P_ID_AMD_STD,
1483 		.nr_regions	= 1,
1484 		.regions	= {
1485 			ERASEINFO(0x01000,256),
1486 		}
1487 	}, {
1488 		.mfr_id		= CFI_MFR_SST,
1489 		.dev_id		= SST49LF030A,
1490 		.name		= "SST 49LF030A",
1491 		.devtypes	= CFI_DEVICETYPE_X8,
1492 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1493 		.dev_size	= SIZE_512KiB,
1494 		.cmd_set	= P_ID_AMD_STD,
1495 		.nr_regions	= 1,
1496 		.regions	= {
1497 			ERASEINFO(0x01000,96),
1498 		}
1499 	}, {
1500 		.mfr_id		= CFI_MFR_SST,
1501 		.dev_id		= SST49LF040A,
1502 		.name		= "SST 49LF040A",
1503 		.devtypes	= CFI_DEVICETYPE_X8,
1504 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1505 		.dev_size	= SIZE_512KiB,
1506 		.cmd_set	= P_ID_AMD_STD,
1507 		.nr_regions	= 1,
1508 		.regions	= {
1509 			ERASEINFO(0x01000,128),
1510 		}
1511 	}, {
1512 		.mfr_id		= CFI_MFR_SST,
1513 		.dev_id		= SST49LF080A,
1514 		.name		= "SST 49LF080A",
1515 		.devtypes	= CFI_DEVICETYPE_X8,
1516 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1517 		.dev_size	= SIZE_1MiB,
1518 		.cmd_set	= P_ID_AMD_STD,
1519 		.nr_regions	= 1,
1520 		.regions	= {
1521 			ERASEINFO(0x01000,256),
1522 		}
1523 	}, {
1524 		.mfr_id		= CFI_MFR_SST,     /* should be CFI */
1525 		.dev_id		= SST39LF160,
1526 		.name		= "SST 39LF160",
1527 		.devtypes	= CFI_DEVICETYPE_X16,
1528 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1529 		.dev_size	= SIZE_2MiB,
1530 		.cmd_set	= P_ID_AMD_STD,
1531 		.nr_regions	= 2,
1532 		.regions	= {
1533 			ERASEINFO(0x1000,256),
1534 			ERASEINFO(0x1000,256)
1535 		}
1536 	}, {
1537 		.mfr_id		= CFI_MFR_SST,     /* should be CFI */
1538 		.dev_id		= SST39VF1601,
1539 		.name		= "SST 39VF1601",
1540 		.devtypes	= CFI_DEVICETYPE_X16,
1541 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1542 		.dev_size	= SIZE_2MiB,
1543 		.cmd_set	= P_ID_AMD_STD,
1544 		.nr_regions	= 2,
1545 		.regions	= {
1546 			ERASEINFO(0x1000,256),
1547 			ERASEINFO(0x1000,256)
1548 		}
1549 	}, {
1550 		/* CFI is broken: reports AMD_STD, but needs custom uaddr */
1551 		.mfr_id		= CFI_MFR_SST,
1552 		.dev_id		= SST39WF1601,
1553 		.name		= "SST 39WF1601",
1554 		.devtypes	= CFI_DEVICETYPE_X16,
1555 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1556 		.dev_size	= SIZE_2MiB,
1557 		.cmd_set	= P_ID_AMD_STD,
1558 		.nr_regions	= 2,
1559 		.regions	= {
1560 			ERASEINFO(0x1000,256),
1561 			ERASEINFO(0x1000,256)
1562 		}
1563 	}, {
1564 		/* CFI is broken: reports AMD_STD, but needs custom uaddr */
1565 		.mfr_id		= CFI_MFR_SST,
1566 		.dev_id		= SST39WF1602,
1567 		.name		= "SST 39WF1602",
1568 		.devtypes	= CFI_DEVICETYPE_X16,
1569 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1570 		.dev_size	= SIZE_2MiB,
1571 		.cmd_set	= P_ID_AMD_STD,
1572 		.nr_regions	= 2,
1573 		.regions	= {
1574 			ERASEINFO(0x1000,256),
1575 			ERASEINFO(0x1000,256)
1576 		}
1577 	}, {
1578 		.mfr_id		= CFI_MFR_SST,     /* should be CFI */
1579 		.dev_id		= SST39VF3201,
1580 		.name		= "SST 39VF3201",
1581 		.devtypes	= CFI_DEVICETYPE_X16,
1582 		.uaddr		= MTD_UADDR_0xAAAA_0x5555,
1583 		.dev_size	= SIZE_4MiB,
1584 		.cmd_set	= P_ID_AMD_STD,
1585 		.nr_regions	= 4,
1586 		.regions	= {
1587 			ERASEINFO(0x1000,256),
1588 			ERASEINFO(0x1000,256),
1589 			ERASEINFO(0x1000,256),
1590 			ERASEINFO(0x1000,256)
1591 		}
1592 	}, {
1593 		.mfr_id		= CFI_MFR_SST,
1594 		.dev_id		= SST36VF3203,
1595 		.name		= "SST 36VF3203",
1596 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1597 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1598 		.dev_size	= SIZE_4MiB,
1599 		.cmd_set	= P_ID_AMD_STD,
1600 		.nr_regions	= 1,
1601 		.regions	= {
1602 			ERASEINFO(0x10000,64),
1603 		}
1604 	}, {
1605 		.mfr_id		= CFI_MFR_ST,
1606 		.dev_id		= M29F800AB,
1607 		.name		= "ST M29F800AB",
1608 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1609 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1610 		.dev_size	= SIZE_1MiB,
1611 		.cmd_set	= P_ID_AMD_STD,
1612 		.nr_regions	= 4,
1613 		.regions	= {
1614 			ERASEINFO(0x04000,1),
1615 			ERASEINFO(0x02000,2),
1616 			ERASEINFO(0x08000,1),
1617 			ERASEINFO(0x10000,15),
1618 		}
1619 	}, {
1620 		.mfr_id		= CFI_MFR_ST,	/* FIXME - CFI device? */
1621 		.dev_id		= M29W800DT,
1622 		.name		= "ST M29W800DT",
1623 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1624 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1625 		.dev_size	= SIZE_1MiB,
1626 		.cmd_set	= P_ID_AMD_STD,
1627 		.nr_regions	= 4,
1628 		.regions	= {
1629 			ERASEINFO(0x10000,15),
1630 			ERASEINFO(0x08000,1),
1631 			ERASEINFO(0x02000,2),
1632 			ERASEINFO(0x04000,1)
1633 		}
1634 	}, {
1635 		.mfr_id		= CFI_MFR_ST,	/* FIXME - CFI device? */
1636 		.dev_id		= M29W800DB,
1637 		.name		= "ST M29W800DB",
1638 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1639 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1640 		.dev_size	= SIZE_1MiB,
1641 		.cmd_set	= P_ID_AMD_STD,
1642 		.nr_regions	= 4,
1643 		.regions	= {
1644 			ERASEINFO(0x04000,1),
1645 			ERASEINFO(0x02000,2),
1646 			ERASEINFO(0x08000,1),
1647 			ERASEINFO(0x10000,15)
1648 		}
1649 	},  {
1650 		.mfr_id         = CFI_MFR_ST,
1651 		.dev_id         = M29W400DT,
1652 		.name           = "ST M29W400DT",
1653 		.devtypes       = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1654 		.uaddr          = MTD_UADDR_0x0AAA_0x0555,
1655 		.dev_size       = SIZE_512KiB,
1656 		.cmd_set        = P_ID_AMD_STD,
1657 		.nr_regions     = 4,
1658 		.regions        = {
1659 			ERASEINFO(0x04000,7),
1660 			ERASEINFO(0x02000,1),
1661 			ERASEINFO(0x08000,2),
1662 			ERASEINFO(0x10000,1)
1663 		}
1664 	}, {
1665 		.mfr_id         = CFI_MFR_ST,
1666 		.dev_id         = M29W400DB,
1667 		.name           = "ST M29W400DB",
1668 		.devtypes       = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1669 		.uaddr          = MTD_UADDR_0x0AAA_0x0555,
1670 		.dev_size       = SIZE_512KiB,
1671 		.cmd_set        = P_ID_AMD_STD,
1672 		.nr_regions     = 4,
1673 		.regions        = {
1674 			ERASEINFO(0x04000,1),
1675 			ERASEINFO(0x02000,2),
1676 			ERASEINFO(0x08000,1),
1677 			ERASEINFO(0x10000,7)
1678 		}
1679 	}, {
1680 		.mfr_id		= CFI_MFR_ST,	/* FIXME - CFI device? */
1681 		.dev_id		= M29W160DT,
1682 		.name		= "ST M29W160DT",
1683 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1684 		.uaddr		= MTD_UADDR_0x0555_0x02AA,	/* ???? */
1685 		.dev_size	= SIZE_2MiB,
1686 		.cmd_set	= P_ID_AMD_STD,
1687 		.nr_regions	= 4,
1688 		.regions	= {
1689 			ERASEINFO(0x10000,31),
1690 			ERASEINFO(0x08000,1),
1691 			ERASEINFO(0x02000,2),
1692 			ERASEINFO(0x04000,1)
1693 		}
1694 	}, {
1695 		.mfr_id		= CFI_MFR_ST,	/* FIXME - CFI device? */
1696 		.dev_id		= M29W160DB,
1697 		.name		= "ST M29W160DB",
1698 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1699 		.uaddr		= MTD_UADDR_0x0555_0x02AA,	/* ???? */
1700 		.dev_size	= SIZE_2MiB,
1701 		.cmd_set	= P_ID_AMD_STD,
1702 		.nr_regions	= 4,
1703 		.regions	= {
1704 			ERASEINFO(0x04000,1),
1705 			ERASEINFO(0x02000,2),
1706 			ERASEINFO(0x08000,1),
1707 			ERASEINFO(0x10000,31)
1708 		}
1709 	}, {
1710 		.mfr_id		= CFI_MFR_ST,
1711 		.dev_id		= M29W040B,
1712 		.name		= "ST M29W040B",
1713 		.devtypes	= CFI_DEVICETYPE_X8,
1714 		.uaddr		= MTD_UADDR_0x0555_0x02AA,
1715 		.dev_size	= SIZE_512KiB,
1716 		.cmd_set	= P_ID_AMD_STD,
1717 		.nr_regions	= 1,
1718 		.regions	= {
1719 			ERASEINFO(0x10000,8),
1720 		}
1721 	}, {
1722 		.mfr_id		= CFI_MFR_ST,
1723 		.dev_id		= M50FW040,
1724 		.name		= "ST M50FW040",
1725 		.devtypes	= CFI_DEVICETYPE_X8,
1726 		.uaddr		= MTD_UADDR_UNNECESSARY,
1727 		.dev_size	= SIZE_512KiB,
1728 		.cmd_set	= P_ID_INTEL_EXT,
1729 		.nr_regions	= 1,
1730 		.regions	= {
1731 			ERASEINFO(0x10000,8),
1732 		}
1733 	}, {
1734 		.mfr_id		= CFI_MFR_ST,
1735 		.dev_id		= M50FW080,
1736 		.name		= "ST M50FW080",
1737 		.devtypes	= CFI_DEVICETYPE_X8,
1738 		.uaddr		= MTD_UADDR_UNNECESSARY,
1739 		.dev_size	= SIZE_1MiB,
1740 		.cmd_set	= P_ID_INTEL_EXT,
1741 		.nr_regions	= 1,
1742 		.regions	= {
1743 			ERASEINFO(0x10000,16),
1744 		}
1745 	}, {
1746 		.mfr_id		= CFI_MFR_ST,
1747 		.dev_id		= M50FW016,
1748 		.name		= "ST M50FW016",
1749 		.devtypes	= CFI_DEVICETYPE_X8,
1750 		.uaddr		= MTD_UADDR_UNNECESSARY,
1751 		.dev_size	= SIZE_2MiB,
1752 		.cmd_set	= P_ID_INTEL_EXT,
1753 		.nr_regions	= 1,
1754 		.regions	= {
1755 			ERASEINFO(0x10000,32),
1756 		}
1757 	}, {
1758 		.mfr_id		= CFI_MFR_ST,
1759 		.dev_id		= M50LPW080,
1760 		.name		= "ST M50LPW080",
1761 		.devtypes	= CFI_DEVICETYPE_X8,
1762 		.uaddr		= MTD_UADDR_UNNECESSARY,
1763 		.dev_size	= SIZE_1MiB,
1764 		.cmd_set	= P_ID_INTEL_EXT,
1765 		.nr_regions	= 1,
1766 		.regions	= {
1767 			ERASEINFO(0x10000,16),
1768 		},
1769 	}, {
1770 		.mfr_id		= CFI_MFR_ST,
1771 		.dev_id		= M50FLW080A,
1772 		.name		= "ST M50FLW080A",
1773 		.devtypes	= CFI_DEVICETYPE_X8,
1774 		.uaddr		= MTD_UADDR_UNNECESSARY,
1775 		.dev_size	= SIZE_1MiB,
1776 		.cmd_set	= P_ID_INTEL_EXT,
1777 		.nr_regions	= 4,
1778 		.regions	= {
1779 			ERASEINFO(0x1000,16),
1780 			ERASEINFO(0x10000,13),
1781 			ERASEINFO(0x1000,16),
1782 			ERASEINFO(0x1000,16),
1783 		}
1784 	}, {
1785 		.mfr_id		= CFI_MFR_ST,
1786 		.dev_id		= M50FLW080B,
1787 		.name		= "ST M50FLW080B",
1788 		.devtypes	= CFI_DEVICETYPE_X8,
1789 		.uaddr		= MTD_UADDR_UNNECESSARY,
1790 		.dev_size	= SIZE_1MiB,
1791 		.cmd_set	= P_ID_INTEL_EXT,
1792 		.nr_regions	= 4,
1793 		.regions	= {
1794 			ERASEINFO(0x1000,16),
1795 			ERASEINFO(0x1000,16),
1796 			ERASEINFO(0x10000,13),
1797 			ERASEINFO(0x1000,16),
1798 		}
1799 	}, {
1800 		.mfr_id		= 0xff00 | CFI_MFR_ST,
1801 		.dev_id		= 0xff00 | PSD4256G6V,
1802 		.name		= "ST PSD4256G6V",
1803 		.devtypes	= CFI_DEVICETYPE_X16,
1804 		.uaddr		= MTD_UADDR_0x0AAA_0x0554,
1805 		.dev_size	= SIZE_1MiB,
1806 		.cmd_set	= P_ID_AMD_STD,
1807 		.nr_regions	= 1,
1808 		.regions	= {
1809 			ERASEINFO(0x10000,16),
1810 		}
1811 	}, {
1812 		.mfr_id		= CFI_MFR_TOSHIBA,
1813 		.dev_id		= TC58FVT160,
1814 		.name		= "Toshiba TC58FVT160",
1815 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1816 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1817 		.dev_size	= SIZE_2MiB,
1818 		.cmd_set	= P_ID_AMD_STD,
1819 		.nr_regions	= 4,
1820 		.regions	= {
1821 			ERASEINFO(0x10000,31),
1822 			ERASEINFO(0x08000,1),
1823 			ERASEINFO(0x02000,2),
1824 			ERASEINFO(0x04000,1)
1825 		}
1826 	}, {
1827 		.mfr_id		= CFI_MFR_TOSHIBA,
1828 		.dev_id		= TC58FVB160,
1829 		.name		= "Toshiba TC58FVB160",
1830 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1831 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1832 		.dev_size	= SIZE_2MiB,
1833 		.cmd_set	= P_ID_AMD_STD,
1834 		.nr_regions	= 4,
1835 		.regions	= {
1836 			ERASEINFO(0x04000,1),
1837 			ERASEINFO(0x02000,2),
1838 			ERASEINFO(0x08000,1),
1839 			ERASEINFO(0x10000,31)
1840 		}
1841 	}, {
1842 		.mfr_id		= CFI_MFR_TOSHIBA,
1843 		.dev_id		= TC58FVB321,
1844 		.name		= "Toshiba TC58FVB321",
1845 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1846 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1847 		.dev_size	= SIZE_4MiB,
1848 		.cmd_set	= P_ID_AMD_STD,
1849 		.nr_regions	= 2,
1850 		.regions	= {
1851 			ERASEINFO(0x02000,8),
1852 			ERASEINFO(0x10000,63)
1853 		}
1854 	}, {
1855 		.mfr_id		= CFI_MFR_TOSHIBA,
1856 		.dev_id		= TC58FVT321,
1857 		.name		= "Toshiba TC58FVT321",
1858 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1859 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1860 		.dev_size	= SIZE_4MiB,
1861 		.cmd_set	= P_ID_AMD_STD,
1862 		.nr_regions	= 2,
1863 		.regions	= {
1864 			ERASEINFO(0x10000,63),
1865 			ERASEINFO(0x02000,8)
1866 		}
1867 	}, {
1868 		.mfr_id		= CFI_MFR_TOSHIBA,
1869 		.dev_id		= TC58FVB641,
1870 		.name		= "Toshiba TC58FVB641",
1871 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1872 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1873 		.dev_size	= SIZE_8MiB,
1874 		.cmd_set	= P_ID_AMD_STD,
1875 		.nr_regions	= 2,
1876 		.regions	= {
1877 			ERASEINFO(0x02000,8),
1878 			ERASEINFO(0x10000,127)
1879 		}
1880 	}, {
1881 		.mfr_id		= CFI_MFR_TOSHIBA,
1882 		.dev_id		= TC58FVT641,
1883 		.name		= "Toshiba TC58FVT641",
1884 		.devtypes	= CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1885 		.uaddr		= MTD_UADDR_0x0AAA_0x0555,
1886 		.dev_size	= SIZE_8MiB,
1887 		.cmd_set	= P_ID_AMD_STD,
1888 		.nr_regions	= 2,
1889 		.regions	= {
1890 			ERASEINFO(0x10000,127),
1891 			ERASEINFO(0x02000,8)
1892 		}
1893 	}, {
1894 		.mfr_id		= CFI_MFR_WINBOND,
1895 		.dev_id		= W49V002A,
1896 		.name		= "Winbond W49V002A",
1897 		.devtypes	= CFI_DEVICETYPE_X8,
1898 		.uaddr		= MTD_UADDR_0x5555_0x2AAA,
1899 		.dev_size	= SIZE_256KiB,
1900 		.cmd_set	= P_ID_AMD_STD,
1901 		.nr_regions	= 4,
1902 		.regions	= {
1903 			ERASEINFO(0x10000, 3),
1904 			ERASEINFO(0x08000, 1),
1905 			ERASEINFO(0x02000, 2),
1906 			ERASEINFO(0x04000, 1),
1907 		}
1908 	}
1909 };
1910 
jedec_read_mfr(struct map_info * map,uint32_t base,struct cfi_private * cfi)1911 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
1912 	struct cfi_private *cfi)
1913 {
1914 	map_word result;
1915 	unsigned long mask;
1916 	int bank = 0;
1917 
1918 	/* According to JEDEC "Standard Manufacturer's Identification Code"
1919 	 * (http://www.jedec.org/download/search/jep106W.pdf)
1920 	 * several first banks can contain 0x7f instead of actual ID
1921 	 */
1922 	do {
1923 		uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi);
1924 		mask = (1 << (cfi->device_type * 8)) - 1;
1925 		if (ofs >= map->size)
1926 			return 0;
1927 		result = map_read(map, base + ofs);
1928 		bank++;
1929 	} while ((result.x[0] & mask) == CFI_MFR_CONTINUATION);
1930 
1931 	return result.x[0] & mask;
1932 }
1933 
jedec_read_id(struct map_info * map,uint32_t base,struct cfi_private * cfi)1934 static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
1935 	struct cfi_private *cfi)
1936 {
1937 	map_word result;
1938 	unsigned long mask;
1939 	u32 ofs = cfi_build_cmd_addr(1, map, cfi);
1940 	mask = (1 << (cfi->device_type * 8)) -1;
1941 	result = map_read(map, base + ofs);
1942 	return result.x[0] & mask;
1943 }
1944 
jedec_reset(u32 base,struct map_info * map,struct cfi_private * cfi)1945 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
1946 {
1947 	/* Reset */
1948 
1949 	/* after checking the datasheets for SST, MACRONIX and ATMEL
1950 	 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
1951 	 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
1952 	 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1953 	 * as they will ignore the writes and don't care what address
1954 	 * the F0 is written to */
1955 	if (cfi->addr_unlock1) {
1956 		pr_debug( "reset unlock called %x %x \n",
1957 		       cfi->addr_unlock1,cfi->addr_unlock2);
1958 		cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1959 		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
1960 	}
1961 
1962 	cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1963 	/* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
1964 	 * so ensure we're in read mode.  Send both the Intel and the AMD command
1965 	 * for this.  Intel uses 0xff for this, AMD uses 0xff for NOP, so
1966 	 * this should be safe.
1967 	 */
1968 	cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
1969 	/* FIXME - should have reset delay before continuing */
1970 }
1971 
1972 
cfi_jedec_setup(struct map_info * map,struct cfi_private * cfi,int index)1973 static int cfi_jedec_setup(struct map_info *map, struct cfi_private *cfi, int index)
1974 {
1975 	int i,num_erase_regions;
1976 	uint8_t uaddr;
1977 
1978 	if (!(jedec_table[index].devtypes & cfi->device_type)) {
1979 		pr_debug("Rejecting potential %s with incompatible %d-bit device type\n",
1980 		      jedec_table[index].name, 4 * (1<<cfi->device_type));
1981 		return 0;
1982 	}
1983 
1984 	printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
1985 
1986 	num_erase_regions = jedec_table[index].nr_regions;
1987 
1988 	cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1989 	if (!cfi->cfiq) {
1990 		//xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
1991 		return 0;
1992 	}
1993 
1994 	memset(cfi->cfiq, 0, sizeof(struct cfi_ident));
1995 
1996 	cfi->cfiq->P_ID = jedec_table[index].cmd_set;
1997 	cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
1998 	cfi->cfiq->DevSize = jedec_table[index].dev_size;
1999 	cfi->cfi_mode = CFI_MODE_JEDEC;
2000 	cfi->sector_erase_cmd = CMD(0x30);
2001 
2002 	for (i=0; i<num_erase_regions; i++){
2003 		cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
2004 	}
2005 	cfi->cmdset_priv = NULL;
2006 
2007 	/* This may be redundant for some cases, but it doesn't hurt */
2008 	cfi->mfr = jedec_table[index].mfr_id;
2009 	cfi->id = jedec_table[index].dev_id;
2010 
2011 	uaddr = jedec_table[index].uaddr;
2012 
2013 	/* The table has unlock addresses in _bytes_, and we try not to let
2014 	   our brains explode when we see the datasheets talking about address
2015 	   lines numbered from A-1 to A18. The CFI table has unlock addresses
2016 	   in device-words according to the mode the device is connected in */
2017 	cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / cfi->device_type;
2018 	cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / cfi->device_type;
2019 
2020 	return 1;	/* ok */
2021 }
2022 
2023 
2024 /*
2025  * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing
2026  * the mapped address, unlock addresses, and proper chip ID.  This function
2027  * attempts to minimize errors.  It is doubtfull that this probe will ever
2028  * be perfect - consequently there should be some module parameters that
2029  * could be manually specified to force the chip info.
2030  */
jedec_match(uint32_t base,struct map_info * map,struct cfi_private * cfi,const struct amd_flash_info * finfo)2031 static inline int jedec_match( uint32_t base,
2032 			       struct map_info *map,
2033 			       struct cfi_private *cfi,
2034 			       const struct amd_flash_info *finfo )
2035 {
2036 	int rc = 0;           /* failure until all tests pass */
2037 	u32 mfr, id;
2038 	uint8_t uaddr;
2039 
2040 	/*
2041 	 * The IDs must match.  For X16 and X32 devices operating in
2042 	 * a lower width ( X8 or X16 ), the device ID's are usually just
2043 	 * the lower byte(s) of the larger device ID for wider mode.  If
2044 	 * a part is found that doesn't fit this assumption (device id for
2045 	 * smaller width mode is completely unrealated to full-width mode)
2046 	 * then the jedec_table[] will have to be augmented with the IDs
2047 	 * for different widths.
2048 	 */
2049 	switch (cfi->device_type) {
2050 	case CFI_DEVICETYPE_X8:
2051 		mfr = (uint8_t)finfo->mfr_id;
2052 		id = (uint8_t)finfo->dev_id;
2053 
2054 		/* bjd: it seems that if we do this, we can end up
2055 		 * detecting 16bit flashes as an 8bit device, even though
2056 		 * there aren't.
2057 		 */
2058 		if (finfo->dev_id > 0xff) {
2059 			pr_debug("%s(): ID is not 8bit\n",
2060 			       __func__);
2061 			goto match_done;
2062 		}
2063 		break;
2064 	case CFI_DEVICETYPE_X16:
2065 		mfr = (uint16_t)finfo->mfr_id;
2066 		id = (uint16_t)finfo->dev_id;
2067 		break;
2068 	case CFI_DEVICETYPE_X32:
2069 		mfr = (uint16_t)finfo->mfr_id;
2070 		id = (uint32_t)finfo->dev_id;
2071 		break;
2072 	default:
2073 		printk(KERN_WARNING
2074 		       "MTD %s(): Unsupported device type %d\n",
2075 		       __func__, cfi->device_type);
2076 		goto match_done;
2077 	}
2078 	if ( cfi->mfr != mfr || cfi->id != id ) {
2079 		goto match_done;
2080 	}
2081 
2082 	/* the part size must fit in the memory window */
2083 	pr_debug("MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
2084 	       __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
2085 	if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
2086 		pr_debug("MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
2087 		       __func__, finfo->mfr_id, finfo->dev_id,
2088 		       1 << finfo->dev_size );
2089 		goto match_done;
2090 	}
2091 
2092 	if (! (finfo->devtypes & cfi->device_type))
2093 		goto match_done;
2094 
2095 	uaddr = finfo->uaddr;
2096 
2097 	pr_debug("MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
2098 	       __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
2099 	if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
2100 	     && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
2101 		  unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
2102 		pr_debug("MTD %s(): 0x%.4x 0x%.4x did not match\n",
2103 			__func__,
2104 			unlock_addrs[uaddr].addr1,
2105 			unlock_addrs[uaddr].addr2);
2106 		goto match_done;
2107 	}
2108 
2109 	/*
2110 	 * Make sure the ID's disappear when the device is taken out of
2111 	 * ID mode.  The only time this should fail when it should succeed
2112 	 * is when the ID's are written as data to the same
2113 	 * addresses.  For this rare and unfortunate case the chip
2114 	 * cannot be probed correctly.
2115 	 * FIXME - write a driver that takes all of the chip info as
2116 	 * module parameters, doesn't probe but forces a load.
2117 	 */
2118 	pr_debug("MTD %s(): check ID's disappear when not in ID mode\n",
2119 	       __func__ );
2120 	jedec_reset( base, map, cfi );
2121 	mfr = jedec_read_mfr( map, base, cfi );
2122 	id = jedec_read_id( map, base, cfi );
2123 	if ( mfr == cfi->mfr && id == cfi->id ) {
2124 		pr_debug("MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
2125 		       "You might need to manually specify JEDEC parameters.\n",
2126 			__func__, cfi->mfr, cfi->id );
2127 		goto match_done;
2128 	}
2129 
2130 	/* all tests passed - mark  as success */
2131 	rc = 1;
2132 
2133 	/*
2134 	 * Put the device back in ID mode - only need to do this if we
2135 	 * were truly frobbing a real device.
2136 	 */
2137 	pr_debug("MTD %s(): return to ID mode\n", __func__ );
2138 	if (cfi->addr_unlock1) {
2139 		cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2140 		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2141 	}
2142 	cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2143 	/* FIXME - should have a delay before continuing */
2144 
2145  match_done:
2146 	return rc;
2147 }
2148 
2149 
jedec_probe_chip(struct map_info * map,__u32 base,unsigned long * chip_map,struct cfi_private * cfi)2150 static int jedec_probe_chip(struct map_info *map, __u32 base,
2151 			    unsigned long *chip_map, struct cfi_private *cfi)
2152 {
2153 	int i;
2154 	enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
2155 	u32 probe_offset1, probe_offset2;
2156 
2157  retry:
2158 	if (!cfi->numchips) {
2159 		uaddr_idx++;
2160 
2161 		if (MTD_UADDR_UNNECESSARY == uaddr_idx)
2162 			return 0;
2163 
2164 		cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
2165 		cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
2166 	}
2167 
2168 	/* Make certain we aren't probing past the end of map */
2169 	if (base >= map->size) {
2170 		printk(KERN_NOTICE
2171 			"Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
2172 			base, map->size -1);
2173 		return 0;
2174 
2175 	}
2176 	/* Ensure the unlock addresses we try stay inside the map */
2177 	probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi);
2178 	probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi);
2179 	if (	((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
2180 		((base + probe_offset2 + map_bankwidth(map)) >= map->size))
2181 		goto retry;
2182 
2183 	/* Reset */
2184 	jedec_reset(base, map, cfi);
2185 
2186 	/* Autoselect Mode */
2187 	if(cfi->addr_unlock1) {
2188 		cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2189 		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2190 	}
2191 	cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2192 	/* FIXME - should have a delay before continuing */
2193 
2194 	if (!cfi->numchips) {
2195 		/* This is the first time we're called. Set up the CFI
2196 		   stuff accordingly and return */
2197 
2198 		cfi->mfr = jedec_read_mfr(map, base, cfi);
2199 		cfi->id = jedec_read_id(map, base, cfi);
2200 		pr_debug("Search for id:(%02x %02x) interleave(%d) type(%d)\n",
2201 			cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type);
2202 		for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
2203 			if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
2204 				pr_debug("MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
2205 				       __func__, cfi->mfr, cfi->id,
2206 				       cfi->addr_unlock1, cfi->addr_unlock2 );
2207 				if (!cfi_jedec_setup(map, cfi, i))
2208 					return 0;
2209 				goto ok_out;
2210 			}
2211 		}
2212 		goto retry;
2213 	} else {
2214 		uint16_t mfr;
2215 		uint16_t id;
2216 
2217 		/* Make sure it is a chip of the same manufacturer and id */
2218 		mfr = jedec_read_mfr(map, base, cfi);
2219 		id = jedec_read_id(map, base, cfi);
2220 
2221 		if ((mfr != cfi->mfr) || (id != cfi->id)) {
2222 			printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
2223 			       map->name, mfr, id, base);
2224 			jedec_reset(base, map, cfi);
2225 			return 0;
2226 		}
2227 	}
2228 
2229 	/* Check each previous chip locations to see if it's an alias */
2230 	for (i=0; i < (base >> cfi->chipshift); i++) {
2231 		unsigned long start;
2232 		if(!test_bit(i, chip_map)) {
2233 			continue; /* Skip location; no valid chip at this address */
2234 		}
2235 		start = i << cfi->chipshift;
2236 		if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
2237 		    jedec_read_id(map, start, cfi) == cfi->id) {
2238 			/* Eep. This chip also looks like it's in autoselect mode.
2239 			   Is it an alias for the new one? */
2240 			jedec_reset(start, map, cfi);
2241 
2242 			/* If the device IDs go away, it's an alias */
2243 			if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
2244 			    jedec_read_id(map, base, cfi) != cfi->id) {
2245 				printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2246 				       map->name, base, start);
2247 				return 0;
2248 			}
2249 
2250 			/* Yes, it's actually got the device IDs as data. Most
2251 			 * unfortunate. Stick the new chip in read mode
2252 			 * too and if it's the same, assume it's an alias. */
2253 			/* FIXME: Use other modes to do a proper check */
2254 			jedec_reset(base, map, cfi);
2255 			if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
2256 			    jedec_read_id(map, base, cfi) == cfi->id) {
2257 				printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2258 				       map->name, base, start);
2259 				return 0;
2260 			}
2261 		}
2262 	}
2263 
2264 	/* OK, if we got to here, then none of the previous chips appear to
2265 	   be aliases for the current one. */
2266 	set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
2267 	cfi->numchips++;
2268 
2269 ok_out:
2270 	/* Put it back into Read Mode */
2271 	jedec_reset(base, map, cfi);
2272 
2273 	printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
2274 	       map->name, cfi_interleave(cfi), cfi->device_type*8, base,
2275 	       map->bankwidth*8);
2276 
2277 	return 1;
2278 }
2279 
2280 static struct chip_probe jedec_chip_probe = {
2281 	.name = "JEDEC",
2282 	.probe_chip = jedec_probe_chip
2283 };
2284 
jedec_probe(struct map_info * map)2285 static struct mtd_info *jedec_probe(struct map_info *map)
2286 {
2287 	/*
2288 	 * Just use the generic probe stuff to call our CFI-specific
2289 	 * chip_probe routine in all the possible permutations, etc.
2290 	 */
2291 	return mtd_do_chip_probe(map, &jedec_chip_probe);
2292 }
2293 
2294 static struct mtd_chip_driver jedec_chipdrv = {
2295 	.probe	= jedec_probe,
2296 	.name	= "jedec_probe",
2297 	.module	= THIS_MODULE
2298 };
2299 
jedec_probe_init(void)2300 static int __init jedec_probe_init(void)
2301 {
2302 	register_mtd_chip_driver(&jedec_chipdrv);
2303 	return 0;
2304 }
2305 
jedec_probe_exit(void)2306 static void __exit jedec_probe_exit(void)
2307 {
2308 	unregister_mtd_chip_driver(&jedec_chipdrv);
2309 }
2310 
2311 module_init(jedec_probe_init);
2312 module_exit(jedec_probe_exit);
2313 
2314 MODULE_LICENSE("GPL");
2315 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
2316 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");
2317