1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/mailbox_controller.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm.h>
13 #include <linux/slab.h>
14
15 #include <soc/tegra/fuse.h>
16
17 #include <dt-bindings/mailbox/tegra186-hsp.h>
18
19 #define HSP_INT_IE(x) (0x100 + ((x) * 4))
20 #define HSP_INT_IV 0x300
21 #define HSP_INT_IR 0x304
22
23 #define HSP_INT_EMPTY_SHIFT 0
24 #define HSP_INT_EMPTY_MASK 0xff
25 #define HSP_INT_FULL_SHIFT 8
26 #define HSP_INT_FULL_MASK 0xff
27
28 #define HSP_INT_DIMENSIONING 0x380
29
30 #define HSP_DB_TRIGGER 0x0
31 #define HSP_DB_ENABLE 0x4
32 #define HSP_DB_RAW 0x8
33 #define HSP_DB_PENDING 0xc
34
35 #define HSP_SM_SHRD_MBOX 0x0
36 #define HSP_SM_SHRD_MBOX_FULL BIT(31)
37 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
38 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
39
40 #define HSP_SHRD_MBOX_TYPE1_TAG 0x40
41 #define HSP_SHRD_MBOX_TYPE1_DATA0 0x48
42 #define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c
43 #define HSP_SHRD_MBOX_TYPE1_DATA2 0x50
44 #define HSP_SHRD_MBOX_TYPE1_DATA3 0x54
45
46 #define HSP_DB_CCPLEX 1
47 #define HSP_DB_BPMP 3
48 #define HSP_DB_MAX 7
49
50 #define HSP_MBOX_TYPE_MASK 0xff
51
52 struct tegra_hsp_channel;
53 struct tegra_hsp;
54
55 struct tegra_hsp_channel {
56 struct tegra_hsp *hsp;
57 struct mbox_chan *chan;
58 void __iomem *regs;
59 };
60
61 struct tegra_hsp_doorbell {
62 struct tegra_hsp_channel channel;
63 struct list_head list;
64 const char *name;
65 unsigned int master;
66 unsigned int index;
67 };
68
69 struct tegra_hsp_sm_ops {
70 void (*send)(struct tegra_hsp_channel *channel, void *data);
71 void (*recv)(struct tegra_hsp_channel *channel);
72 };
73
74 struct tegra_hsp_mailbox {
75 struct tegra_hsp_channel channel;
76 const struct tegra_hsp_sm_ops *ops;
77 unsigned int index;
78 bool producer;
79 };
80
81 struct tegra_hsp_db_map {
82 const char *name;
83 unsigned int master;
84 unsigned int index;
85 };
86
87 struct tegra_hsp_soc {
88 const struct tegra_hsp_db_map *map;
89 bool has_per_mb_ie;
90 bool has_128_bit_mb;
91 unsigned int reg_stride;
92
93 /* Shifts for dimensioning register. */
94 unsigned int si_shift;
95 unsigned int db_shift;
96 unsigned int as_shift;
97 unsigned int ss_shift;
98 unsigned int sm_shift;
99
100 /* Masks for dimensioning register. */
101 unsigned int si_mask;
102 unsigned int db_mask;
103 unsigned int as_mask;
104 unsigned int ss_mask;
105 unsigned int sm_mask;
106 };
107
108 struct tegra_hsp {
109 struct device *dev;
110 const struct tegra_hsp_soc *soc;
111 struct mbox_controller mbox_db;
112 struct mbox_controller mbox_sm;
113 void __iomem *regs;
114 unsigned int doorbell_irq;
115 unsigned int *shared_irqs;
116 unsigned int shared_irq;
117 unsigned int num_sm;
118 unsigned int num_as;
119 unsigned int num_ss;
120 unsigned int num_db;
121 unsigned int num_si;
122
123 spinlock_t lock;
124 struct lock_class_key lock_key;
125
126 struct list_head doorbells;
127 struct tegra_hsp_mailbox *mailboxes;
128
129 unsigned long mask;
130 };
131
tegra_hsp_readl(struct tegra_hsp * hsp,unsigned int offset)132 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
133 {
134 return readl(hsp->regs + offset);
135 }
136
tegra_hsp_writel(struct tegra_hsp * hsp,u32 value,unsigned int offset)137 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
138 unsigned int offset)
139 {
140 writel(value, hsp->regs + offset);
141 }
142
tegra_hsp_channel_readl(struct tegra_hsp_channel * channel,unsigned int offset)143 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
144 unsigned int offset)
145 {
146 return readl(channel->regs + offset);
147 }
148
tegra_hsp_channel_writel(struct tegra_hsp_channel * channel,u32 value,unsigned int offset)149 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
150 u32 value, unsigned int offset)
151 {
152 writel(value, channel->regs + offset);
153 }
154
tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell * db)155 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
156 {
157 u32 value;
158
159 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
160
161 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
162 }
163
164 static struct tegra_hsp_doorbell *
__tegra_hsp_doorbell_get(struct tegra_hsp * hsp,unsigned int master)165 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
166 {
167 struct tegra_hsp_doorbell *entry;
168
169 list_for_each_entry(entry, &hsp->doorbells, list)
170 if (entry->master == master)
171 return entry;
172
173 return NULL;
174 }
175
176 static struct tegra_hsp_doorbell *
tegra_hsp_doorbell_get(struct tegra_hsp * hsp,unsigned int master)177 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
178 {
179 struct tegra_hsp_doorbell *db;
180 unsigned long flags;
181
182 spin_lock_irqsave(&hsp->lock, flags);
183 db = __tegra_hsp_doorbell_get(hsp, master);
184 spin_unlock_irqrestore(&hsp->lock, flags);
185
186 return db;
187 }
188
tegra_hsp_doorbell_irq(int irq,void * data)189 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
190 {
191 struct tegra_hsp *hsp = data;
192 struct tegra_hsp_doorbell *db;
193 unsigned long master, value;
194
195 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
196 if (!db)
197 return IRQ_NONE;
198
199 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
200 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
201
202 spin_lock(&hsp->lock);
203
204 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
205 struct tegra_hsp_doorbell *db;
206
207 db = __tegra_hsp_doorbell_get(hsp, master);
208 /*
209 * Depending on the bootloader chain, the CCPLEX doorbell will
210 * have some doorbells enabled, which means that requesting an
211 * interrupt will immediately fire.
212 *
213 * In that case, db->channel.chan will still be NULL here and
214 * cause a crash if not properly guarded.
215 *
216 * It remains to be seen if ignoring the doorbell in that case
217 * is the correct solution.
218 */
219 if (db && db->channel.chan)
220 mbox_chan_received_data(db->channel.chan, NULL);
221 }
222
223 spin_unlock(&hsp->lock);
224
225 return IRQ_HANDLED;
226 }
227
tegra_hsp_shared_irq(int irq,void * data)228 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
229 {
230 struct tegra_hsp *hsp = data;
231 unsigned long bit, mask;
232 u32 status;
233
234 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
235
236 /* process EMPTY interrupts first */
237 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
238
239 for_each_set_bit(bit, &mask, hsp->num_sm) {
240 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
241
242 if (mb->producer) {
243 /*
244 * Disable EMPTY interrupts until data is sent with
245 * the next message. These interrupts are level-
246 * triggered, so if we kept them enabled they would
247 * constantly trigger until we next write data into
248 * the message.
249 */
250 spin_lock(&hsp->lock);
251
252 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
253 tegra_hsp_writel(hsp, hsp->mask,
254 HSP_INT_IE(hsp->shared_irq));
255
256 spin_unlock(&hsp->lock);
257
258 mbox_chan_txdone(mb->channel.chan, 0);
259 }
260 }
261
262 /* process FULL interrupts */
263 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
264
265 for_each_set_bit(bit, &mask, hsp->num_sm) {
266 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
267
268 if (!mb->producer)
269 mb->ops->recv(&mb->channel);
270 }
271
272 return IRQ_HANDLED;
273 }
274
275 static struct tegra_hsp_channel *
tegra_hsp_doorbell_create(struct tegra_hsp * hsp,const char * name,unsigned int master,unsigned int index)276 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
277 unsigned int master, unsigned int index)
278 {
279 struct tegra_hsp_doorbell *db;
280 unsigned int offset;
281 unsigned long flags;
282
283 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
284 if (!db)
285 return ERR_PTR(-ENOMEM);
286
287 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
288 offset += index * hsp->soc->reg_stride;
289
290 db->channel.regs = hsp->regs + offset;
291 db->channel.hsp = hsp;
292
293 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
294 db->master = master;
295 db->index = index;
296
297 spin_lock_irqsave(&hsp->lock, flags);
298 list_add_tail(&db->list, &hsp->doorbells);
299 spin_unlock_irqrestore(&hsp->lock, flags);
300
301 return &db->channel;
302 }
303
tegra_hsp_doorbell_send_data(struct mbox_chan * chan,void * data)304 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
305 {
306 struct tegra_hsp_doorbell *db = chan->con_priv;
307
308 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
309
310 return 0;
311 }
312
tegra_hsp_doorbell_startup(struct mbox_chan * chan)313 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
314 {
315 struct tegra_hsp_doorbell *db = chan->con_priv;
316 struct tegra_hsp *hsp = db->channel.hsp;
317 struct tegra_hsp_doorbell *ccplex;
318 unsigned long flags;
319 u32 value;
320
321 if (db->master >= chan->mbox->num_chans) {
322 dev_err(chan->mbox->dev,
323 "invalid master ID %u for HSP channel\n",
324 db->master);
325 return -EINVAL;
326 }
327
328 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
329 if (!ccplex)
330 return -ENODEV;
331
332 /*
333 * On simulation platforms the BPMP hasn't had a chance yet to mark
334 * the doorbell as ringable by the CCPLEX, so we want to skip extra
335 * checks here.
336 */
337 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
338 return -ENODEV;
339
340 spin_lock_irqsave(&hsp->lock, flags);
341
342 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
343 value |= BIT(db->master);
344 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
345
346 spin_unlock_irqrestore(&hsp->lock, flags);
347
348 return 0;
349 }
350
tegra_hsp_doorbell_shutdown(struct mbox_chan * chan)351 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
352 {
353 struct tegra_hsp_doorbell *db = chan->con_priv;
354 struct tegra_hsp *hsp = db->channel.hsp;
355 struct tegra_hsp_doorbell *ccplex;
356 unsigned long flags;
357 u32 value;
358
359 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
360 if (!ccplex)
361 return;
362
363 spin_lock_irqsave(&hsp->lock, flags);
364
365 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
366 value &= ~BIT(db->master);
367 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
368
369 spin_unlock_irqrestore(&hsp->lock, flags);
370 }
371
372 static const struct mbox_chan_ops tegra_hsp_db_ops = {
373 .send_data = tegra_hsp_doorbell_send_data,
374 .startup = tegra_hsp_doorbell_startup,
375 .shutdown = tegra_hsp_doorbell_shutdown,
376 };
377
tegra_hsp_sm_send32(struct tegra_hsp_channel * channel,void * data)378 static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data)
379 {
380 u32 value;
381
382 /* copy data and mark mailbox full */
383 value = (u32)(unsigned long)data;
384 value |= HSP_SM_SHRD_MBOX_FULL;
385
386 tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX);
387 }
388
tegra_hsp_sm_recv32(struct tegra_hsp_channel * channel)389 static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
390 {
391 u32 value;
392 void *msg;
393
394 value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
395 value &= ~HSP_SM_SHRD_MBOX_FULL;
396 msg = (void *)(unsigned long)value;
397
398 /*
399 * Need to clear all bits here since some producers, such as TCU, depend
400 * on fields in the register getting cleared by the consumer.
401 *
402 * The mailbox API doesn't give the consumers a way of doing that
403 * explicitly, so we have to make sure we cover all possible cases.
404 */
405 tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
406
407 mbox_chan_received_data(channel->chan, msg);
408 }
409
410 static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
411 .send = tegra_hsp_sm_send32,
412 .recv = tegra_hsp_sm_recv32,
413 };
414
tegra_hsp_sm_send128(struct tegra_hsp_channel * channel,void * data)415 static void tegra_hsp_sm_send128(struct tegra_hsp_channel *channel, void *data)
416 {
417 u32 value[4];
418
419 memcpy(value, data, sizeof(value));
420
421 /* Copy data */
422 tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0);
423 tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1);
424 tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2);
425 tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3);
426
427 /* Update tag to mark mailbox full */
428 tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL,
429 HSP_SHRD_MBOX_TYPE1_TAG);
430 }
431
tegra_hsp_sm_recv128(struct tegra_hsp_channel * channel)432 static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
433 {
434 u32 value[4];
435 void *msg;
436
437 value[0] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0);
438 value[1] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1);
439 value[2] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2);
440 value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3);
441
442 msg = (void *)(unsigned long)value;
443
444 /*
445 * Clear data registers and tag.
446 */
447 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0);
448 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1);
449 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2);
450 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3);
451 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG);
452
453 mbox_chan_received_data(channel->chan, msg);
454 }
455
456 static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = {
457 .send = tegra_hsp_sm_send128,
458 .recv = tegra_hsp_sm_recv128,
459 };
460
tegra_hsp_mailbox_send_data(struct mbox_chan * chan,void * data)461 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
462 {
463 struct tegra_hsp_mailbox *mb = chan->con_priv;
464 struct tegra_hsp *hsp = mb->channel.hsp;
465 unsigned long flags;
466
467 if (WARN_ON(!mb->producer))
468 return -EPERM;
469
470 mb->ops->send(&mb->channel, data);
471
472 /* enable EMPTY interrupt for the shared mailbox */
473 spin_lock_irqsave(&hsp->lock, flags);
474
475 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
476 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
477
478 spin_unlock_irqrestore(&hsp->lock, flags);
479
480 return 0;
481 }
482
tegra_hsp_mailbox_flush(struct mbox_chan * chan,unsigned long timeout)483 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
484 unsigned long timeout)
485 {
486 struct tegra_hsp_mailbox *mb = chan->con_priv;
487 struct tegra_hsp_channel *ch = &mb->channel;
488 u32 value;
489
490 timeout = jiffies + msecs_to_jiffies(timeout);
491
492 while (time_before(jiffies, timeout)) {
493 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
494 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
495 mbox_chan_txdone(chan, 0);
496
497 /* Wait until channel is empty */
498 if (chan->active_req != MBOX_NO_MSG)
499 continue;
500
501 return 0;
502 }
503
504 udelay(1);
505 }
506
507 return -ETIME;
508 }
509
tegra_hsp_mailbox_startup(struct mbox_chan * chan)510 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
511 {
512 struct tegra_hsp_mailbox *mb = chan->con_priv;
513 struct tegra_hsp_channel *ch = &mb->channel;
514 struct tegra_hsp *hsp = mb->channel.hsp;
515 unsigned long flags;
516
517 chan->txdone_method = MBOX_TXDONE_BY_IRQ;
518
519 /*
520 * Shared mailboxes start out as consumers by default. FULL and EMPTY
521 * interrupts are coalesced at the same shared interrupt.
522 *
523 * Keep EMPTY interrupts disabled at startup and only enable them when
524 * the mailbox is actually full. This is required because the FULL and
525 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
526 * enabled all the time would cause an interrupt storm while mailboxes
527 * are idle.
528 */
529
530 spin_lock_irqsave(&hsp->lock, flags);
531
532 if (mb->producer)
533 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
534 else
535 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
536
537 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
538
539 spin_unlock_irqrestore(&hsp->lock, flags);
540
541 if (hsp->soc->has_per_mb_ie) {
542 if (mb->producer)
543 tegra_hsp_channel_writel(ch, 0x0,
544 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
545 else
546 tegra_hsp_channel_writel(ch, 0x1,
547 HSP_SM_SHRD_MBOX_FULL_INT_IE);
548 }
549
550 return 0;
551 }
552
tegra_hsp_mailbox_shutdown(struct mbox_chan * chan)553 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
554 {
555 struct tegra_hsp_mailbox *mb = chan->con_priv;
556 struct tegra_hsp_channel *ch = &mb->channel;
557 struct tegra_hsp *hsp = mb->channel.hsp;
558 unsigned long flags;
559
560 if (hsp->soc->has_per_mb_ie) {
561 if (mb->producer)
562 tegra_hsp_channel_writel(ch, 0x0,
563 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
564 else
565 tegra_hsp_channel_writel(ch, 0x0,
566 HSP_SM_SHRD_MBOX_FULL_INT_IE);
567 }
568
569 spin_lock_irqsave(&hsp->lock, flags);
570
571 if (mb->producer)
572 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
573 else
574 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
575
576 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
577
578 spin_unlock_irqrestore(&hsp->lock, flags);
579 }
580
581 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
582 .send_data = tegra_hsp_mailbox_send_data,
583 .flush = tegra_hsp_mailbox_flush,
584 .startup = tegra_hsp_mailbox_startup,
585 .shutdown = tegra_hsp_mailbox_shutdown,
586 };
587
tegra_hsp_db_xlate(struct mbox_controller * mbox,const struct of_phandle_args * args)588 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
589 const struct of_phandle_args *args)
590 {
591 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
592 unsigned int type = args->args[0], master = args->args[1];
593 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
594 struct tegra_hsp_doorbell *db;
595 struct mbox_chan *chan;
596 unsigned long flags;
597 unsigned int i;
598
599 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
600 return ERR_PTR(-ENODEV);
601
602 db = tegra_hsp_doorbell_get(hsp, master);
603 if (db)
604 channel = &db->channel;
605
606 if (IS_ERR(channel))
607 return ERR_CAST(channel);
608
609 spin_lock_irqsave(&hsp->lock, flags);
610
611 for (i = 0; i < mbox->num_chans; i++) {
612 chan = &mbox->chans[i];
613 if (!chan->con_priv) {
614 channel->chan = chan;
615 chan->con_priv = db;
616 break;
617 }
618
619 chan = NULL;
620 }
621
622 spin_unlock_irqrestore(&hsp->lock, flags);
623
624 return chan ?: ERR_PTR(-EBUSY);
625 }
626
tegra_hsp_sm_xlate(struct mbox_controller * mbox,const struct of_phandle_args * args)627 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
628 const struct of_phandle_args *args)
629 {
630 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
631 unsigned int type = args->args[0], index;
632 struct tegra_hsp_mailbox *mb;
633
634 index = args->args[1] & TEGRA_HSP_SM_MASK;
635
636 if ((type & HSP_MBOX_TYPE_MASK) != TEGRA_HSP_MBOX_TYPE_SM ||
637 !hsp->shared_irqs || index >= hsp->num_sm)
638 return ERR_PTR(-ENODEV);
639
640 mb = &hsp->mailboxes[index];
641
642 if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) {
643 if (!hsp->soc->has_128_bit_mb)
644 return ERR_PTR(-ENODEV);
645
646 mb->ops = &tegra_hsp_sm_128bit_ops;
647 } else {
648 mb->ops = &tegra_hsp_sm_32bit_ops;
649 }
650
651 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
652 mb->producer = false;
653 else
654 mb->producer = true;
655
656 return mb->channel.chan;
657 }
658
tegra_hsp_add_doorbells(struct tegra_hsp * hsp)659 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
660 {
661 const struct tegra_hsp_db_map *map = hsp->soc->map;
662 struct tegra_hsp_channel *channel;
663
664 while (map->name) {
665 channel = tegra_hsp_doorbell_create(hsp, map->name,
666 map->master, map->index);
667 if (IS_ERR(channel))
668 return PTR_ERR(channel);
669
670 map++;
671 }
672
673 return 0;
674 }
675
tegra_hsp_add_mailboxes(struct tegra_hsp * hsp,struct device * dev)676 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
677 {
678 int i;
679
680 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
681 GFP_KERNEL);
682 if (!hsp->mailboxes)
683 return -ENOMEM;
684
685 for (i = 0; i < hsp->num_sm; i++) {
686 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
687
688 mb->index = i;
689
690 mb->channel.hsp = hsp;
691 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
692 mb->channel.chan = &hsp->mbox_sm.chans[i];
693 mb->channel.chan->con_priv = mb;
694 }
695
696 return 0;
697 }
698
tegra_hsp_request_shared_irq(struct tegra_hsp * hsp)699 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
700 {
701 unsigned int i, irq = 0;
702 int err;
703
704 for (i = 0; i < hsp->num_si; i++) {
705 irq = hsp->shared_irqs[i];
706 if (irq <= 0)
707 continue;
708
709 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
710 dev_name(hsp->dev), hsp);
711 if (err < 0)
712 continue;
713
714 hsp->shared_irq = i;
715
716 /* disable all interrupts */
717 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
718
719 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
720
721 break;
722 }
723
724 if (i == hsp->num_si) {
725 dev_err(hsp->dev, "failed to find available interrupt\n");
726 return -ENOENT;
727 }
728
729 return 0;
730 }
731
tegra_hsp_probe(struct platform_device * pdev)732 static int tegra_hsp_probe(struct platform_device *pdev)
733 {
734 struct tegra_hsp *hsp;
735 unsigned int i;
736 u32 value;
737 int err;
738
739 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
740 if (!hsp)
741 return -ENOMEM;
742
743 hsp->dev = &pdev->dev;
744 hsp->soc = of_device_get_match_data(&pdev->dev);
745 INIT_LIST_HEAD(&hsp->doorbells);
746 spin_lock_init(&hsp->lock);
747
748 hsp->regs = devm_platform_ioremap_resource(pdev, 0);
749 if (IS_ERR(hsp->regs))
750 return PTR_ERR(hsp->regs);
751
752 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
753 hsp->num_sm = (value >> hsp->soc->sm_shift) & hsp->soc->sm_mask;
754 hsp->num_ss = (value >> hsp->soc->ss_shift) & hsp->soc->ss_mask;
755 hsp->num_as = (value >> hsp->soc->as_shift) & hsp->soc->as_mask;
756 hsp->num_db = (value >> hsp->soc->db_shift) & hsp->soc->db_mask;
757 hsp->num_si = (value >> hsp->soc->si_shift) & hsp->soc->si_mask;
758
759 err = platform_get_irq_byname_optional(pdev, "doorbell");
760 if (err >= 0)
761 hsp->doorbell_irq = err;
762
763 if (hsp->num_si > 0) {
764 unsigned int count = 0;
765
766 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
767 sizeof(*hsp->shared_irqs),
768 GFP_KERNEL);
769 if (!hsp->shared_irqs)
770 return -ENOMEM;
771
772 for (i = 0; i < hsp->num_si; i++) {
773 char *name;
774
775 name = kasprintf(GFP_KERNEL, "shared%u", i);
776 if (!name)
777 return -ENOMEM;
778
779 err = platform_get_irq_byname_optional(pdev, name);
780 if (err >= 0) {
781 hsp->shared_irqs[i] = err;
782 count++;
783 }
784
785 kfree(name);
786 }
787
788 if (count == 0) {
789 devm_kfree(&pdev->dev, hsp->shared_irqs);
790 hsp->shared_irqs = NULL;
791 }
792 }
793
794 /* setup the doorbell controller */
795 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
796 hsp->mbox_db.num_chans = 32;
797 hsp->mbox_db.dev = &pdev->dev;
798 hsp->mbox_db.ops = &tegra_hsp_db_ops;
799
800 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
801 sizeof(*hsp->mbox_db.chans),
802 GFP_KERNEL);
803 if (!hsp->mbox_db.chans)
804 return -ENOMEM;
805
806 if (hsp->doorbell_irq) {
807 err = tegra_hsp_add_doorbells(hsp);
808 if (err < 0) {
809 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
810 err);
811 return err;
812 }
813 }
814
815 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
816 if (err < 0) {
817 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
818 err);
819 return err;
820 }
821
822 /* setup the shared mailbox controller */
823 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
824 hsp->mbox_sm.num_chans = hsp->num_sm;
825 hsp->mbox_sm.dev = &pdev->dev;
826 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
827
828 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
829 sizeof(*hsp->mbox_sm.chans),
830 GFP_KERNEL);
831 if (!hsp->mbox_sm.chans)
832 return -ENOMEM;
833
834 if (hsp->shared_irqs) {
835 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
836 if (err < 0) {
837 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
838 err);
839 return err;
840 }
841 }
842
843 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
844 if (err < 0) {
845 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
846 err);
847 return err;
848 }
849
850 platform_set_drvdata(pdev, hsp);
851
852 if (hsp->doorbell_irq) {
853 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
854 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
855 dev_name(&pdev->dev), hsp);
856 if (err < 0)
857 return err;
858 }
859
860 if (hsp->shared_irqs) {
861 err = tegra_hsp_request_shared_irq(hsp);
862 if (err < 0)
863 return err;
864 }
865
866 lockdep_register_key(&hsp->lock_key);
867 lockdep_set_class(&hsp->lock, &hsp->lock_key);
868
869 return 0;
870 }
871
tegra_hsp_remove(struct platform_device * pdev)872 static void tegra_hsp_remove(struct platform_device *pdev)
873 {
874 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
875
876 lockdep_unregister_key(&hsp->lock_key);
877 }
878
tegra_hsp_resume(struct device * dev)879 static int __maybe_unused tegra_hsp_resume(struct device *dev)
880 {
881 struct tegra_hsp *hsp = dev_get_drvdata(dev);
882 unsigned int i;
883 struct tegra_hsp_doorbell *db;
884
885 list_for_each_entry(db, &hsp->doorbells, list) {
886 if (db->channel.chan)
887 tegra_hsp_doorbell_startup(db->channel.chan);
888 }
889
890 if (hsp->mailboxes) {
891 for (i = 0; i < hsp->num_sm; i++) {
892 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
893
894 if (mb->channel.chan->cl)
895 tegra_hsp_mailbox_startup(mb->channel.chan);
896 }
897 }
898
899 return 0;
900 }
901
902 static const struct dev_pm_ops tegra_hsp_pm_ops = {
903 .resume_noirq = tegra_hsp_resume,
904 };
905
906 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
907 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
908 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
909 { /* sentinel */ }
910 };
911
912 static const struct tegra_hsp_soc tegra186_hsp_soc = {
913 .map = tegra186_hsp_db_map,
914 .has_per_mb_ie = false,
915 .has_128_bit_mb = false,
916 .reg_stride = 0x100,
917 .si_shift = 16,
918 .db_shift = 12,
919 .as_shift = 8,
920 .ss_shift = 4,
921 .sm_shift = 0,
922 .si_mask = 0xf,
923 .db_mask = 0xf,
924 .as_mask = 0xf,
925 .ss_mask = 0xf,
926 .sm_mask = 0xf,
927 };
928
929 static const struct tegra_hsp_soc tegra194_hsp_soc = {
930 .map = tegra186_hsp_db_map,
931 .has_per_mb_ie = true,
932 .has_128_bit_mb = false,
933 .reg_stride = 0x100,
934 .si_shift = 16,
935 .db_shift = 12,
936 .as_shift = 8,
937 .ss_shift = 4,
938 .sm_shift = 0,
939 .si_mask = 0xf,
940 .db_mask = 0xf,
941 .as_mask = 0xf,
942 .ss_mask = 0xf,
943 .sm_mask = 0xf,
944 };
945
946 static const struct tegra_hsp_soc tegra234_hsp_soc = {
947 .map = tegra186_hsp_db_map,
948 .has_per_mb_ie = false,
949 .has_128_bit_mb = true,
950 .reg_stride = 0x100,
951 .si_shift = 16,
952 .db_shift = 12,
953 .as_shift = 8,
954 .ss_shift = 4,
955 .sm_shift = 0,
956 .si_mask = 0xf,
957 .db_mask = 0xf,
958 .as_mask = 0xf,
959 .ss_mask = 0xf,
960 .sm_mask = 0xf,
961 };
962
963 static const struct tegra_hsp_soc tegra264_hsp_soc = {
964 .map = tegra186_hsp_db_map,
965 .has_per_mb_ie = false,
966 .has_128_bit_mb = true,
967 .reg_stride = 0x1000,
968 .si_shift = 17,
969 .db_shift = 12,
970 .as_shift = 8,
971 .ss_shift = 4,
972 .sm_shift = 0,
973 .si_mask = 0x1f,
974 .db_mask = 0x1f,
975 .as_mask = 0xf,
976 .ss_mask = 0xf,
977 .sm_mask = 0xf,
978 };
979
980 static const struct of_device_id tegra_hsp_match[] = {
981 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
982 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
983 { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
984 { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
985 { }
986 };
987
988 static struct platform_driver tegra_hsp_driver = {
989 .driver = {
990 .name = "tegra-hsp",
991 .of_match_table = tegra_hsp_match,
992 .pm = &tegra_hsp_pm_ops,
993 },
994 .probe = tegra_hsp_probe,
995 .remove = tegra_hsp_remove,
996 };
997
tegra_hsp_init(void)998 static int __init tegra_hsp_init(void)
999 {
1000 return platform_driver_register(&tegra_hsp_driver);
1001 }
1002 core_initcall(tegra_hsp_init);
1003