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Searched refs:HS (Results 1 – 25 of 59) sorted by relevance

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/linux/Documentation/gpu/nova/core/
H A Dfalcon.rst28 Falcons can run in Non-secure (NS), Light Secure (LS), or Heavy Secure (HS)
31 Heavy Secured (HS) also known as Privilege Level 3 (PL3)
33 HS ucode is the most trusted code and has access to pretty much everything on
34 the chip. The HS binary includes a signature in it which is verified at boot.
37 GSP in HS mode. FRTS, which involves setting up and loading content into the WPR
38 (Write Protect Region), has to be done by the HS ucode and cannot be done by the
43 These modes are less secure than HS. Like HS, the LS or NS ucode binary also
45 Falcon, another Falcon needs to be running in HS mode, which also establishes the
47 ucode in HS mode on the SEC2 Falcon, which then authenticates and runs the
61 BROM and DMA registers to trigger the Falcon to load the HS ucode from the system
[all …]
/linux/arch/sparc/kernel/
H A Dviohs.c60 viodbg(HS, "SEND VERSION INFO maj[%u] min[%u] devclass[%u]\n", in send_version()
70 viodbg(HS, "START HANDSHAKE\n"); in start_handshake()
144 viodbg(HS, "HANDSHAKE FAILURE\n"); in handshake_failure()
165 viodbg(HS, "UNKNOWN CONTROL [%02x:%02x:%04x:%08x]\n", in process_unknown()
201 viodbg(HS, "SEND DRING_REG INFO ndesc[%u] dsz[%u] opt[0x%x] " in send_dreg()
209 viodbg(HS, "DRING COOKIE(%d) [%016llx:%016llx]\n", in send_dreg()
226 viodbg(HS, "SEND RDX INFO\n"); in send_rdx()
261 viodbg(HS, "GOT VERSION INFO maj[%u] min[%u] devclass[%u]\n", in process_ver_info()
278 viodbg(HS, "SEND VERSION NACK maj[0] min[0]\n"); in process_ver_info()
284 viodbg(HS, "SEND VERSION NACK maj[%u] min[%u]\n", in process_ver_info()
[all …]
H A Dldc.c375 ldcdbg(HS, "SEND VER INFO maj[%u] min[%u]\n", in start_handshake()
402 ldcdbg(HS, "SEND VER NACK maj[%u] min[%u]\n", in send_version_nack()
419 ldcdbg(HS, "SEND VER ACK maj[%u] min[%u]\n", in send_version_ack()
439 ldcdbg(HS, "SEND RTS env[0x%x] seqid[0x%x]\n", in send_rts()
458 ldcdbg(HS, "SEND RTR env[0x%x] seqid[0x%x]\n", in send_rtr()
478 ldcdbg(HS, "SEND RDX env[0x%x] seqid[0x%x] ackid[0x%x]\n", in send_rdx()
502 ldcdbg(HS, "SEND DATA NACK type[0x%x] ctl[0x%x] seq[0x%x] ack[0x%x]\n", in send_data_nack()
578 ldcdbg(HS, "GOT VERSION INFO major[%x] minor[%x]\n", in process_ver_info()
609 ldcdbg(HS, "GOT VERSION ACK major[%x] minor[%x]\n", in process_ver_ack()
672 ldcdbg(HS, "GOT RTS stype[%x] seqid[%x] env[%x]\n", in process_rts()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6797-x20-dev.dts39 /* HS - I2C2 */
46 /* HS - I2C3 */
/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S72 cmp r9, #0x1 @ Check for HS device
106 cmp r9, #0x1 @ Check for HS device
209 cmp r9, #0x1 @ Check for HS device
292 cmp r1, #0x1 @ Check for HS device
H A DKconfig191 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
195 lost during off-mode entry on HS/EMU devices. This feature
196 requires support from PPA / boot-loader in HS/EMU devices, which
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_chameleon96.dts90 label = "HS-I2C2";
102 label = "HS-SPI1";
/linux/drivers/phy/qualcomm/
H A DKconfig138 tristate "Qualcomm M31 HS PHY driver support"
142 Enable this to support M31 HS PHY transceivers on Qualcomm chips
172 tristate "Qualcomm USB HS PHY module"
181 tristate "Qualcomm SNPS FEMTO USB HS PHY V2 module"
225 both HS and SS PHY controllers.
/linux/Documentation/ABI/testing/
H A Dconfigfs-usb-gadget-uac211 c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto)
26 p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto)
/linux/Documentation/arch/arc/
H A Darc.rst26 Manual, AKA PRM for ARC HS processors
27 <https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-HS.pdf>`_)
45 Configuration for ARC Linux" in the ARC HS Databook for configurability
/linux/Documentation/devicetree/bindings/arc/
H A Dhsdk.txt1 Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-beagle-xm-ab.dts9 /* HS USB Port 2 Power enable was inverted with the xM C */
H A Domap3-evm-common.dtsi16 /* HS USB Port 2 Power */
27 /* HS USB Host PHY on PORT 2 */
H A Domap3-igep0020-common.dtsi43 /* HS USB Port 1 Power */
53 /* HS USB Host PHY on PORT 1 */
H A Domap3-tao3530.dtsi35 /* HS USB Port 2 Power */
45 /* HS USB Host PHY on PORT 2 */
H A Domap3-beagle-xm.dts82 /* HS USB Port 2 Power */
92 /* HS USB Host PHY on PORT 2 */
/linux/arch/arc/plat-hsdk/
H A DKconfig6 bool "ARC HS Development Kit SOC"
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt1 OMAP HS USB Host
66 The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
H A Domap-usb-tll.txt1 OMAP HS USB Host TLL (Transceiver-Less Interface)
/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox3-hs.dts3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
15 model = "Overkiz KIZBOX3-HS";
/linux/drivers/gpib/
H A DKconfig109 GPIB-USB-HS
110 GPIB-USB-HS+
186 GPIB-HS-NT
/linux/drivers/usb/cdns3/
H A DKconfig36 This controller supports FF, HS and SS mode. It doesn't support
119 This controller supports FF, HS, SS and SSP mode.
/linux/drivers/phy/socionext/
H A DKconfig17 of USB3 HS-PHY.
/linux/arch/arm64/boot/dts/freescale/
H A Ds32g274a-rdb2.dts75 * HS*00 may be enabled, but the interface might be unstable because of
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-rock960.dts138 /* On High speed expansion (HS-SPI1) */

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