1 /* SPDX-License-Identifier: GPL-2.0-only or Apache-2.0 */ 2 /* 3 * WF200 hardware interface definitions 4 * 5 * Copyright (c) 2018-2020, Silicon Laboratories Inc. 6 */ 7 8 #ifndef WFX_HIF_API_MIB_H 9 #define WFX_HIF_API_MIB_H 10 11 #include "hif_api_general.h" 12 13 #define HIF_API_IPV4_ADDRESS_SIZE 4 14 #define HIF_API_IPV6_ADDRESS_SIZE 16 15 16 enum wfx_hif_mib_ids { 17 HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE = 0x2000, 18 HIF_MIB_ID_GL_BLOCK_ACK_INFO = 0x2001, 19 HIF_MIB_ID_GL_SET_MULTI_MSG = 0x2002, 20 HIF_MIB_ID_CCA_CONFIG = 0x2003, 21 HIF_MIB_ID_ETHERTYPE_DATAFRAME_CONDITION = 0x2010, 22 HIF_MIB_ID_PORT_DATAFRAME_CONDITION = 0x2011, 23 HIF_MIB_ID_MAGIC_DATAFRAME_CONDITION = 0x2012, 24 HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION = 0x2013, 25 HIF_MIB_ID_IPV4_ADDR_DATAFRAME_CONDITION = 0x2014, 26 HIF_MIB_ID_IPV6_ADDR_DATAFRAME_CONDITION = 0x2015, 27 HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION = 0x2016, 28 HIF_MIB_ID_CONFIG_DATA_FILTER = 0x2017, 29 HIF_MIB_ID_SET_DATA_FILTERING = 0x2018, 30 HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE = 0x2019, 31 HIF_MIB_ID_NS_IP_ADDRESSES_TABLE = 0x201A, 32 HIF_MIB_ID_RX_FILTER = 0x201B, 33 HIF_MIB_ID_BEACON_FILTER_TABLE = 0x201C, 34 HIF_MIB_ID_BEACON_FILTER_ENABLE = 0x201D, 35 HIF_MIB_ID_GRP_SEQ_COUNTER = 0x2030, 36 HIF_MIB_ID_TSF_COUNTER = 0x2031, 37 HIF_MIB_ID_STATISTICS_TABLE = 0x2032, 38 HIF_MIB_ID_COUNTERS_TABLE = 0x2033, 39 HIF_MIB_ID_MAX_TX_POWER_LEVEL = 0x2034, 40 HIF_MIB_ID_EXTENDED_COUNTERS_TABLE = 0x2035, 41 HIF_MIB_ID_DOT11_MAC_ADDRESS = 0x2040, 42 HIF_MIB_ID_DOT11_MAX_TRANSMIT_MSDU_LIFETIME = 0x2041, 43 HIF_MIB_ID_DOT11_MAX_RECEIVE_LIFETIME = 0x2042, 44 HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID = 0x2043, 45 HIF_MIB_ID_DOT11_RTS_THRESHOLD = 0x2044, 46 HIF_MIB_ID_SLOT_TIME = 0x2045, 47 HIF_MIB_ID_CURRENT_TX_POWER_LEVEL = 0x2046, 48 HIF_MIB_ID_NON_ERP_PROTECTION = 0x2047, 49 HIF_MIB_ID_TEMPLATE_FRAME = 0x2048, 50 HIF_MIB_ID_BEACON_WAKEUP_PERIOD = 0x2049, 51 HIF_MIB_ID_RCPI_RSSI_THRESHOLD = 0x204A, 52 HIF_MIB_ID_BLOCK_ACK_POLICY = 0x204B, 53 HIF_MIB_ID_OVERRIDE_INTERNAL_TX_RATE = 0x204C, 54 HIF_MIB_ID_SET_ASSOCIATION_MODE = 0x204D, 55 HIF_MIB_ID_SET_UAPSD_INFORMATION = 0x204E, 56 HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY = 0x204F, 57 HIF_MIB_ID_PROTECTED_MGMT_POLICY = 0x2050, 58 HIF_MIB_ID_SET_HT_PROTECTION = 0x2051, 59 HIF_MIB_ID_KEEP_ALIVE_PERIOD = 0x2052, 60 HIF_MIB_ID_ARP_KEEP_ALIVE_PERIOD = 0x2053, 61 HIF_MIB_ID_INACTIVITY_TIMER = 0x2054, 62 HIF_MIB_ID_INTERFACE_PROTECTION = 0x2055, 63 HIF_MIB_ID_BEACON_STATS = 0x2056, 64 }; 65 66 enum wfx_hif_op_power_mode { 67 HIF_OP_POWER_MODE_ACTIVE = 0x0, 68 HIF_OP_POWER_MODE_DOZE = 0x1, 69 HIF_OP_POWER_MODE_QUIESCENT = 0x2 70 }; 71 72 struct wfx_hif_mib_gl_operational_power_mode { 73 u8 power_mode:4; 74 u8 reserved1:3; 75 u8 wup_ind_activation:1; 76 u8 reserved2[3]; 77 } __packed; 78 79 struct wfx_hif_mib_gl_set_multi_msg { 80 u8 enable_multi_tx_conf:1; 81 u8 reserved1:7; 82 u8 reserved2[3]; 83 } __packed; 84 85 enum wfx_hif_arp_ns_frame_treatment { 86 HIF_ARP_NS_FILTERING_DISABLE = 0x0, 87 HIF_ARP_NS_FILTERING_ENABLE = 0x1, 88 HIF_ARP_NS_REPLY_ENABLE = 0x2 89 }; 90 91 struct wfx_hif_mib_arp_ip_addr_table { 92 u8 condition_idx; 93 u8 arp_enable; 94 u8 reserved[2]; 95 u8 ipv4_address[HIF_API_IPV4_ADDRESS_SIZE]; 96 } __packed; 97 98 struct wfx_hif_mib_rx_filter { 99 u8 reserved1:1; 100 u8 bssid_filter:1; 101 u8 reserved2:1; 102 u8 fwd_probe_req:1; 103 u8 keep_alive_filter:1; 104 u8 reserved3:3; 105 u8 reserved4[3]; 106 } __packed; 107 108 struct wfx_hif_ie_table_entry { 109 u8 ie_id; 110 u8 has_changed:1; 111 u8 no_longer:1; 112 u8 has_appeared:1; 113 u8 reserved:1; 114 u8 num_match_data:4; 115 u8 oui[3]; 116 u8 match_data[3]; 117 } __packed; 118 119 struct wfx_hif_mib_bcn_filter_table { 120 __le32 num_of_info_elmts; 121 struct wfx_hif_ie_table_entry ie_table[]; 122 } __packed; 123 124 enum wfx_hif_beacon_filter { 125 HIF_BEACON_FILTER_DISABLE = 0x0, 126 HIF_BEACON_FILTER_ENABLE = 0x1, 127 HIF_BEACON_FILTER_AUTO_ERP = 0x2 128 }; 129 130 struct wfx_hif_mib_bcn_filter_enable { 131 __le32 enable; 132 __le32 bcn_count; 133 } __packed; 134 135 struct wfx_hif_mib_extended_count_table { 136 __le32 count_drop_plcp; 137 __le32 count_drop_fcs; 138 __le32 count_tx_frames; 139 __le32 count_rx_frames; 140 __le32 count_rx_frames_failed; 141 __le32 count_drop_decryption; 142 __le32 count_drop_tkip_mic; 143 __le32 count_drop_no_key; 144 __le32 count_tx_frames_multicast; 145 __le32 count_tx_frames_success; 146 __le32 count_tx_frames_failed; 147 __le32 count_tx_frames_retried; 148 __le32 count_tx_frames_multi_retried; 149 __le32 count_drop_duplicate; 150 __le32 count_rts_success; 151 __le32 count_rts_failed; 152 __le32 count_ack_failed; 153 __le32 count_rx_frames_multicast; 154 __le32 count_rx_frames_success; 155 __le32 count_drop_cmac_icv; 156 __le32 count_drop_cmac_replay; 157 __le32 count_drop_ccmp_replay; 158 __le32 count_drop_bip_mic; 159 __le32 count_rx_bcn_success; 160 __le32 count_rx_bcn_miss; 161 __le32 count_rx_bcn_dtim; 162 __le32 count_rx_bcn_dtim_aid0_clr; 163 __le32 count_rx_bcn_dtim_aid0_set; 164 __le32 reserved[12]; 165 } __packed; 166 167 struct wfx_hif_mib_count_table { 168 __le32 count_drop_plcp; 169 __le32 count_drop_fcs; 170 __le32 count_tx_frames; 171 __le32 count_rx_frames; 172 __le32 count_rx_frames_failed; 173 __le32 count_drop_decryption; 174 __le32 count_drop_tkip_mic; 175 __le32 count_drop_no_key; 176 __le32 count_tx_frames_multicast; 177 __le32 count_tx_frames_success; 178 __le32 count_tx_frames_failed; 179 __le32 count_tx_frames_retried; 180 __le32 count_tx_frames_multi_retried; 181 __le32 count_drop_duplicate; 182 __le32 count_rts_success; 183 __le32 count_rts_failed; 184 __le32 count_ack_failed; 185 __le32 count_rx_frames_multicast; 186 __le32 count_rx_frames_success; 187 __le32 count_drop_cmac_icv; 188 __le32 count_drop_cmac_replay; 189 __le32 count_drop_ccmp_replay; 190 __le32 count_drop_bip_mic; 191 } __packed; 192 193 struct wfx_hif_mib_mac_address { 194 u8 mac_addr[ETH_ALEN]; 195 __le16 reserved; 196 } __packed; 197 198 struct wfx_hif_mib_wep_default_key_id { 199 u8 wep_default_key_id; 200 u8 reserved[3]; 201 } __packed; 202 203 struct wfx_hif_mib_dot11_rts_threshold { 204 __le32 threshold; 205 } __packed; 206 207 struct wfx_hif_mib_slot_time { 208 __le32 slot_time; 209 } __packed; 210 211 struct wfx_hif_mib_current_tx_power_level { 212 __le32 power_level; /* signed value */ 213 } __packed; 214 215 struct wfx_hif_mib_non_erp_protection { 216 u8 use_cts_to_self:1; 217 u8 reserved1:7; 218 u8 reserved2[3]; 219 } __packed; 220 221 enum wfx_hif_tmplt { 222 HIF_TMPLT_PRBREQ = 0x0, 223 HIF_TMPLT_BCN = 0x1, 224 HIF_TMPLT_NULL = 0x2, 225 HIF_TMPLT_QOSNUL = 0x3, 226 HIF_TMPLT_PSPOLL = 0x4, 227 HIF_TMPLT_PRBRES = 0x5, 228 HIF_TMPLT_ARP = 0x6, 229 HIF_TMPLT_NA = 0x7 230 }; 231 232 #define HIF_API_MAX_TEMPLATE_FRAME_SIZE 700 233 234 struct wfx_hif_mib_template_frame { 235 u8 frame_type; 236 u8 init_rate:7; 237 u8 mode:1; 238 __le16 frame_length; 239 u8 frame[]; 240 } __packed; 241 242 struct wfx_hif_mib_beacon_wake_up_period { 243 u8 wakeup_period_min; 244 u8 receive_dtim:1; 245 u8 reserved1:7; 246 u8 wakeup_period_max; 247 u8 reserved2; 248 } __packed; 249 250 struct wfx_hif_mib_rcpi_rssi_threshold { 251 u8 detection:1; 252 u8 rcpi_rssi:1; 253 u8 upperthresh:1; 254 u8 lowerthresh:1; 255 u8 reserved:4; 256 u8 lower_threshold; 257 u8 upper_threshold; 258 u8 rolling_average_count; 259 } __packed; 260 261 #define DEFAULT_BA_MAX_RX_BUFFER_SIZE 16 262 263 struct wfx_hif_mib_block_ack_policy { 264 u8 block_ack_tx_tid_policy; 265 u8 reserved1; 266 u8 block_ack_rx_tid_policy; 267 u8 block_ack_rx_max_buffer_size; 268 } __packed; 269 270 enum wfx_hif_mpdu_start_spacing { 271 HIF_MPDU_START_SPACING_NO_RESTRIC = 0x0, 272 HIF_MPDU_START_SPACING_QUARTER = 0x1, 273 HIF_MPDU_START_SPACING_HALF = 0x2, 274 HIF_MPDU_START_SPACING_ONE = 0x3, 275 HIF_MPDU_START_SPACING_TWO = 0x4, 276 HIF_MPDU_START_SPACING_FOUR = 0x5, 277 HIF_MPDU_START_SPACING_EIGHT = 0x6, 278 HIF_MPDU_START_SPACING_SIXTEEN = 0x7 279 }; 280 281 struct wfx_hif_mib_set_association_mode { 282 u8 preambtype_use:1; 283 u8 mode:1; 284 u8 rateset:1; 285 u8 spacing:1; 286 u8 reserved1:4; 287 u8 short_preamble:1; 288 u8 reserved2:7; 289 u8 greenfield:1; 290 u8 reserved3:7; 291 u8 mpdu_start_spacing; 292 __le32 basic_rate_set; 293 } __packed; 294 295 struct wfx_hif_mib_set_uapsd_information { 296 u8 trig_bckgrnd:1; 297 u8 trig_be:1; 298 u8 trig_video:1; 299 u8 trig_voice:1; 300 u8 reserved1:4; 301 u8 deliv_bckgrnd:1; 302 u8 deliv_be:1; 303 u8 deliv_video:1; 304 u8 deliv_voice:1; 305 u8 reserved2:4; 306 __le16 min_auto_trigger_interval; 307 __le16 max_auto_trigger_interval; 308 __le16 auto_trigger_step; 309 } __packed; 310 311 struct wfx_hif_tx_rate_retry_policy { 312 u8 policy_index; 313 u8 short_retry_count; 314 u8 long_retry_count; 315 u8 first_rate_sel:2; 316 u8 terminate:1; 317 u8 count_init:1; 318 u8 reserved1:4; 319 u8 rate_recovery_count; 320 u8 reserved2[3]; 321 u8 rates[12]; 322 } __packed; 323 324 #define HIF_TX_RETRY_POLICY_MAX 15 325 #define HIF_TX_RETRY_POLICY_INVALID HIF_TX_RETRY_POLICY_MAX 326 327 struct wfx_hif_mib_set_tx_rate_retry_policy { 328 u8 num_tx_rate_policies; 329 u8 reserved[3]; 330 struct wfx_hif_tx_rate_retry_policy tx_rate_retry_policy[]; 331 } __packed; 332 333 struct wfx_hif_mib_protected_mgmt_policy { 334 u8 pmf_enable:1; 335 u8 unpmf_allowed:1; 336 u8 host_enc_auth_frames:1; 337 u8 reserved1:5; 338 u8 reserved2[3]; 339 } __packed; 340 341 struct wfx_hif_mib_keep_alive_period { 342 __le16 keep_alive_period; 343 u8 reserved[2]; 344 } __packed; 345 346 #endif 347