xref: /linux/drivers/staging/media/meson/vdec/hevc_regs.h (revision ead5d1f4d877e92c051e1a1ade623d0d30e71619)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
4  */
5 
6 #ifndef __MESON_VDEC_HEVC_REGS_H_
7 #define __MESON_VDEC_HEVC_REGS_H_
8 
9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
10 
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
13 
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
21 #define HEVC_ASSIST_SCRATCH_7 0xc31c
22 #define HEVC_ASSIST_SCRATCH_8 0xc320
23 #define HEVC_ASSIST_SCRATCH_9 0xc324
24 #define HEVC_ASSIST_SCRATCH_A 0xc328
25 #define HEVC_ASSIST_SCRATCH_B 0xc32c
26 #define HEVC_ASSIST_SCRATCH_C 0xc330
27 #define HEVC_ASSIST_SCRATCH_D 0xc334
28 #define HEVC_ASSIST_SCRATCH_E 0xc338
29 #define HEVC_ASSIST_SCRATCH_F 0xc33c
30 #define HEVC_ASSIST_SCRATCH_G 0xc340
31 #define HEVC_ASSIST_SCRATCH_H 0xc344
32 #define HEVC_ASSIST_SCRATCH_I 0xc348
33 #define HEVC_ASSIST_SCRATCH_J 0xc34c
34 #define HEVC_ASSIST_SCRATCH_K 0xc350
35 #define HEVC_ASSIST_SCRATCH_L 0xc354
36 #define HEVC_ASSIST_SCRATCH_M 0xc358
37 #define HEVC_ASSIST_SCRATCH_N 0xc35c
38 
39 #define HEVC_PARSER_VERSION 0xc400
40 #define HEVC_STREAM_CONTROL 0xc404
41 #define HEVC_STREAM_START_ADDR 0xc408
42 #define HEVC_STREAM_END_ADDR 0xc40c
43 #define HEVC_STREAM_WR_PTR 0xc410
44 #define HEVC_STREAM_RD_PTR 0xc414
45 #define HEVC_STREAM_LEVEL 0xc418
46 #define HEVC_STREAM_FIFO_CTL 0xc41c
47 #define HEVC_SHIFT_CONTROL 0xc420
48 #define HEVC_SHIFT_STARTCODE 0xc424
49 #define HEVC_SHIFT_EMULATECODE 0xc428
50 #define HEVC_SHIFT_STATUS 0xc42c
51 #define HEVC_SHIFTED_DATA 0xc430
52 #define HEVC_SHIFT_BYTE_COUNT 0xc434
53 #define HEVC_SHIFT_COMMAND 0xc438
54 #define HEVC_ELEMENT_RESULT 0xc43c
55 #define HEVC_CABAC_CONTROL 0xc440
56 #define HEVC_PARSER_SLICE_INFO 0xc444
57 #define HEVC_PARSER_CMD_WRITE 0xc448
58 #define HEVC_PARSER_CORE_CONTROL 0xc44c
59 #define HEVC_PARSER_CMD_FETCH 0xc450
60 #define HEVC_PARSER_CMD_STATUS 0xc454
61 #define HEVC_PARSER_LCU_INFO 0xc458
62 #define HEVC_PARSER_HEADER_INFO 0xc45c
63 #define HEVC_PARSER_INT_CONTROL 0xc480
64 #define HEVC_PARSER_INT_STATUS 0xc484
65 #define HEVC_PARSER_IF_CONTROL 0xc488
66 #define HEVC_PARSER_PICTURE_SIZE 0xc48c
67 #define HEVC_PARSER_LCU_START 0xc490
68 #define HEVC_PARSER_HEADER_INFO2 0xc494
69 #define HEVC_PARSER_QUANT_READ 0xc498
70 #define HEVC_PARSER_RESERVED_27 0xc49c
71 #define HEVC_PARSER_CMD_SKIP_0 0xc4a0
72 #define HEVC_PARSER_CMD_SKIP_1 0xc4a4
73 #define HEVC_PARSER_CMD_SKIP_2 0xc4a8
74 #define HEVC_SAO_IF_STATUS 0xc4c0
75 #define HEVC_SAO_IF_DATA_Y 0xc4c4
76 #define HEVC_SAO_IF_DATA_U 0xc4c8
77 #define HEVC_SAO_IF_DATA_V 0xc4cc
78 #define HEVC_STREAM_SWAP_ADDR 0xc4d0
79 #define HEVC_STREAM_SWAP_CTRL 0xc4d4
80 #define HEVC_IQIT_IF_WAIT_CNT 0xc4d8
81 #define HEVC_MPRED_IF_WAIT_CNT 0xc4dc
82 #define HEVC_SAO_IF_WAIT_CNT 0xc4e0
83 
84 #define HEVC_MPRED_VERSION 0xc800
85 #define HEVC_MPRED_CTRL0 0xc804
86 	#define MPRED_CTRL0_NEW_PIC	BIT(2)
87 	#define MPRED_CTRL0_NEW_TILE	BIT(3)
88 	#define MPRED_CTRL0_NEW_SLI_SEG	BIT(4)
89 	#define MPRED_CTRL0_TMVP	BIT(5)
90 	#define MPRED_CTRL0_LDC		BIT(6)
91 	#define MPRED_CTRL0_COL_FROM_L0	BIT(7)
92 	#define MPRED_CTRL0_ABOVE_EN	BIT(9)
93 	#define MPRED_CTRL0_MV_WR_EN	BIT(10)
94 	#define MPRED_CTRL0_MV_RD_EN	BIT(11)
95 	#define MPRED_CTRL0_BUF_LINEAR	BIT(13)
96 #define HEVC_MPRED_CTRL1 0xc808
97 #define HEVC_MPRED_INT_EN 0xc80c
98 #define HEVC_MPRED_INT_STATUS 0xc810
99 #define HEVC_MPRED_PIC_SIZE 0xc814
100 #define HEVC_MPRED_PIC_SIZE_LCU 0xc818
101 #define HEVC_MPRED_TILE_START 0xc81c
102 #define HEVC_MPRED_TILE_SIZE_LCU 0xc820
103 #define HEVC_MPRED_REF_NUM 0xc824
104 #define HEVC_MPRED_REF_EN_L0 0xc830
105 #define HEVC_MPRED_REF_EN_L1 0xc834
106 #define HEVC_MPRED_COLREF_EN_L0 0xc838
107 #define HEVC_MPRED_COLREF_EN_L1 0xc83c
108 #define HEVC_MPRED_AXI_WCTRL 0xc840
109 #define HEVC_MPRED_AXI_RCTRL 0xc844
110 #define HEVC_MPRED_ABV_START_ADDR 0xc848
111 #define HEVC_MPRED_MV_WR_START_ADDR 0xc84c
112 #define HEVC_MPRED_MV_RD_START_ADDR 0xc850
113 #define HEVC_MPRED_MV_WPTR 0xc854
114 #define HEVC_MPRED_MV_RPTR 0xc858
115 #define HEVC_MPRED_MV_WR_ROW_JUMP 0xc85c
116 #define HEVC_MPRED_MV_RD_ROW_JUMP 0xc860
117 #define HEVC_MPRED_CURR_LCU 0xc864
118 #define HEVC_MPRED_ABV_WPTR 0xc868
119 #define HEVC_MPRED_ABV_RPTR 0xc86c
120 #define HEVC_MPRED_CTRL2 0xc870
121 #define HEVC_MPRED_CTRL3 0xc874
122 #define HEVC_MPRED_L0_REF00_POC 0xc880
123 #define HEVC_MPRED_L1_REF00_POC 0xc8c0
124 
125 #define HEVC_MPRED_CTRL4 0xc930
126 
127 #define HEVC_MPRED_CUR_POC 0xc980
128 #define HEVC_MPRED_COL_POC 0xc984
129 #define HEVC_MPRED_MV_RD_END_ADDR 0xc988
130 
131 #define HEVC_MSP 0xcc00
132 #define HEVC_MPSR 0xcc04
133 #define HEVC_MCPU_INTR_MSK 0xcc10
134 #define HEVC_MCPU_INTR_REQ 0xcc14
135 #define HEVC_CPSR 0xcc84
136 
137 #define HEVC_IMEM_DMA_CTRL 0xcd00
138 #define HEVC_IMEM_DMA_ADR 0xcd04
139 #define HEVC_IMEM_DMA_COUNT 0xcd08
140 
141 #define HEVCD_IPP_TOP_CNTL 0xd000
142 #define HEVCD_IPP_LINEBUFF_BASE 0xd024
143 #define HEVCD_IPP_AXIIF_CONFIG 0xd02c
144 
145 #define VP9D_MPP_REF_SCALE_ENBL		0xd104
146 #define VP9D_MPP_REFINFO_TBL_ACCCONFIG	0xd108
147 #define VP9D_MPP_REFINFO_DATA		0xd10c
148 
149 #define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 0xd180
150 #define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 0xd184
151 #define HEVCD_MPP_ANC2AXI_TBL_DATA 0xd190
152 
153 #define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 0xd300
154 #define HEVCD_MPP_ANC_CANVAS_DATA_ADDR 0xd304
155 #define HEVCD_MPP_DECOMP_CTL1 0xd308
156 #define HEVCD_MPP_DECOMP_CTL2 0xd30c
157 #define HEVCD_MCRCC_CTL1 0xd3c0
158 #define HEVCD_MCRCC_CTL2 0xd3c4
159 #define HEVCD_MCRCC_CTL3 0xd3c8
160 
161 #define HEVC_DBLK_CFG0 0xd400
162 #define HEVC_DBLK_CFG1 0xd404
163 #define HEVC_DBLK_CFG2 0xd408
164 #define HEVC_DBLK_CFG3 0xd40c
165 #define HEVC_DBLK_CFG4 0xd410
166 #define HEVC_DBLK_CFG5 0xd414
167 #define HEVC_DBLK_CFG6 0xd418
168 #define HEVC_DBLK_CFG7 0xd41c
169 #define HEVC_DBLK_CFG8 0xd420
170 #define HEVC_DBLK_CFG9 0xd424
171 #define HEVC_DBLK_CFGA 0xd428
172 #define HEVC_DBLK_STS0 0xd42c
173 #define HEVC_DBLK_CFGB 0xd42c
174 #define HEVC_DBLK_STS1 0xd430
175 #define HEVC_DBLK_CFGE 0xd438
176 
177 #define HEVC_SAO_VERSION 0xd800
178 #define HEVC_SAO_CTRL0 0xd804
179 #define HEVC_SAO_CTRL1 0xd808
180 #define HEVC_SAO_PIC_SIZE 0xd814
181 #define HEVC_SAO_PIC_SIZE_LCU 0xd818
182 #define HEVC_SAO_TILE_START 0xd81c
183 #define HEVC_SAO_TILE_SIZE_LCU 0xd820
184 #define HEVC_SAO_Y_START_ADDR 0xd82c
185 #define HEVC_SAO_Y_LENGTH 0xd830
186 #define HEVC_SAO_C_START_ADDR 0xd834
187 #define HEVC_SAO_C_LENGTH 0xd838
188 #define HEVC_SAO_Y_WPTR 0xd83c
189 #define HEVC_SAO_C_WPTR 0xd840
190 #define HEVC_SAO_ABV_START_ADDR 0xd844
191 #define HEVC_SAO_VB_WR_START_ADDR 0xd848
192 #define HEVC_SAO_VB_RD_START_ADDR 0xd84c
193 #define HEVC_SAO_ABV_WPTR 0xd850
194 #define HEVC_SAO_ABV_RPTR 0xd854
195 #define HEVC_SAO_VB_WPTR 0xd858
196 #define HEVC_SAO_VB_RPTR 0xd85c
197 #define HEVC_SAO_CTRL2 0xd880
198 #define HEVC_SAO_CTRL3 0xd884
199 #define HEVC_SAO_CTRL4 0xd888
200 #define HEVC_SAO_CTRL5 0xd88c
201 #define HEVC_SAO_CTRL6 0xd890
202 #define HEVC_SAO_CTRL7 0xd894
203 #define HEVC_CM_BODY_START_ADDR 0xd898
204 #define HEVC_CM_BODY_LENGTH 0xd89c
205 #define HEVC_CM_HEADER_START_ADDR 0xd8a0
206 #define HEVC_CM_HEADER_LENGTH 0xd8a4
207 #define HEVC_CM_HEADER_OFFSET 0xd8ac
208 #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
209 #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
210 
211 #define HEVC_IQIT_CLK_RST_CTRL 0xdc00
212 #define HEVC_IQIT_SCALELUT_WR_ADDR 0xdc08
213 #define HEVC_IQIT_SCALELUT_RD_ADDR 0xdc0c
214 #define HEVC_IQIT_SCALELUT_DATA 0xdc10
215 
216 #define HEVC_PSCALE_CTRL 0xe444
217 
218 #endif
219