| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | hdp_v4_0.c | 48 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
49 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v4_0_invalidate_hdp()
52 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v4_0_invalidate_hdp()
68 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_query_ras_error_count()
77 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); in hdp_v4_0_reset_ras_error_count()
80 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_reset_ras_error_count()
92 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_update_clock_gating()
100 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating()
102 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating()
116 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
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| H A D | hdp_v5_0.c | 34 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v5_0_invalidate_hdp()
35 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v5_0_invalidate_hdp()
38 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v5_0_invalidate_hdp()
53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
62 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
82 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
124 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
133 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
144 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
[all …]
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| H A D | hdp_v6_0.c | 45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
55 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
76 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
112 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
122 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
131 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_get_clockgating_state()
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| H A D | hdp_v5_2.c | 65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
92 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
127 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
167 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_medium_grain_clock_gating()
176 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
186 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
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| H A D | hdp_v7_0.c | 41 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
42 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_update_clock_gating()
48 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
67 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
103 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
110 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
119 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_get_clockgating_state()
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| /linux/drivers/pinctrl/stm32/ |
| H A D | Kconfig | 62 tristate "STMicroelectronics STM32 Hardware Debug Port (HDP) pin control"
72 It permits the observation of up to 16 signals per HDP line.
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| /linux/include/dt-bindings/clock/ |
| H A D | stm32mp13-clks.h | 72 #define HDP 44 macro
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| H A D | stm32mp1-clks.h | 68 #define HDP 55 macro
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp13.c | 1362 STM32_GATE_CFG(HDP, hdp, SECF_NONE),
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| H A D | clk-stm32mp1.c | 1939 PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp131.dtsi | 966 clocks = <&rcc HDP>;
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| /linux/ |
| H A D | MAINTAINERS | 25009 ST STM32 HDP PINCTRL DRIVER
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