xref: /linux/drivers/net/wireless/ath/ath11k/hal_desc.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 #include "core.h"
7 
8 #ifndef ATH11K_HAL_DESC_H
9 #define ATH11K_HAL_DESC_H
10 
11 #define BUFFER_ADDR_INFO0_ADDR         GENMASK(31, 0)
12 
13 #define BUFFER_ADDR_INFO1_ADDR         GENMASK(7, 0)
14 #define BUFFER_ADDR_INFO1_RET_BUF_MGR  GENMASK(10, 8)
15 #define BUFFER_ADDR_INFO1_SW_COOKIE    GENMASK(31, 11)
16 
17 struct ath11k_buffer_addr {
18 	u32 info0;
19 	u32 info1;
20 } __packed;
21 
22 /* ath11k_buffer_addr
23  *
24  * info0
25  *		Address (lower 32 bits) of the msdu buffer or msdu extension
26  *		descriptor or Link descriptor
27  *
28  * addr
29  *		Address (upper 8 bits) of the msdu buffer or msdu extension
30  *		descriptor or Link descriptor
31  *
32  * return_buffer_manager (RBM)
33  *		Consumer: WBM
34  *		Producer: SW/FW
35  *		Indicates to which buffer manager the buffer or MSDU_EXTENSION
36  *		descriptor or link descriptor that is being pointed to shall be
37  *		returned after the frame has been processed. It is used by WBM
38  *		for routing purposes.
39  *
40  *		Values are defined in enum %HAL_RX_BUF_RBM_
41  *
42  * sw_buffer_cookie
43  *		Cookie field exclusively used by SW. HW ignores the contents,
44  *		accept that it passes the programmed value on to other
45  *		descriptors together with the physical address.
46  *
47  *		Field can be used by SW to for example associate the buffers
48  *		physical address with the virtual address.
49  */
50 
51 enum hal_tlv_tag {
52 	HAL_MACTX_CBF_START                    =   0 /* 0x0 */,
53 	HAL_PHYRX_DATA                         =   1 /* 0x1 */,
54 	HAL_PHYRX_CBF_DATA_RESP                =   2 /* 0x2 */,
55 	HAL_PHYRX_ABORT_REQUEST                =   3 /* 0x3 */,
56 	HAL_PHYRX_USER_ABORT_NOTIFICATION      =   4 /* 0x4 */,
57 	HAL_MACTX_DATA_RESP                    =   5 /* 0x5 */,
58 	HAL_MACTX_CBF_DATA                     =   6 /* 0x6 */,
59 	HAL_MACTX_CBF_DONE                     =   7 /* 0x7 */,
60 	HAL_MACRX_CBF_READ_REQUEST             =   8 /* 0x8 */,
61 	HAL_MACRX_CBF_DATA_REQUEST             =   9 /* 0x9 */,
62 	HAL_MACRX_EXPECT_NDP_RECEPTION         =  10 /* 0xa */,
63 	HAL_MACRX_FREEZE_CAPTURE_CHANNEL       =  11 /* 0xb */,
64 	HAL_MACRX_NDP_TIMEOUT                  =  12 /* 0xc */,
65 	HAL_MACRX_ABORT_ACK                    =  13 /* 0xd */,
66 	HAL_MACRX_REQ_IMPLICIT_FB              =  14 /* 0xe */,
67 	HAL_MACRX_CHAIN_MASK                   =  15 /* 0xf */,
68 	HAL_MACRX_NAP_USER                     =  16 /* 0x10 */,
69 	HAL_MACRX_ABORT_REQUEST                =  17 /* 0x11 */,
70 	HAL_PHYTX_OTHER_TRANSMIT_INFO16        =  18 /* 0x12 */,
71 	HAL_PHYTX_ABORT_ACK                    =  19 /* 0x13 */,
72 	HAL_PHYTX_ABORT_REQUEST                =  20 /* 0x14 */,
73 	HAL_PHYTX_PKT_END                      =  21 /* 0x15 */,
74 	HAL_PHYTX_PPDU_HEADER_INFO_REQUEST     =  22 /* 0x16 */,
75 	HAL_PHYTX_REQUEST_CTRL_INFO            =  23 /* 0x17 */,
76 	HAL_PHYTX_DATA_REQUEST                 =  24 /* 0x18 */,
77 	HAL_PHYTX_BF_CV_LOADING_DONE           =  25 /* 0x19 */,
78 	HAL_PHYTX_NAP_ACK                      =  26 /* 0x1a */,
79 	HAL_PHYTX_NAP_DONE                     =  27 /* 0x1b */,
80 	HAL_PHYTX_OFF_ACK                      =  28 /* 0x1c */,
81 	HAL_PHYTX_ON_ACK                       =  29 /* 0x1d */,
82 	HAL_PHYTX_SYNTH_OFF_ACK                =  30 /* 0x1e */,
83 	HAL_PHYTX_DEBUG16                      =  31 /* 0x1f */,
84 	HAL_MACTX_ABORT_REQUEST                =  32 /* 0x20 */,
85 	HAL_MACTX_ABORT_ACK                    =  33 /* 0x21 */,
86 	HAL_MACTX_PKT_END                      =  34 /* 0x22 */,
87 	HAL_MACTX_PRE_PHY_DESC                 =  35 /* 0x23 */,
88 	HAL_MACTX_BF_PARAMS_COMMON             =  36 /* 0x24 */,
89 	HAL_MACTX_BF_PARAMS_PER_USER           =  37 /* 0x25 */,
90 	HAL_MACTX_PREFETCH_CV                  =  38 /* 0x26 */,
91 	HAL_MACTX_USER_DESC_COMMON             =  39 /* 0x27 */,
92 	HAL_MACTX_USER_DESC_PER_USER           =  40 /* 0x28 */,
93 	HAL_EXAMPLE_USER_TLV_16                =  41 /* 0x29 */,
94 	HAL_EXAMPLE_TLV_16                     =  42 /* 0x2a */,
95 	HAL_MACTX_PHY_OFF                      =  43 /* 0x2b */,
96 	HAL_MACTX_PHY_ON                       =  44 /* 0x2c */,
97 	HAL_MACTX_SYNTH_OFF                    =  45 /* 0x2d */,
98 	HAL_MACTX_EXPECT_CBF_COMMON            =  46 /* 0x2e */,
99 	HAL_MACTX_EXPECT_CBF_PER_USER          =  47 /* 0x2f */,
100 	HAL_MACTX_PHY_DESC                     =  48 /* 0x30 */,
101 	HAL_MACTX_L_SIG_A                      =  49 /* 0x31 */,
102 	HAL_MACTX_L_SIG_B                      =  50 /* 0x32 */,
103 	HAL_MACTX_HT_SIG                       =  51 /* 0x33 */,
104 	HAL_MACTX_VHT_SIG_A                    =  52 /* 0x34 */,
105 	HAL_MACTX_VHT_SIG_B_SU20               =  53 /* 0x35 */,
106 	HAL_MACTX_VHT_SIG_B_SU40               =  54 /* 0x36 */,
107 	HAL_MACTX_VHT_SIG_B_SU80               =  55 /* 0x37 */,
108 	HAL_MACTX_VHT_SIG_B_SU160              =  56 /* 0x38 */,
109 	HAL_MACTX_VHT_SIG_B_MU20               =  57 /* 0x39 */,
110 	HAL_MACTX_VHT_SIG_B_MU40               =  58 /* 0x3a */,
111 	HAL_MACTX_VHT_SIG_B_MU80               =  59 /* 0x3b */,
112 	HAL_MACTX_VHT_SIG_B_MU160              =  60 /* 0x3c */,
113 	HAL_MACTX_SERVICE                      =  61 /* 0x3d */,
114 	HAL_MACTX_HE_SIG_A_SU                  =  62 /* 0x3e */,
115 	HAL_MACTX_HE_SIG_A_MU_DL               =  63 /* 0x3f */,
116 	HAL_MACTX_HE_SIG_A_MU_UL               =  64 /* 0x40 */,
117 	HAL_MACTX_HE_SIG_B1_MU                 =  65 /* 0x41 */,
118 	HAL_MACTX_HE_SIG_B2_MU                 =  66 /* 0x42 */,
119 	HAL_MACTX_HE_SIG_B2_OFDMA              =  67 /* 0x43 */,
120 	HAL_MACTX_DELETE_CV                    =  68 /* 0x44 */,
121 	HAL_MACTX_MU_UPLINK_COMMON             =  69 /* 0x45 */,
122 	HAL_MACTX_MU_UPLINK_USER_SETUP         =  70 /* 0x46 */,
123 	HAL_MACTX_OTHER_TRANSMIT_INFO          =  71 /* 0x47 */,
124 	HAL_MACTX_PHY_NAP                      =  72 /* 0x48 */,
125 	HAL_MACTX_DEBUG                        =  73 /* 0x49 */,
126 	HAL_PHYRX_ABORT_ACK                    =  74 /* 0x4a */,
127 	HAL_PHYRX_GENERATED_CBF_DETAILS        =  75 /* 0x4b */,
128 	HAL_PHYRX_RSSI_LEGACY                  =  76 /* 0x4c */,
129 	HAL_PHYRX_RSSI_HT                      =  77 /* 0x4d */,
130 	HAL_PHYRX_USER_INFO                    =  78 /* 0x4e */,
131 	HAL_PHYRX_PKT_END                      =  79 /* 0x4f */,
132 	HAL_PHYRX_DEBUG                        =  80 /* 0x50 */,
133 	HAL_PHYRX_CBF_TRANSFER_DONE            =  81 /* 0x51 */,
134 	HAL_PHYRX_CBF_TRANSFER_ABORT           =  82 /* 0x52 */,
135 	HAL_PHYRX_L_SIG_A                      =  83 /* 0x53 */,
136 	HAL_PHYRX_L_SIG_B                      =  84 /* 0x54 */,
137 	HAL_PHYRX_HT_SIG                       =  85 /* 0x55 */,
138 	HAL_PHYRX_VHT_SIG_A                    =  86 /* 0x56 */,
139 	HAL_PHYRX_VHT_SIG_B_SU20               =  87 /* 0x57 */,
140 	HAL_PHYRX_VHT_SIG_B_SU40               =  88 /* 0x58 */,
141 	HAL_PHYRX_VHT_SIG_B_SU80               =  89 /* 0x59 */,
142 	HAL_PHYRX_VHT_SIG_B_SU160              =  90 /* 0x5a */,
143 	HAL_PHYRX_VHT_SIG_B_MU20               =  91 /* 0x5b */,
144 	HAL_PHYRX_VHT_SIG_B_MU40               =  92 /* 0x5c */,
145 	HAL_PHYRX_VHT_SIG_B_MU80               =  93 /* 0x5d */,
146 	HAL_PHYRX_VHT_SIG_B_MU160              =  94 /* 0x5e */,
147 	HAL_PHYRX_HE_SIG_A_SU                  =  95 /* 0x5f */,
148 	HAL_PHYRX_HE_SIG_A_MU_DL               =  96 /* 0x60 */,
149 	HAL_PHYRX_HE_SIG_A_MU_UL               =  97 /* 0x61 */,
150 	HAL_PHYRX_HE_SIG_B1_MU                 =  98 /* 0x62 */,
151 	HAL_PHYRX_HE_SIG_B2_MU                 =  99 /* 0x63 */,
152 	HAL_PHYRX_HE_SIG_B2_OFDMA              = 100 /* 0x64 */,
153 	HAL_PHYRX_OTHER_RECEIVE_INFO           = 101 /* 0x65 */,
154 	HAL_PHYRX_COMMON_USER_INFO             = 102 /* 0x66 */,
155 	HAL_PHYRX_DATA_DONE                    = 103 /* 0x67 */,
156 	HAL_RECEIVE_RSSI_INFO                  = 104 /* 0x68 */,
157 	HAL_RECEIVE_USER_INFO                  = 105 /* 0x69 */,
158 	HAL_MIMO_CONTROL_INFO                  = 106 /* 0x6a */,
159 	HAL_RX_LOCATION_INFO                   = 107 /* 0x6b */,
160 	HAL_COEX_TX_REQ                        = 108 /* 0x6c */,
161 	HAL_DUMMY                              = 109 /* 0x6d */,
162 	HAL_RX_TIMING_OFFSET_INFO              = 110 /* 0x6e */,
163 	HAL_EXAMPLE_TLV_32_NAME                = 111 /* 0x6f */,
164 	HAL_MPDU_LIMIT                         = 112 /* 0x70 */,
165 	HAL_NA_LENGTH_END                      = 113 /* 0x71 */,
166 	HAL_OLE_BUF_STATUS                     = 114 /* 0x72 */,
167 	HAL_PCU_PPDU_SETUP_DONE                = 115 /* 0x73 */,
168 	HAL_PCU_PPDU_SETUP_END                 = 116 /* 0x74 */,
169 	HAL_PCU_PPDU_SETUP_INIT                = 117 /* 0x75 */,
170 	HAL_PCU_PPDU_SETUP_START               = 118 /* 0x76 */,
171 	HAL_PDG_FES_SETUP                      = 119 /* 0x77 */,
172 	HAL_PDG_RESPONSE                       = 120 /* 0x78 */,
173 	HAL_PDG_TX_REQ                         = 121 /* 0x79 */,
174 	HAL_SCH_WAIT_INSTR                     = 122 /* 0x7a */,
175 	HAL_SCHEDULER_TLV                      = 123 /* 0x7b */,
176 	HAL_TQM_FLOW_EMPTY_STATUS              = 124 /* 0x7c */,
177 	HAL_TQM_FLOW_NOT_EMPTY_STATUS          = 125 /* 0x7d */,
178 	HAL_TQM_GEN_MPDU_LENGTH_LIST           = 126 /* 0x7e */,
179 	HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS    = 127 /* 0x7f */,
180 	HAL_TQM_GEN_MPDUS                      = 128 /* 0x80 */,
181 	HAL_TQM_GEN_MPDUS_STATUS               = 129 /* 0x81 */,
182 	HAL_TQM_REMOVE_MPDU                    = 130 /* 0x82 */,
183 	HAL_TQM_REMOVE_MPDU_STATUS             = 131 /* 0x83 */,
184 	HAL_TQM_REMOVE_MSDU                    = 132 /* 0x84 */,
185 	HAL_TQM_REMOVE_MSDU_STATUS             = 133 /* 0x85 */,
186 	HAL_TQM_UPDATE_TX_MPDU_COUNT           = 134 /* 0x86 */,
187 	HAL_TQM_WRITE_CMD                      = 135 /* 0x87 */,
188 	HAL_OFDMA_TRIGGER_DETAILS              = 136 /* 0x88 */,
189 	HAL_TX_DATA                            = 137 /* 0x89 */,
190 	HAL_TX_FES_SETUP                       = 138 /* 0x8a */,
191 	HAL_RX_PACKET                          = 139 /* 0x8b */,
192 	HAL_EXPECTED_RESPONSE                  = 140 /* 0x8c */,
193 	HAL_TX_MPDU_END                        = 141 /* 0x8d */,
194 	HAL_TX_MPDU_START                      = 142 /* 0x8e */,
195 	HAL_TX_MSDU_END                        = 143 /* 0x8f */,
196 	HAL_TX_MSDU_START                      = 144 /* 0x90 */,
197 	HAL_TX_SW_MODE_SETUP                   = 145 /* 0x91 */,
198 	HAL_TXPCU_BUFFER_STATUS                = 146 /* 0x92 */,
199 	HAL_TXPCU_USER_BUFFER_STATUS           = 147 /* 0x93 */,
200 	HAL_DATA_TO_TIME_CONFIG                = 148 /* 0x94 */,
201 	HAL_EXAMPLE_USER_TLV_32                = 149 /* 0x95 */,
202 	HAL_MPDU_INFO                          = 150 /* 0x96 */,
203 	HAL_PDG_USER_SETUP                     = 151 /* 0x97 */,
204 	HAL_TX_11AH_SETUP                      = 152 /* 0x98 */,
205 	HAL_REO_UPDATE_RX_REO_QUEUE_STATUS     = 153 /* 0x99 */,
206 	HAL_TX_PEER_ENTRY                      = 154 /* 0x9a */,
207 	HAL_TX_RAW_OR_NATIVE_FRAME_SETUP       = 155 /* 0x9b */,
208 	HAL_EXAMPLE_STRUCT_NAME                = 156 /* 0x9c */,
209 	HAL_PCU_PPDU_SETUP_END_INFO            = 157 /* 0x9d */,
210 	HAL_PPDU_RATE_SETTING                  = 158 /* 0x9e */,
211 	HAL_PROT_RATE_SETTING                  = 159 /* 0x9f */,
212 	HAL_RX_MPDU_DETAILS                    = 160 /* 0xa0 */,
213 	HAL_EXAMPLE_USER_TLV_42                = 161 /* 0xa1 */,
214 	HAL_RX_MSDU_LINK                       = 162 /* 0xa2 */,
215 	HAL_RX_REO_QUEUE                       = 163 /* 0xa3 */,
216 	HAL_ADDR_SEARCH_ENTRY                  = 164 /* 0xa4 */,
217 	HAL_SCHEDULER_CMD                      = 165 /* 0xa5 */,
218 	HAL_TX_FLUSH                           = 166 /* 0xa6 */,
219 	HAL_TQM_ENTRANCE_RING                  = 167 /* 0xa7 */,
220 	HAL_TX_DATA_WORD                       = 168 /* 0xa8 */,
221 	HAL_TX_MPDU_DETAILS                    = 169 /* 0xa9 */,
222 	HAL_TX_MPDU_LINK                       = 170 /* 0xaa */,
223 	HAL_TX_MPDU_LINK_PTR                   = 171 /* 0xab */,
224 	HAL_TX_MPDU_QUEUE_HEAD                 = 172 /* 0xac */,
225 	HAL_TX_MPDU_QUEUE_EXT                  = 173 /* 0xad */,
226 	HAL_TX_MPDU_QUEUE_EXT_PTR              = 174 /* 0xae */,
227 	HAL_TX_MSDU_DETAILS                    = 175 /* 0xaf */,
228 	HAL_TX_MSDU_EXTENSION                  = 176 /* 0xb0 */,
229 	HAL_TX_MSDU_FLOW                       = 177 /* 0xb1 */,
230 	HAL_TX_MSDU_LINK                       = 178 /* 0xb2 */,
231 	HAL_TX_MSDU_LINK_ENTRY_PTR             = 179 /* 0xb3 */,
232 	HAL_RESPONSE_RATE_SETTING              = 180 /* 0xb4 */,
233 	HAL_TXPCU_BUFFER_BASICS                = 181 /* 0xb5 */,
234 	HAL_UNIFORM_DESCRIPTOR_HEADER          = 182 /* 0xb6 */,
235 	HAL_UNIFORM_TQM_CMD_HEADER             = 183 /* 0xb7 */,
236 	HAL_UNIFORM_TQM_STATUS_HEADER          = 184 /* 0xb8 */,
237 	HAL_USER_RATE_SETTING                  = 185 /* 0xb9 */,
238 	HAL_WBM_BUFFER_RING                    = 186 /* 0xba */,
239 	HAL_WBM_LINK_DESCRIPTOR_RING           = 187 /* 0xbb */,
240 	HAL_WBM_RELEASE_RING                   = 188 /* 0xbc */,
241 	HAL_TX_FLUSH_REQ                       = 189 /* 0xbd */,
242 	HAL_RX_MSDU_DETAILS                    = 190 /* 0xbe */,
243 	HAL_TQM_WRITE_CMD_STATUS               = 191 /* 0xbf */,
244 	HAL_TQM_GET_MPDU_QUEUE_STATS           = 192 /* 0xc0 */,
245 	HAL_TQM_GET_MSDU_FLOW_STATS            = 193 /* 0xc1 */,
246 	HAL_EXAMPLE_USER_CTLV_32               = 194 /* 0xc2 */,
247 	HAL_TX_FES_STATUS_START                = 195 /* 0xc3 */,
248 	HAL_TX_FES_STATUS_USER_PPDU            = 196 /* 0xc4 */,
249 	HAL_TX_FES_STATUS_USER_RESPONSE        = 197 /* 0xc5 */,
250 	HAL_TX_FES_STATUS_END                  = 198 /* 0xc6 */,
251 	HAL_RX_TRIG_INFO                       = 199 /* 0xc7 */,
252 	HAL_RXPCU_TX_SETUP_CLEAR               = 200 /* 0xc8 */,
253 	HAL_RX_FRAME_BITMAP_REQ                = 201 /* 0xc9 */,
254 	HAL_RX_FRAME_BITMAP_ACK                = 202 /* 0xca */,
255 	HAL_COEX_RX_STATUS                     = 203 /* 0xcb */,
256 	HAL_RX_START_PARAM                     = 204 /* 0xcc */,
257 	HAL_RX_PPDU_START                      = 205 /* 0xcd */,
258 	HAL_RX_PPDU_END                        = 206 /* 0xce */,
259 	HAL_RX_MPDU_START                      = 207 /* 0xcf */,
260 	HAL_RX_MPDU_END                        = 208 /* 0xd0 */,
261 	HAL_RX_MSDU_START                      = 209 /* 0xd1 */,
262 	HAL_RX_MSDU_END                        = 210 /* 0xd2 */,
263 	HAL_RX_ATTENTION                       = 211 /* 0xd3 */,
264 	HAL_RECEIVED_RESPONSE_INFO             = 212 /* 0xd4 */,
265 	HAL_RX_PHY_SLEEP                       = 213 /* 0xd5 */,
266 	HAL_RX_HEADER                          = 214 /* 0xd6 */,
267 	HAL_RX_PEER_ENTRY                      = 215 /* 0xd7 */,
268 	HAL_RX_FLUSH                           = 216 /* 0xd8 */,
269 	HAL_RX_RESPONSE_REQUIRED_INFO          = 217 /* 0xd9 */,
270 	HAL_RX_FRAMELESS_BAR_DETAILS           = 218 /* 0xda */,
271 	HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS    = 219 /* 0xdb */,
272 	HAL_TQM_GET_MSDU_FLOW_STATS_STATUS     = 220 /* 0xdc */,
273 	HAL_TX_CBF_INFO                        = 221 /* 0xdd */,
274 	HAL_PCU_PPDU_SETUP_USER                = 222 /* 0xde */,
275 	HAL_RX_MPDU_PCU_START                  = 223 /* 0xdf */,
276 	HAL_RX_PM_INFO                         = 224 /* 0xe0 */,
277 	HAL_RX_USER_PPDU_END                   = 225 /* 0xe1 */,
278 	HAL_RX_PRE_PPDU_START                  = 226 /* 0xe2 */,
279 	HAL_RX_PREAMBLE                        = 227 /* 0xe3 */,
280 	HAL_TX_FES_SETUP_COMPLETE              = 228 /* 0xe4 */,
281 	HAL_TX_LAST_MPDU_FETCHED               = 229 /* 0xe5 */,
282 	HAL_TXDMA_STOP_REQUEST                 = 230 /* 0xe6 */,
283 	HAL_RXPCU_SETUP                        = 231 /* 0xe7 */,
284 	HAL_RXPCU_USER_SETUP                   = 232 /* 0xe8 */,
285 	HAL_TX_FES_STATUS_ACK_OR_BA            = 233 /* 0xe9 */,
286 	HAL_TQM_ACKED_MPDU                     = 234 /* 0xea */,
287 	HAL_COEX_TX_RESP                       = 235 /* 0xeb */,
288 	HAL_COEX_TX_STATUS                     = 236 /* 0xec */,
289 	HAL_MACTX_COEX_PHY_CTRL                = 237 /* 0xed */,
290 	HAL_COEX_STATUS_BROADCAST              = 238 /* 0xee */,
291 	HAL_RESPONSE_START_STATUS              = 239 /* 0xef */,
292 	HAL_RESPONSE_END_STATUS                = 240 /* 0xf0 */,
293 	HAL_CRYPTO_STATUS                      = 241 /* 0xf1 */,
294 	HAL_RECEIVED_TRIGGER_INFO              = 242 /* 0xf2 */,
295 	HAL_REO_ENTRANCE_RING                  = 243 /* 0xf3 */,
296 	HAL_RX_MPDU_LINK                       = 244 /* 0xf4 */,
297 	HAL_COEX_TX_STOP_CTRL                  = 245 /* 0xf5 */,
298 	HAL_RX_PPDU_ACK_REPORT                 = 246 /* 0xf6 */,
299 	HAL_RX_PPDU_NO_ACK_REPORT              = 247 /* 0xf7 */,
300 	HAL_SCH_COEX_STATUS                    = 248 /* 0xf8 */,
301 	HAL_SCHEDULER_COMMAND_STATUS           = 249 /* 0xf9 */,
302 	HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */,
303 	HAL_TX_FES_STATUS_PROT                 = 251 /* 0xfb */,
304 	HAL_TX_FES_STATUS_START_PPDU           = 252 /* 0xfc */,
305 	HAL_TX_FES_STATUS_START_PROT           = 253 /* 0xfd */,
306 	HAL_TXPCU_PHYTX_DEBUG32                = 254 /* 0xfe */,
307 	HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32  = 255 /* 0xff */,
308 	HAL_TX_MPDU_COUNT_TRANSFER_END         = 256 /* 0x100 */,
309 	HAL_WHO_ANCHOR_OFFSET                  = 257 /* 0x101 */,
310 	HAL_WHO_ANCHOR_VALUE                   = 258 /* 0x102 */,
311 	HAL_WHO_CCE_INFO                       = 259 /* 0x103 */,
312 	HAL_WHO_COMMIT                         = 260 /* 0x104 */,
313 	HAL_WHO_COMMIT_DONE                    = 261 /* 0x105 */,
314 	HAL_WHO_FLUSH                          = 262 /* 0x106 */,
315 	HAL_WHO_L2_LLC                         = 263 /* 0x107 */,
316 	HAL_WHO_L2_PAYLOAD                     = 264 /* 0x108 */,
317 	HAL_WHO_L3_CHECKSUM                    = 265 /* 0x109 */,
318 	HAL_WHO_L3_INFO                        = 266 /* 0x10a */,
319 	HAL_WHO_L4_CHECKSUM                    = 267 /* 0x10b */,
320 	HAL_WHO_L4_INFO                        = 268 /* 0x10c */,
321 	HAL_WHO_MSDU                           = 269 /* 0x10d */,
322 	HAL_WHO_MSDU_MISC                      = 270 /* 0x10e */,
323 	HAL_WHO_PACKET_DATA                    = 271 /* 0x10f */,
324 	HAL_WHO_PACKET_HDR                     = 272 /* 0x110 */,
325 	HAL_WHO_PPDU_END                       = 273 /* 0x111 */,
326 	HAL_WHO_PPDU_START                     = 274 /* 0x112 */,
327 	HAL_WHO_TSO                            = 275 /* 0x113 */,
328 	HAL_WHO_WMAC_HEADER_PV0                = 276 /* 0x114 */,
329 	HAL_WHO_WMAC_HEADER_PV1                = 277 /* 0x115 */,
330 	HAL_WHO_WMAC_IV                        = 278 /* 0x116 */,
331 	HAL_MPDU_INFO_END                      = 279 /* 0x117 */,
332 	HAL_MPDU_INFO_BITMAP                   = 280 /* 0x118 */,
333 	HAL_TX_QUEUE_EXTENSION                 = 281 /* 0x119 */,
334 	HAL_RX_PEER_ENTRY_DETAILS              = 282 /* 0x11a */,
335 	HAL_RX_REO_QUEUE_REFERENCE             = 283 /* 0x11b */,
336 	HAL_RX_REO_QUEUE_EXT                   = 284 /* 0x11c */,
337 	HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS  = 285 /* 0x11d */,
338 	HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS    = 286 /* 0x11e */,
339 	HAL_TQM_ACKED_MPDU_STATUS              = 287 /* 0x11f */,
340 	HAL_TQM_ADD_MSDU_STATUS                = 288 /* 0x120 */,
341 	HAL_RX_MPDU_LINK_PTR                   = 289 /* 0x121 */,
342 	HAL_REO_DESTINATION_RING               = 290 /* 0x122 */,
343 	HAL_TQM_LIST_GEN_DONE                  = 291 /* 0x123 */,
344 	HAL_WHO_TERMINATE                      = 292 /* 0x124 */,
345 	HAL_TX_LAST_MPDU_END                   = 293 /* 0x125 */,
346 	HAL_TX_CV_DATA                         = 294 /* 0x126 */,
347 	HAL_TCL_ENTRANCE_FROM_PPE_RING         = 295 /* 0x127 */,
348 	HAL_PPDU_TX_END                        = 296 /* 0x128 */,
349 	HAL_PROT_TX_END                        = 297 /* 0x129 */,
350 	HAL_PDG_RESPONSE_RATE_SETTING          = 298 /* 0x12a */,
351 	HAL_MPDU_INFO_GLOBAL_END               = 299 /* 0x12b */,
352 	HAL_TQM_SCH_INSTR_GLOBAL_END           = 300 /* 0x12c */,
353 	HAL_RX_PPDU_END_USER_STATS             = 301 /* 0x12d */,
354 	HAL_RX_PPDU_END_USER_STATS_EXT         = 302 /* 0x12e */,
355 	HAL_NO_ACK_REPORT                      = 303 /* 0x12f */,
356 	HAL_ACK_REPORT                         = 304 /* 0x130 */,
357 	HAL_UNIFORM_REO_CMD_HEADER             = 305 /* 0x131 */,
358 	HAL_REO_GET_QUEUE_STATS                = 306 /* 0x132 */,
359 	HAL_REO_FLUSH_QUEUE                    = 307 /* 0x133 */,
360 	HAL_REO_FLUSH_CACHE                    = 308 /* 0x134 */,
361 	HAL_REO_UNBLOCK_CACHE                  = 309 /* 0x135 */,
362 	HAL_UNIFORM_REO_STATUS_HEADER          = 310 /* 0x136 */,
363 	HAL_REO_GET_QUEUE_STATS_STATUS         = 311 /* 0x137 */,
364 	HAL_REO_FLUSH_QUEUE_STATUS             = 312 /* 0x138 */,
365 	HAL_REO_FLUSH_CACHE_STATUS             = 313 /* 0x139 */,
366 	HAL_REO_UNBLOCK_CACHE_STATUS           = 314 /* 0x13a */,
367 	HAL_TQM_FLUSH_CACHE                    = 315 /* 0x13b */,
368 	HAL_TQM_UNBLOCK_CACHE                  = 316 /* 0x13c */,
369 	HAL_TQM_FLUSH_CACHE_STATUS             = 317 /* 0x13d */,
370 	HAL_TQM_UNBLOCK_CACHE_STATUS           = 318 /* 0x13e */,
371 	HAL_RX_PPDU_END_STATUS_DONE            = 319 /* 0x13f */,
372 	HAL_RX_STATUS_BUFFER_DONE              = 320 /* 0x140 */,
373 	HAL_BUFFER_ADDR_INFO                   = 321 /* 0x141 */,
374 	HAL_RX_MSDU_DESC_INFO                  = 322 /* 0x142 */,
375 	HAL_RX_MPDU_DESC_INFO                  = 323 /* 0x143 */,
376 	HAL_TCL_DATA_CMD                       = 324 /* 0x144 */,
377 	HAL_TCL_GSE_CMD                        = 325 /* 0x145 */,
378 	HAL_TCL_EXIT_BASE                      = 326 /* 0x146 */,
379 	HAL_TCL_COMPACT_EXIT_RING              = 327 /* 0x147 */,
380 	HAL_TCL_REGULAR_EXIT_RING              = 328 /* 0x148 */,
381 	HAL_TCL_EXTENDED_EXIT_RING             = 329 /* 0x149 */,
382 	HAL_UPLINK_COMMON_INFO                 = 330 /* 0x14a */,
383 	HAL_UPLINK_USER_SETUP_INFO             = 331 /* 0x14b */,
384 	HAL_TX_DATA_SYNC                       = 332 /* 0x14c */,
385 	HAL_PHYRX_CBF_READ_REQUEST_ACK         = 333 /* 0x14d */,
386 	HAL_TCL_STATUS_RING                    = 334 /* 0x14e */,
387 	HAL_TQM_GET_MPDU_HEAD_INFO             = 335 /* 0x14f */,
388 	HAL_TQM_SYNC_CMD                       = 336 /* 0x150 */,
389 	HAL_TQM_GET_MPDU_HEAD_INFO_STATUS      = 337 /* 0x151 */,
390 	HAL_TQM_SYNC_CMD_STATUS                = 338 /* 0x152 */,
391 	HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */,
392 	HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */,
393 	HAL_REO_FLUSH_TIMEOUT_LIST             = 341 /* 0x155 */,
394 	HAL_REO_FLUSH_TIMEOUT_LIST_STATUS      = 342 /* 0x156 */,
395 	HAL_REO_TO_PPE_RING                    = 343 /* 0x157 */,
396 	HAL_RX_MPDU_INFO                       = 344 /* 0x158 */,
397 	HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */,
398 	HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */,
399 	HAL_EXAMPLE_USER_TLV_32_NAME           = 347 /* 0x15b */,
400 	HAL_RX_PPDU_START_USER_INFO            = 348 /* 0x15c */,
401 	HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW   = 349 /* 0x15d */,
402 	HAL_RX_RING_MASK                       = 350 /* 0x15e */,
403 	HAL_WHO_CLASSIFY_INFO                  = 351 /* 0x15f */,
404 	HAL_TXPT_CLASSIFY_INFO                 = 352 /* 0x160 */,
405 	HAL_RXPT_CLASSIFY_INFO                 = 353 /* 0x161 */,
406 	HAL_TX_FLOW_SEARCH_ENTRY               = 354 /* 0x162 */,
407 	HAL_RX_FLOW_SEARCH_ENTRY               = 355 /* 0x163 */,
408 	HAL_RECEIVED_TRIGGER_INFO_DETAILS      = 356 /* 0x164 */,
409 	HAL_COEX_MAC_NAP                       = 357 /* 0x165 */,
410 	HAL_MACRX_ABORT_REQUEST_INFO           = 358 /* 0x166 */,
411 	HAL_MACTX_ABORT_REQUEST_INFO           = 359 /* 0x167 */,
412 	HAL_PHYRX_ABORT_REQUEST_INFO           = 360 /* 0x168 */,
413 	HAL_PHYTX_ABORT_REQUEST_INFO           = 361 /* 0x169 */,
414 	HAL_RXPCU_PPDU_END_INFO                = 362 /* 0x16a */,
415 	HAL_WHO_MESH_CONTROL                   = 363 /* 0x16b */,
416 	HAL_L_SIG_A_INFO                       = 364 /* 0x16c */,
417 	HAL_L_SIG_B_INFO                       = 365 /* 0x16d */,
418 	HAL_HT_SIG_INFO                        = 366 /* 0x16e */,
419 	HAL_VHT_SIG_A_INFO                     = 367 /* 0x16f */,
420 	HAL_VHT_SIG_B_SU20_INFO                = 368 /* 0x170 */,
421 	HAL_VHT_SIG_B_SU40_INFO                = 369 /* 0x171 */,
422 	HAL_VHT_SIG_B_SU80_INFO                = 370 /* 0x172 */,
423 	HAL_VHT_SIG_B_SU160_INFO               = 371 /* 0x173 */,
424 	HAL_VHT_SIG_B_MU20_INFO                = 372 /* 0x174 */,
425 	HAL_VHT_SIG_B_MU40_INFO                = 373 /* 0x175 */,
426 	HAL_VHT_SIG_B_MU80_INFO                = 374 /* 0x176 */,
427 	HAL_VHT_SIG_B_MU160_INFO               = 375 /* 0x177 */,
428 	HAL_SERVICE_INFO                       = 376 /* 0x178 */,
429 	HAL_HE_SIG_A_SU_INFO                   = 377 /* 0x179 */,
430 	HAL_HE_SIG_A_MU_DL_INFO                = 378 /* 0x17a */,
431 	HAL_HE_SIG_A_MU_UL_INFO                = 379 /* 0x17b */,
432 	HAL_HE_SIG_B1_MU_INFO                  = 380 /* 0x17c */,
433 	HAL_HE_SIG_B2_MU_INFO                  = 381 /* 0x17d */,
434 	HAL_HE_SIG_B2_OFDMA_INFO               = 382 /* 0x17e */,
435 	HAL_PDG_SW_MODE_BW_START               = 383 /* 0x17f */,
436 	HAL_PDG_SW_MODE_BW_END                 = 384 /* 0x180 */,
437 	HAL_PDG_WAIT_FOR_MAC_REQUEST           = 385 /* 0x181 */,
438 	HAL_PDG_WAIT_FOR_PHY_REQUEST           = 386 /* 0x182 */,
439 	HAL_SCHEDULER_END                      = 387 /* 0x183 */,
440 	HAL_PEER_TABLE_ENTRY                   = 388 /* 0x184 */,
441 	HAL_SW_PEER_INFO                       = 389 /* 0x185 */,
442 	HAL_RXOLE_CCE_CLASSIFY_INFO            = 390 /* 0x186 */,
443 	HAL_TCL_CCE_CLASSIFY_INFO              = 391 /* 0x187 */,
444 	HAL_RXOLE_CCE_INFO                     = 392 /* 0x188 */,
445 	HAL_TCL_CCE_INFO                       = 393 /* 0x189 */,
446 	HAL_TCL_CCE_SUPERRULE                  = 394 /* 0x18a */,
447 	HAL_CCE_RULE                           = 395 /* 0x18b */,
448 	HAL_RX_PPDU_START_DROPPED              = 396 /* 0x18c */,
449 	HAL_RX_PPDU_END_DROPPED                = 397 /* 0x18d */,
450 	HAL_RX_PPDU_END_STATUS_DONE_DROPPED    = 398 /* 0x18e */,
451 	HAL_RX_MPDU_START_DROPPED              = 399 /* 0x18f */,
452 	HAL_RX_MSDU_START_DROPPED              = 400 /* 0x190 */,
453 	HAL_RX_MSDU_END_DROPPED                = 401 /* 0x191 */,
454 	HAL_RX_MPDU_END_DROPPED                = 402 /* 0x192 */,
455 	HAL_RX_ATTENTION_DROPPED               = 403 /* 0x193 */,
456 	HAL_TXPCU_USER_SETUP                   = 404 /* 0x194 */,
457 	HAL_RXPCU_USER_SETUP_EXT               = 405 /* 0x195 */,
458 	HAL_CE_SRC_DESC                        = 406 /* 0x196 */,
459 	HAL_CE_STAT_DESC                       = 407 /* 0x197 */,
460 	HAL_RXOLE_CCE_SUPERRULE                = 408 /* 0x198 */,
461 	HAL_TX_RATE_STATS_INFO                 = 409 /* 0x199 */,
462 	HAL_CMD_PART_0_END                     = 410 /* 0x19a */,
463 	HAL_MACTX_SYNTH_ON                     = 411 /* 0x19b */,
464 	HAL_SCH_CRITICAL_TLV_REFERENCE         = 412 /* 0x19c */,
465 	HAL_TQM_MPDU_GLOBAL_START              = 413 /* 0x19d */,
466 	HAL_EXAMPLE_TLV_32                     = 414 /* 0x19e */,
467 	HAL_TQM_UPDATE_TX_MSDU_FLOW            = 415 /* 0x19f */,
468 	HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD      = 416 /* 0x1a0 */,
469 	HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS     = 417 /* 0x1a1 */,
470 	HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */,
471 	HAL_REO_UPDATE_RX_REO_QUEUE            = 419 /* 0x1a3 */,
472 	HAL_CE_DST_DESC			       = 420 /* 0x1a4 */,
473 	HAL_TLV_BASE                           = 511 /* 0x1ff */,
474 };
475 
476 #define HAL_TLV_HDR_TAG		GENMASK(9, 1)
477 #define HAL_TLV_HDR_LEN		GENMASK(25, 10)
478 #define HAL_TLV_USR_ID		GENMASK(31, 26)
479 
480 #define HAL_TLV_ALIGN	4
481 
482 struct hal_tlv_hdr {
483 	u32 tl;
484 	u8 value[];
485 } __packed;
486 
487 #define RX_MPDU_DESC_INFO0_MSDU_COUNT		GENMASK(7, 0)
488 #define RX_MPDU_DESC_INFO0_SEQ_NUM		GENMASK(19, 8)
489 #define RX_MPDU_DESC_INFO0_FRAG_FLAG		BIT(20)
490 #define RX_MPDU_DESC_INFO0_MPDU_RETRY		BIT(21)
491 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG		BIT(22)
492 #define RX_MPDU_DESC_INFO0_BAR_FRAME		BIT(23)
493 #define RX_MPDU_DESC_INFO0_VALID_PN		BIT(24)
494 #define RX_MPDU_DESC_INFO0_VALID_SA		BIT(25)
495 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT	BIT(26)
496 #define RX_MPDU_DESC_INFO0_VALID_DA		BIT(27)
497 #define RX_MPDU_DESC_INFO0_DA_MCBC		BIT(28)
498 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT	BIT(29)
499 #define RX_MPDU_DESC_INFO0_RAW_MPDU		BIT(30)
500 
501 #define RX_MPDU_DESC_META_DATA_PEER_ID		GENMASK(15, 0)
502 
503 struct rx_mpdu_desc {
504 	u32 info0; /* %RX_MPDU_DESC_INFO */
505 	u32 meta_data;
506 } __packed;
507 
508 /* rx_mpdu_desc
509  *		Producer: RXDMA
510  *		Consumer: REO/SW/FW
511  *
512  * msdu_count
513  *		The number of MSDUs within the MPDU
514  *
515  * mpdu_sequence_number
516  *		The field can have two different meanings based on the setting
517  *		of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU
518  *		start sequence number from the BAR frame otherwise it means
519  *		the MPDU sequence number of the received frame.
520  *
521  * fragment_flag
522  *		When set, this MPDU is a fragment and REO should forward this
523  *		fragment MPDU to the REO destination ring without any reorder
524  *		checks, pn checks or bitmap update. This implies that REO is
525  *		forwarding the pointer to the MSDU link descriptor.
526  *
527  * mpdu_retry_bit
528  *		The retry bit setting from the MPDU header of the received frame
529  *
530  * ampdu_flag
531  *		Indicates the MPDU was received as part of an A-MPDU.
532  *
533  * bar_frame
534  *		Indicates the received frame is a BAR frame. After processing,
535  *		this frame shall be pushed to SW or deleted.
536  *
537  * valid_pn
538  *		When not set, REO will not perform a PN sequence number check.
539  *
540  * valid_sa
541  *		Indicates OLE found a valid SA entry for all MSDUs in this MPDU.
542  *
543  * sa_idx_timeout
544  *		Indicates, at least 1 MSDU within the MPDU has an unsuccessful
545  *		MAC source address search due to the expiration of search timer.
546  *
547  * valid_da
548  *		When set, OLE found a valid DA entry for all MSDUs in this MPDU.
549  *
550  * da_mcbc
551  *		Field Only valid if valid_da is set. Indicates at least one of
552  *		the DA addresses is a Multicast or Broadcast address.
553  *
554  * da_idx_timeout
555  *		Indicates, at least 1 MSDU within the MPDU has an unsuccessful
556  *		MAC destination address search due to the expiration of search
557  *		timer.
558  *
559  * raw_mpdu
560  *		Field only valid when first_msdu_in_mpdu_flag is set. Indicates
561  *		the contents in the MSDU buffer contains a 'RAW' MPDU.
562  */
563 
564 enum hal_rx_msdu_desc_reo_dest_ind {
565 	HAL_RX_MSDU_DESC_REO_DEST_IND_TCL,
566 	HAL_RX_MSDU_DESC_REO_DEST_IND_SW1,
567 	HAL_RX_MSDU_DESC_REO_DEST_IND_SW2,
568 	HAL_RX_MSDU_DESC_REO_DEST_IND_SW3,
569 	HAL_RX_MSDU_DESC_REO_DEST_IND_SW4,
570 	HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE,
571 	HAL_RX_MSDU_DESC_REO_DEST_IND_FW,
572 };
573 
574 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU	BIT(0)
575 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU	BIT(1)
576 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION	BIT(2)
577 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH		GENMASK(16, 3)
578 #define RX_MSDU_DESC_INFO0_REO_DEST_IND		GENMASK(21, 17)
579 #define RX_MSDU_DESC_INFO0_MSDU_DROP		BIT(22)
580 #define RX_MSDU_DESC_INFO0_VALID_SA		BIT(23)
581 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT	BIT(24)
582 #define RX_MSDU_DESC_INFO0_VALID_DA		BIT(25)
583 #define RX_MSDU_DESC_INFO0_DA_MCBC		BIT(26)
584 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT	BIT(27)
585 
586 #define HAL_RX_MSDU_PKT_LENGTH_GET(val)		\
587 	(FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
588 
589 struct rx_msdu_desc {
590 	u32 info0;
591 	u32 rsvd0;
592 } __packed;
593 
594 /* rx_msdu_desc
595  *
596  * first_msdu_in_mpdu
597  *		Indicates first msdu in mpdu.
598  *
599  * last_msdu_in_mpdu
600  *		Indicates last msdu in mpdu. This flag can be true only when
601  *		'Msdu_continuation' set to 0. This implies that when an msdu
602  *		is spread out over multiple buffers and thus msdu_continuation
603  *		is set, only for the very last buffer of the msdu, can the
604  *		'last_msdu_in_mpdu' be set.
605  *
606  *		When both first_msdu_in_mpdu and last_msdu_in_mpdu are set,
607  *		the MPDU that this MSDU belongs to only contains a single MSDU.
608  *
609  * msdu_continuation
610  *		When set, this MSDU buffer was not able to hold the entire MSDU.
611  *		The next buffer will therefore contain additional information
612  *		related to this MSDU.
613  *
614  * msdu_length
615  *		Field is only valid in combination with the 'first_msdu_in_mpdu'
616  *		being set. Full MSDU length in bytes after decapsulation. This
617  *		field is still valid for MPDU frames without A-MSDU. It still
618  *		represents MSDU length after decapsulation Or in case of RAW
619  *		MPDUs, it indicates the length of the entire MPDU (without FCS
620  *		field).
621  *
622  * reo_destination_indication
623  *		The id of the reo exit ring where the msdu frame shall push
624  *		after (MPDU level) reordering has finished. Values are defined
625  *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
626  *
627  * msdu_drop
628  *		Indicates that REO shall drop this MSDU and not forward it to
629  *		any other ring.
630  *
631  * valid_sa
632  *		Indicates OLE found a valid SA entry for this MSDU.
633  *
634  * sa_idx_timeout
635  *		Indicates, an unsuccessful MAC source address search due to
636  *		the expiration of search timer for this MSDU.
637  *
638  * valid_da
639  *		When set, OLE found a valid DA entry for this MSDU.
640  *
641  * da_mcbc
642  *		Field Only valid if valid_da is set. Indicates the DA address
643  *		is a Multicast or Broadcast address for this MSDU.
644  *
645  * da_idx_timeout
646  *		Indicates, an unsuccessful MAC destination address search due
647  *		to the expiration of search timer for this MSDU.
648  */
649 
650 enum hal_reo_dest_ring_buffer_type {
651 	HAL_REO_DEST_RING_BUFFER_TYPE_MSDU,
652 	HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC,
653 };
654 
655 enum hal_reo_dest_ring_push_reason {
656 	HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED,
657 	HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION,
658 };
659 
660 enum hal_reo_dest_ring_error_code {
661 	HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO,
662 	HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID,
663 	HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA,
664 	HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE,
665 	HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE,
666 	HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP,
667 	HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP,
668 	HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR,
669 	HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR,
670 	HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION,
671 	HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN,
672 	HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED,
673 	HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET,
674 	HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET,
675 	HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED,
676 	HAL_REO_DEST_RING_ERROR_CODE_MAX,
677 };
678 
679 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
680 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE		BIT(8)
681 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON		GENMASK(10, 9)
682 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE		GENMASK(15, 11)
683 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM		GENMASK(31, 16)
684 
685 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID	BIT(0)
686 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE		GENMASK(4, 1)
687 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX	GENMASK(12, 5)
688 
689 #define HAL_REO_DEST_RING_INFO2_RING_ID			GENMASK(27, 20)
690 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT		GENMASK(31, 28)
691 
692 struct hal_reo_dest_ring {
693 	struct ath11k_buffer_addr buf_addr_info;
694 	struct rx_mpdu_desc rx_mpdu_info;
695 	struct rx_msdu_desc rx_msdu_info;
696 	u32 queue_addr_lo;
697 	u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */
698 	u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */
699 	u32 rsvd0;
700 	u32 rsvd1;
701 	u32 rsvd2;
702 	u32 rsvd3;
703 	u32 rsvd4;
704 	u32 rsvd5;
705 	u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */
706 } __packed;
707 
708 /* hal_reo_dest_ring
709  *
710  *		Producer: RXDMA
711  *		Consumer: REO/SW/FW
712  *
713  * buf_addr_info
714  *		Details of the physical address of a buffer or MSDU
715  *		link descriptor.
716  *
717  * rx_mpdu_info
718  *		General information related to the MPDU that is passed
719  *		on from REO entrance ring to the REO destination ring.
720  *
721  * rx_msdu_info
722  *		General information related to the MSDU that is passed
723  *		on from RXDMA all the way to the REO destination ring.
724  *
725  * queue_addr_lo
726  *		Address (lower 32 bits) of the REO queue descriptor.
727  *
728  * queue_addr_hi
729  *		Address (upper 8 bits) of the REO queue descriptor.
730  *
731  * buffer_type
732  *		Indicates the type of address provided in the buf_addr_info.
733  *		Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
734  *
735  * push_reason
736  *		Reason for pushing this frame to this exit ring. Values are
737  *		defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
738  *
739  * error_code
740  *		Valid only when 'push_reason' is set. All error codes are
741  *		defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
742  *
743  * rx_queue_num
744  *		Indicates the REO MPDU reorder queue id from which this frame
745  *		originated.
746  *
747  * reorder_info_valid
748  *		When set, REO has been instructed to not perform the actual
749  *		re-ordering of frames for this queue, but just to insert
750  *		the reorder opcodes.
751  *
752  * reorder_opcode
753  *		Field is valid when 'reorder_info_valid' is set. This field is
754  *		always valid for debug purpose as well.
755  *
756  * reorder_slot_idx
757  *		Valid only when 'reorder_info_valid' is set.
758  *
759  * ring_id
760  *		The buffer pointer ring id.
761  *		0 - Idle ring
762  *		1 - N refers to other rings.
763  *
764  * looping_count
765  *		Indicates the number of times the producer of entries into
766  *		this ring has looped around the ring.
767  */
768 
769 enum hal_reo_entr_rxdma_ecode {
770 	HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR,
771 	HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR,
772 	HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR,
773 	HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR,
774 	HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR,
775 	HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR,
776 	HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR,
777 	HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR,
778 	HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR,
779 	HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR,
780 	HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR,
781 	HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR,
782 	HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR,
783 	HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR,
784 	HAL_REO_ENTR_RING_RXDMA_ECODE_MAX,
785 };
786 
787 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
788 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT		GENMASK(21, 8)
789 #define HAL_REO_ENTR_RING_INFO0_DEST_IND		GENMASK(26, 22)
790 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR		BIT(27)
791 
792 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON	GENMASK(1, 0)
793 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE	GENMASK(6, 2)
794 
795 struct hal_reo_entrance_ring {
796 	struct ath11k_buffer_addr buf_addr_info;
797 	struct rx_mpdu_desc rx_mpdu_info;
798 	u32 queue_addr_lo;
799 	u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */
800 	u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */
801 	u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */
802 
803 } __packed;
804 
805 /* hal_reo_entrance_ring
806  *
807  *		Producer: RXDMA
808  *		Consumer: REO
809  *
810  * buf_addr_info
811  *		Details of the physical address of a buffer or MSDU
812  *		link descriptor.
813  *
814  * rx_mpdu_info
815  *		General information related to the MPDU that is passed
816  *		on from REO entrance ring to the REO destination ring.
817  *
818  * queue_addr_lo
819  *		Address (lower 32 bits) of the REO queue descriptor.
820  *
821  * queue_addr_hi
822  *		Address (upper 8 bits) of the REO queue descriptor.
823  *
824  * mpdu_byte_count
825  *		An approximation of the number of bytes received in this MPDU.
826  *		Used to keeps stats on the amount of data flowing
827  *		through a queue.
828  *
829  * reo_destination_indication
830  *		The id of the reo exit ring where the msdu frame shall push
831  *		after (MPDU level) reordering has finished. Values are defined
832  *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
833  *
834  * frameless_bar
835  *		Indicates that this REO entrance ring struct contains BAR info
836  *		from a multi TID BAR frame. The original multi TID BAR frame
837  *		itself contained all the REO info for the first TID, but all
838  *		the subsequent TID info and their linkage to the REO descriptors
839  *		is passed down as 'frameless' BAR info.
840  *
841  *		The only fields valid in this descriptor when this bit is set
842  *		are queue_addr_lo, queue_addr_hi, mpdu_sequence_number,
843  *		bar_frame and peer_meta_data.
844  *
845  * rxdma_push_reason
846  *		Reason for pushing this frame to this exit ring. Values are
847  *		defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
848  *
849  * rxdma_error_code
850  *		Valid only when 'push_reason' is set. All error codes are
851  *		defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
852  *
853  * ring_id
854  *		The buffer pointer ring id.
855  *		0 - Idle ring
856  *		1 - N refers to other rings.
857  *
858  * looping_count
859  *		Indicates the number of times the producer of entries into
860  *		this ring has looped around the ring.
861  */
862 
863 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON	GENMASK(1, 0)
864 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE	GENMASK(6, 2)
865 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER	GENMASK(10, 7)
866 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR	BIT(11)
867 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT	GENMASK(15, 12)
868 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU	BIT(16)
869 
870 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID	GENMASK(15, 0)
871 #define HAL_SW_MON_RING_INFO1_RING_ID		GENMASK(27, 20)
872 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT	GENMASK(31, 28)
873 
874 struct hal_sw_monitor_ring {
875 	struct ath11k_buffer_addr buf_addr_info;
876 	struct rx_mpdu_desc rx_mpdu_info;
877 	struct ath11k_buffer_addr status_buf_addr_info;
878 	u32 info0;
879 	u32 info1;
880 } __packed;
881 
882 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER	GENMASK(15, 0)
883 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED	BIT(16)
884 
885 struct hal_reo_cmd_hdr {
886 	u32 info0;
887 } __packed;
888 
889 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI	GENMASK(7, 0)
890 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS	BIT(8)
891 
892 struct hal_reo_get_queue_stats {
893 	struct hal_reo_cmd_hdr cmd;
894 	u32 queue_addr_lo;
895 	u32 info0;
896 	u32 rsvd0[6];
897 } __packed;
898 
899 /* hal_reo_get_queue_stats
900  *		Producer: SW
901  *		Consumer: REO
902  *
903  * cmd
904  *		Details for command execution tracking purposes.
905  *
906  * queue_addr_lo
907  *		Address (lower 32 bits) of the REO queue descriptor.
908  *
909  * queue_addr_hi
910  *		Address (upper 8 bits) of the REO queue descriptor.
911  *
912  * clear_stats
913  *		Clear stats settings. When set, Clear the stats after
914  *		generating the status.
915  *
916  *		Following stats will be cleared.
917  *		Timeout_count
918  *		Forward_due_to_bar_count
919  *		Duplicate_count
920  *		Frames_in_order_count
921  *		BAR_received_count
922  *		MPDU_Frames_processed_count
923  *		MSDU_Frames_processed_count
924  *		Total_processed_byte_count
925  *		Late_receive_MPDU_count
926  *		window_jump_2k
927  *		Hole_count
928  */
929 
930 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI		GENMASK(7, 0)
931 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR	BIT(8)
932 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX	GENMASK(10, 9)
933 
934 struct hal_reo_flush_queue {
935 	struct hal_reo_cmd_hdr cmd;
936 	u32 desc_addr_lo;
937 	u32 info0;
938 	u32 rsvd0[6];
939 } __packed;
940 
941 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI		GENMASK(7, 0)
942 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS		BIT(8)
943 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX	BIT(9)
944 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX	GENMASK(11, 10)
945 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE	BIT(12)
946 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE	BIT(13)
947 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL		BIT(14)
948 
949 struct hal_reo_flush_cache {
950 	struct hal_reo_cmd_hdr cmd;
951 	u32 cache_addr_lo;
952 	u32 info0;
953 	u32 rsvd0[6];
954 } __packed;
955 
956 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE	BIT(0)
957 #define HAL_TCL_DATA_CMD_INFO0_EPD		BIT(1)
958 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE	GENMASK(3, 2)
959 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE	GENMASK(7, 4)
960 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP	BIT(8)
961 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP	BIT(9)
962 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE	GENMASK(13, 12)
963 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN		GENMASK(15, 14)
964 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM		GENMASK(31, 16)
965 
966 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN		GENMASK(15, 0)
967 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN	BIT(16)
968 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN	BIT(17)
969 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN	BIT(18)
970 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN	BIT(19)
971 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN	BIT(20)
972 #define HAL_TCL_DATA_CMD_INFO1_TO_FW		BIT(21)
973 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET	GENMASK(31, 23)
974 
975 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP		GENMASK(18, 0)
976 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID		BIT(19)
977 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE	BIT(20)
978 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE		BIT(21)
979 #define HAL_TCL_DATA_CMD_INFO2_TID			GENMASK(25, 22)
980 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID			GENMASK(27, 26)
981 
982 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX	GENMASK(5, 0)
983 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX		GENMASK(25, 6)
984 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM		GENMASK(29, 26)
985 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE	GENMASK(31, 30)
986 
987 #define HAL_TCL_DATA_CMD_INFO4_RING_ID			GENMASK(27, 20)
988 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT		GENMASK(31, 28)
989 
990 enum hal_encrypt_type {
991 	HAL_ENCRYPT_TYPE_WEP_40,
992 	HAL_ENCRYPT_TYPE_WEP_104,
993 	HAL_ENCRYPT_TYPE_TKIP_NO_MIC,
994 	HAL_ENCRYPT_TYPE_WEP_128,
995 	HAL_ENCRYPT_TYPE_TKIP_MIC,
996 	HAL_ENCRYPT_TYPE_WAPI,
997 	HAL_ENCRYPT_TYPE_CCMP_128,
998 	HAL_ENCRYPT_TYPE_OPEN,
999 	HAL_ENCRYPT_TYPE_CCMP_256,
1000 	HAL_ENCRYPT_TYPE_GCMP_128,
1001 	HAL_ENCRYPT_TYPE_AES_GCMP_256,
1002 	HAL_ENCRYPT_TYPE_WAPI_GCM_SM4,
1003 };
1004 
1005 enum hal_tcl_encap_type {
1006 	HAL_TCL_ENCAP_TYPE_RAW,
1007 	HAL_TCL_ENCAP_TYPE_NATIVE_WIFI,
1008 	HAL_TCL_ENCAP_TYPE_ETHERNET,
1009 	HAL_TCL_ENCAP_TYPE_802_3 = 3,
1010 };
1011 
1012 enum hal_tcl_desc_type {
1013 	HAL_TCL_DESC_TYPE_BUFFER,
1014 	HAL_TCL_DESC_TYPE_EXT_DESC,
1015 };
1016 
1017 enum hal_wbm_htt_tx_comp_status {
1018 	HAL_WBM_REL_HTT_TX_COMP_STATUS_OK,
1019 	HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP,
1020 	HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL,
1021 	HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ,
1022 	HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT,
1023 	HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY,
1024 };
1025 
1026 struct hal_tcl_data_cmd {
1027 	struct ath11k_buffer_addr buf_addr_info;
1028 	u32 info0;
1029 	u32 info1;
1030 	u32 info2;
1031 	u32 info3;
1032 	u32 info4;
1033 } __packed;
1034 
1035 /* hal_tcl_data_cmd
1036  *
1037  * buf_addr_info
1038  *		Details of the physical address of a buffer or MSDU
1039  *		link descriptor.
1040  *
1041  * desc_type
1042  *		Indicates the type of address provided in the buf_addr_info.
1043  *		Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
1044  *
1045  * epd
1046  *		When this bit is set then input packet is an EPD type.
1047  *
1048  * encap_type
1049  *		Indicates the encapsulation that HW will perform. Values are
1050  *		defined in enum %HAL_TCL_ENCAP_TYPE_.
1051  *
1052  * encrypt_type
1053  *		Field only valid for encap_type: RAW
1054  *		Values are defined in enum %HAL_ENCRYPT_TYPE_.
1055  *
1056  * src_buffer_swap
1057  *		Treats source memory (packet buffer) organization as big-endian.
1058  *		1'b0: Source memory is little endian
1059  *		1'b1: Source memory is big endian
1060  *
1061  * link_meta_swap
1062  *		Treats link descriptor and Metadata as big-endian.
1063  *		1'b0: memory is little endian
1064  *		1'b1: memory is big endian
1065  *
1066  * search_type
1067  *		Search type select
1068  *		0 - Normal search, 1 - Index based address search,
1069  *		2 - Index based flow search
1070  *
1071  * addrx_en
1072  * addry_en
1073  *		Address X/Y search enable in ASE correspondingly.
1074  *		1'b0: Search disable
1075  *		1'b1: Search Enable
1076  *
1077  * cmd_num
1078  *		This number can be used to match against status.
1079  *
1080  * data_length
1081  *		MSDU length in case of direct descriptor. Length of link
1082  *		extension descriptor in case of Link extension descriptor.
1083  *
1084  * *_checksum_en
1085  *		Enable checksum replacement for ipv4, udp_over_ipv4, ipv6,
1086  *		udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6.
1087  *
1088  * to_fw
1089  *		Forward packet to FW along with classification result. The
1090  *		packet will not be forward to TQM when this bit is set.
1091  *		1'b0: Use classification result to forward the packet.
1092  *		1'b1: Override classification result & forward packet only to fw
1093  *
1094  * packet_offset
1095  *		Packet offset from Metadata in case of direct buffer descriptor.
1096  *
1097  * buffer_timestamp
1098  * buffer_timestamp_valid
1099  *		Frame system entrance timestamp. It shall be filled by first
1100  *		module (SW, TCL or TQM) that sees the frames first.
1101  *
1102  * mesh_enable
1103  *		For raw WiFi frames, this indicates transmission to a mesh STA,
1104  *		enabling the interpretation of the 'Mesh Control Present' bit
1105  *		(bit 8) of QoS Control.
1106  *		For native WiFi frames, this indicates that a 'Mesh Control'
1107  *		field is present between the header and the LLC.
1108  *
1109  * hlos_tid_overwrite
1110  *
1111  *		When set, TCL shall ignore the IP DSCP and VLAN PCP
1112  *		fields and use HLOS_TID as the final TID. Otherwise TCL
1113  *		shall consider the DSCP and PCP fields as well as HLOS_TID
1114  *		and choose a final TID based on the configured priority
1115  *
1116  * hlos_tid
1117  *		HLOS MSDU priority
1118  *		Field is used when HLOS_TID_overwrite is set.
1119  *
1120  * lmac_id
1121  *		TCL uses this LMAC_ID in address search, i.e, while
1122  *		finding matching entry for the packet in AST corresponding
1123  *		to given LMAC_ID
1124  *
1125  *		If LMAC ID is all 1s (=> value 3), it indicates wildcard
1126  *		match for any MAC
1127  *
1128  * dscp_tid_table_num
1129  *		DSCP to TID mapping table number that need to be used
1130  *		for the MSDU.
1131  *
1132  * search_index
1133  *		The index that will be used for index based address or
1134  *		flow search. The field is valid when 'search_type' is  1 or 2.
1135  *
1136  * cache_set_num
1137  *
1138  *		Cache set number that should be used to cache the index
1139  *		based search results, for address and flow search. This
1140  *		value should be equal to LSB four bits of the hash value of
1141  *		match data, in case of search index points to an entry which
1142  *		may be used in content based search also. The value can be
1143  *		anything when the entry pointed by search index will not be
1144  *		used for content based search.
1145  *
1146  * ring_id
1147  *		The buffer pointer ring ID.
1148  *		0 refers to the IDLE ring
1149  *		1 - N refers to other rings
1150  *
1151  * looping_count
1152  *
1153  *		A count value that indicates the number of times the
1154  *		producer of entries into the Ring has looped around the
1155  *		ring.
1156  *
1157  *		At initialization time, this value is set to 0. On the
1158  *		first loop, this value is set to 1. After the max value is
1159  *		reached allowed by the number of bits for this field, the
1160  *		count value continues with 0 again.
1161  *
1162  *		In case SW is the consumer of the ring entries, it can
1163  *		use this field to figure out up to where the producer of
1164  *		entries has created new entries. This eliminates the need to
1165  *		check where the head pointer' of the ring is located once
1166  *		the SW starts processing an interrupt indicating that new
1167  *		entries have been put into this ring...
1168  *
1169  *		Also note that SW if it wants only needs to look at the
1170  *		LSB bit of this count value.
1171  */
1172 
1173 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
1174 
1175 enum hal_tcl_gse_ctrl {
1176 	HAL_TCL_GSE_CTRL_RD_STAT,
1177 	HAL_TCL_GSE_CTRL_SRCH_DIS,
1178 	HAL_TCL_GSE_CTRL_WR_BK_SINGLE,
1179 	HAL_TCL_GSE_CTRL_WR_BK_ALL,
1180 	HAL_TCL_GSE_CTRL_INVAL_SINGLE,
1181 	HAL_TCL_GSE_CTRL_INVAL_ALL,
1182 	HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE,
1183 	HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL,
1184 	HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE,
1185 };
1186 
1187 /* hal_tcl_gse_ctrl
1188  *
1189  * rd_stat
1190  *		Report or Read statistics
1191  * srch_dis
1192  *		Search disable. Report only Hash.
1193  * wr_bk_single
1194  *		Write Back single entry
1195  * wr_bk_all
1196  *		Write Back entire cache entry
1197  * inval_single
1198  *		Invalidate single cache entry
1199  * inval_all
1200  *		Invalidate entire cache
1201  * wr_bk_inval_single
1202  *		Write back and invalidate single entry in cache
1203  * wr_bk_inval_all
1204  *		Write back and invalidate entire cache
1205  * clr_stat_single
1206  *		Clear statistics for single entry
1207  */
1208 
1209 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI		GENMASK(7, 0)
1210 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL			GENMASK(11, 8)
1211 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL			BIT(12)
1212 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID	BIT(13)
1213 #define HAL_TCL_GSE_CMD_INFO0_SWAP			BIT(14)
1214 
1215 #define HAL_TCL_GSE_CMD_INFO1_RING_ID			GENMASK(27, 20)
1216 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT		GENMASK(31, 28)
1217 
1218 struct hal_tcl_gse_cmd {
1219 	u32 ctrl_buf_addr_lo;
1220 	u32 info0;
1221 	u32 meta_data[2];
1222 	u32 rsvd0[2];
1223 	u32 info1;
1224 } __packed;
1225 
1226 /* hal_tcl_gse_cmd
1227  *
1228  * ctrl_buf_addr_lo, ctrl_buf_addr_hi
1229  *		Address of a control buffer containing additional info needed
1230  *		for this command execution.
1231  *
1232  * gse_ctrl
1233  *		GSE control operations. This includes cache operations and table
1234  *		entry statistics read/clear operation. Values are defined in
1235  *		enum %HAL_TCL_GSE_CTRL.
1236  *
1237  * gse_sel
1238  *		To select the ASE/FSE to do the operation mention by GSE_ctrl.
1239  *		0: FSE select 1: ASE select
1240  *
1241  * status_destination_ring_id
1242  *		TCL status ring to which the GSE status needs to be send.
1243  *
1244  * swap
1245  *		Bit to enable byte swapping of contents of buffer.
1246  *
1247  * meta_data
1248  *		Meta data to be returned in the status descriptor
1249  */
1250 
1251 enum hal_tcl_cache_op_res {
1252 	HAL_TCL_CACHE_OP_RES_DONE,
1253 	HAL_TCL_CACHE_OP_RES_NOT_FOUND,
1254 	HAL_TCL_CACHE_OP_RES_TIMEOUT,
1255 };
1256 
1257 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL		GENMASK(3, 0)
1258 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL		BIT(4)
1259 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES		GENMASK(6, 5)
1260 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT		GENMASK(31, 8)
1261 
1262 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX		GENMASK(19, 0)
1263 
1264 #define HAL_TCL_STATUS_RING_INFO2_RING_ID		GENMASK(27, 20)
1265 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT		GENMASK(31, 28)
1266 
1267 struct hal_tcl_status_ring {
1268 	u32 info0;
1269 	u32 msdu_byte_count;
1270 	u32 msdu_timestamp;
1271 	u32 meta_data[2];
1272 	u32 info1;
1273 	u32 rsvd0;
1274 	u32 info2;
1275 } __packed;
1276 
1277 /* hal_tcl_status_ring
1278  *
1279  * gse_ctrl
1280  *		GSE control operations. This includes cache operations and table
1281  *		entry statistics read/clear operation. Values are defined in
1282  *		enum %HAL_TCL_GSE_CTRL.
1283  *
1284  * gse_sel
1285  *		To select the ASE/FSE to do the operation mention by GSE_ctrl.
1286  *		0: FSE select 1: ASE select
1287  *
1288  * cache_op_res
1289  *		Cache operation result. Values are defined in enum
1290  *		%HAL_TCL_CACHE_OP_RES_.
1291  *
1292  * msdu_cnt
1293  * msdu_byte_count
1294  *		MSDU count of Entry and MSDU byte count for entry 1.
1295  *
1296  * hash_indx
1297  *		Hash value of the entry in case of search failed or disabled.
1298  */
1299 
1300 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI	GENMASK(7, 0)
1301 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN	BIT(8)
1302 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP	BIT(9)
1303 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP	BIT(10)
1304 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER	BIT(11)
1305 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN		GENMASK(31, 16)
1306 
1307 #define HAL_CE_SRC_DESC_META_INFO_DATA		GENMASK(15, 0)
1308 
1309 #define HAL_CE_SRC_DESC_FLAGS_RING_ID		GENMASK(27, 20)
1310 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT		HAL_SRNG_DESC_LOOP_CNT
1311 
1312 struct hal_ce_srng_src_desc {
1313 	u32 buffer_addr_low;
1314 	u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */
1315 	u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
1316 	u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */
1317 } __packed;
1318 
1319 /*
1320  * hal_ce_srng_src_desc
1321  *
1322  * buffer_addr_lo
1323  *		LSB 32 bits of the 40 Bit Pointer to the source buffer
1324  *
1325  * buffer_addr_hi
1326  *		MSB 8 bits of the 40 Bit Pointer to the source buffer
1327  *
1328  * toeplitz_en
1329  *		Enable generation of 32-bit Toeplitz-LFSR hash for
1330  *		data transfer. In case of gather field in first source
1331  *		ring entry of the gather copy cycle in taken into account.
1332  *
1333  * src_swap
1334  *		Treats source memory organization as big-endian. For
1335  *		each dword read (4 bytes), the byte 0 is swapped with byte 3
1336  *		and byte 1 is swapped with byte 2.
1337  *		In case of gather field in first source ring entry of
1338  *		the gather copy cycle in taken into account.
1339  *
1340  * dest_swap
1341  *		Treats destination memory organization as big-endian.
1342  *		For each dword write (4 bytes), the byte 0 is swapped with
1343  *		byte 3 and byte 1 is swapped with byte 2.
1344  *		In case of gather field in first source ring entry of
1345  *		the gather copy cycle in taken into account.
1346  *
1347  * gather
1348  *		Enables gather of multiple copy engine source
1349  *		descriptors to one destination.
1350  *
1351  * ce_res_0
1352  *		Reserved
1353  *
1354  *
1355  * length
1356  *		Length of the buffer in units of octets of the current
1357  *		descriptor
1358  *
1359  * fw_metadata
1360  *		Meta data used by FW.
1361  *		In case of gather field in first source ring entry of
1362  *		the gather copy cycle in taken into account.
1363  *
1364  * ce_res_1
1365  *		Reserved
1366  *
1367  * ce_res_2
1368  *		Reserved
1369  *
1370  * ring_id
1371  *		The buffer pointer ring ID.
1372  *		0 refers to the IDLE ring
1373  *		1 - N refers to other rings
1374  *		Helps with debugging when dumping ring contents.
1375  *
1376  * looping_count
1377  *		A count value that indicates the number of times the
1378  *		producer of entries into the Ring has looped around the
1379  *		ring.
1380  *
1381  *		At initialization time, this value is set to 0. On the
1382  *		first loop, this value is set to 1. After the max value is
1383  *		reached allowed by the number of bits for this field, the
1384  *		count value continues with 0 again.
1385  *
1386  *		In case SW is the consumer of the ring entries, it can
1387  *		use this field to figure out up to where the producer of
1388  *		entries has created new entries. This eliminates the need to
1389  *		check where the head pointer' of the ring is located once
1390  *		the SW starts processing an interrupt indicating that new
1391  *		entries have been put into this ring...
1392  *
1393  *		Also note that SW if it wants only needs to look at the
1394  *		LSB bit of this count value.
1395  */
1396 
1397 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI		GENMASK(7, 0)
1398 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID		GENMASK(27, 20)
1399 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT		HAL_SRNG_DESC_LOOP_CNT
1400 
1401 struct hal_ce_srng_dest_desc {
1402 	u32 buffer_addr_low;
1403 	u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */
1404 } __packed;
1405 
1406 /* hal_ce_srng_dest_desc
1407  *
1408  * dst_buffer_low
1409  *		LSB 32 bits of the 40 Bit Pointer to the Destination
1410  *		buffer
1411  *
1412  * dst_buffer_high
1413  *		MSB 8 bits of the 40 Bit Pointer to the Destination
1414  *		buffer
1415  *
1416  * ce_res_4
1417  *		Reserved
1418  *
1419  * ring_id
1420  *		The buffer pointer ring ID.
1421  *		0 refers to the IDLE ring
1422  *		1 - N refers to other rings
1423  *		Helps with debugging when dumping ring contents.
1424  *
1425  * looping_count
1426  *		A count value that indicates the number of times the
1427  *		producer of entries into the Ring has looped around the
1428  *		ring.
1429  *
1430  *		At initialization time, this value is set to 0. On the
1431  *		first loop, this value is set to 1. After the max value is
1432  *		reached allowed by the number of bits for this field, the
1433  *		count value continues with 0 again.
1434  *
1435  *		In case SW is the consumer of the ring entries, it can
1436  *		use this field to figure out up to where the producer of
1437  *		entries has created new entries. This eliminates the need to
1438  *		check where the head pointer' of the ring is located once
1439  *		the SW starts processing an interrupt indicating that new
1440  *		entries have been put into this ring...
1441  *
1442  *		Also note that SW if it wants only needs to look at the
1443  *		LSB bit of this count value.
1444  */
1445 
1446 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN		BIT(8)
1447 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP		BIT(9)
1448 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP		BIT(10)
1449 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER		BIT(11)
1450 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN		GENMASK(31, 16)
1451 
1452 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA		GENMASK(15, 0)
1453 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID	GENMASK(27, 20)
1454 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT	HAL_SRNG_DESC_LOOP_CNT
1455 
1456 struct hal_ce_srng_dst_status_desc {
1457 	u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */
1458 	u32 toeplitz_hash0;
1459 	u32 toeplitz_hash1;
1460 	u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
1461 } __packed;
1462 
1463 /* hal_ce_srng_dst_status_desc
1464  *
1465  * ce_res_5
1466  *		Reserved
1467  *
1468  * toeplitz_en
1469  *
1470  * src_swap
1471  *		Source memory buffer swapped
1472  *
1473  * dest_swap
1474  *		Destination  memory buffer swapped
1475  *
1476  * gather
1477  *		Gather of multiple copy engine source descriptors to one
1478  *		destination enabled
1479  *
1480  * ce_res_6
1481  *		Reserved
1482  *
1483  * length
1484  *		Sum of all the Lengths of the source descriptor in the
1485  *		gather chain
1486  *
1487  * toeplitz_hash_0
1488  *		32 LS bits of 64 bit Toeplitz LFSR hash result
1489  *
1490  * toeplitz_hash_1
1491  *		32 MS bits of 64 bit Toeplitz LFSR hash result
1492  *
1493  * fw_metadata
1494  *		Meta data used by FW
1495  *		In case of gather field in first source ring entry of
1496  *		the gather copy cycle in taken into account.
1497  *
1498  * ce_res_7
1499  *		Reserved
1500  *
1501  * ring_id
1502  *		The buffer pointer ring ID.
1503  *		0 refers to the IDLE ring
1504  *		1 - N refers to other rings
1505  *		Helps with debugging when dumping ring contents.
1506  *
1507  * looping_count
1508  *		A count value that indicates the number of times the
1509  *		producer of entries into the Ring has looped around the
1510  *		ring.
1511  *
1512  *		At initialization time, this value is set to 0. On the
1513  *		first loop, this value is set to 1. After the max value is
1514  *		reached allowed by the number of bits for this field, the
1515  *		count value continues with 0 again.
1516  *
1517  *		In case SW is the consumer of the ring entries, it can
1518  *		use this field to figure out up to where the producer of
1519  *		entries has created new entries. This eliminates the need to
1520  *		check where the head pointer' of the ring is located once
1521  *		the SW starts processing an interrupt indicating that new
1522  *		entries have been put into this ring...
1523  *
1524  *		Also note that SW if it wants only needs to look at the
1525  *			LSB bit of this count value.
1526  */
1527 
1528 #define HAL_TX_RATE_STATS_INFO0_VALID		BIT(0)
1529 #define HAL_TX_RATE_STATS_INFO0_BW		GENMASK(2, 1)
1530 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE	GENMASK(6, 3)
1531 #define HAL_TX_RATE_STATS_INFO0_STBC		BIT(7)
1532 #define HAL_TX_RATE_STATS_INFO0_LDPC		BIT(8)
1533 #define HAL_TX_RATE_STATS_INFO0_SGI		GENMASK(10, 9)
1534 #define HAL_TX_RATE_STATS_INFO0_MCS		GENMASK(14, 11)
1535 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX	BIT(15)
1536 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU	GENMASK(27, 16)
1537 
1538 enum hal_tx_rate_stats_bw {
1539 	HAL_TX_RATE_STATS_BW_20,
1540 	HAL_TX_RATE_STATS_BW_40,
1541 	HAL_TX_RATE_STATS_BW_80,
1542 	HAL_TX_RATE_STATS_BW_160,
1543 };
1544 
1545 enum hal_tx_rate_stats_pkt_type {
1546 	HAL_TX_RATE_STATS_PKT_TYPE_11A,
1547 	HAL_TX_RATE_STATS_PKT_TYPE_11B,
1548 	HAL_TX_RATE_STATS_PKT_TYPE_11N,
1549 	HAL_TX_RATE_STATS_PKT_TYPE_11AC,
1550 	HAL_TX_RATE_STATS_PKT_TYPE_11AX,
1551 };
1552 
1553 enum hal_tx_rate_stats_sgi {
1554 	HAL_TX_RATE_STATS_SGI_08US,
1555 	HAL_TX_RATE_STATS_SGI_04US,
1556 	HAL_TX_RATE_STATS_SGI_16US,
1557 	HAL_TX_RATE_STATS_SGI_32US,
1558 };
1559 
1560 struct hal_tx_rate_stats {
1561 	u32 info0;
1562 	u32 tsf;
1563 } __packed;
1564 
1565 struct hal_wbm_link_desc {
1566 	struct ath11k_buffer_addr buf_addr_info;
1567 } __packed;
1568 
1569 /* hal_wbm_link_desc
1570  *
1571  *	Producer: WBM
1572  *	Consumer: WBM
1573  *
1574  * buf_addr_info
1575  *		Details of the physical address of a buffer or MSDU
1576  *		link descriptor.
1577  */
1578 
1579 enum hal_wbm_rel_src_module {
1580 	HAL_WBM_REL_SRC_MODULE_TQM,
1581 	HAL_WBM_REL_SRC_MODULE_RXDMA,
1582 	HAL_WBM_REL_SRC_MODULE_REO,
1583 	HAL_WBM_REL_SRC_MODULE_FW,
1584 	HAL_WBM_REL_SRC_MODULE_SW,
1585 };
1586 
1587 enum hal_wbm_rel_desc_type {
1588 	HAL_WBM_REL_DESC_TYPE_REL_MSDU,
1589 	HAL_WBM_REL_DESC_TYPE_MSDU_LINK,
1590 	HAL_WBM_REL_DESC_TYPE_MPDU_LINK,
1591 	HAL_WBM_REL_DESC_TYPE_MSDU_EXT,
1592 	HAL_WBM_REL_DESC_TYPE_QUEUE_EXT,
1593 };
1594 
1595 /* hal_wbm_rel_desc_type
1596  *
1597  * msdu_buffer
1598  *	The address points to an MSDU buffer
1599  *
1600  * msdu_link_descriptor
1601  *	The address points to an Tx MSDU link descriptor
1602  *
1603  * mpdu_link_descriptor
1604  *	The address points to an MPDU link descriptor
1605  *
1606  * msdu_ext_descriptor
1607  *	The address points to an MSDU extension descriptor
1608  *
1609  * queue_ext_descriptor
1610  *	The address points to an TQM queue extension descriptor. WBM should
1611  *	treat this is the same way as a link descriptor.
1612  */
1613 
1614 enum hal_wbm_rel_bm_act {
1615 	HAL_WBM_REL_BM_ACT_PUT_IN_IDLE,
1616 	HAL_WBM_REL_BM_ACT_REL_MSDU,
1617 };
1618 
1619 /* hal_wbm_rel_bm_act
1620  *
1621  * put_in_idle_list
1622  *	Put the buffer or descriptor back in the idle list. In case of MSDU or
1623  *	MDPU link descriptor, BM does not need to check to release any
1624  *	individual MSDU buffers.
1625  *
1626  * release_msdu_list
1627  *	This BM action can only be used in combination with desc_type being
1628  *	msdu_link_descriptor. Field first_msdu_index points out which MSDU
1629  *	pointer in the MSDU link descriptor is the first of an MPDU that is
1630  *	released. BM shall release all the MSDU buffers linked to this first
1631  *	MSDU buffer pointer. All related MSDU buffer pointer entries shall be
1632  *	set to value 0, which represents the 'NULL' pointer. When all MSDU
1633  *	buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link
1634  *	descriptor itself shall also be released.
1635  */
1636 
1637 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE		GENMASK(2, 0)
1638 #define HAL_WBM_RELEASE_INFO0_BM_ACTION			GENMASK(5, 3)
1639 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE			GENMASK(8, 6)
1640 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX		GENMASK(12, 9)
1641 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON	GENMASK(16, 13)
1642 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON		GENMASK(18, 17)
1643 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE		GENMASK(23, 19)
1644 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON		GENMASK(25, 24)
1645 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE		GENMASK(30, 26)
1646 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR	BIT(31)
1647 
1648 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER		GENMASK(23, 0)
1649 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT		GENMASK(30, 24)
1650 
1651 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI		GENMASK(7, 0)
1652 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID	BIT(8)
1653 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU		BIT(9)
1654 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU			BIT(10)
1655 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU		BIT(11)
1656 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME		BIT(12)
1657 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP		GENMASK(31, 13)
1658 
1659 #define HAL_WBM_RELEASE_INFO3_PEER_ID			GENMASK(15, 0)
1660 #define HAL_WBM_RELEASE_INFO3_TID			GENMASK(19, 16)
1661 #define HAL_WBM_RELEASE_INFO3_RING_ID			GENMASK(27, 20)
1662 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT		GENMASK(31, 28)
1663 
1664 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS		GENMASK(12, 9)
1665 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON	GENMASK(16, 13)
1666 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME		BIT(17)
1667 
1668 struct hal_wbm_release_ring {
1669 	struct ath11k_buffer_addr buf_addr_info;
1670 	u32 info0;
1671 	u32 info1;
1672 	u32 info2;
1673 	struct hal_tx_rate_stats rate_stats;
1674 	u32 info3;
1675 } __packed;
1676 
1677 /* hal_wbm_release_ring
1678  *
1679  *	Producer: SW/TQM/RXDMA/REO/SWITCH
1680  *	Consumer: WBM/SW/FW
1681  *
1682  * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5
1683  * for software based completions.
1684  *
1685  * buf_addr_info
1686  *	Details of the physical address of the buffer or link descriptor.
1687  *
1688  * release_source_module
1689  *	Indicates which module initiated the release of this buffer/descriptor.
1690  *	Values are defined in enum %HAL_WBM_REL_SRC_MODULE_.
1691  *
1692  * bm_action
1693  *	Field only valid when the field return_buffer_manager in
1694  *	Released_buff_or_desc_addr_info indicates:
1695  *		WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST
1696  *	Values are defined in enum %HAL_WBM_REL_BM_ACT_.
1697  *
1698  * buffer_or_desc_type
1699  *	Field only valid when WBM is marked as the return_buffer_manager in
1700  *	the Released_Buffer_address_info. Indicates that type of buffer or
1701  *	descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE.
1702  *
1703  * first_msdu_index
1704  *	Field only valid for the bm_action release_msdu_list. The index of the
1705  *	first MSDU in an MSDU link descriptor all belonging to the same MPDU.
1706  *
1707  * tqm_release_reason
1708  *	Field only valid when Release_source_module is set to release_source_TQM
1709  *	Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_.
1710  *
1711  * rxdma_push_reason
1712  * reo_push_reason
1713  *	Indicates why rxdma/reo pushed the frame to this ring and values are
1714  *	defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
1715  *
1716  * rxdma_error_code
1717  *	Field only valid when 'rxdma_push_reason' set to 'error_detected'.
1718  *	Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
1719  *
1720  * reo_error_code
1721  *	Field only valid when 'reo_push_reason' set to 'error_detected'. Values
1722  *	are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
1723  *
1724  * wbm_internal_error
1725  *	Is set when WBM got a buffer pointer but the action was to push it to
1726  *	the idle link descriptor ring or do link related activity OR
1727  *	Is set when WBM got a link buffer pointer but the action was to push it
1728  *	to the buffer descriptor ring.
1729  *
1730  * tqm_status_number
1731  *	The value in this field is equal to tqm_cmd_number in TQM command. It is
1732  *	used to correlate the statu with TQM commands. Only valid when
1733  *	release_source_module is TQM.
1734  *
1735  * transmit_count
1736  *	The number of times the frame has been transmitted, valid only when
1737  *	release source in TQM.
1738  *
1739  * ack_frame_rssi
1740  *	This field is only valid when the source is TQM. If this frame is
1741  *	removed as the result of the reception of an ACK or BA, this field
1742  *	indicates the RSSI of the received ACK or BA frame.
1743  *
1744  * sw_release_details_valid
1745  *	This is set when WMB got a 'release_msdu_list' command from TQM and
1746  *	return buffer manager is not WMB. WBM will then de-aggregate all MSDUs
1747  *	and pass them one at a time on to the 'buffer owner'.
1748  *
1749  * first_msdu
1750  *	Field only valid when SW_release_details_valid is set.
1751  *	When set, this MSDU is the first MSDU pointed to in the
1752  *	'release_msdu_list' command.
1753  *
1754  * last_msdu
1755  *	Field only valid when SW_release_details_valid is set.
1756  *	When set, this MSDU is the last MSDU pointed to in the
1757  *	'release_msdu_list' command.
1758  *
1759  * msdu_part_of_amsdu
1760  *	Field only valid when SW_release_details_valid is set.
1761  *	When set, this MSDU was part of an A-MSDU in MPDU
1762  *
1763  * fw_tx_notify_frame
1764  *	Field only valid when SW_release_details_valid is set.
1765  *
1766  * buffer_timestamp
1767  *	Field only valid when SW_release_details_valid is set.
1768  *	This is the Buffer_timestamp field from the
1769  *	Timestamp in units of 1024 us
1770  *
1771  * struct hal_tx_rate_stats rate_stats
1772  *	Details for command execution tracking purposes.
1773  *
1774  * sw_peer_id
1775  * tid
1776  *	Field only valid when Release_source_module is set to
1777  *	release_source_TQM
1778  *
1779  *	1) Release of msdu buffer due to drop_frame = 1. Flow is
1780  *	not fetched and hence sw_peer_id and tid = 0
1781  *
1782  *	buffer_or_desc_type = e_num 0
1783  *	MSDU_rel_buffertqm_release_reason = e_num 1
1784  *	tqm_rr_rem_cmd_rem
1785  *
1786  *	2) Release of msdu buffer due to Flow is not fetched and
1787  *	hence sw_peer_id and tid = 0
1788  *
1789  *	buffer_or_desc_type = e_num 0
1790  *	MSDU_rel_buffertqm_release_reason = e_num 1
1791  *	tqm_rr_rem_cmd_rem
1792  *
1793  *	3) Release of msdu link due to remove_mpdu or acked_mpdu
1794  *	command.
1795  *
1796  *	buffer_or_desc_type = e_num1
1797  *	msdu_link_descriptortqm_release_reason can be:e_num 1
1798  *	tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
1799  *	e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
1800  *
1801  *	This field represents the TID from the TX_MSDU_FLOW
1802  *	descriptor or TX_MPDU_QUEUE descriptor
1803  *
1804  * rind_id
1805  *	For debugging.
1806  *	This field is filled in by the SRNG module.
1807  *	It help to identify the ring that is being looked
1808  *
1809  * looping_count
1810  *	A count value that indicates the number of times the
1811  *	producer of entries into the Buffer Manager Ring has looped
1812  *	around the ring.
1813  *
1814  *	At initialization time, this value is set to 0. On the
1815  *	first loop, this value is set to 1. After the max value is
1816  *	reached allowed by the number of bits for this field, the
1817  *	count value continues with 0 again.
1818  *
1819  *	In case SW is the consumer of the ring entries, it can
1820  *	use this field to figure out up to where the producer of
1821  *	entries has created new entries. This eliminates the need to
1822  *	check where the head pointer' of the ring is located once
1823  *	the SW starts processing an interrupt indicating that new
1824  *	entries have been put into this ring...
1825  *
1826  *	Also note that SW if it wants only needs to look at the
1827  *	LSB bit of this count value.
1828  */
1829 
1830 /**
1831  * enum hal_wbm_tqm_rel_reason - TQM release reason code
1832  * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame
1833  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW
1834  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus
1835  *	initiated by sw.
1836  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus
1837  *	initiated by sw.
1838  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or
1839  *	mpdus.
1840  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by
1841  *	fw with fw_reason1.
1842  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by
1843  *	fw with fw_reason2.
1844  * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by
1845  *	fw with fw_reason3.
1846  */
1847 enum hal_wbm_tqm_rel_reason {
1848 	HAL_WBM_TQM_REL_REASON_FRAME_ACKED,
1849 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU,
1850 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX,
1851 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX,
1852 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES,
1853 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1,
1854 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2,
1855 	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3,
1856 };
1857 
1858 struct hal_wbm_buffer_ring {
1859 	struct ath11k_buffer_addr buf_addr_info;
1860 };
1861 
1862 enum hal_desc_owner {
1863 	HAL_DESC_OWNER_WBM,
1864 	HAL_DESC_OWNER_SW,
1865 	HAL_DESC_OWNER_TQM,
1866 	HAL_DESC_OWNER_RXDMA,
1867 	HAL_DESC_OWNER_REO,
1868 	HAL_DESC_OWNER_SWITCH,
1869 };
1870 
1871 enum hal_desc_buf_type {
1872 	HAL_DESC_BUF_TYPE_TX_MSDU_LINK,
1873 	HAL_DESC_BUF_TYPE_TX_MPDU_LINK,
1874 	HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD,
1875 	HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT,
1876 	HAL_DESC_BUF_TYPE_TX_FLOW,
1877 	HAL_DESC_BUF_TYPE_TX_BUFFER,
1878 	HAL_DESC_BUF_TYPE_RX_MSDU_LINK,
1879 	HAL_DESC_BUF_TYPE_RX_MPDU_LINK,
1880 	HAL_DESC_BUF_TYPE_RX_REO_QUEUE,
1881 	HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT,
1882 	HAL_DESC_BUF_TYPE_RX_BUFFER,
1883 	HAL_DESC_BUF_TYPE_IDLE_LINK,
1884 };
1885 
1886 #define HAL_DESC_REO_OWNED		4
1887 #define HAL_DESC_REO_QUEUE_DESC		8
1888 #define HAL_DESC_REO_QUEUE_EXT_DESC	9
1889 #define HAL_DESC_REO_NON_QOS_TID	16
1890 
1891 #define HAL_DESC_HDR_INFO0_OWNER	GENMASK(3, 0)
1892 #define HAL_DESC_HDR_INFO0_BUF_TYPE	GENMASK(7, 4)
1893 #define HAL_DESC_HDR_INFO0_DBG_RESERVED	GENMASK(31, 8)
1894 
1895 struct hal_desc_header {
1896 	u32 info0;
1897 } __packed;
1898 
1899 struct hal_rx_mpdu_link_ptr {
1900 	struct ath11k_buffer_addr addr_info;
1901 } __packed;
1902 
1903 struct hal_rx_msdu_details {
1904 	struct ath11k_buffer_addr buf_addr_info;
1905 	struct rx_msdu_desc rx_msdu_info;
1906 } __packed;
1907 
1908 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER		GENMASK(15, 0)
1909 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK		BIT(16)
1910 
1911 struct hal_rx_msdu_link {
1912 	struct hal_desc_header desc_hdr;
1913 	struct ath11k_buffer_addr buf_addr_info;
1914 	u32 info0;
1915 	u32 pn[4];
1916 	struct hal_rx_msdu_details msdu_link[6];
1917 } __packed;
1918 
1919 struct hal_rx_reo_queue_ext {
1920 	struct hal_desc_header desc_hdr;
1921 	u32 rsvd;
1922 	struct hal_rx_mpdu_link_ptr mpdu_link[15];
1923 } __packed;
1924 
1925 /* hal_rx_reo_queue_ext
1926  *	Consumer: REO
1927  *	Producer: REO
1928  *
1929  * descriptor_header
1930  *	Details about which module owns this struct.
1931  *
1932  * mpdu_link
1933  *	Pointer to the next MPDU_link descriptor in the MPDU queue.
1934  */
1935 
1936 enum hal_rx_reo_queue_pn_size {
1937 	HAL_RX_REO_QUEUE_PN_SIZE_24,
1938 	HAL_RX_REO_QUEUE_PN_SIZE_48,
1939 	HAL_RX_REO_QUEUE_PN_SIZE_128,
1940 };
1941 
1942 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER		GENMASK(15, 0)
1943 
1944 #define HAL_RX_REO_QUEUE_INFO0_VLD			BIT(0)
1945 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER	GENMASK(2, 1)
1946 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION	BIT(3)
1947 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN		BIT(4)
1948 #define HAL_RX_REO_QUEUE_INFO0_AC			GENMASK(6, 5)
1949 #define HAL_RX_REO_QUEUE_INFO0_BAR			BIT(7)
1950 #define HAL_RX_REO_QUEUE_INFO0_RETRY			BIT(8)
1951 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE		BIT(9)
1952 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE			BIT(10)
1953 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE		GENMASK(18, 11)
1954 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK			BIT(19)
1955 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN			BIT(20)
1956 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN		BIT(21)
1957 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE		BIT(22)
1958 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE			GENMASK(24, 23)
1959 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG		BIT(25)
1960 
1961 #define HAL_RX_REO_QUEUE_INFO1_SVLD			BIT(0)
1962 #define HAL_RX_REO_QUEUE_INFO1_SSN			GENMASK(12, 1)
1963 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX		GENMASK(20, 13)
1964 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR		BIT(21)
1965 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR			BIT(22)
1966 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID			BIT(31)
1967 
1968 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT		GENMASK(6, 0)
1969 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT		(31, 7)
1970 
1971 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT		GENMASK(9, 4)
1972 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT	GENMASK(15, 10)
1973 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT		GENMASK(31, 16)
1974 
1975 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT	GENMASK(23, 0)
1976 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT		GENMASK(31, 24)
1977 
1978 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT	GENMASK(11, 0)
1979 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K		GENMASK(15, 12)
1980 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT		GENMASK(31, 16)
1981 
1982 struct hal_rx_reo_queue {
1983 	struct hal_desc_header desc_hdr;
1984 	u32 rx_queue_num;
1985 	u32 info0;
1986 	u32 info1;
1987 	u32 pn[4];
1988 	u32 last_rx_enqueue_timestamp;
1989 	u32 last_rx_dequeue_timestamp;
1990 	u32 next_aging_queue[2];
1991 	u32 prev_aging_queue[2];
1992 	u32 rx_bitmap[8];
1993 	u32 info2;
1994 	u32 info3;
1995 	u32 info4;
1996 	u32 processed_mpdus;
1997 	u32 processed_msdus;
1998 	u32 processed_total_bytes;
1999 	u32 info5;
2000 	u32 rsvd[3];
2001 	struct hal_rx_reo_queue_ext ext_desc[];
2002 } __packed;
2003 
2004 /* hal_rx_reo_queue
2005  *
2006  * descriptor_header
2007  *	Details about which module owns this struct. Note that sub field
2008  *	Buffer_type shall be set to receive_reo_queue_descriptor.
2009  *
2010  * receive_queue_number
2011  *	Indicates the MPDU queue ID to which this MPDU link descriptor belongs.
2012  *
2013  * vld
2014  *	Valid bit indicating a session is established and the queue descriptor
2015  *	is valid.
2016  * associated_link_descriptor_counter
2017  *	Indicates which of the 3 link descriptor counters shall be incremented
2018  *	or decremented when link descriptors are added or removed from this
2019  *	flow queue.
2020  * disable_duplicate_detection
2021  *	When set, do not perform any duplicate detection.
2022  * soft_reorder_enable
2023  *	When set, REO has been instructed to not perform the actual re-ordering
2024  *	of frames for this queue, but just to insert the reorder opcodes.
2025  * ac
2026  *	Indicates the access category of the queue descriptor.
2027  * bar
2028  *	Indicates if BAR has been received.
2029  * retry
2030  *	Retry bit is checked if this bit is set.
2031  * chk_2k_mode
2032  *	Indicates what type of operation is expected from Reo when the received
2033  *	frame SN falls within the 2K window.
2034  * oor_mode
2035  *	Indicates what type of operation is expected when the received frame
2036  *	falls within the OOR window.
2037  * ba_window_size
2038  *	Indicates the negotiated (window size + 1). Max of 256 bits.
2039  *
2040  *	A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
2041  *	session, with window size of 0). The 3 values here are the main values
2042  *	validated, but other values should work as well.
2043  *
2044  *	A BA window size of 0 (=> one frame entry bitmat), means that there is
2045  *	no additional rx_reo_queue_ext desc. following rx_reo_queue in memory.
2046  *	A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext.
2047  *	A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext.
2048  *	A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext.
2049  * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable,
2050  * pn_size
2051  *	REO shall perform the PN increment check, even number check, uneven
2052  *	number check, PN error check and size of the PN field check.
2053  * ignore_ampdu_flag
2054  *	REO shall ignore the ampdu_flag on entrance descriptor for this queue.
2055  *
2056  * svld
2057  *	Sequence number in next field is valid one.
2058  * ssn
2059  *	 Starting Sequence number of the session.
2060  * current_index
2061  *	Points to last forwarded packet
2062  * seq_2k_error_detected_flag
2063  *	REO has detected a 2k error jump in the sequence number and from that
2064  *	moment forward, all new frames are forwarded directly to FW, without
2065  *	duplicate detect, reordering, etc.
2066  * pn_error_detected_flag
2067  *	REO has detected a PN error.
2068  */
2069 
2070 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
2071 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM		BIT(8)
2072 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD			BIT(9)
2073 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT	BIT(10)
2074 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION	BIT(11)
2075 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN		BIT(12)
2076 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC			BIT(13)
2077 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR			BIT(14)
2078 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY			BIT(15)
2079 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE		BIT(16)
2080 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE			BIT(17)
2081 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE		BIT(18)
2082 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK			BIT(19)
2083 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN			BIT(20)
2084 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN		BIT(21)
2085 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE		BIT(22)
2086 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE			BIT(23)
2087 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG		BIT(24)
2088 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD			BIT(25)
2089 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN			BIT(26)
2090 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR		BIT(27)
2091 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR			BIT(28)
2092 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID			BIT(29)
2093 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN			BIT(30)
2094 
2095 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER		GENMASK(15, 0)
2096 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD				BIT(16)
2097 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER	GENMASK(18, 17)
2098 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION		BIT(19)
2099 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN		BIT(20)
2100 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC				GENMASK(22, 21)
2101 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR				BIT(23)
2102 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY			BIT(24)
2103 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE		BIT(25)
2104 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE			BIT(26)
2105 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK			BIT(27)
2106 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN			BIT(28)
2107 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN			BIT(29)
2108 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE		BIT(30)
2109 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG		BIT(31)
2110 
2111 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE		GENMASK(7, 0)
2112 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE			GENMASK(9, 8)
2113 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD				BIT(10)
2114 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN				GENMASK(22, 11)
2115 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR			BIT(23)
2116 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR			BIT(24)
2117 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID			BIT(25)
2118 
2119 struct hal_reo_update_rx_queue {
2120 	struct hal_reo_cmd_hdr cmd;
2121 	u32 queue_addr_lo;
2122 	u32 info0;
2123 	u32 info1;
2124 	u32 info2;
2125 	u32 pn[4];
2126 } __packed;
2127 
2128 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE		BIT(0)
2129 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX	GENMASK(2, 1)
2130 
2131 struct hal_reo_unblock_cache {
2132 	struct hal_reo_cmd_hdr cmd;
2133 	u32 info0;
2134 	u32 rsvd[7];
2135 } __packed;
2136 
2137 enum hal_reo_exec_status {
2138 	HAL_REO_EXEC_STATUS_SUCCESS,
2139 	HAL_REO_EXEC_STATUS_BLOCKED,
2140 	HAL_REO_EXEC_STATUS_FAILED,
2141 	HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED,
2142 };
2143 
2144 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM	GENMASK(15, 0)
2145 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME	GENMASK(25, 16)
2146 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS	GENMASK(27, 26)
2147 
2148 struct hal_reo_status_hdr {
2149 	u32 info0;
2150 	u32 timestamp;
2151 } __packed;
2152 
2153 /* hal_reo_status_hdr
2154  *		Producer: REO
2155  *		Consumer: SW
2156  *
2157  * status_num
2158  *		The value in this field is equal to value of the reo command
2159  *		number. This field helps to correlate the statuses with the REO
2160  *		commands.
2161  *
2162  * execution_time (in us)
2163  *		The amount of time REO took to execute the command. Note that
2164  *		this time does not include the duration of the command waiting
2165  *		in the command ring, before the execution started.
2166  *
2167  * execution_status
2168  *		Execution status of the command. Values are defined in
2169  *		enum %HAL_REO_EXEC_STATUS_.
2170  */
2171 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN		GENMASK(11, 0)
2172 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX		GENMASK(19, 12)
2173 
2174 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT		GENMASK(6, 0)
2175 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT		GENMASK(31, 7)
2176 
2177 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT	GENMASK(9, 4)
2178 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT		GENMASK(15, 10)
2179 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT	GENMASK(31, 16)
2180 
2181 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT		GENMASK(23, 0)
2182 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT	GENMASK(31, 24)
2183 
2184 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU	GENMASK(11, 0)
2185 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K	GENMASK(15, 12)
2186 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT		GENMASK(31, 16)
2187 
2188 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT	GENMASK(31, 28)
2189 
2190 struct hal_reo_get_queue_stats_status {
2191 	struct hal_reo_status_hdr hdr;
2192 	u32 info0;
2193 	u32 pn[4];
2194 	u32 last_rx_enqueue_timestamp;
2195 	u32 last_rx_dequeue_timestamp;
2196 	u32 rx_bitmap[8];
2197 	u32 info1;
2198 	u32 info2;
2199 	u32 info3;
2200 	u32 num_mpdu_frames;
2201 	u32 num_msdu_frames;
2202 	u32 total_bytes;
2203 	u32 info4;
2204 	u32 info5;
2205 } __packed;
2206 
2207 /* hal_reo_get_queue_stats_status
2208  *		Producer: REO
2209  *		Consumer: SW
2210  *
2211  * status_hdr
2212  *		Details that can link this status with the original command. It
2213  *		also contains info on how long REO took to execute this command.
2214  *
2215  * ssn
2216  *		Starting Sequence number of the session, this changes whenever
2217  *		window moves (can be filled by SW then maintained by REO).
2218  *
2219  * current_index
2220  *		Points to last forwarded packet.
2221  *
2222  * pn
2223  *		Bits of the PN number.
2224  *
2225  * last_rx_enqueue_timestamp
2226  * last_rx_dequeue_timestamp
2227  *		Timestamp of arrival of the last MPDU for this queue and
2228  *		Timestamp of forwarding an MPDU accordingly.
2229  *
2230  * rx_bitmap
2231  *		When a bit is set, the corresponding frame is currently held
2232  *		in the re-order queue. The bitmap  is Fully managed by HW.
2233  *
2234  * current_mpdu_count
2235  * current_msdu_count
2236  *		The number of MPDUs and MSDUs in the queue.
2237  *
2238  * timeout_count
2239  *		The number of times REO started forwarding frames even though
2240  *		there is a hole in the bitmap. Forwarding reason is timeout.
2241  *
2242  * forward_due_to_bar_count
2243  *		The number of times REO started forwarding frames even though
2244  *		there is a hole in the bitmap. Fwd reason is reception of BAR.
2245  *
2246  * duplicate_count
2247  *		The number of duplicate frames that have been detected.
2248  *
2249  * frames_in_order_count
2250  *		The number of frames that have been received in order (without
2251  *		a hole that prevented them from being forwarded immediately).
2252  *
2253  * bar_received_count
2254  *		The number of times a BAR frame is received.
2255  *
2256  * mpdu_frames_processed_count
2257  * msdu_frames_processed_count
2258  *		The total number of MPDU/MSDU frames that have been processed.
2259  *
2260  * total_bytes
2261  *		An approximation of the number of bytes received for this queue.
2262  *
2263  * late_receive_mpdu_count
2264  *		The number of MPDUs received after the window had already moved
2265  *		on. The 'late' sequence window is defined as
2266  *		(Window SSN - 256) - (Window SSN - 1).
2267  *
2268  * window_jump_2k
2269  *		The number of times the window moved more than 2K
2270  *
2271  * hole_count
2272  *		The number of times a hole was created in the receive bitmap.
2273  *
2274  * looping_count
2275  *		A count value that indicates the number of times the producer of
2276  *		entries into this Ring has looped around the ring.
2277  */
2278 
2279 #define HAL_REO_STATUS_LOOP_CNT			GENMASK(31, 28)
2280 
2281 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED	BIT(0)
2282 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD		GENMASK(31, 1)
2283 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD		GENMASK(27, 0)
2284 
2285 struct hal_reo_flush_queue_status {
2286 	struct hal_reo_status_hdr hdr;
2287 	u32 info0;
2288 	u32 rsvd0[21];
2289 	u32 info1;
2290 } __packed;
2291 
2292 /* hal_reo_flush_queue_status
2293  *		Producer: REO
2294  *		Consumer: SW
2295  *
2296  * status_hdr
2297  *		Details that can link this status with the original command. It
2298  *		also contains info on how long REO took to execute this command.
2299  *
2300  * error_detected
2301  *		Status of blocking resource
2302  *
2303  *		0 - No error has been detected while executing this command
2304  *		1 - Error detected. The resource to be used for blocking was
2305  *		    already in use.
2306  *
2307  * looping_count
2308  *		A count value that indicates the number of times the producer of
2309  *		entries into this Ring has looped around the ring.
2310  */
2311 
2312 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR			BIT(0)
2313 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE		GENMASK(2, 1)
2314 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT	BIT(8)
2315 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE	GENMASK(11, 9)
2316 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID	GENMASK(15, 12)
2317 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR		GENMASK(17, 16)
2318 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT		GENMASK(25, 18)
2319 
2320 struct hal_reo_flush_cache_status {
2321 	struct hal_reo_status_hdr hdr;
2322 	u32 info0;
2323 	u32 rsvd0[21];
2324 	u32 info1;
2325 } __packed;
2326 
2327 /* hal_reo_flush_cache_status
2328  *		Producer: REO
2329  *		Consumer: SW
2330  *
2331  * status_hdr
2332  *		Details that can link this status with the original command. It
2333  *		also contains info on how long REO took to execute this command.
2334  *
2335  * error_detected
2336  *		Status for blocking resource handling
2337  *
2338  *		0 - No error has been detected while executing this command
2339  *		1 - An error in the blocking resource management was detected
2340  *
2341  * block_error_details
2342  *		only valid when error_detected is set
2343  *
2344  *		0 - No blocking related errors found
2345  *		1 - Blocking resource is already in use
2346  *		2 - Resource requested to be unblocked, was not blocked
2347  *
2348  * cache_controller_flush_status_hit
2349  *		The status that the cache controller returned on executing the
2350  *		flush command.
2351  *
2352  *		0 - miss; 1 - hit
2353  *
2354  * cache_controller_flush_status_desc_type
2355  *		Flush descriptor type
2356  *
2357  * cache_controller_flush_status_client_id
2358  *		Module who made the flush request
2359  *
2360  *		In REO, this is always 0
2361  *
2362  * cache_controller_flush_status_error
2363  *		Error condition
2364  *
2365  *		0 - No error found
2366  *		1 - HW interface is still busy
2367  *		2 - Line currently locked. Used for one line flush command
2368  *		3 - At least one line is still locked.
2369  *		    Used for cache flush command.
2370  *
2371  * cache_controller_flush_count
2372  *		The number of lines that were actually flushed out
2373  *
2374  * looping_count
2375  *		A count value that indicates the number of times the producer of
2376  *		entries into this Ring has looped around the ring.
2377  */
2378 
2379 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR	BIT(0)
2380 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE		BIT(1)
2381 
2382 struct hal_reo_unblock_cache_status {
2383 	struct hal_reo_status_hdr hdr;
2384 	u32 info0;
2385 	u32 rsvd0[21];
2386 	u32 info1;
2387 } __packed;
2388 
2389 /* hal_reo_unblock_cache_status
2390  *		Producer: REO
2391  *		Consumer: SW
2392  *
2393  * status_hdr
2394  *		Details that can link this status with the original command. It
2395  *		also contains info on how long REO took to execute this command.
2396  *
2397  * error_detected
2398  *		0 - No error has been detected while executing this command
2399  *		1 - The blocking resource was not in use, and therefore it could
2400  *		    not be unblocked.
2401  *
2402  * unblock_type
2403  *		Reference to the type of unblock command
2404  *		0 - Unblock a blocking resource
2405  *		1 - The entire cache usage is unblock
2406  *
2407  * looping_count
2408  *		A count value that indicates the number of times the producer of
2409  *		entries into this Ring has looped around the ring.
2410  */
2411 
2412 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR		BIT(0)
2413 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY		BIT(1)
2414 
2415 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT	GENMASK(15, 0)
2416 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT	GENMASK(31, 16)
2417 
2418 struct hal_reo_flush_timeout_list_status {
2419 	struct hal_reo_status_hdr hdr;
2420 	u32 info0;
2421 	u32 info1;
2422 	u32 rsvd0[20];
2423 	u32 info2;
2424 } __packed;
2425 
2426 /* hal_reo_flush_timeout_list_status
2427  *		Producer: REO
2428  *		Consumer: SW
2429  *
2430  * status_hdr
2431  *		Details that can link this status with the original command. It
2432  *		also contains info on how long REO took to execute this command.
2433  *
2434  * error_detected
2435  *		0 - No error has been detected while executing this command
2436  *		1 - Command not properly executed and returned with error
2437  *
2438  * timeout_list_empty
2439  *		When set, REO has depleted the timeout list and all entries are
2440  *		gone.
2441  *
2442  * release_desc_count
2443  *		Producer: SW; Consumer: REO
2444  *		The number of link descriptor released
2445  *
2446  * forward_buf_count
2447  *		Producer: SW; Consumer: REO
2448  *		The number of buffers forwarded to the REO destination rings
2449  *
2450  * looping_count
2451  *		A count value that indicates the number of times the producer of
2452  *		entries into this Ring has looped around the ring.
2453  */
2454 
2455 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX		GENMASK(1, 0)
2456 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0	GENMASK(23, 0)
2457 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1	GENMASK(23, 0)
2458 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2	GENMASK(23, 0)
2459 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM	GENMASK(25, 0)
2460 
2461 struct hal_reo_desc_thresh_reached_status {
2462 	struct hal_reo_status_hdr hdr;
2463 	u32 info0;
2464 	u32 info1;
2465 	u32 info2;
2466 	u32 info3;
2467 	u32 info4;
2468 	u32 rsvd0[17];
2469 	u32 info5;
2470 } __packed;
2471 
2472 /* hal_reo_desc_thresh_reached_status
2473  *		Producer: REO
2474  *		Consumer: SW
2475  *
2476  * status_hdr
2477  *		Details that can link this status with the original command. It
2478  *		also contains info on how long REO took to execute this command.
2479  *
2480  * threshold_index
2481  *		The index of the threshold register whose value got reached
2482  *
2483  * link_descriptor_counter0
2484  * link_descriptor_counter1
2485  * link_descriptor_counter2
2486  * link_descriptor_counter_sum
2487  *		Value of the respective counters at generation of this message
2488  *
2489  * looping_count
2490  *		A count value that indicates the number of times the producer of
2491  *		entries into this Ring has looped around the ring.
2492  */
2493 
2494 #endif /* ATH11K_HAL_DESC_H */
2495