1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 */
6
7 #include <linux/err.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/gpio/generic.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14
15 #define MTK_BANK_CNT 3
16 #define MTK_BANK_WIDTH 32
17
18 #define GPIO_BANK_STRIDE 0x04
19 #define GPIO_REG_CTRL 0x00
20 #define GPIO_REG_POL 0x10
21 #define GPIO_REG_DATA 0x20
22 #define GPIO_REG_DSET 0x30
23 #define GPIO_REG_DCLR 0x40
24 #define GPIO_REG_REDGE 0x50
25 #define GPIO_REG_FEDGE 0x60
26 #define GPIO_REG_HLVL 0x70
27 #define GPIO_REG_LLVL 0x80
28 #define GPIO_REG_STAT 0x90
29 #define GPIO_REG_EDGE 0xA0
30
31 struct mtk_gc {
32 struct gpio_generic_chip chip;
33 struct mtk *parent_priv;
34 int bank;
35 u32 rising;
36 u32 falling;
37 u32 hlevel;
38 u32 llevel;
39 };
40
41 /**
42 * struct mtk - state container for
43 * data of the platform driver. It is 3
44 * separate gpio-chip having an IRQ
45 * linear domain shared for all of them
46 * @pdev: platform device instance
47 * @base: memory base address
48 * @irq_domain: IRQ linear domain shared across the three gpio chips
49 * @gpio_irq: irq number from the device tree
50 * @num_gpios: total number of gpio pins on the three gpio chips
51 * @gc_map: array of the gpio chips
52 */
53 struct mtk {
54 struct platform_device *pdev;
55 void __iomem *base;
56 struct irq_domain *irq_domain;
57 int gpio_irq;
58 int num_gpios;
59 struct mtk_gc gc_map[MTK_BANK_CNT];
60 };
61
62 static inline struct mtk *
mt7621_gpio_gc_to_priv(struct gpio_chip * gc)63 mt7621_gpio_gc_to_priv(struct gpio_chip *gc)
64 {
65 struct mtk_gc *bank = gpiochip_get_data(gc);
66
67 return bank->parent_priv;
68 }
69
70 static inline struct mtk_gc *
to_mt7621_gpio(struct gpio_chip * chip)71 to_mt7621_gpio(struct gpio_chip *chip)
72 {
73 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(chip);
74
75 return container_of(gen_gc, struct mtk_gc, chip);
76 }
77
78 static inline void
mtk_gpio_w32(struct mtk_gc * rg,u32 offset,u32 val)79 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
80 {
81 struct gpio_chip *gc = &rg->chip.gc;
82 struct mtk *mtk = mt7621_gpio_gc_to_priv(gc);
83
84 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
85 gpio_generic_write_reg(&rg->chip, mtk->base + offset, val);
86 }
87
88 static inline u32
mtk_gpio_r32(struct mtk_gc * rg,u32 offset)89 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
90 {
91 struct gpio_chip *gc = &rg->chip.gc;
92 struct mtk *mtk = mt7621_gpio_gc_to_priv(gc);
93
94 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
95 return gpio_generic_read_reg(&rg->chip, mtk->base + offset);
96 }
97
98 static void
mt7621_gpio_irq_bank_handler(struct mtk_gc * bank)99 mt7621_gpio_irq_bank_handler(struct mtk_gc *bank)
100 {
101 struct mtk *priv = bank->parent_priv;
102 struct irq_domain *domain = priv->irq_domain;
103 int hwbase = bank->chip.gc.offset;
104 unsigned long pending;
105 unsigned int offset;
106
107 pending = mtk_gpio_r32(bank, GPIO_REG_STAT);
108 if (!pending)
109 return;
110
111 mtk_gpio_w32(bank, GPIO_REG_STAT, pending);
112
113 for_each_set_bit(offset, &pending, MTK_BANK_WIDTH)
114 generic_handle_domain_irq(domain, hwbase + offset);
115 }
116
117 static void
mt7621_gpio_irq_handler(struct irq_desc * desc)118 mt7621_gpio_irq_handler(struct irq_desc *desc)
119 {
120 struct mtk *priv = irq_desc_get_handler_data(desc);
121 struct irq_chip *chip = irq_desc_get_chip(desc);
122 int i;
123
124 chained_irq_enter(chip, desc);
125 for (i = 0; i < MTK_BANK_CNT; i++) {
126 struct mtk_gc *bank = &priv->gc_map[i];
127
128 mt7621_gpio_irq_bank_handler(bank);
129 }
130 chained_irq_exit(chip, desc);
131 }
132
133 static int
mt7621_gpio_hwirq_to_offset(irq_hw_number_t hwirq,struct mtk_gc * bank)134 mt7621_gpio_hwirq_to_offset(irq_hw_number_t hwirq, struct mtk_gc *bank)
135 {
136 return hwirq - bank->chip.gc.offset;
137 }
138
139 static void
mt7621_gpio_irq_unmask(struct irq_data * d)140 mt7621_gpio_irq_unmask(struct irq_data *d)
141 {
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct mtk_gc *rg = gpiochip_get_data(gc);
144 u32 mask = mt7621_gpio_hwirq_to_offset(d->hwirq, rg);
145 u32 rise, fall, high, low;
146
147 gpiochip_enable_irq(gc, mask);
148
149 guard(gpio_generic_lock_irqsave)(&rg->chip);
150
151 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
152 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
153 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
154 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
155 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(mask) & rg->rising));
156 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(mask) & rg->falling));
157 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(mask) & rg->hlevel));
158 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(mask) & rg->llevel));
159 }
160
161 static void
mt7621_gpio_irq_mask(struct irq_data * d)162 mt7621_gpio_irq_mask(struct irq_data *d)
163 {
164 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
165 struct mtk_gc *rg = gpiochip_get_data(gc);
166 u32 mask = mt7621_gpio_hwirq_to_offset(d->hwirq, rg);
167 u32 rise, fall, high, low;
168
169 scoped_guard(gpio_generic_lock_irqsave, &rg->chip) {
170 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
171 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
172 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
173 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
174 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(mask));
175 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(mask));
176 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(mask));
177 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(mask));
178 }
179
180 gpiochip_disable_irq(gc, mask);
181 }
182
183 static int
mt7621_gpio_irq_type(struct irq_data * d,unsigned int type)184 mt7621_gpio_irq_type(struct irq_data *d, unsigned int type)
185 {
186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
187 struct mtk_gc *rg = gpiochip_get_data(gc);
188 u32 mask = BIT(mt7621_gpio_hwirq_to_offset(d->hwirq, rg));
189
190 guard(gpio_generic_lock_irqsave)(&rg->chip);
191
192 if (type == IRQ_TYPE_PROBE) {
193 if ((rg->rising | rg->falling |
194 rg->hlevel | rg->llevel) & mask)
195 return 0;
196
197 type = IRQ_TYPE_EDGE_BOTH;
198 }
199
200 rg->rising &= ~mask;
201 rg->falling &= ~mask;
202 rg->hlevel &= ~mask;
203 rg->llevel &= ~mask;
204
205 switch (type & IRQ_TYPE_SENSE_MASK) {
206 case IRQ_TYPE_EDGE_BOTH:
207 rg->rising |= mask;
208 rg->falling |= mask;
209 break;
210 case IRQ_TYPE_EDGE_RISING:
211 rg->rising |= mask;
212 break;
213 case IRQ_TYPE_EDGE_FALLING:
214 rg->falling |= mask;
215 break;
216 case IRQ_TYPE_LEVEL_HIGH:
217 rg->hlevel |= mask;
218 break;
219 case IRQ_TYPE_LEVEL_LOW:
220 rg->llevel |= mask;
221 break;
222 }
223
224 return 0;
225 }
226
227 static int
mt7621_gpio_irq_reqres(struct irq_data * d)228 mt7621_gpio_irq_reqres(struct irq_data *d)
229 {
230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
231 struct mtk_gc *rg = gpiochip_get_data(gc);
232 unsigned int irq = mt7621_gpio_hwirq_to_offset(d->hwirq, rg);
233
234 return gpiochip_reqres_irq(gc, irq);
235 }
236
237 static void
mt7621_gpio_irq_relres(struct irq_data * d)238 mt7621_gpio_irq_relres(struct irq_data *d)
239 {
240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
241 struct mtk_gc *rg = gpiochip_get_data(gc);
242 unsigned int irq = mt7621_gpio_hwirq_to_offset(d->hwirq, rg);
243
244 gpiochip_relres_irq(gc, irq);
245 }
246
247 static int
mt7621_gpio_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)248 mt7621_gpio_xlate(struct gpio_chip *chip,
249 const struct of_phandle_args *spec, u32 *flags)
250 {
251 int gpio = spec->args[0];
252 struct mtk_gc *rg = to_mt7621_gpio(chip);
253
254 if (rg->bank != gpio / MTK_BANK_WIDTH)
255 return -EINVAL;
256
257 if (flags)
258 *flags = spec->args[1];
259
260 return gpio % MTK_BANK_WIDTH;
261 }
262
263 static const struct irq_chip mt7621_irq_chip = {
264 .name = "mt7621-gpio",
265 .irq_request_resources = mt7621_gpio_irq_reqres,
266 .irq_release_resources = mt7621_gpio_irq_relres,
267 .irq_mask_ack = mt7621_gpio_irq_mask,
268 .irq_mask = mt7621_gpio_irq_mask,
269 .irq_unmask = mt7621_gpio_irq_unmask,
270 .irq_set_type = mt7621_gpio_irq_type,
271 .flags = IRQCHIP_IMMUTABLE,
272 };
273
274 static void
mt7621_gpio_remove(void * data)275 mt7621_gpio_remove(void *data)
276 {
277 struct mtk *priv = data;
278 int offset, virq;
279
280 if (priv->gpio_irq > 0)
281 irq_set_chained_handler_and_data(priv->gpio_irq, NULL, NULL);
282
283 /* Remove all IRQ mappings and delete the domain */
284 if (priv->irq_domain) {
285 for (offset = 0; offset < priv->num_gpios; offset++) {
286 virq = irq_find_mapping(priv->irq_domain, offset);
287 irq_dispose_mapping(virq);
288 }
289 irq_domain_remove(priv->irq_domain);
290 }
291 }
292
293 static struct mtk_gc *
mt7621_gpio_hwirq_to_bank(struct mtk * priv,irq_hw_number_t hwirq)294 mt7621_gpio_hwirq_to_bank(struct mtk *priv, irq_hw_number_t hwirq)
295 {
296 int i;
297
298 for (i = 0; i < MTK_BANK_CNT; i++) {
299 struct mtk_gc *bank = &priv->gc_map[i];
300
301 if (hwirq >= bank->chip.gc.offset &&
302 hwirq < (bank->chip.gc.offset + bank->chip.gc.ngpio))
303 return bank;
304 }
305
306 return NULL;
307 }
308
309 static int
mt7621_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)310 mt7621_gpio_irq_map(struct irq_domain *d, unsigned int irq,
311 irq_hw_number_t hwirq)
312 {
313 struct mtk *priv = d->host_data;
314 struct mtk_gc *bank = mt7621_gpio_hwirq_to_bank(priv, hwirq);
315 struct platform_device *pdev = priv->pdev;
316 int ret;
317
318 if (!bank)
319 return -EINVAL;
320
321 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
322 irq, (int)hwirq, bank->bank);
323
324 ret = irq_set_chip_data(irq, &bank->chip.gc);
325 if (ret < 0)
326 return ret;
327
328 irq_set_chip_and_handler(irq, &mt7621_irq_chip, handle_simple_irq);
329 irq_set_noprobe(irq);
330
331 return 0;
332 }
333
334 static void
mt7621_gpio_irq_unmap(struct irq_domain * d,unsigned int irq)335 mt7621_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
336 {
337 irq_set_chip_and_handler(irq, NULL, NULL);
338 irq_set_chip_data(irq, NULL);
339 }
340
341 static const struct irq_domain_ops mt7621_gpio_irq_domain_ops = {
342 .map = mt7621_gpio_irq_map,
343 .unmap = mt7621_gpio_irq_unmap,
344 .xlate = irq_domain_xlate_twocell,
345 };
346
347 static int
mt7621_gpio_irq_setup(struct platform_device * pdev,struct mtk * priv)348 mt7621_gpio_irq_setup(struct platform_device *pdev,
349 struct mtk *priv)
350 {
351 struct device *dev = &pdev->dev;
352
353 priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
354 priv->num_gpios,
355 &mt7621_gpio_irq_domain_ops,
356 priv);
357 if (!priv->irq_domain) {
358 dev_err(dev, "Couldn't allocate IRQ domain\n");
359 return -ENXIO;
360 }
361
362 irq_set_chained_handler_and_data(priv->gpio_irq,
363 mt7621_gpio_irq_handler, priv);
364 irq_set_status_flags(priv->gpio_irq, IRQ_DISABLE_UNLAZY);
365
366 return 0;
367 }
368
369 static int
mt7621_gpio_to_irq(struct gpio_chip * gc,unsigned int offset)370 mt7621_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
371 {
372 struct mtk *priv = mt7621_gpio_gc_to_priv(gc);
373 /* gc_offset is relative to this gpio_chip; want real offset */
374 int hwirq = offset + gc->offset;
375
376 if (hwirq >= priv->num_gpios)
377 return -ENXIO;
378
379 return irq_create_mapping(priv->irq_domain, hwirq);
380 }
381
382 static int
mt7621_gpio_bank_probe(struct device * dev,int bank)383 mt7621_gpio_bank_probe(struct device *dev, int bank)
384 {
385 struct gpio_generic_chip_config config;
386 struct mtk *mtk = dev_get_drvdata(dev);
387 struct mtk_gc *rg;
388 void __iomem *dat, *set, *ctrl, *diro;
389 int ret;
390
391 rg = &mtk->gc_map[bank];
392 memset(rg, 0, sizeof(*rg));
393
394 rg->parent_priv = mtk;
395 rg->bank = bank;
396
397 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
398 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
399 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
400 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
401
402 config = (struct gpio_generic_chip_config) {
403 .dev = dev,
404 .sz = 4,
405 .dat = dat,
406 .set = set,
407 .clr = ctrl,
408 .dirout = diro,
409 .flags = GPIO_GENERIC_NO_SET_ON_INPUT,
410 };
411
412 ret = gpio_generic_chip_init(&rg->chip, &config);
413 if (ret) {
414 dev_err(dev, "failed to initialize generic GPIO chip\n");
415 return ret;
416 }
417
418 rg->chip.gc.of_gpio_n_cells = 2;
419 rg->chip.gc.of_xlate = mt7621_gpio_xlate;
420 rg->chip.gc.ngpio = MTK_BANK_WIDTH;
421 rg->chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
422 dev_name(dev), bank);
423 if (!rg->chip.gc.label)
424 return -ENOMEM;
425
426 rg->chip.gc.offset = bank * MTK_BANK_WIDTH;
427 if (mtk->gpio_irq > 0)
428 rg->chip.gc.to_irq = mt7621_gpio_to_irq;
429
430 ret = devm_gpiochip_add_data(dev, &rg->chip.gc, rg);
431 if (ret < 0) {
432 dev_err(dev, "Could not register gpio %d, ret=%d\n",
433 rg->chip.gc.ngpio, ret);
434 return ret;
435 }
436
437 /* set polarity to low for all gpios */
438 mtk_gpio_w32(rg, GPIO_REG_POL, 0);
439
440 dev_info(dev, "registering %d gpios\n", rg->chip.gc.ngpio);
441
442 return 0;
443 }
444
445 static int
mt7621_gpio_probe(struct platform_device * pdev)446 mt7621_gpio_probe(struct platform_device *pdev)
447 {
448 struct device *dev = &pdev->dev;
449 struct mtk *mtk;
450 int i;
451 int ret;
452
453 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
454 if (!mtk)
455 return -ENOMEM;
456
457 mtk->base = devm_platform_ioremap_resource(pdev, 0);
458 if (IS_ERR(mtk->base))
459 return PTR_ERR(mtk->base);
460
461 mtk->gpio_irq = platform_get_irq(pdev, 0);
462 if (mtk->gpio_irq < 0)
463 return mtk->gpio_irq;
464
465 mtk->pdev = pdev;
466 mtk->num_gpios = MTK_BANK_WIDTH * MTK_BANK_CNT;
467 platform_set_drvdata(pdev, mtk);
468
469 if (mtk->gpio_irq > 0) {
470 ret = mt7621_gpio_irq_setup(pdev, mtk);
471 if (ret)
472 return ret;
473 }
474
475 ret = devm_add_action_or_reset(dev, mt7621_gpio_remove, mtk);
476 if (ret)
477 return ret;
478
479 for (i = 0; i < MTK_BANK_CNT; i++) {
480 ret = mt7621_gpio_bank_probe(dev, i);
481 if (ret)
482 return ret;
483 }
484
485 return 0;
486 }
487
488 static const struct of_device_id mt7621_gpio_match[] = {
489 { .compatible = "mediatek,mt7621-gpio" },
490 {},
491 };
492 MODULE_DEVICE_TABLE(of, mt7621_gpio_match);
493
494 static struct platform_driver mt7621_gpio_driver = {
495 .probe = mt7621_gpio_probe,
496 .driver = {
497 .name = "mt7621_gpio",
498 .of_match_table = mt7621_gpio_match,
499 },
500 };
501
502 builtin_platform_driver(mt7621_gpio_driver);
503