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Searched refs:GET_WIDTH (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/renesas/
H A Dr9a09g077-cpg.c50 #define GET_WIDTH(val) FIELD_GET(WIDTH_MASK, val) macro
398 GET_WIDTH(core->conf), in r9a09g077_cpg_div_clk_register()
408 GET_WIDTH(core->conf), in r9a09g077_cpg_div_clk_register()
429 GET_WIDTH(core->conf), in r9a09g077_cpg_mux_clk_register()
568 div->width = GET_WIDTH(core->conf); in r9a09g077_cpg_fselxspi_div_clk_register()
780 val &= ~(clk_div_mask(GET_WIDTH(dsi_div->conf)) << shift); in r9a09g077_cpg_lcdc_div_set_rate()
796 div &= clk_div_mask(GET_WIDTH(dsi_div->conf)); in r9a09g077_cpg_lcdc_div_recalc_rate()
H A Drzg2l-cpg.c47 #define GET_WIDTH(val) ((val >> 8) & 0xf) macro
210 u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf); in rzg2l_cpg_wait_clk_update_done()
282 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); in rzg3s_cpg_div_clk_notifier()
334 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); in rzg3s_div_clk_recalc_rate()
462 GET_WIDTH(core->conf), in rzg2l_cpg_div_clk_register()
471 GET_WIDTH(core->conf), in rzg2l_cpg_div_clk_register()
491 GET_WIDTH(core->conf), in rzg2l_cpg_mux_clk_register()
536 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); in rzg2l_cpg_sd_clk_mux_get_parent()