Searched refs:GET_SHIFT (Results 1 – 2 of 2) sorted by relevance
49 #define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val) macro397 GET_SHIFT(core->conf), in r9a09g077_cpg_div_clk_register()407 GET_SHIFT(core->conf), in r9a09g077_cpg_div_clk_register()428 GET_SHIFT(core->conf), in r9a09g077_cpg_mux_clk_register()567 div->shift = GET_SHIFT(core->conf); in r9a09g077_cpg_fselxspi_div_clk_register()778 shift = GET_SHIFT(dsi_div->conf); in r9a09g077_cpg_lcdc_div_set_rate()795 div >>= GET_SHIFT(dsi_div->conf); in r9a09g077_cpg_lcdc_div_recalc_rate()
46 #define GET_SHIFT(val) ((val >> 12) & 0xff) macro210 u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf); in rzg2l_cpg_wait_clk_update_done()225 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_notifier()269 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg3s_cpg_div_clk_notifier()333 val >>= GET_SHIFT(clk_hw_data->conf); in rzg3s_div_clk_recalc_rate()359 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg3s_div_clk_set_rate()461 GET_SHIFT(core->conf), in rzg2l_cpg_div_clk_register()470 GET_SHIFT(core->conf), in rzg2l_cpg_div_clk_register()490 GET_SHIFT(core->conf), in rzg2l_cpg_mux_clk_register()505 u32 shift = GET_SHIFT(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_set_parent()[all …]