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Searched refs:GENMASK_ULL (Results 1 – 25 of 206) sorted by relevance

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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h194 #define EVTREG_ID GENMASK_ULL(8, 3)
201 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
206 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
207 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
212 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
217 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
222 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
227 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
228 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
252 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
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H A Dnpc.h438 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
444 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)
447 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
448 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
449 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)
452 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
456 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
458 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
460 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
462 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
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H A Dcgx.h25 #define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)
52 #define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)
54 #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
59 #define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32)
60 #define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24)
86 #define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32)
/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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/linux/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h46 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
50 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
56 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
61 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
62 #define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
74 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
75 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
78 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
80 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(5
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/linux/drivers/mmc/host/
H A Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
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/linux/arch/x86/include/asm/
H A Dsev-common.h60 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0)
65 #define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0)
74 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
81 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
100 ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \
104 #define GHCB_MSR_PSC_REQ_TO_GFN(msr) (((msr) & GENMASK_ULL(51, 12)) >> 12)
105 #define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52)
110 (((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
119 ((((u64)(v) & GENMASK_ULL(7, 0)) << 32) | \
126 (((u64)(v) & GENMASK_ULL(63, 32)) >> 32)
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/linux/include/linux/irqchip/
H A Darm-gic-v5.h22 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
170 #define GICV5_IRS_IST_BASER_ADDR_MASK GENMASK_ULL(55, 6)
177 #define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12)
221 #define GICV5_ITS_DT_BASER_ADDR_MASK GENMASK_ULL(55, 3)
227 #define GICV5_ITS_DIDR_DEVICEID GENMASK_ULL(31, 0)
239 #define GICV5_ITS_SYNCR_DEVICEID GENMASK_ULL(31, 0)
245 #define GICV5_DTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)
246 #define GICV5_DTL1E_SPAN GENMASK_ULL(63, 60)
249 #define GICV5_DTL2E_ITT_L2SZ GENMASK_ULL(2, 1)
251 #define GICV5_DTL2E_ITT_ADDR_MASK GENMASK_ULL(5
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/linux/drivers/gpu/drm/xe/regs/
H A Dxe_mchbar_regs.h22 #define PKG_TDP GENMASK_ULL(14, 0)
23 #define PKG_MIN_PWR GENMASK_ULL(30, 16)
24 #define PKG_MAX_PWR GENMASK_ULL(46, 32)
25 #define PKG_MAX_WIN GENMASK_ULL(54, 48)
26 #define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
27 #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
/linux/include/linux/net/intel/libie/
H A Dcontrolq.h196 #define LIBIE_CTLQ_DESC_INFRA_OPCODE GENMASK_ULL(31, 16)
197 #define LIBIE_CTLQ_DESC_DATA_LEN GENMASK_ULL(47, 32)
198 #define LIBIE_CTLQ_DESC_HW_RETVAL GENMASK_ULL(63, 48)
200 #define LIBIE_CTLQ_DESC_PFID_VFID GENMASK_ULL(63, 48)
204 #define LIBIE_CTLQ_DESC_VIRTCHNL_DESC_TYPE GENMASK_ULL(31, 28)
205 #define LIBIE_CTLQ_DESC_VIRTCHNL_MSG_RET_VAL GENMASK_ULL(63, 32)
208 #define LIBIE_CTLQ_DESC_MSG_PARAM0 GENMASK_ULL(31, 0)
209 #define LIBIE_CTLQ_DESC_SW_COOKIE GENMASK_ULL(47, 32)
210 #define LIBIE_CTLQ_DESC_VIRTCHNL_FLAGS GENMASK_ULL(63, 48)
213 #define LIBIE_CTLQ_DESC_DATA_ADDR_HIGH GENMASK_ULL(31, 0)
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_parser.c275 #define ICE_IM_PGKB_F0_IDX GENMASK_ULL(6, 1)
277 #define ICE_IM_PGKB_F1_IDX GENMASK_ULL(13, 8)
279 #define ICE_IM_PGKB_F2_IDX GENMASK_ULL(20, 15)
281 #define ICE_IM_PGKB_F3_IDX GENMASK_ULL(27, 22)
282 #define ICE_IM_PGKB_AR_IDX GENMASK_ULL(34, 28)
302 #define ICE_IM_ALU_OPC GENMASK_ULL(5, 0)
303 #define ICE_IM_ALU_SS GENMASK_ULL(13, 6)
304 #define ICE_IM_ALU_SL GENMASK_ULL(18, 14)
306 #define ICE_IM_ALU_SXK GENMASK_ULL(23, 20)
307 #define ICE_IM_ALU_SRID GENMASK_ULL(30, 24)
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/linux/tools/include/linux/
H A Dcoresight-pmu.h36 #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
37 #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)
39 #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
40 #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine_types.h26 #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
36 #define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
45 #define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
50 #define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
55 #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
/linux/drivers/dma/amd/qdma/
H A Dqdma.h235 #define QDMA_INTR_MASK_PIDX GENMASK_ULL(15, 0)
236 #define QDMA_INTR_MASK_CIDX GENMASK_ULL(31, 16)
237 #define QDMA_INTR_MASK_DESC_COLOR GENMASK_ULL(32, 32)
238 #define QDMA_INTR_MASK_STATE GENMASK_ULL(34, 33)
239 #define QDMA_INTR_MASK_ERROR GENMASK_ULL(36, 35)
240 #define QDMA_INTR_MASK_TYPE GENMASK_ULL(38, 38)
241 #define QDMA_INTR_MASK_QID GENMASK_ULL(62, 39)
242 #define QDMA_INTR_MASK_COLOR GENMASK_ULL(63, 63)
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dcn10k_ipsec.h208 #define CPT_LF_INPROG_INFLIGHT GENMASK_ULL(8, 0)
209 #define CPT_LF_INPROG_GRB_CNT GENMASK_ULL(39, 32)
210 #define CPT_LF_INPROG_GWB_CNT GENMASK_ULL(47, 40)
213 #define CPT_LF_Q_GRP_PTR_DQ_PTR GENMASK_ULL(14, 0)
214 #define CPT_LF_Q_GRP_PTR_NQ_PTR GENMASK_ULL(46, 32)
217 #define CPT_LF_Q_BASE_ADDR GENMASK_ULL(52, 7)
220 #define CPT_LF_Q_SIZE_DIV40 GENMASK_ULL(14, 0)
223 #define CPT_LF_CTX_FLUSH_CPTR GENMASK_ULL(45, 0)
/linux/arch/arm64/include/asm/
H A Dsysreg.h334 #define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)
335 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
338 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
342 #define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)
343 #define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
344 #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
1058 #define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)
1059 #define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)
1061 #define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)
1064 #define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)
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H A Dtlbflush.h53 __ta &= GENMASK_ULL(43, 0); \
129 #define TLBI_TTL_MASK GENMASK_ULL(47, 44)
215 #define TLBIR_ASID_MASK GENMASK_ULL(63, 48)
216 #define TLBIR_TG_MASK GENMASK_ULL(47, 46)
217 #define TLBIR_SCALE_MASK GENMASK_ULL(45, 44)
218 #define TLBIR_NUM_MASK GENMASK_ULL(43, 39)
219 #define TLBIR_TTL_MASK GENMASK_ULL(38, 37)
220 #define TLBIR_BADDR_MASK GENMASK_ULL(36, 0)
/linux/drivers/firmware/efi/
H A Dcper-x86.c13 #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2)
14 #define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8)
48 #define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0)))
49 #define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16)
50 #define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18)
51 #define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22)
58 #define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30)
60 #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33)
69 #define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16)
/linux/drivers/net/wireless/realtek/rtw89/
H A Dphy.h31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
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/linux/drivers/spi/
H A Dspi-altera-dfl.c32 #define DATA_WIDTH GENMASK_ULL(7, 2)
33 #define NUM_CHIPSELECT GENMASK_ULL(13, 8)
36 #define PERIPHERAL_ID GENMASK_ULL(47, 32)
37 #define SPI_CLK GENMASK_ULL(31, 22)
44 #define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
/linux/include/linux/i3c/
H A Ddevice.h90 #define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
92 #define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
93 #define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
94 #define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
95 #define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
/linux/drivers/perf/
H A Dcxl_pmu.c28 #define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0)
29 #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8)
30 #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20)
31 #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32)
34 #define CXL_PMU_CAP_MSI_N_MSK GENMASK_ULL(47, 44)
38 #define CXL_PMU_CAP_VERSION_MSK GENMASK_ULL(63, 60)
43 #define CXL_PMU_EVENT_CAP_SUPPORTED_EVENTS_MSK GENMASK_ULL(31, 0)
44 #define CXL_PMU_EVENT_CAP_GROUP_ID_MSK GENMASK_ULL(47, 32)
45 #define CXL_PMU_EVENT_CAP_VENDOR_ID_MSK GENMASK_ULL(63, 48)
48 #define CXL_PMU_COUNTER_CFG_TYPE_MSK GENMASK_ULL(1, 0)
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/linux/drivers/soc/apple/
H A Drtkit.c27 #define APPLE_RTKIT_MGMT_TYPE GENMASK_ULL(59, 52)
41 #define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK_ULL(15, 0)
42 #define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK_ULL(31, 16)
45 #define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK_ULL(34, 32)
46 #define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK_ULL(31, 0)
50 #define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK_ULL(39, 32)
53 #define APPLE_RTKIT_MGMT_PWR_STATE GENMASK_ULL(15, 0)
58 #define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK_ULL(51, 44)
59 #define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK_ULL(43, 0)
61 #define APPLE_RTKIT_SYSLOG_TYPE GENMASK_ULL(59, 52)
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/linux/tools/testing/selftests/kvm/include/x86/
H A Dpmu.h29 #define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0)
30 #define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8)
39 #define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24)
/linux/drivers/iommu/intel/
H A Dpasid.h132 pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); in pasid_set_domain_id()
141 return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0)); in pasid_get_domain_id()
161 pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); in pasid_set_address_width()
171 pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); in pasid_set_translation_type()
290 pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); in pasid_set_flpm()

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