Home
last modified time | relevance | path

Searched refs:GENMASK_ULL (Results 1 – 25 of 269) sorted by relevance

1234567891011

/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
376 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
377 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
378 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
379 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
380 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
383 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
385 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
[all …]
H A Duda_d.h19 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
20 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
21 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
[all …]
H A Dicrdma_hw.h54 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
56 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
58 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
60 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h170 #define EVTREG_ID GENMASK_ULL(8, 3)
177 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
182 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
183 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
188 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
193 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
198 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
203 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
204 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
228 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
[all …]
H A Dnpc.h417 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
423 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)
426 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
427 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
428 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)
431 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
434 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
436 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
438 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
440 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
[all …]
H A Drvu_npc_hash.h104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
127 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
128 [1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
[all …]
H A Drvu_reg.h442 #define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0)
443 #define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16)
444 #define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32)
446 #define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12)
447 #define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0)
448 #define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48)
450 #define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16)
451 #define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16)
452 #define NIX_AF_TL3_PARENT_MASK GENMASK_ULL(23, 16)
453 #define NIX_AF_TL2_PARENT_MASK GENMASK_ULL(20, 16)
[all …]
/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
[all …]
/linux/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h44 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
48 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
54 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
59 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
60 #define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
72 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
73 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
76 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
78 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
86 #define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dwow.h8 #define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
9 #define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
10 #define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
11 #define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
12 #define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
13 #define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
15 #define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)
16 #define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)
17 #define RTW89_IGTK_IPN_2 GENMASK_ULL(23, 16)
18 #define RTW89_IGTK_IPN_3 GENMASK_ULL(31, 24)
[all …]
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_txrx.h65 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11)
67 #define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
96 #define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
98 #define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30)
100 #define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4)
102 #define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0)
104 #define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48)
106 #define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34)
108 #define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16)
110 #define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4)
[all …]
/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_mchbar_regs.h22 #define PKG_TDP GENMASK_ULL(14, 0)
23 #define PKG_MIN_PWR GENMASK_ULL(30, 16)
24 #define PKG_MAX_PWR GENMASK_ULL(46, 32)
25 #define PKG_MAX_WIN GENMASK_ULL(54, 48)
26 #define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
27 #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
/linux/include/linux/irqchip/
H A Darm-gic-v3.h173 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
199 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
200 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
248 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
300 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
302 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_parser.c275 #define ICE_IM_PGKB_F0_IDX GENMASK_ULL(6, 1)
277 #define ICE_IM_PGKB_F1_IDX GENMASK_ULL(13, 8)
279 #define ICE_IM_PGKB_F2_IDX GENMASK_ULL(20, 15)
281 #define ICE_IM_PGKB_F3_IDX GENMASK_ULL(27, 22)
282 #define ICE_IM_PGKB_AR_IDX GENMASK_ULL(34, 28)
302 #define ICE_IM_ALU_OPC GENMASK_ULL(5, 0)
303 #define ICE_IM_ALU_SS GENMASK_ULL(13, 6)
304 #define ICE_IM_ALU_SL GENMASK_ULL(18, 14)
306 #define ICE_IM_ALU_SXK GENMASK_ULL(23, 20)
307 #define ICE_IM_ALU_SRID GENMASK_ULL(30, 24)
[all …]
/linux/lib/
H A Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/linux/drivers/ras/amd/atl/
H A Ddenormalize.c490 cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3; in get_logical_coh_st_fabric_id_for_current_spa()
498 cs_id = FIELD_GET(GENMASK_ULL(63, 14), denorm_ctx->current_spa) << 4; in get_logical_coh_st_fabric_id_for_current_spa()
506 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
513 cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3; in get_logical_coh_st_fabric_id_for_current_spa()
521 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
530 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
538 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
539 cs_id |= FIELD_GET(GENMASK_ULL(9, 8), denorm_ctx->current_spa); in get_logical_coh_st_fabric_id_for_current_spa()
545 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
618 temp_addr_b = GENMASK_ULL(low_bit - 1, intlv_bit) & ctx->ret_addr; in denorm_addr_df3_6chan()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine_types.h26 #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
36 #define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
45 #define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
50 #define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
55 #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
/linux/drivers/dma/amd/qdma/
H A Dqdma.h235 #define QDMA_INTR_MASK_PIDX GENMASK_ULL(15, 0)
236 #define QDMA_INTR_MASK_CIDX GENMASK_ULL(31, 16)
237 #define QDMA_INTR_MASK_DESC_COLOR GENMASK_ULL(32, 32)
238 #define QDMA_INTR_MASK_STATE GENMASK_ULL(34, 33)
239 #define QDMA_INTR_MASK_ERROR GENMASK_ULL(36, 35)
240 #define QDMA_INTR_MASK_TYPE GENMASK_ULL(38, 38)
241 #define QDMA_INTR_MASK_QID GENMASK_ULL(62, 39)
242 #define QDMA_INTR_MASK_COLOR GENMASK_ULL(63, 63)
/linux/include/linux/
H A Dcoresight-pmu.h60 #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
61 #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)
63 #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
64 #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)
/linux/tools/include/linux/
H A Dcoresight-pmu.h60 #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
61 #define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)
63 #define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
64 #define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)
/linux/drivers/gpu/drm/imagination/
H A Dpvr_device.h459 ((((u64)(b) & GENMASK_ULL(15, 0)) << 48) | \
460 (((u64)(v) & GENMASK_ULL(15, 0)) << 32) | \
461 (((u64)(n) & GENMASK_ULL(15, 0)) << 16) | \
462 (((u64)(c) & GENMASK_ULL(15, 0)) << 0))
492 gpu_id->b = (bvnc & GENMASK_ULL(63, 48)) >> 48; in packed_bvnc_to_pvr_gpu_id()
493 gpu_id->v = (bvnc & GENMASK_ULL(47, 32)) >> 32; in packed_bvnc_to_pvr_gpu_id()
494 gpu_id->n = (bvnc & GENMASK_ULL(31, 16)) >> 16; in packed_bvnc_to_pvr_gpu_id()
495 gpu_id->c = bvnc & GENMASK_ULL(15, 0); in packed_bvnc_to_pvr_gpu_id()
/linux/arch/arm64/kvm/vgic/
H A Dvgic.h74 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
77 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
78 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
82 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
84 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
85 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
88 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
90 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
91 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
93 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
[all …]
/linux/drivers/firmware/efi/
H A Dcper-x86.c13 #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2)
14 #define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8)
48 #define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0)))
49 #define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16)
50 #define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18)
51 #define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22)
58 #define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30)
60 #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33)
69 #define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16)

1234567891011