1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Atmel MACB Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7 #ifndef _MACB_H
8 #define _MACB_H
9
10 #include <linux/clk.h>
11 #include <linux/phylink.h>
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
15 #include <linux/phy/phy.h>
16 #include <linux/workqueue.h>
17
18 #define MACB_GREGS_NBR 16
19 #define MACB_GREGS_VERSION 2
20 #define MACB_MAX_QUEUES 8
21
22 /* MACB register offsets */
23 #define MACB_NCR 0x0000 /* Network Control */
24 #define MACB_NCFGR 0x0004 /* Network Config */
25 #define MACB_NSR 0x0008 /* Network Status */
26 #define MACB_TAR 0x000c /* AT91RM9200 only */
27 #define MACB_TCR 0x0010 /* AT91RM9200 only */
28 #define MACB_TSR 0x0014 /* Transmit Status */
29 #define MACB_RBQP 0x0018 /* RX Q Base Address */
30 #define MACB_TBQP 0x001c /* TX Q Base Address */
31 #define MACB_RSR 0x0020 /* Receive Status */
32 #define MACB_ISR 0x0024 /* Interrupt Status */
33 #define MACB_IER 0x0028 /* Interrupt Enable */
34 #define MACB_IDR 0x002c /* Interrupt Disable */
35 #define MACB_IMR 0x0030 /* Interrupt Mask */
36 #define MACB_MAN 0x0034 /* PHY Maintenance */
37 #define MACB_PTR 0x0038
38 #define MACB_PFR 0x003c
39 #define MACB_FTO 0x0040
40 #define MACB_SCF 0x0044
41 #define MACB_MCF 0x0048
42 #define MACB_FRO 0x004c
43 #define MACB_FCSE 0x0050
44 #define MACB_ALE 0x0054
45 #define MACB_DTF 0x0058
46 #define MACB_LCOL 0x005c
47 #define MACB_EXCOL 0x0060
48 #define MACB_TUND 0x0064
49 #define MACB_CSE 0x0068
50 #define MACB_RRE 0x006c
51 #define MACB_ROVR 0x0070
52 #define MACB_RSE 0x0074
53 #define MACB_ELE 0x0078
54 #define MACB_RJA 0x007c
55 #define MACB_USF 0x0080
56 #define MACB_STE 0x0084
57 #define MACB_RLE 0x0088
58 #define MACB_TPF 0x008c
59 #define MACB_HRB 0x0090
60 #define MACB_HRT 0x0094
61 #define MACB_SA1B 0x0098
62 #define MACB_SA1T 0x009c
63 #define MACB_SA2B 0x00a0
64 #define MACB_SA2T 0x00a4
65 #define MACB_SA3B 0x00a8
66 #define MACB_SA3T 0x00ac
67 #define MACB_SA4B 0x00b0
68 #define MACB_SA4T 0x00b4
69 #define MACB_TID 0x00b8
70 #define MACB_TPQ 0x00bc
71 #define MACB_USRIO 0x00c0
72 #define MACB_WOL 0x00c4
73 #define MACB_MID 0x00fc
74 #define MACB_TBQPH 0x04C8
75 #define MACB_RBQPH 0x04D4
76
77 /* GEM register offsets. */
78 #define GEM_NCR 0x0000 /* Network Control */
79 #define GEM_NCFGR 0x0004 /* Network Config */
80 #define GEM_USRIO 0x000c /* User IO */
81 #define GEM_DMACFG 0x0010 /* DMA Configuration */
82 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
83 #define GEM_JML 0x0048 /* Jumbo Max Length */
84 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
85 #define GEM_HRB 0x0080 /* Hash Bottom */
86 #define GEM_HRT 0x0084 /* Hash Top */
87 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
88 #define GEM_SA1T 0x008C /* Specific1 Top */
89 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
90 #define GEM_SA2T 0x0094 /* Specific2 Top */
91 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
92 #define GEM_SA3T 0x009C /* Specific3 Top */
93 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
94 #define GEM_SA4T 0x00A4 /* Specific4 Top */
95 #define GEM_WOL 0x00b8 /* Wake on LAN */
96 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
97 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
98 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
99 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
100 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
101 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
102 #define GEM_OTX 0x0100 /* Octets transmitted */
103 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
104 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
105 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
106 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
107 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
108 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
109 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
110 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
111 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
112 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
113 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
114 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
115 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
116 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
117 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
118 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
119 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
120 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
121 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
122 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
123 #define GEM_ORX 0x0150 /* Octets received */
124 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
125 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
126 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
127 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
128 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
129 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
130 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
131 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
132 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
133 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
134 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
135 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
136 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
137 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
138 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
139 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
140 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
141 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
142 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
143 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
144 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
145 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
146 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
147 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
148 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
149 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
150 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
151 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
152 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
153 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
154 #define GEM_TI 0x01dc /* 1588 Timer Increment */
155 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
156 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
157 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
158 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
159 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
160 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
161 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
162 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
163 #define GEM_PCSCNTRL 0x0200 /* PCS Control */
164 #define GEM_PCSSTS 0x0204 /* PCS Status */
165 #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */
166 #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */
167 #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */
168 #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */
169 #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */
170 #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */
171 #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */
172 #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */
173 #define GEM_RXLPI 0x0270 /* RX LPI Transitions */
174 #define GEM_RXLPITIME 0x0274 /* RX LPI Time */
175 #define GEM_TXLPI 0x0278 /* TX LPI Transitions */
176 #define GEM_TXLPITIME 0x027c /* TX LPI Time */
177 #define GEM_DCFG1 0x0280 /* Design Config 1 */
178 #define GEM_DCFG2 0x0284 /* Design Config 2 */
179 #define GEM_DCFG3 0x0288 /* Design Config 3 */
180 #define GEM_DCFG4 0x028c /* Design Config 4 */
181 #define GEM_DCFG5 0x0290 /* Design Config 5 */
182 #define GEM_DCFG6 0x0294 /* Design Config 6 */
183 #define GEM_DCFG7 0x0298 /* Design Config 7 */
184 #define GEM_DCFG8 0x029C /* Design Config 8 */
185 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
186 #define GEM_DCFG12 0x02AC /* Design Config 12 */
187 #define GEM_ENST_CONTROL 0x0880 /* ENST control register */
188 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */
189 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */
190
191 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
192 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
193
194 /* Screener Type 2 match registers */
195 #define GEM_SCRT2 0x540
196
197 /* EtherType registers */
198 #define GEM_ETHT 0x06E0
199
200 /* Type 2 compare registers */
201 #define GEM_T2CMPW0 0x0700
202 #define GEM_T2CMPW1 0x0704
203 #define T2CMP_OFST(t2idx) (t2idx * 2)
204
205 /* type 2 compare registers
206 * each location requires 3 compare regs
207 */
208 #define GEM_IP4SRC_CMP(idx) (idx * 3)
209 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
210 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
211
212 /* Which screening type 2 EtherType register will be used (0 - 7) */
213 #define SCRT2_ETHT 0
214
215 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
216 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
217 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
218 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
219 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
220 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
221 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
222
223 #define GEM_ENST_START_TIME(hw_q) (0x0800 + ((hw_q) << 2))
224 #define GEM_ENST_ON_TIME(hw_q) (0x0820 + ((hw_q) << 2))
225 #define GEM_ENST_OFF_TIME(hw_q) (0x0840 + ((hw_q) << 2))
226
227 /* Bitfields in ENST_CONTROL */
228 #define GEM_ENST_DISABLE_QUEUE_OFFSET 16
229
230 /* Bitfields in NCR */
231 #define MACB_LB_OFFSET 0 /* reserved */
232 #define MACB_LB_SIZE 1
233 #define MACB_LLB_OFFSET 1 /* Loop back local */
234 #define MACB_LLB_SIZE 1
235 #define MACB_RE_OFFSET 2 /* Receive enable */
236 #define MACB_RE_SIZE 1
237 #define MACB_TE_OFFSET 3 /* Transmit enable */
238 #define MACB_TE_SIZE 1
239 #define MACB_MPE_OFFSET 4 /* Management port enable */
240 #define MACB_MPE_SIZE 1
241 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
242 #define MACB_CLRSTAT_SIZE 1
243 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
244 #define MACB_INCSTAT_SIZE 1
245 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
246 #define MACB_WESTAT_SIZE 1
247 #define MACB_BP_OFFSET 8 /* Back pressure */
248 #define MACB_BP_SIZE 1
249 #define MACB_TSTART_OFFSET 9 /* Start transmission */
250 #define MACB_TSTART_SIZE 1
251 #define MACB_THALT_OFFSET 10 /* Transmit halt */
252 #define MACB_THALT_SIZE 1
253 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
254 #define MACB_NCR_TPF_SIZE 1
255 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
256 #define MACB_TZQ_SIZE 1
257 #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
258 #define MACB_PTPUNI_OFFSET 20 /* PTP Unicast packet enable */
259 #define MACB_PTPUNI_SIZE 1
260 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
261 #define MACB_OSSMODE_SIZE 1
262 #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
263 #define MACB_MIIONRGMII_SIZE 1
264
265 /* Bitfields in NCFGR */
266 #define MACB_SPD_OFFSET 0 /* Speed */
267 #define MACB_SPD_SIZE 1
268 #define MACB_FD_OFFSET 1 /* Full duplex */
269 #define MACB_FD_SIZE 1
270 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
271 #define MACB_BIT_RATE_SIZE 1
272 #define MACB_JFRAME_OFFSET 3 /* reserved */
273 #define MACB_JFRAME_SIZE 1
274 #define MACB_CAF_OFFSET 4 /* Copy all frames */
275 #define MACB_CAF_SIZE 1
276 #define MACB_NBC_OFFSET 5 /* No broadcast */
277 #define MACB_NBC_SIZE 1
278 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
279 #define MACB_NCFGR_MTI_SIZE 1
280 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
281 #define MACB_UNI_SIZE 1
282 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
283 #define MACB_BIG_SIZE 1
284 #define MACB_EAE_OFFSET 9 /* External address match enable */
285 #define MACB_EAE_SIZE 1
286 #define MACB_CLK_OFFSET 10
287 #define MACB_CLK_SIZE 2
288 #define MACB_RTY_OFFSET 12 /* Retry test */
289 #define MACB_RTY_SIZE 1
290 #define MACB_PAE_OFFSET 13 /* Pause enable */
291 #define MACB_PAE_SIZE 1
292 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
293 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
294 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
295 #define MACB_RBOF_SIZE 2
296 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
297 #define MACB_RLCE_SIZE 1
298 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
299 #define MACB_DRFCS_SIZE 1
300 #define MACB_EFRHD_OFFSET 18
301 #define MACB_EFRHD_SIZE 1
302 #define MACB_IRXFCS_OFFSET 19
303 #define MACB_IRXFCS_SIZE 1
304
305 /* GEM specific NCR bitfields. */
306 #define GEM_TXLPIEN_OFFSET 19
307 #define GEM_TXLPIEN_SIZE 1
308 #define GEM_ENABLE_HS_MAC_OFFSET 31
309 #define GEM_ENABLE_HS_MAC_SIZE 1
310
311 /* GEM specific NCFGR bitfields. */
312 #define GEM_FD_OFFSET 1 /* Full duplex */
313 #define GEM_FD_SIZE 1
314 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
315 #define GEM_GBE_SIZE 1
316 #define GEM_PCSSEL_OFFSET 11
317 #define GEM_PCSSEL_SIZE 1
318 #define GEM_PAE_OFFSET 13 /* Pause enable */
319 #define GEM_PAE_SIZE 1
320 #define GEM_CLK_OFFSET 18 /* MDC clock division */
321 #define GEM_CLK_SIZE 3
322 #define GEM_DBW_OFFSET 21 /* Data bus width */
323 #define GEM_DBW_SIZE 2
324 #define GEM_RXCOEN_OFFSET 24
325 #define GEM_RXCOEN_SIZE 1
326 #define GEM_SGMIIEN_OFFSET 27
327 #define GEM_SGMIIEN_SIZE 1
328
329
330 /* Constants for data bus width. */
331 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
332 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
333 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
334
335 /* Bitfields in DMACFG. */
336 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
337 #define GEM_FBLDO_SIZE 5
338 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
339 #define GEM_ENDIA_DESC_SIZE 1
340 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
341 #define GEM_ENDIA_PKT_SIZE 1
342 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
343 #define GEM_RXBMS_SIZE 2
344 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
345 #define GEM_TXPBMS_SIZE 1
346 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
347 #define GEM_TXCOEN_SIZE 1
348 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
349 #define GEM_RXBS_SIZE 8
350 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
351 #define GEM_DDRP_SIZE 1
352 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
353 #define GEM_RXEXT_SIZE 1
354 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
355 #define GEM_TXEXT_SIZE 1
356 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
357 #define GEM_ADDR64_SIZE 1
358
359
360 /* Bitfields in PBUFRXCUT */
361 #define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */
362 #define GEM_ENCUTTHRU_SIZE 1
363
364 /* Bitfields in NSR */
365 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
366 #define MACB_NSR_LINK_SIZE 1
367 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
368 #define MACB_MDIO_SIZE 1
369 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
370 #define MACB_IDLE_SIZE 1
371
372 /* Bitfields in TSR */
373 #define MACB_UBR_OFFSET 0 /* Used bit read */
374 #define MACB_UBR_SIZE 1
375 #define MACB_COL_OFFSET 1 /* Collision occurred */
376 #define MACB_COL_SIZE 1
377 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
378 #define MACB_TSR_RLE_SIZE 1
379 #define MACB_TGO_OFFSET 3 /* Transmit go */
380 #define MACB_TGO_SIZE 1
381 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
382 #define MACB_BEX_SIZE 1
383 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
384 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
385 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
386 #define MACB_COMP_SIZE 1
387 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
388 #define MACB_UND_SIZE 1
389
390 /* Bitfields in RSR */
391 #define MACB_BNA_OFFSET 0 /* Buffer not available */
392 #define MACB_BNA_SIZE 1
393 #define MACB_REC_OFFSET 1 /* Frame received */
394 #define MACB_REC_SIZE 1
395 #define MACB_OVR_OFFSET 2 /* Receive overrun */
396 #define MACB_OVR_SIZE 1
397
398 /* Bitfields in ISR/IER/IDR/IMR */
399 #define MACB_MFD_OFFSET 0 /* Management frame sent */
400 #define MACB_MFD_SIZE 1
401 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
402 #define MACB_RCOMP_SIZE 1
403 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
404 #define MACB_RXUBR_SIZE 1
405 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
406 #define MACB_TXUBR_SIZE 1
407 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
408 #define MACB_ISR_TUND_SIZE 1
409 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
410 #define MACB_ISR_RLE_SIZE 1
411 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
412 #define MACB_TXERR_SIZE 1
413 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
414 #define MACB_RM9200_TBRE_SIZE 1
415 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
416 #define MACB_TCOMP_SIZE 1
417 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
418 #define MACB_ISR_LINK_SIZE 1
419 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
420 #define MACB_ISR_ROVR_SIZE 1
421 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
422 #define MACB_HRESP_SIZE 1
423 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
424 #define MACB_PFR_SIZE 1
425 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
426 #define MACB_PTZ_SIZE 1
427 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
428 #define MACB_WOL_SIZE 1
429 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
430 #define MACB_DRQFR_SIZE 1
431 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
432 #define MACB_SFR_SIZE 1
433 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
434 #define MACB_DRQFT_SIZE 1
435 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
436 #define MACB_SFT_SIZE 1
437 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
438 #define MACB_PDRQFR_SIZE 1
439 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
440 #define MACB_PDRSFR_SIZE 1
441 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
442 #define MACB_PDRQFT_SIZE 1
443 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
444 #define MACB_PDRSFT_SIZE 1
445 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
446 #define MACB_SRI_SIZE 1
447 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
448 #define GEM_WOL_SIZE 1
449
450 /* Timer increment fields */
451 #define MACB_TI_CNS_OFFSET 0
452 #define MACB_TI_CNS_SIZE 8
453 #define MACB_TI_ACNS_OFFSET 8
454 #define MACB_TI_ACNS_SIZE 8
455 #define MACB_TI_NIT_OFFSET 16
456 #define MACB_TI_NIT_SIZE 8
457
458 /* Bitfields in MAN */
459 #define MACB_DATA_OFFSET 0 /* data */
460 #define MACB_DATA_SIZE 16
461 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
462 #define MACB_CODE_SIZE 2
463 #define MACB_REGA_OFFSET 18 /* Register address */
464 #define MACB_REGA_SIZE 5
465 #define MACB_PHYA_OFFSET 23 /* PHY address */
466 #define MACB_PHYA_SIZE 5
467 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
468 #define MACB_RW_SIZE 2
469 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
470 #define MACB_SOF_SIZE 2
471
472 /* Bitfields in USRIO (AVR32) */
473 #define MACB_MII_OFFSET 0
474 #define MACB_MII_SIZE 1
475 #define MACB_EAM_OFFSET 1
476 #define MACB_EAM_SIZE 1
477 #define MACB_TX_PAUSE_OFFSET 2
478 #define MACB_TX_PAUSE_SIZE 1
479 #define MACB_TX_PAUSE_ZERO_OFFSET 3
480 #define MACB_TX_PAUSE_ZERO_SIZE 1
481
482 /* Bitfields in USRIO (AT91) */
483 #define MACB_RMII_OFFSET 0
484 #define MACB_RMII_SIZE 1
485 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
486 #define GEM_RGMII_SIZE 1
487 #define MACB_CLKEN_OFFSET 1
488 #define MACB_CLKEN_SIZE 1
489
490 /* Bitfields in WOL */
491 #define MACB_IP_OFFSET 0
492 #define MACB_IP_SIZE 16
493 #define MACB_MAG_OFFSET 16
494 #define MACB_MAG_SIZE 1
495 #define MACB_ARP_OFFSET 17
496 #define MACB_ARP_SIZE 1
497 #define MACB_SA1_OFFSET 18
498 #define MACB_SA1_SIZE 1
499 #define MACB_WOL_MTI_OFFSET 19
500 #define MACB_WOL_MTI_SIZE 1
501
502 /* Bitfields in MID */
503 #define MACB_IDNUM_OFFSET 16
504 #define MACB_IDNUM_SIZE 12
505 #define MACB_REV_OFFSET 0
506 #define MACB_REV_SIZE 16
507
508 /* Bitfield in HS_MAC_CONFIG */
509 #define GEM_HS_MAC_SPEED_OFFSET 0
510 #define GEM_HS_MAC_SPEED_SIZE 3
511
512 /* Bitfields in PCSCNTRL */
513 #define GEM_PCSAUTONEG_OFFSET 12
514 #define GEM_PCSAUTONEG_SIZE 1
515
516 /* Bitfields in DCFG1. */
517 #define GEM_IRQCOR_OFFSET 23
518 #define GEM_IRQCOR_SIZE 1
519 #define GEM_DBWDEF_OFFSET 25
520 #define GEM_DBWDEF_SIZE 3
521 #define GEM_USERIO_OFFSET 9
522 #define GEM_USERIO_SIZE 1
523 #define GEM_NO_PCS_OFFSET 0
524 #define GEM_NO_PCS_SIZE 1
525
526 /* Bitfields in DCFG2. */
527 #define GEM_RX_PKT_BUFF_OFFSET 20
528 #define GEM_RX_PKT_BUFF_SIZE 1
529 #define GEM_TX_PKT_BUFF_OFFSET 21
530 #define GEM_TX_PKT_BUFF_SIZE 1
531
532 #define GEM_RX_PBUF_ADDR_OFFSET 22
533 #define GEM_RX_PBUF_ADDR_SIZE 4
534
535 /* Bitfields in DCFG5. */
536 #define GEM_TSU_OFFSET 8
537 #define GEM_TSU_SIZE 1
538
539 /* Bitfields in DCFG6. */
540 #define GEM_PBUF_LSO_OFFSET 27
541 #define GEM_PBUF_LSO_SIZE 1
542 #define GEM_PBUF_RSC_OFFSET 26
543 #define GEM_PBUF_RSC_SIZE 1
544 #define GEM_PBUF_CUTTHRU_OFFSET 25
545 #define GEM_PBUF_CUTTHRU_SIZE 1
546 #define GEM_DAW64_OFFSET 23
547 #define GEM_DAW64_SIZE 1
548
549 /* Bitfields in DCFG8. */
550 #define GEM_T1SCR_OFFSET 24
551 #define GEM_T1SCR_SIZE 8
552 #define GEM_T2SCR_OFFSET 16
553 #define GEM_T2SCR_SIZE 8
554 #define GEM_SCR2ETH_OFFSET 8
555 #define GEM_SCR2ETH_SIZE 8
556 #define GEM_SCR2CMP_OFFSET 0
557 #define GEM_SCR2CMP_SIZE 8
558
559 /* Bitfields in DCFG10 */
560 #define GEM_TXBD_RDBUFF_OFFSET 12
561 #define GEM_TXBD_RDBUFF_SIZE 4
562 #define GEM_RXBD_RDBUFF_OFFSET 8
563 #define GEM_RXBD_RDBUFF_SIZE 4
564
565 /* Bitfields in DCFG12. */
566 #define GEM_HIGH_SPEED_OFFSET 26
567 #define GEM_HIGH_SPEED_SIZE 1
568
569 /* Bitfields in ENST_START_TIME_Qx. */
570 #define GEM_START_TIME_SEC_OFFSET 30
571 #define GEM_START_TIME_SEC_SIZE 2
572 #define GEM_START_TIME_NSEC_OFFSET 0
573 #define GEM_START_TIME_NSEC_SIZE 30
574
575 /* Bitfields in ENST_ON_TIME_Qx. */
576 #define GEM_ON_TIME_OFFSET 0
577 #define GEM_ON_TIME_SIZE 17
578
579 /* Bitfields in ENST_OFF_TIME_Qx. */
580 #define GEM_OFF_TIME_OFFSET 0
581 #define GEM_OFF_TIME_SIZE 17
582
583 /* Hardware ENST timing registers granularity */
584 #define ENST_TIME_GRANULARITY_NS 8
585
586 /* Bitfields in USX_CONTROL. */
587 #define GEM_USX_CTRL_SPEED_OFFSET 14
588 #define GEM_USX_CTRL_SPEED_SIZE 3
589 #define GEM_SERDES_RATE_OFFSET 12
590 #define GEM_SERDES_RATE_SIZE 2
591 #define GEM_RX_SCR_BYPASS_OFFSET 9
592 #define GEM_RX_SCR_BYPASS_SIZE 1
593 #define GEM_TX_SCR_BYPASS_OFFSET 8
594 #define GEM_TX_SCR_BYPASS_SIZE 1
595 #define GEM_TX_EN_OFFSET 1
596 #define GEM_TX_EN_SIZE 1
597 #define GEM_SIGNAL_OK_OFFSET 0
598 #define GEM_SIGNAL_OK_SIZE 1
599
600 /* Bitfields in USX_STATUS. */
601 #define GEM_USX_BLOCK_LOCK_OFFSET 0
602 #define GEM_USX_BLOCK_LOCK_SIZE 1
603
604 /* Bitfields in TISUBN */
605 #define GEM_SUBNSINCR_OFFSET 0
606 #define GEM_SUBNSINCRL_OFFSET 24
607 #define GEM_SUBNSINCRL_SIZE 8
608 #define GEM_SUBNSINCRH_OFFSET 0
609 #define GEM_SUBNSINCRH_SIZE 16
610 #define GEM_SUBNSINCR_SIZE 24
611
612 /* Bitfields in TI */
613 #define GEM_NSINCR_OFFSET 0
614 #define GEM_NSINCR_SIZE 8
615
616 /* Bitfields in TSH */
617 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
618 #define GEM_TSH_SIZE 16
619
620 /* Bitfields in TSL */
621 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
622 #define GEM_TSL_SIZE 32
623
624 /* Bitfields in TN */
625 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
626 #define GEM_TN_SIZE 30
627
628 /* Bitfields in TXBDCTRL */
629 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
630 #define GEM_TXTSMODE_SIZE 2
631
632 /* Bitfields in RXBDCTRL */
633 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
634 #define GEM_RXTSMODE_SIZE 2
635
636 /* Bitfields in SCRT2 */
637 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
638 #define GEM_QUEUE_SIZE 4
639 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
640 #define GEM_VLANPR_SIZE 3
641 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
642 #define GEM_VLANEN_SIZE 1
643 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
644 #define GEM_ETHT2IDX_SIZE 3
645 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
646 #define GEM_ETHTEN_SIZE 1
647 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
648 #define GEM_CMPA_SIZE 5
649 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
650 #define GEM_CMPAEN_SIZE 1
651 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
652 #define GEM_CMPB_SIZE 5
653 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
654 #define GEM_CMPBEN_SIZE 1
655 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
656 #define GEM_CMPC_SIZE 5
657 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
658 #define GEM_CMPCEN_SIZE 1
659
660 /* Bitfields in ETHT */
661 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
662 #define GEM_ETHTCMP_SIZE 16
663
664 /* Bitfields in T2CMPW0 */
665 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
666 #define GEM_T2CMP_SIZE 16
667 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
668 #define GEM_T2MASK_SIZE 16
669
670 /* Bitfields in T2CMPW1 */
671 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
672 #define GEM_T2DISMSK_SIZE 1
673 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
674 #define GEM_T2CMPOFST_SIZE 2
675 #define GEM_T2OFST_OFFSET 0 /* offset value */
676 #define GEM_T2OFST_SIZE 7
677
678 /* Bitfields in queue pointer registers */
679 #define MACB_QUEUE_DISABLE_OFFSET 0 /* disable queue */
680 #define MACB_QUEUE_DISABLE_SIZE 1
681
682 /* Offset for screener type 2 compare values (T2CMPOFST).
683 * Note the offset is applied after the specified point,
684 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
685 * of 12 bytes from this would be the source IP address in an IP header
686 */
687 #define GEM_T2COMPOFST_SOF 0
688 #define GEM_T2COMPOFST_ETYPE 1
689 #define GEM_T2COMPOFST_IPHDR 2
690 #define GEM_T2COMPOFST_TCPUDP 3
691
692 /* offset from EtherType to IP address */
693 #define ETYPE_SRCIP_OFFSET 12
694 #define ETYPE_DSTIP_OFFSET 16
695
696 /* offset from IP header to port */
697 #define IPHDR_SRCPORT_OFFSET 0
698 #define IPHDR_DSTPORT_OFFSET 2
699
700 /* Transmit DMA buffer descriptor Word 1 */
701 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
702 #define GEM_DMA_TXVALID_SIZE 1
703
704 /* Receive DMA buffer descriptor Word 0 */
705 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
706 #define GEM_DMA_RXVALID_SIZE 1
707
708 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
709 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
710 #define GEM_DMA_SECL_SIZE 2
711 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
712 #define GEM_DMA_NSEC_SIZE 30
713
714 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
715
716 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
717 * Old hardware supports only 6 bit precision but it is enough for PTP.
718 * Less accuracy is used always instead of checking hardware version.
719 */
720 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
721 #define GEM_DMA_SECH_SIZE 4
722 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
723 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
724 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
725
726 /* Bitfields in ADJ */
727 #define GEM_ADDSUB_OFFSET 31
728 #define GEM_ADDSUB_SIZE 1
729 /* Constants for CLK */
730 #define MACB_CLK_DIV8 0
731 #define MACB_CLK_DIV16 1
732 #define MACB_CLK_DIV32 2
733 #define MACB_CLK_DIV64 3
734
735 /* GEM specific constants for CLK. */
736 #define GEM_CLK_DIV8 0
737 #define GEM_CLK_DIV16 1
738 #define GEM_CLK_DIV32 2
739 #define GEM_CLK_DIV48 3
740 #define GEM_CLK_DIV64 4
741 #define GEM_CLK_DIV96 5
742 #define GEM_CLK_DIV128 6
743 #define GEM_CLK_DIV224 7
744
745 /* Constants for MAN register */
746 #define MACB_MAN_C22_SOF 1
747 #define MACB_MAN_C22_WRITE 1
748 #define MACB_MAN_C22_READ 2
749 #define MACB_MAN_C22_CODE 2
750
751 #define MACB_MAN_C45_SOF 0
752 #define MACB_MAN_C45_ADDR 0
753 #define MACB_MAN_C45_WRITE 1
754 #define MACB_MAN_C45_POST_READ_INCR 2
755 #define MACB_MAN_C45_READ 3
756 #define MACB_MAN_C45_CODE 2
757
758 /* Capability mask bits */
759 #define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
760 #define MACB_CAPS_USRIO_HAS_CLKEN BIT(1)
761 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2)
762 #define MACB_CAPS_NO_GIGABIT_HALF BIT(3)
763 #define MACB_CAPS_USRIO_DISABLED BIT(4)
764 #define MACB_CAPS_JUMBO BIT(5)
765 #define MACB_CAPS_GEM_HAS_PTP BIT(6)
766 #define MACB_CAPS_BD_RD_PREFETCH BIT(7)
767 #define MACB_CAPS_NEEDS_RSTONUBR BIT(8)
768 #define MACB_CAPS_MIIONRGMII BIT(9)
769 #define MACB_CAPS_NEED_TSUCLK BIT(10)
770 #define MACB_CAPS_QUEUE_DISABLE BIT(11)
771 #define MACB_CAPS_QBV BIT(12)
772 #define MACB_CAPS_PCS BIT(13)
773 #define MACB_CAPS_HIGH_SPEED BIT(14)
774 #define MACB_CAPS_CLK_HW_CHG BIT(15)
775 #define MACB_CAPS_MACB_IS_EMAC BIT(16)
776 #define MACB_CAPS_FIFO_MODE BIT(17)
777 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(18)
778 #define MACB_CAPS_SG_DISABLED BIT(19)
779 #define MACB_CAPS_MACB_IS_GEM BIT(20)
780 #define MACB_CAPS_DMA_64B BIT(21)
781 #define MACB_CAPS_DMA_PTP BIT(22)
782 #define MACB_CAPS_RSC BIT(23)
783 #define MACB_CAPS_NO_LSO BIT(24)
784 #define MACB_CAPS_EEE BIT(25)
785 #define MACB_CAPS_USRIO_HAS_MII BIT(26)
786 #define MACB_CAPS_USRIO_HAS_REFCLK_SOURCE BIT(27)
787 #define MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE BIT(28)
788
789 /* LSO settings */
790 #define MACB_LSO_UFO_ENABLE 0x01
791 #define MACB_LSO_TSO_ENABLE 0x02
792
793 /* Bit manipulation macros */
794 #define MACB_BIT(name) \
795 (1 << MACB_##name##_OFFSET)
796 #define MACB_BF(name,value) \
797 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
798 << MACB_##name##_OFFSET)
799 #define MACB_BFEXT(name,value)\
800 (((value) >> MACB_##name##_OFFSET) \
801 & ((1 << MACB_##name##_SIZE) - 1))
802 #define MACB_BFINS(name,value,old) \
803 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
804 << MACB_##name##_OFFSET)) \
805 | MACB_BF(name,value))
806
807 #define GEM_BIT(name) \
808 (1 << GEM_##name##_OFFSET)
809 #define GEM_BF(name, value) \
810 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
811 << GEM_##name##_OFFSET)
812 #define GEM_BFEXT(name, value)\
813 (((value) >> GEM_##name##_OFFSET) \
814 & ((1 << GEM_##name##_SIZE) - 1))
815 #define GEM_BFINS(name, value, old) \
816 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
817 << GEM_##name##_OFFSET)) \
818 | GEM_BF(name, value))
819
820 /* Register access macros */
821 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
822 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
823 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
824 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
825 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
826 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
827 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
828 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
829
830 /* Conditional GEM/MACB macros. These perform the operation to the correct
831 * register dependent on whether the device is a GEM or a MACB. For registers
832 * and bitfields that are common across both devices, use macb_{read,write}l
833 * to avoid the cost of the conditional.
834 */
835 #define macb_or_gem_writel(__bp, __reg, __value) \
836 ({ \
837 if (macb_is_gem((__bp))) \
838 gem_writel((__bp), __reg, __value); \
839 else \
840 macb_writel((__bp), __reg, __value); \
841 })
842
843 #define macb_or_gem_readl(__bp, __reg) \
844 ({ \
845 u32 __v; \
846 if (macb_is_gem((__bp))) \
847 __v = gem_readl((__bp), __reg); \
848 else \
849 __v = macb_readl((__bp), __reg); \
850 __v; \
851 })
852
853 #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
854
855 /* struct macb_dma_desc - Hardware DMA descriptor
856 * @addr: DMA address of data buffer
857 * @ctrl: Control and status bits
858 */
859 struct macb_dma_desc {
860 u32 addr;
861 u32 ctrl;
862 };
863
864 struct macb_dma_desc_64 {
865 u32 addrh;
866 u32 resvd;
867 };
868
869 struct macb_dma_desc_ptp {
870 u32 ts_1;
871 u32 ts_2;
872 };
873
874 /* DMA descriptor bitfields */
875 #define MACB_RX_USED_OFFSET 0
876 #define MACB_RX_USED_SIZE 1
877 #define MACB_RX_WRAP_OFFSET 1
878 #define MACB_RX_WRAP_SIZE 1
879 #define MACB_RX_WADDR_OFFSET 2
880 #define MACB_RX_WADDR_SIZE 30
881
882 #define MACB_RX_FRMLEN_OFFSET 0
883 #define MACB_RX_FRMLEN_SIZE 12
884 #define MACB_RX_OFFSET_OFFSET 12
885 #define MACB_RX_OFFSET_SIZE 2
886 #define MACB_RX_SOF_OFFSET 14
887 #define MACB_RX_SOF_SIZE 1
888 #define MACB_RX_EOF_OFFSET 15
889 #define MACB_RX_EOF_SIZE 1
890 #define MACB_RX_CFI_OFFSET 16
891 #define MACB_RX_CFI_SIZE 1
892 #define MACB_RX_VLAN_PRI_OFFSET 17
893 #define MACB_RX_VLAN_PRI_SIZE 3
894 #define MACB_RX_PRI_TAG_OFFSET 20
895 #define MACB_RX_PRI_TAG_SIZE 1
896 #define MACB_RX_VLAN_TAG_OFFSET 21
897 #define MACB_RX_VLAN_TAG_SIZE 1
898 #define MACB_RX_TYPEID_MATCH_OFFSET 22
899 #define MACB_RX_TYPEID_MATCH_SIZE 1
900 #define MACB_RX_SA4_MATCH_OFFSET 23
901 #define MACB_RX_SA4_MATCH_SIZE 1
902 #define MACB_RX_SA3_MATCH_OFFSET 24
903 #define MACB_RX_SA3_MATCH_SIZE 1
904 #define MACB_RX_SA2_MATCH_OFFSET 25
905 #define MACB_RX_SA2_MATCH_SIZE 1
906 #define MACB_RX_SA1_MATCH_OFFSET 26
907 #define MACB_RX_SA1_MATCH_SIZE 1
908 #define MACB_RX_EXT_MATCH_OFFSET 28
909 #define MACB_RX_EXT_MATCH_SIZE 1
910 #define MACB_RX_UHASH_MATCH_OFFSET 29
911 #define MACB_RX_UHASH_MATCH_SIZE 1
912 #define MACB_RX_MHASH_MATCH_OFFSET 30
913 #define MACB_RX_MHASH_MATCH_SIZE 1
914 #define MACB_RX_BROADCAST_OFFSET 31
915 #define MACB_RX_BROADCAST_SIZE 1
916
917 #define MACB_RX_FRMLEN_MASK 0xFFF
918 #define MACB_RX_JFRMLEN_MASK 0x3FFF
919
920 /* RX checksum offload disabled: bit 24 clear in NCFGR */
921 #define GEM_RX_TYPEID_MATCH_OFFSET 22
922 #define GEM_RX_TYPEID_MATCH_SIZE 2
923
924 /* RX checksum offload enabled: bit 24 set in NCFGR */
925 #define GEM_RX_CSUM_OFFSET 22
926 #define GEM_RX_CSUM_SIZE 2
927
928 #define MACB_TX_FRMLEN_OFFSET 0
929 #define MACB_TX_FRMLEN_SIZE 11
930 #define MACB_TX_LAST_OFFSET 15
931 #define MACB_TX_LAST_SIZE 1
932 #define MACB_TX_NOCRC_OFFSET 16
933 #define MACB_TX_NOCRC_SIZE 1
934 #define MACB_MSS_MFS_OFFSET 16
935 #define MACB_MSS_MFS_SIZE 14
936 #define MACB_TX_LSO_OFFSET 17
937 #define MACB_TX_LSO_SIZE 2
938 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
939 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
940 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
941 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
942 #define MACB_TX_UNDERRUN_OFFSET 28
943 #define MACB_TX_UNDERRUN_SIZE 1
944 #define MACB_TX_ERROR_OFFSET 29
945 #define MACB_TX_ERROR_SIZE 1
946 #define MACB_TX_WRAP_OFFSET 30
947 #define MACB_TX_WRAP_SIZE 1
948 #define MACB_TX_USED_OFFSET 31
949 #define MACB_TX_USED_SIZE 1
950
951 #define GEM_TX_FRMLEN_OFFSET 0
952 #define GEM_TX_FRMLEN_SIZE 14
953
954 /* Buffer descriptor constants */
955 #define GEM_RX_CSUM_NONE 0
956 #define GEM_RX_CSUM_IP_ONLY 1
957 #define GEM_RX_CSUM_IP_TCP 2
958 #define GEM_RX_CSUM_IP_UDP 3
959
960 /* limit RX checksum offload to TCP and UDP packets */
961 #define GEM_RX_CSUM_CHECKED_MASK 2
962
963 /* Scaled PPM fraction */
964 #define PPM_FRACTION 16
965
966 /* struct macb_tx_skb - data about an skb which is being transmitted
967 * @skb: skb currently being transmitted, only set for the last buffer
968 * of the frame
969 * @mapping: DMA address of the skb's fragment buffer
970 * @size: size of the DMA mapped buffer
971 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
972 * false when buffer was mapped with dma_map_single()
973 */
974 struct macb_tx_skb {
975 struct sk_buff *skb;
976 dma_addr_t mapping;
977 size_t size;
978 bool mapped_as_page;
979 };
980
981 /* Hardware-collected statistics. Used when updating the network
982 * device stats by a periodic timer.
983 */
984 struct macb_stats {
985 u64 rx_pause_frames;
986 u64 tx_ok;
987 u64 tx_single_cols;
988 u64 tx_multiple_cols;
989 u64 rx_ok;
990 u64 rx_fcs_errors;
991 u64 rx_align_errors;
992 u64 tx_deferred;
993 u64 tx_late_cols;
994 u64 tx_excessive_cols;
995 u64 tx_underruns;
996 u64 tx_carrier_errors;
997 u64 rx_resource_errors;
998 u64 rx_overruns;
999 u64 rx_symbol_errors;
1000 u64 rx_oversize_pkts;
1001 u64 rx_jabbers;
1002 u64 rx_undersize_pkts;
1003 u64 sqe_test_errors;
1004 u64 rx_length_mismatch;
1005 u64 tx_pause_frames;
1006 };
1007
1008 struct gem_stats {
1009 u64 tx_octets;
1010 u64 tx_frames;
1011 u64 tx_broadcast_frames;
1012 u64 tx_multicast_frames;
1013 u64 tx_pause_frames;
1014 u64 tx_64_byte_frames;
1015 u64 tx_65_127_byte_frames;
1016 u64 tx_128_255_byte_frames;
1017 u64 tx_256_511_byte_frames;
1018 u64 tx_512_1023_byte_frames;
1019 u64 tx_1024_1518_byte_frames;
1020 u64 tx_greater_than_1518_byte_frames;
1021 u64 tx_underrun;
1022 u64 tx_single_collision_frames;
1023 u64 tx_multiple_collision_frames;
1024 u64 tx_excessive_collisions;
1025 u64 tx_late_collisions;
1026 u64 tx_deferred_frames;
1027 u64 tx_carrier_sense_errors;
1028 u64 rx_octets;
1029 u64 rx_frames;
1030 u64 rx_broadcast_frames;
1031 u64 rx_multicast_frames;
1032 u64 rx_pause_frames;
1033 u64 rx_64_byte_frames;
1034 u64 rx_65_127_byte_frames;
1035 u64 rx_128_255_byte_frames;
1036 u64 rx_256_511_byte_frames;
1037 u64 rx_512_1023_byte_frames;
1038 u64 rx_1024_1518_byte_frames;
1039 u64 rx_greater_than_1518_byte_frames;
1040 u64 rx_undersized_frames;
1041 u64 rx_oversize_frames;
1042 u64 rx_jabbers;
1043 u64 rx_frame_check_sequence_errors;
1044 u64 rx_length_field_frame_errors;
1045 u64 rx_symbol_errors;
1046 u64 rx_alignment_errors;
1047 u64 rx_resource_errors;
1048 u64 rx_overruns;
1049 u64 rx_ip_header_checksum_errors;
1050 u64 rx_tcp_checksum_errors;
1051 u64 rx_udp_checksum_errors;
1052 u64 rx_lpi_transitions;
1053 u64 rx_lpi_time;
1054 u64 tx_lpi_transitions;
1055 u64 tx_lpi_time;
1056 };
1057
1058 /* Describes the name and offset of an individual statistic register, as
1059 * returned by `ethtool -S`. Also describes which net_device_stats statistics
1060 * this register should contribute to.
1061 */
1062 struct gem_statistic {
1063 char stat_string[ETH_GSTRING_LEN] __nonstring;
1064 int offset;
1065 u32 stat_bits;
1066 };
1067
1068 /* Bitfield defs for net_device_stat statistics */
1069 #define GEM_NDS_RXERR_OFFSET 0
1070 #define GEM_NDS_RXLENERR_OFFSET 1
1071 #define GEM_NDS_RXOVERERR_OFFSET 2
1072 #define GEM_NDS_RXCRCERR_OFFSET 3
1073 #define GEM_NDS_RXFRAMEERR_OFFSET 4
1074 #define GEM_NDS_RXFIFOERR_OFFSET 5
1075 #define GEM_NDS_TXERR_OFFSET 6
1076 #define GEM_NDS_TXABORTEDERR_OFFSET 7
1077 #define GEM_NDS_TXCARRIERERR_OFFSET 8
1078 #define GEM_NDS_TXFIFOERR_OFFSET 9
1079 #define GEM_NDS_COLLISIONS_OFFSET 10
1080
1081 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
1082 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
1083 .stat_string = title, \
1084 .offset = GEM_##name, \
1085 .stat_bits = bits \
1086 }
1087
1088 /* list of gem statistic registers. The names MUST match the
1089 * corresponding GEM_* definitions.
1090 */
1091 static const struct gem_statistic gem_statistics[] = {
1092 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
1093 GEM_STAT_TITLE(TXCNT, "tx_frames"),
1094 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
1095 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
1096 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
1097 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
1098 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
1099 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
1100 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
1101 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
1102 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
1103 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
1104 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
1105 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
1106 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
1107 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1108 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
1109 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1110 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1111 GEM_BIT(NDS_TXERR)|
1112 GEM_BIT(NDS_TXABORTEDERR)|
1113 GEM_BIT(NDS_COLLISIONS)),
1114 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1115 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1116 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1117 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1118 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1119 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1120 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1121 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1122 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1123 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1124 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1125 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1126 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1127 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1128 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1129 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1130 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1131 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1132 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1133 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1134 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1135 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1136 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1137 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1138 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1139 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1140 GEM_BIT(NDS_RXERR)),
1141 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1142 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1143 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1144 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1145 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1146 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1147 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1148 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1149 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1150 GEM_BIT(NDS_RXERR)),
1151 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1152 GEM_BIT(NDS_RXERR)),
1153 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1154 GEM_BIT(NDS_RXERR)),
1155 GEM_STAT_TITLE(RXLPI, "rx_lpi_transitions"),
1156 GEM_STAT_TITLE(RXLPITIME, "rx_lpi_time"),
1157 GEM_STAT_TITLE(TXLPI, "tx_lpi_transitions"),
1158 GEM_STAT_TITLE(TXLPITIME, "tx_lpi_time"),
1159 };
1160
1161 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1162
1163 #define QUEUE_STAT_TITLE(title) { \
1164 .stat_string = title, \
1165 }
1166
1167 /* per queue statistics, each should be unsigned long type */
1168 struct queue_stats {
1169 union {
1170 unsigned long first;
1171 unsigned long rx_packets;
1172 };
1173 unsigned long rx_bytes;
1174 unsigned long rx_dropped;
1175 unsigned long tx_packets;
1176 unsigned long tx_bytes;
1177 unsigned long tx_dropped;
1178 };
1179
1180 static const struct gem_statistic queue_statistics[] = {
1181 QUEUE_STAT_TITLE("rx_packets"),
1182 QUEUE_STAT_TITLE("rx_bytes"),
1183 QUEUE_STAT_TITLE("rx_dropped"),
1184 QUEUE_STAT_TITLE("tx_packets"),
1185 QUEUE_STAT_TITLE("tx_bytes"),
1186 QUEUE_STAT_TITLE("tx_dropped"),
1187 };
1188
1189 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1190
1191 struct macb;
1192 struct macb_queue;
1193
1194 struct macb_or_gem_ops {
1195 int (*mog_alloc_rx_buffers)(struct macb *bp);
1196 void (*mog_free_rx_buffers)(struct macb *bp);
1197 void (*mog_init_rings)(struct macb *bp);
1198 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1199 int budget);
1200 };
1201
1202 /* MACB-PTP interface: adapt to platform needs. */
1203 struct macb_ptp_info {
1204 void (*ptp_init)(struct net_device *netdev);
1205 void (*ptp_remove)(struct net_device *netdev);
1206 s32 (*get_ptp_max_adj)(void);
1207 unsigned int (*get_tsu_rate)(struct macb *bp);
1208 int (*get_ts_info)(struct net_device *netdev,
1209 struct kernel_ethtool_ts_info *info);
1210 int (*get_hwtst)(struct net_device *netdev,
1211 struct kernel_hwtstamp_config *tstamp_config);
1212 int (*set_hwtst)(struct net_device *netdev,
1213 struct kernel_hwtstamp_config *tstamp_config,
1214 struct netlink_ext_ack *extack);
1215 };
1216
1217 struct macb_pm_data {
1218 u32 scrt2;
1219 u32 usrio;
1220 };
1221
1222 struct macb_usrio_config {
1223 u32 mii;
1224 u32 rmii;
1225 u32 rgmii;
1226 u32 refclk;
1227 u32 clken;
1228 u32 hdfctlen;
1229 u32 tsu_source;
1230 bool refclk_default_external;
1231 };
1232
1233 struct macb_config {
1234 u32 caps;
1235 unsigned int dma_burst_length;
1236 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1237 struct clk **hclk, struct clk **tx_clk,
1238 struct clk **rx_clk, struct clk **tsu_clk);
1239 int (*init)(struct platform_device *pdev);
1240 unsigned int max_tx_length;
1241 int jumbo_max_len;
1242 const struct macb_usrio_config *usrio;
1243 };
1244
1245 struct tsu_incr {
1246 u32 sub_ns;
1247 u32 ns;
1248 };
1249
1250 struct macb_queue {
1251 struct macb *bp;
1252 int irq;
1253
1254 unsigned int ISR;
1255 unsigned int IER;
1256 unsigned int IDR;
1257 unsigned int IMR;
1258 unsigned int TBQP;
1259 unsigned int RBQS;
1260 unsigned int RBQP;
1261
1262 /* ENST register offsets for this queue */
1263 unsigned int ENST_START_TIME;
1264 unsigned int ENST_ON_TIME;
1265 unsigned int ENST_OFF_TIME;
1266
1267 /* Lock to protect tx_head and tx_tail */
1268 spinlock_t tx_ptr_lock;
1269 unsigned int tx_head, tx_tail;
1270 struct macb_dma_desc *tx_ring;
1271 struct macb_tx_skb *tx_skb;
1272 dma_addr_t tx_ring_dma;
1273 struct work_struct tx_error_task;
1274 bool txubr_pending;
1275 struct napi_struct napi_tx;
1276
1277 dma_addr_t rx_ring_dma;
1278 dma_addr_t rx_buffers_dma;
1279 unsigned int rx_tail;
1280 unsigned int rx_prepared_head;
1281 struct macb_dma_desc *rx_ring;
1282 struct sk_buff **rx_skbuff;
1283 void *rx_buffers;
1284 struct napi_struct napi_rx;
1285 struct queue_stats stats;
1286 };
1287
1288 struct ethtool_rx_fs_item {
1289 struct ethtool_rx_flow_spec fs;
1290 struct list_head list;
1291 };
1292
1293 struct ethtool_rx_fs_list {
1294 struct list_head list;
1295 unsigned int count;
1296 };
1297
1298 struct macb {
1299 void __iomem *regs;
1300 bool native_io;
1301
1302 /* hardware IO accessors */
1303 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1304 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1305
1306 struct macb_dma_desc *rx_ring_tieoff;
1307 dma_addr_t rx_ring_tieoff_dma;
1308 size_t rx_buffer_size;
1309
1310 unsigned int rx_ring_size;
1311 unsigned int tx_ring_size;
1312
1313 unsigned int num_queues;
1314 struct macb_queue queues[MACB_MAX_QUEUES];
1315
1316 spinlock_t lock;
1317 struct platform_device *pdev;
1318 struct clk *pclk;
1319 struct clk *hclk;
1320 struct clk *tx_clk;
1321 struct clk *rx_clk;
1322 struct clk *tsu_clk;
1323 struct net_device *netdev;
1324 /* Protects hw_stats and ethtool_stats */
1325 spinlock_t stats_lock;
1326 union {
1327 struct macb_stats macb;
1328 struct gem_stats gem;
1329 } hw_stats;
1330
1331 struct macb_or_gem_ops macbgem_ops;
1332
1333 struct mii_bus *mii_bus;
1334 struct phylink *phylink;
1335 struct phylink_config phylink_config;
1336 struct phylink_pcs phylink_usx_pcs;
1337 struct phylink_pcs phylink_sgmii_pcs;
1338
1339 u32 caps;
1340 unsigned int dma_burst_length;
1341
1342 phy_interface_t phy_interface;
1343
1344 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1345 struct macb_tx_skb rm9200_txq[2];
1346 unsigned int max_tx_length;
1347
1348 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1349
1350 unsigned int rx_frm_len_mask;
1351 unsigned int jumbo_max_len;
1352
1353 u32 wol;
1354 u32 wolopts;
1355
1356 /* holds value of rx watermark value for pbuf_rxcutthru register */
1357 u32 rx_watermark;
1358
1359 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1360
1361 struct phy *phy;
1362
1363 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1364 unsigned int tsu_rate;
1365 struct ptp_clock *ptp_clock;
1366 struct ptp_clock_info ptp_clock_info;
1367 struct tsu_incr tsu_incr;
1368 struct kernel_hwtstamp_config tstamp_config;
1369
1370 /* RX queue filer rule set*/
1371 struct ethtool_rx_fs_list rx_fs_list;
1372 spinlock_t rx_fs_lock;
1373 unsigned int max_tuples;
1374
1375 struct work_struct hresp_err_bh_work;
1376
1377 /* EEE / LPI state */
1378 bool eee_active;
1379 struct delayed_work tx_lpi_work;
1380 u32 tx_lpi_timer;
1381
1382 int rx_bd_rd_prefetch;
1383 int tx_bd_rd_prefetch;
1384
1385 u32 rx_intr_mask;
1386
1387 struct macb_pm_data pm_data;
1388 const struct macb_usrio_config *usrio;
1389 };
1390
1391 #ifdef CONFIG_MACB_USE_HWSTAMP
1392 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1393 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1394 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1395
1396 enum macb_bd_control {
1397 TSTAMP_DISABLED,
1398 TSTAMP_FRAME_PTP_EVENT_ONLY,
1399 TSTAMP_ALL_PTP_FRAMES,
1400 TSTAMP_ALL_FRAMES,
1401 };
1402
1403 void gem_ptp_init(struct net_device *netdev);
1404 void gem_ptp_remove(struct net_device *netdev);
1405 void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1406 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1407 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1408 {
1409 if (bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1410 return;
1411
1412 gem_ptp_txstamp(bp, skb, desc);
1413 }
1414
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1415 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1416 {
1417 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1418 return;
1419
1420 gem_ptp_rxstamp(bp, skb, desc);
1421 }
1422
1423 int gem_get_hwtst(struct net_device *netdev,
1424 struct kernel_hwtstamp_config *tstamp_config);
1425 int gem_set_hwtst(struct net_device *netdev,
1426 struct kernel_hwtstamp_config *tstamp_config,
1427 struct netlink_ext_ack *extack);
1428 #else
gem_ptp_init(struct net_device * netdev)1429 static inline void gem_ptp_init(struct net_device *netdev) { }
gem_ptp_remove(struct net_device * netdev)1430 static inline void gem_ptp_remove(struct net_device *netdev) { }
1431
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1432 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1433 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1434 #endif
1435
macb_is_gem(struct macb * bp)1436 static inline bool macb_is_gem(struct macb *bp)
1437 {
1438 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1439 }
1440
gem_has_ptp(struct macb * bp)1441 static inline bool gem_has_ptp(struct macb *bp)
1442 {
1443 return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP);
1444 }
1445
1446 /* ENST Helper functions */
enst_ns_to_hw_units(size_t ns,u32 speed_mbps)1447 static inline u64 enst_ns_to_hw_units(size_t ns, u32 speed_mbps)
1448 {
1449 return DIV_ROUND_UP((ns) * (speed_mbps),
1450 (ENST_TIME_GRANULARITY_NS * 1000));
1451 }
1452
enst_max_hw_interval(u32 speed_mbps)1453 static inline u64 enst_max_hw_interval(u32 speed_mbps)
1454 {
1455 return DIV_ROUND_UP(GENMASK(GEM_ON_TIME_SIZE - 1, 0) *
1456 ENST_TIME_GRANULARITY_NS * 1000, (speed_mbps));
1457 }
1458
macb_dma64(struct macb * bp)1459 static inline bool macb_dma64(struct macb *bp)
1460 {
1461 return IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
1462 bp->caps & MACB_CAPS_DMA_64B;
1463 }
1464
macb_dma_ptp(struct macb * bp)1465 static inline bool macb_dma_ptp(struct macb *bp)
1466 {
1467 return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) &&
1468 bp->caps & MACB_CAPS_DMA_PTP;
1469 }
1470
macb_queue_isr_clear(struct macb * bp,struct macb_queue * queue,u32 value)1471 static inline void macb_queue_isr_clear(struct macb *bp,
1472 struct macb_queue *queue, u32 value)
1473 {
1474 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1475 queue_writel(queue, ISR, value);
1476 }
1477
1478 /**
1479 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
1480 * @pclk: platform clock
1481 * @hclk: AHB clock
1482 */
1483 struct macb_platform_data {
1484 struct clk *pclk;
1485 struct clk *hclk;
1486 };
1487
1488 /**
1489 * struct macb_queue_enst_config - Configuration for Enhanced Scheduled Traffic
1490 * @start_time_mask: Bitmask representing the start time for the queue
1491 * @on_time_bytes: "on" time nsec expressed in bytes
1492 * @off_time_bytes: "off" time nsec expressed in bytes
1493 * @queue_id: Identifier for the queue
1494 *
1495 * This structure holds the configuration parameters for an ENST queue,
1496 * used to control time-based transmission scheduling in the MACB driver.
1497 */
1498 struct macb_queue_enst_config {
1499 u32 start_time_mask;
1500 u32 on_time_bytes;
1501 u32 off_time_bytes;
1502 u8 queue_id;
1503 };
1504
1505 #endif /* _MACB_H */
1506