1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #if !defined (_soc24_ENUM_HEADER) 24 #define _soc24_ENUM_HEADER 25 26 #ifndef _DRIVER_BUILD 27 #ifndef GL_ZERO 28 #define GL__ZERO BLEND_ZERO 29 #define GL__ONE BLEND_ONE 30 #define GL__SRC_COLOR BLEND_SRC_COLOR 31 #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR 32 #define GL__DST_COLOR BLEND_DST_COLOR 33 #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR 34 #define GL__SRC_ALPHA BLEND_SRC_ALPHA 35 #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA 36 #define GL__DST_ALPHA BLEND_DST_ALPHA 37 #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA 38 #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE 39 #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR 40 #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR 41 #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA 42 #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA 43 #endif 44 #endif 45 46 47 /* 48 * CP_PERFMON_ENABLE_MODE enum 49 */ 50 51 typedef enum CP_PERFMON_ENABLE_MODE { 52 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, 53 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, 54 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, 55 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, 56 } CP_PERFMON_ENABLE_MODE; 57 58 /* 59 * CP_PERFMON_STATE enum 60 */ 61 62 typedef enum CP_PERFMON_STATE { 63 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 64 CP_PERFMON_STATE_START_COUNTING = 0x00000001, 65 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, 66 CP_PERFMON_STATE_RESERVED_3 = 0x00000003, 67 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 68 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 69 } CP_PERFMON_STATE; 70 71 /* 72 * ENUM_NUM_SIMD_PER_CU enum 73 */ 74 75 typedef enum ENUM_NUM_SIMD_PER_CU { 76 NUM_SIMD_PER_CU = 0x00000002, 77 } ENUM_NUM_SIMD_PER_CU; 78 79 /* 80 * GATCL1RequestType enum 81 */ 82 83 typedef enum GATCL1RequestType { 84 GATCL1_TYPE_NORMAL = 0x00000000, 85 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 86 GATCL1_TYPE_BYPASS = 0x00000002, 87 } GATCL1RequestType; 88 89 /* 90 * GL0V_CACHE_POLICIES enum 91 */ 92 93 typedef enum GL0V_CACHE_POLICIES { 94 GL0V_CACHE_POLICY_MISS_LRU = 0x00000000, 95 GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001, 96 GL0V_CACHE_POLICY_HIT_LRU = 0x00000002, 97 GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003, 98 GL0V_CACHE_POLICY_MISS_INVAL = 0x00000004, 99 } GL0V_CACHE_POLICIES; 100 101 /* 102 * GL1_CACHE_POLICIES enum 103 */ 104 105 typedef enum GL1_CACHE_POLICIES { 106 GL1_CACHE_POLICY_MISS_LRU = 0x00000000, 107 GL1_CACHE_POLICY_MISS_EVICT = 0x00000001, 108 GL1_CACHE_POLICY_HIT_LRU = 0x00000002, 109 GL1_CACHE_POLICY_HIT_EVICT = 0x00000003, 110 } GL1_CACHE_POLICIES; 111 112 /* 113 * GL1_CACHE_STORE_POLICIES enum 114 */ 115 116 typedef enum GL1_CACHE_STORE_POLICIES { 117 GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000, 118 } GL1_CACHE_STORE_POLICIES; 119 120 /* 121 * GL2_CACHE_POLICIES enum 122 */ 123 124 typedef enum GL2_CACHE_POLICIES { 125 GL2_CACHE_POLICY_LRU = 0x00000000, 126 GL2_CACHE_POLICY_STREAM = 0x00000001, 127 GL2_CACHE_POLICY_NOA = 0x00000002, 128 GL2_CACHE_POLICY_BYPASS = 0x00000003, 129 } GL2_CACHE_POLICIES; 130 131 /* 132 * GL2_NACKS enum 133 */ 134 135 typedef enum GL2_NACKS { 136 GL2_NACK_NO_FAULT = 0x00000000, 137 GL2_NACK_PAGE_FAULT = 0x00000001, 138 GL2_NACK_PROTECTION_FAULT = 0x00000002, 139 GL2_NACK_DATA_ERROR = 0x00000003, 140 } GL2_NACKS; 141 142 /* 143 * GL2_OP enum 144 */ 145 146 typedef enum GL2_OP { 147 GL2_OP_READ = 0x00000000, 148 GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, 149 GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, 150 GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, 151 GL2_OP_ATOMIC_PK_ADD_FP16_RTN = 0x00000004, 152 GL2_OP_ATOMIC_FADD_RTN_32 = 0x00000005, 153 GL2_OP_ATOMIC_PK_ADD_BF16_RTN = 0x00000006, 154 GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, 155 GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, 156 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, 157 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, 158 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, 159 GL2_OP_PROBE_FILTER = 0x0000000c, 160 GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, 161 GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, 162 GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, 163 GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010, 164 GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, 165 GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, 166 GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, 167 GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, 168 GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015, 169 GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016, 170 GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017, 171 GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018, 172 GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019, 173 GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 0x0000001a, 174 GL2_OP_ATOMIC_COND_SUB_RTN_32 = 0x0000001b, 175 GL2_OP_UTC_PROBE = 0x0000001d, 176 GL2_OP_LOAD_RESERVE = 0x0000001e, 177 GL2_OP_WRITE = 0x00000020, 178 GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, 179 GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, 180 GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, 181 GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, 182 GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, 183 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, 184 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, 185 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, 186 GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, 187 GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030, 188 GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, 189 GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, 190 GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, 191 GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, 192 GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035, 193 GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036, 194 GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037, 195 GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038, 196 GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039, 197 GL2_OP_WRITE_ZERO_SIZE = 0x0000003b, 198 GL2_OP_GL2_INV = 0x0000003d, 199 GL2_OP_ATOMIC_STORE_COND_RTN = 0x0000003e, 200 GL2_OP_GL1_INV = 0x00000040, 201 GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, 202 GL2_OP_ATOMIC_FMIN_32 = 0x00000042, 203 GL2_OP_ATOMIC_FMAX_32 = 0x00000043, 204 GL2_OP_ATOMIC_PK_ADD_FP16 = 0x00000044, 205 GL2_OP_ATOMIC_FADD_32 = 0x00000045, 206 GL2_OP_ATOMIC_PK_ADD_BF16 = 0x00000046, 207 GL2_OP_ATOMIC_SWAP_32 = 0x00000047, 208 GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048, 209 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, 210 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, 211 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, 212 GL2_OP_ATOMIC_UMIN_8 = 0x0000004c, 213 GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, 214 GL2_OP_ATOMIC_ADD_32 = 0x0000004f, 215 GL2_OP_ATOMIC_SUB_32 = 0x00000050, 216 GL2_OP_ATOMIC_SMIN_32 = 0x00000051, 217 GL2_OP_ATOMIC_UMIN_32 = 0x00000052, 218 GL2_OP_ATOMIC_SMAX_32 = 0x00000053, 219 GL2_OP_ATOMIC_UMAX_32 = 0x00000054, 220 GL2_OP_ATOMIC_AND_32 = 0x00000055, 221 GL2_OP_ATOMIC_OR_32 = 0x00000056, 222 GL2_OP_ATOMIC_XOR_32 = 0x00000057, 223 GL2_OP_ATOMIC_INC_32 = 0x00000058, 224 GL2_OP_ATOMIC_DEC_32 = 0x00000059, 225 GL2_OP_NOP_RTN0 = 0x0000005b, 226 GL2_OP_GL2_WB = 0x0000005d, 227 GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 0x0000005e, 228 GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, 229 GL2_OP_ATOMIC_FMIN_64 = 0x00000062, 230 GL2_OP_ATOMIC_FMAX_64 = 0x00000063, 231 GL2_OP_ATOMIC_SWAP_64 = 0x00000067, 232 GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068, 233 GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, 234 GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, 235 GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, 236 GL2_OP_ATOMIC_ADD_64 = 0x0000006f, 237 GL2_OP_ATOMIC_SUB_64 = 0x00000070, 238 GL2_OP_ATOMIC_SMIN_64 = 0x00000071, 239 GL2_OP_ATOMIC_UMIN_64 = 0x00000072, 240 GL2_OP_ATOMIC_SMAX_64 = 0x00000073, 241 GL2_OP_ATOMIC_UMAX_64 = 0x00000074, 242 GL2_OP_ATOMIC_AND_64 = 0x00000075, 243 GL2_OP_ATOMIC_OR_64 = 0x00000076, 244 GL2_OP_ATOMIC_XOR_64 = 0x00000077, 245 GL2_OP_ATOMIC_INC_64 = 0x00000078, 246 GL2_OP_ATOMIC_DEC_64 = 0x00000079, 247 GL2_OP_ATOMIC_UMAX_8 = 0x0000007a, 248 GL2_OP_NOP_ACK = 0x0000007b, 249 GL2_OP_GL2_WBINV = 0x0000007d, 250 GL2_OP_READ_COMPRESSION_KEY = 0x0000007e, 251 } GL2_OP; 252 253 /* 254 * GL2_OP_MASKS enum 255 */ 256 257 typedef enum GL2_OP_MASKS { 258 GL2_OP_MASK_FLUSH_DENROM = 0x00000008, 259 GL2_OP_MASK_64 = 0x00000020, 260 GL2_OP_MASK_NO_RTN = 0x00000040, 261 } GL2_OP_MASKS; 262 263 /* 264 * Hdp_SurfaceEndian enum 265 */ 266 267 typedef enum Hdp_SurfaceEndian { 268 HDP_ENDIAN_NONE = 0x00000000, 269 HDP_ENDIAN_8IN16 = 0x00000001, 270 HDP_ENDIAN_8IN32 = 0x00000002, 271 HDP_ENDIAN_8IN64 = 0x00000003, 272 } Hdp_SurfaceEndian; 273 274 /* 275 * MTYPE enum 276 */ 277 278 typedef enum MTYPE { 279 MTYPE_C_RW_US = 0x00000000, 280 MTYPE_RESERVED_1 = 0x00000001, 281 MTYPE_C_RO_S = 0x00000002, 282 MTYPE_UC = 0x00000003, 283 MTYPE_C_RW_S = 0x00000004, 284 MTYPE_RESERVED_5 = 0x00000005, 285 MTYPE_C_RO_US = 0x00000006, 286 MTYPE_RESERVED_7 = 0x00000007, 287 } MTYPE; 288 289 /* 290 * PERFMON_COUNTER_MODE enum 291 */ 292 293 typedef enum PERFMON_COUNTER_MODE { 294 PERFMON_COUNTER_MODE_ACCUM = 0x00000000, 295 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, 296 PERFMON_COUNTER_MODE_MAX = 0x00000002, 297 PERFMON_COUNTER_MODE_DIRTY = 0x00000003, 298 PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, 299 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, 300 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, 301 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, 302 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, 303 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, 304 PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, 305 } PERFMON_COUNTER_MODE; 306 307 /* 308 * PERFMON_SPM_MODE enum 309 */ 310 311 typedef enum PERFMON_SPM_MODE { 312 PERFMON_SPM_MODE_OFF = 0x00000000, 313 PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, 314 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, 315 PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, 316 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, 317 PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, 318 PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, 319 PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, 320 PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, 321 PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, 322 PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, 323 } PERFMON_SPM_MODE; 324 325 /* 326 * READ_COMPRESSION_MODE enum 327 */ 328 329 typedef enum READ_COMPRESSION_MODE { 330 COMPRESSION_MODE_BYPASS_COMPRESSION = 0x00000000, 331 COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 0x00000001, 332 COMPRESSION_MODE_READ_DECOMPRESSED = 0x00000002, 333 } READ_COMPRESSION_MODE; 334 335 /* 336 * ReadPolicy enum 337 */ 338 339 typedef enum ReadPolicy { 340 CACHE_LRU_RD = 0x00000000, 341 CACHE_STREAM_RD = 0x00000001, 342 CACHE_NOA = 0x00000002, 343 RESERVED_RDPOLICY = 0x00000003, 344 } ReadPolicy; 345 346 /* 347 * SCOPE enum 348 */ 349 350 typedef enum SCOPE { 351 SCOPE_CU = 0x00000000, 352 SCOPE_SE = 0x00000001, 353 SCOPE_DEV = 0x00000002, 354 SCOPE_SYS = 0x00000003, 355 } SCOPE; 356 357 /* 358 * SDMA_PERFMON_SEL enum 359 */ 360 361 typedef enum SDMA_PERFMON_SEL { 362 SDMA_PERFMON_SEL_CYCLE = 0x00000000, 363 SDMA_PERFMON_SEL_IDLE = 0x00000001, 364 SDMA_PERFMON_SEL_REG_IDLE = 0x00000002, 365 SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003, 366 SDMA_PERFMON_SEL_RB_FULL = 0x00000004, 367 SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005, 368 SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006, 369 SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007, 370 SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008, 371 SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009, 372 SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a, 373 SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b, 374 SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c, 375 SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d, 376 SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e, 377 SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, 378 SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010, 379 SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011, 380 SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012, 381 SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013, 382 SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014, 383 SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015, 384 SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016, 385 SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017, 386 SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a, 387 SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b, 388 SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c, 389 SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d, 390 SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e, 391 SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f, 392 SDMA_PERFMON_SEL_INT_IDLE = 0x00000020, 393 SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021, 394 SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022, 395 SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023, 396 SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024, 397 SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025, 398 SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027, 399 SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028, 400 SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029, 401 SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a, 402 SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b, 403 SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c, 404 SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d, 405 SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030, 406 SDMA_PERFMON_SEL_DUMMY_0 = 0x00000031, 407 SDMA_PERFMON_SEL_DUMMY_1 = 0x00000032, 408 SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033, 409 SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034, 410 SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035, 411 SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036, 412 SDMA_PERFMON_SEL_QUEUE0_SELECT = 0x00000037, 413 SDMA_PERFMON_SEL_QUEUE1_SELECT = 0x00000038, 414 SDMA_PERFMON_SEL_QUEUE2_SELECT = 0x00000039, 415 SDMA_PERFMON_SEL_QUEUE3_SELECT = 0x0000003a, 416 SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b, 417 SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c, 418 SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d, 419 SDMA_PERFMON_SEL_DOORBELL = 0x0000003e, 420 SDMA_PERFMON_SEL_MCU_L1_WR_VLD = 0x0000003f, 421 SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040, 422 SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041, 423 SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042, 424 SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043, 425 SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044, 426 SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, 427 SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, 428 SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047, 429 SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048, 430 SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049, 431 SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a, 432 SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b, 433 SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c, 434 SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d, 435 SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e, 436 SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f, 437 SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050, 438 SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051, 439 SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052, 440 SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053, 441 SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054, 442 SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055, 443 SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056, 444 SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057, 445 SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058, 446 SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, 447 SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, 448 SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, 449 SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, 450 SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d, 451 SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e, 452 SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f, 453 SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060, 454 SDMA_PERFMON_SEL_GCR_SEND = 0x00000061, 455 SDMA_PERFMON_SEL_GCR_RTN = 0x00000062, 456 SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063, 457 SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064, 458 } SDMA_PERFMON_SEL; 459 460 /* 461 * SDMA_PERF_SEL enum 462 */ 463 464 typedef enum SDMA_PERF_SEL { 465 SDMA_PERF_SEL_CYCLE = 0x00000000, 466 SDMA_PERF_SEL_IDLE = 0x00000001, 467 SDMA_PERF_SEL_REG_IDLE = 0x00000002, 468 SDMA_PERF_SEL_RB_EMPTY = 0x00000003, 469 SDMA_PERF_SEL_RB_FULL = 0x00000004, 470 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, 471 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, 472 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, 473 SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, 474 SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, 475 SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, 476 SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, 477 SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, 478 SDMA_PERF_SEL_EX_IDLE = 0x0000000d, 479 SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, 480 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, 481 SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, 482 SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, 483 SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, 484 SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, 485 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, 486 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, 487 SDMA_PERF_SEL_SEM_IDLE = 0x00000018, 488 SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, 489 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, 490 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, 491 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, 492 SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, 493 SDMA_PERF_SEL_INT_IDLE = 0x0000001e, 494 SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, 495 SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, 496 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, 497 SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, 498 SDMA_PERF_SEL_NUM_PACKET = 0x00000023, 499 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, 500 SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, 501 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, 502 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, 503 SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, 504 SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, 505 SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, 506 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, 507 SDMA_PERF_SEL_DUMMY_0 = 0x0000002f, 508 SDMA_PERF_SEL_DUMMY_1 = 0x00000030, 509 SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, 510 SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, 511 SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, 512 SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, 513 SDMA_PERF_SEL_QUEUE0_SELECT = 0x00000035, 514 SDMA_PERF_SEL_QUEUE1_SELECT = 0x00000036, 515 SDMA_PERF_SEL_QUEUE2_SELECT = 0x00000037, 516 SDMA_PERF_SEL_QUEUE3_SELECT = 0x00000038, 517 SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, 518 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, 519 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, 520 SDMA_PERF_SEL_DOORBELL = 0x0000003c, 521 SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, 522 SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, 523 SDMA_PERF_SEL_MCU_L1_WR_VLD = 0x0000003f, 524 SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, 525 SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041, 526 SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042, 527 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043, 528 SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044, 529 SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, 530 SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, 531 SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047, 532 SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048, 533 SDMA_PERF_SEL_UTCL2_FREE = 0x00000049, 534 SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a, 535 SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b, 536 SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c, 537 SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d, 538 SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e, 539 SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f, 540 SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050, 541 SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051, 542 SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052, 543 SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053, 544 SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054, 545 SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055, 546 SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056, 547 SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057, 548 SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058, 549 SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, 550 SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, 551 SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, 552 SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, 553 SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d, 554 SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e, 555 SDMA_PERF_SEL_TLBI_SEND = 0x0000005f, 556 SDMA_PERF_SEL_TLBI_RTN = 0x00000060, 557 SDMA_PERF_SEL_GCR_SEND = 0x00000061, 558 SDMA_PERF_SEL_GCR_RTN = 0x00000062, 559 SDMA_PERF_SEL_CGCG_FENCE = 0x00000063, 560 SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064, 561 SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065, 562 SDMA_PERF_SEL_MCU_CH_WR_REQ = 0x00000066, 563 SDMA_PERF_SEL_MCU_CH_WR_RET = 0x00000067, 564 SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ = 0x00000068, 565 SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET = 0x00000069, 566 SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a, 567 SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b, 568 SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c, 569 SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d, 570 SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e, 571 SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f, 572 SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070, 573 SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071, 574 SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072, 575 SDMA_PERF_SEL_CMD_OP_START = 0x00000073, 576 SDMA_PERF_SEL_CMD_OP_END = 0x00000074, 577 SDMA_PERF_SEL_CE_BUSY = 0x00000075, 578 SDMA_PERF_SEL_CE_BUSY_START = 0x00000076, 579 SDMA_PERF_SEL_CE_BUSY_END = 0x00000077, 580 SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER = 0x00000078, 581 SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START = 0x00000079, 582 SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END = 0x0000007a, 583 SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b, 584 SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c, 585 SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d, 586 SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e, 587 SDMA_PERF_SEL_QUEUE4_SELECT = 0x0000007f, 588 SDMA_PERF_SEL_QUEUE5_SELECT = 0x00000080, 589 SDMA_PERF_SEL_QUEUE6_SELECT = 0x00000081, 590 SDMA_PERF_SEL_QUEUE7_SELECT = 0x00000082, 591 } SDMA_PERF_SEL; 592 593 /* 594 * SPM_PERFMON_STATE enum 595 */ 596 597 typedef enum SPM_PERFMON_STATE { 598 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 599 STRM_PERFMON_STATE_START_COUNTING = 0x00000001, 600 STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, 601 STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, 602 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 603 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 604 } SPM_PERFMON_STATE; 605 606 /* 607 * TCC_MTYPE enum 608 */ 609 610 typedef enum TCC_MTYPE { 611 MTYPE_NC = 0x00000000, 612 MTYPE_WC = 0x00000001, 613 MTYPE_CC = 0x00000002, 614 } TCC_MTYPE; 615 616 /* 617 * UTCL0FaultType enum 618 */ 619 620 typedef enum UTCL0FaultType { 621 UTCL0_XNACK_SUCCESS = 0x00000000, 622 UTCL0_XNACK_RETRY = 0x00000001, 623 UTCL0_XNACK_PRT = 0x00000002, 624 UTCL0_XNACK_NO_RETRY = 0x00000003, 625 } UTCL0FaultType; 626 627 /* 628 * UTCL0RequestType enum 629 */ 630 631 typedef enum UTCL0RequestType { 632 UTCL0_TYPE_NORMAL = 0x00000000, 633 UTCL0_TYPE_SHOOTDOWN = 0x00000001, 634 UTCL0_TYPE_BYPASS = 0x00000002, 635 } UTCL0RequestType; 636 637 /* 638 * UTCL1FaultType enum 639 */ 640 641 typedef enum UTCL1FaultType { 642 UTCL1_XNACK_SUCCESS = 0x00000000, 643 UTCL1_XNACK_RETRY = 0x00000001, 644 UTCL1_XNACK_PRT = 0x00000002, 645 UTCL1_XNACK_NO_RETRY = 0x00000003, 646 } UTCL1FaultType; 647 648 /* 649 * UTCL1RequestType enum 650 */ 651 652 typedef enum UTCL1RequestType { 653 UTCL1_TYPE_NORMAL = 0x00000000, 654 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 655 UTCL1_TYPE_BYPASS = 0x00000002, 656 } UTCL1RequestType; 657 658 /* 659 * WRITE_COMPRESSION_MODE enum 660 */ 661 662 typedef enum WRITE_COMPRESSION_MODE { 663 COMPRESSION_MODE_BYPASS_METADATA_CACHE = 0x00000000, 664 COMPRESSION_MODE_COMPRESSION_ENABLED = 0x00000001, 665 COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 0x00000002, 666 } WRITE_COMPRESSION_MODE; 667 668 /* 669 * WritePolicy enum 670 */ 671 672 typedef enum WritePolicy { 673 CACHE_LRU_WR = 0x00000000, 674 CACHE_STREAM = 0x00000001, 675 CACHE_NOA_WR = 0x00000002, 676 CACHE_BYPASS = 0x00000003, 677 } WritePolicy; 678 679 /* 680 * COLOR_KEYER_ENABLE enum 681 */ 682 683 typedef enum COLOR_KEYER_ENABLE { 684 COLOR_KEY_EN = 0x00000000, 685 COLOR_KEY_DIS = 0x00000001, 686 } COLOR_KEYER_ENABLE; 687 688 /* 689 * COLOR_KEYER_MODE enum 690 */ 691 692 typedef enum COLOR_KEYER_MODE { 693 FORCE_00 = 0x00000000, 694 FORCE_FF = 0x00000001, 695 RANGE_00 = 0x00000002, 696 RANGE_FF = 0x00000003, 697 } COLOR_KEYER_MODE; 698 699 /* 700 * DENORM_TRUNCATE enum 701 */ 702 703 typedef enum DENORM_TRUNCATE { 704 CNVC_ROUND = 0x00000000, 705 CNVC_TRUNCATE = 0x00000001, 706 } DENORM_TRUNCATE; 707 708 /* 709 * FORMAT_CROSSBAR enum 710 */ 711 712 typedef enum FORMAT_CROSSBAR { 713 FORMAT_CROSSBAR_R = 0x00000000, 714 FORMAT_CROSSBAR_G = 0x00000001, 715 FORMAT_CROSSBAR_B = 0x00000002, 716 } FORMAT_CROSSBAR; 717 718 /* 719 * LUMA_KEYER_ENABLE enum 720 */ 721 722 typedef enum LUMA_KEYER_ENABLE { 723 LUMA_KEY_EN = 0x00000000, 724 LUMA_KEY_DIS = 0x00000001, 725 } LUMA_KEYER_ENABLE; 726 727 /* 728 * PIX_EXPAND_MODE enum 729 */ 730 731 typedef enum PIX_EXPAND_MODE { 732 PIX_DYNAMIC_EXPANSION = 0x00000000, 733 PIX_ZERO_EXPANSION = 0x00000001, 734 } PIX_EXPAND_MODE; 735 736 /* 737 * PRE_CSC_MODE_ENUM enum 738 */ 739 740 typedef enum PRE_CSC_MODE_ENUM { 741 PRE_CSC_BYPASS = 0x00000000, 742 PRE_CSC_SET_A = 0x00000001, 743 PRE_CSC_SET_B = 0x00000002, 744 } PRE_CSC_MODE_ENUM; 745 746 /* 747 * PRE_DEGAM_MODE enum 748 */ 749 750 typedef enum PRE_DEGAM_MODE { 751 PRE_DEGAM_BYPASS = 0x00000000, 752 PRE_DEGAM_ENABLE = 0x00000001, 753 } PRE_DEGAM_MODE; 754 755 /* 756 * PRE_DEGAM_SELECT enum 757 */ 758 759 typedef enum PRE_DEGAM_SELECT { 760 PRE_DEGAM_SRGB = 0x00000000, 761 PRE_DEGAM_GAMMA_22 = 0x00000001, 762 PRE_DEGAM_GAMMA_24 = 0x00000002, 763 PRE_DEGAM_GAMMA_26 = 0x00000003, 764 PRE_DEGAM_BT2020 = 0x00000004, 765 PRE_DEGAM_BT2100PQ = 0x00000005, 766 PRE_DEGAM_BT2100HLG = 0x00000006, 767 } PRE_DEGAM_SELECT; 768 769 /* 770 * SURFACE_PIXEL_FORMAT enum 771 */ 772 773 typedef enum SURFACE_PIXEL_FORMAT { 774 ARGB1555 = 0x00000001, 775 RGBA5551 = 0x00000002, 776 RGB565 = 0x00000003, 777 BGR565 = 0x00000004, 778 ARGB4444 = 0x00000005, 779 RGBA4444 = 0x00000006, 780 ARGB8888 = 0x00000008, 781 RGBA8888 = 0x00000009, 782 ARGB2101010 = 0x0000000a, 783 RGBA1010102 = 0x0000000b, 784 AYCrCb8888 = 0x0000000c, 785 YCrCbA8888 = 0x0000000d, 786 ACrYCb8888 = 0x0000000e, 787 CrYCbA8888 = 0x0000000f, 788 ARGB16161616_10MSB = 0x00000010, 789 RGBA16161616_10MSB = 0x00000011, 790 ARGB16161616_10LSB = 0x00000012, 791 RGBA16161616_10LSB = 0x00000013, 792 ARGB16161616_12MSB = 0x00000014, 793 RGBA16161616_12MSB = 0x00000015, 794 ARGB16161616_12LSB = 0x00000016, 795 RGBA16161616_12LSB = 0x00000017, 796 ARGB16161616_FLOAT = 0x00000018, 797 RGBA16161616_FLOAT = 0x00000019, 798 ARGB16161616_UNORM = 0x0000001a, 799 RGBA16161616_UNORM = 0x0000001b, 800 ARGB16161616_SNORM = 0x0000001c, 801 RGBA16161616_SNORM = 0x0000001d, 802 AYCrCb16161616_10MSB = 0x00000020, 803 AYCrCb16161616_10LSB = 0x00000021, 804 YCrCbA16161616_10MSB = 0x00000022, 805 YCrCbA16161616_10LSB = 0x00000023, 806 ACrYCb16161616_10MSB = 0x00000024, 807 ACrYCb16161616_10LSB = 0x00000025, 808 CrYCbA16161616_10MSB = 0x00000026, 809 CrYCbA16161616_10LSB = 0x00000027, 810 AYCrCb16161616_12MSB = 0x00000028, 811 AYCrCb16161616_12LSB = 0x00000029, 812 YCrCbA16161616_12MSB = 0x0000002a, 813 YCrCbA16161616_12LSB = 0x0000002b, 814 ACrYCb16161616_12MSB = 0x0000002c, 815 ACrYCb16161616_12LSB = 0x0000002d, 816 CrYCbA16161616_12MSB = 0x0000002e, 817 CrYCbA16161616_12LSB = 0x0000002f, 818 Y8_CrCb88_420_PLANAR = 0x00000040, 819 Y8_CbCr88_420_PLANAR = 0x00000041, 820 Y10_CrCb1010_420_PLANAR = 0x00000042, 821 Y10_CbCr1010_420_PLANAR = 0x00000043, 822 Y12_CrCb1212_420_PLANAR = 0x00000044, 823 Y12_CbCr1212_420_PLANAR = 0x00000045, 824 YCrYCb8888_422_PACKED = 0x00000048, 825 YCbYCr8888_422_PACKED = 0x00000049, 826 CrYCbY8888_422_PACKED = 0x0000004a, 827 CbYCrY8888_422_PACKED = 0x0000004b, 828 YCrYCb10101010_422_PACKED = 0x0000004c, 829 YCbYCr10101010_422_PACKED = 0x0000004d, 830 CrYCbY10101010_422_PACKED = 0x0000004e, 831 CbYCrY10101010_422_PACKED = 0x0000004f, 832 YCrYCb12121212_422_PACKED = 0x00000050, 833 YCbYCr12121212_422_PACKED = 0x00000051, 834 CrYCbY12121212_422_PACKED = 0x00000052, 835 CbYCrY12121212_422_PACKED = 0x00000053, 836 RGB111110_FIX = 0x00000070, 837 BGR101111_FIX = 0x00000071, 838 ACrYCb2101010 = 0x00000072, 839 CrYCbA1010102 = 0x00000073, 840 RGBE = 0x00000074, 841 RGB111110_FLOAT = 0x00000076, 842 BGR101111_FLOAT = 0x00000077, 843 MONO_8 = 0x00000078, 844 MONO_10MSB = 0x00000079, 845 MONO_10LSB = 0x0000007a, 846 MONO_12MSB = 0x0000007b, 847 MONO_12LSB = 0x0000007c, 848 MONO_16 = 0x0000007d, 849 } SURFACE_PIXEL_FORMAT; 850 851 /* 852 * XNORM enum 853 */ 854 855 typedef enum XNORM { 856 XNORM_A = 0x00000000, 857 XNORM_B = 0x00000001, 858 } XNORM; 859 860 /* 861 * CUR_ENABLE enum 862 */ 863 864 typedef enum CUR_ENABLE { 865 CUR_DIS = 0x00000000, 866 CUR_EN = 0x00000001, 867 } CUR_ENABLE; 868 869 /* 870 * CUR_EXPAND_MODE enum 871 */ 872 873 typedef enum CUR_EXPAND_MODE { 874 CUR_DYNAMIC_EXPANSION = 0x00000000, 875 CUR_ZERO_EXPANSION = 0x00000001, 876 } CUR_EXPAND_MODE; 877 878 /* 879 * CUR_INV_CLAMP enum 880 */ 881 882 typedef enum CUR_INV_CLAMP { 883 CUR_CLAMP_DIS = 0x00000000, 884 CUR_CLAMP_EN = 0x00000001, 885 } CUR_INV_CLAMP; 886 887 /* 888 * CUR_MATRIX_COEF_FORMAT_ENUM enum 889 */ 890 891 typedef enum CUR_MATRIX_COEF_FORMAT_ENUM { 892 CUR_MATRIX_FIX_S2_13 = 0x00000000, 893 CUR_MATRIX_FIX_S3_12 = 0x00000001, 894 } CUR_MATRIX_COEF_FORMAT_ENUM; 895 896 /* 897 * CUR_MODE enum 898 */ 899 900 typedef enum CUR_MODE { 901 MONO_2BIT = 0x00000000, 902 COLOR_24BIT_1BIT_AND = 0x00000001, 903 COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, 904 COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, 905 COLOR_64BIT_FP_PREMULT = 0x00000004, 906 COLOR_64BIT_FP_UNPREMULT = 0x00000005, 907 } CUR_MODE; 908 909 /* 910 * CUR_PENDING enum 911 */ 912 913 typedef enum CUR_PENDING { 914 CUR_NOT_PENDING = 0x00000000, 915 CUR_YES_PENDING = 0x00000001, 916 } CUR_PENDING; 917 918 /* 919 * CUR_ROM_EN enum 920 */ 921 922 typedef enum CUR_ROM_EN { 923 CUR_FP_NO_ROM = 0x00000000, 924 CUR_FP_USE_ROM = 0x00000001, 925 } CUR_ROM_EN; 926 927 /* 928 * COEF_RAM_SELECT_RD enum 929 */ 930 931 typedef enum COEF_RAM_SELECT_RD { 932 COEF_RAM_SELECT_BACK = 0x00000000, 933 COEF_RAM_SELECT_CURRENT = 0x00000001, 934 } COEF_RAM_SELECT_RD; 935 936 /* 937 * DSCL_MODE_SEL enum 938 */ 939 940 typedef enum DSCL_MODE_SEL { 941 DSCL_MODE_SCALING_444_BYPASS = 0x00000000, 942 DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, 943 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, 944 DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, 945 DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004, 946 DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005, 947 DSCL_MODE_DSCL_BYPASS = 0x00000006, 948 } DSCL_MODE_SEL; 949 950 /* 951 * ISHARP_FMT_MODE_ENUM enum 952 */ 953 954 typedef enum ISHARP_FMT_MODE_ENUM { 955 ISHARP_FMT_MODE_0 = 0x00000000, 956 ISHARP_FMT_MODE_1 = 0x00000001, 957 } ISHARP_FMT_MODE_ENUM; 958 959 /* 960 * ISHARP_LBA_MODE_ENUM enum 961 */ 962 963 typedef enum ISHARP_LBA_MODE_ENUM { 964 ISHARP_LBA_MODE_0 = 0x00000000, 965 ISHARP_LBA_MODE_1 = 0x00000001, 966 } ISHARP_LBA_MODE_ENUM; 967 968 /* 969 * ISHARP_NOISEDET_MODE_ENUM enum 970 */ 971 972 typedef enum ISHARP_NOISEDET_MODE_ENUM { 973 ISHARP_NOISEDET_MODE_0 = 0x00000000, 974 ISHARP_NOISEDET_MODE_1 = 0x00000001, 975 ISHARP_NOISEDET_MODE_2 = 0x00000002, 976 ISHARP_NOISEDET_MODE_3 = 0x00000003, 977 } ISHARP_NOISEDET_MODE_ENUM; 978 979 /* 980 * LB_ALPHA_EN enum 981 */ 982 983 typedef enum LB_ALPHA_EN { 984 LB_ALPHA_DISABLE = 0x00000000, 985 LB_ALPHA_ENABLE = 0x00000001, 986 } LB_ALPHA_EN; 987 988 /* 989 * LB_INTERLEAVE_EN enum 990 */ 991 992 typedef enum LB_INTERLEAVE_EN { 993 LB_INTERLEAVE_DISABLE = 0x00000000, 994 LB_INTERLEAVE_ENABLE = 0x00000001, 995 } LB_INTERLEAVE_EN; 996 997 /* 998 * LB_MEMORY_CONFIG enum 999 */ 1000 1001 typedef enum LB_MEMORY_CONFIG { 1002 LB_MEMORY_CONFIG_0 = 0x00000000, 1003 LB_MEMORY_CONFIG_1 = 0x00000001, 1004 LB_MEMORY_CONFIG_2 = 0x00000002, 1005 LB_MEMORY_CONFIG_3 = 0x00000003, 1006 } LB_MEMORY_CONFIG; 1007 1008 /* 1009 * MATRIX_MODE_ENUM enum 1010 */ 1011 1012 typedef enum MATRIX_MODE_ENUM { 1013 MATRIX_MODE_0 = 0x00000000, 1014 MATRIX_MODE_1 = 0x00000001, 1015 } MATRIX_MODE_ENUM; 1016 1017 /* 1018 * OBUF_BYPASS_SEL enum 1019 */ 1020 1021 typedef enum OBUF_BYPASS_SEL { 1022 OBUF_BYPASS_DIS = 0x00000000, 1023 OBUF_BYPASS_EN = 0x00000001, 1024 } OBUF_BYPASS_SEL; 1025 1026 /* 1027 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum 1028 */ 1029 1030 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL { 1031 OBUF_FULL_RECOUT = 0x00000000, 1032 OBUF_HALF_RECOUT = 0x00000001, 1033 } OBUF_IS_HALF_RECOUT_WIDTH_SEL; 1034 1035 /* 1036 * OBUF_USE_FULL_BUFFER_SEL enum 1037 */ 1038 1039 typedef enum OBUF_USE_FULL_BUFFER_SEL { 1040 OBUF_RECOUT = 0x00000000, 1041 OBUF_FULL = 0x00000001, 1042 } OBUF_USE_FULL_BUFFER_SEL; 1043 1044 /* 1045 * SCL_2TAP_HARDCODE enum 1046 */ 1047 1048 typedef enum SCL_2TAP_HARDCODE { 1049 SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000, 1050 SCL_COEF_2TAP_HARDCODE_ON = 0x00000001, 1051 } SCL_2TAP_HARDCODE; 1052 1053 /* 1054 * SCL_ALPHA_COEF enum 1055 */ 1056 1057 typedef enum SCL_ALPHA_COEF { 1058 SCL_ALPHA_COEF_FIRST = 0x00000000, 1059 SCL_ALPHA_COEF_SECOND = 0x00000001, 1060 } SCL_ALPHA_COEF; 1061 1062 /* 1063 * SCL_AUTOCAL_MODE enum 1064 */ 1065 1066 typedef enum SCL_AUTOCAL_MODE { 1067 AUTOCAL_MODE_OFF = 0x00000000, 1068 AUTOCAL_MODE_AUTOSCALE = 0x00000001, 1069 AUTOCAL_MODE_AUTOCENTER = 0x00000002, 1070 AUTOCAL_MODE_AUTOREPLICATE = 0x00000003, 1071 } SCL_AUTOCAL_MODE; 1072 1073 /* 1074 * SCL_BOUNDARY enum 1075 */ 1076 1077 typedef enum SCL_BOUNDARY { 1078 SCL_BOUNDARY_EDGE = 0x00000000, 1079 SCL_BOUNDARY_BLACK = 0x00000001, 1080 } SCL_BOUNDARY; 1081 1082 /* 1083 * SCL_CHROMA_COEF enum 1084 */ 1085 1086 typedef enum SCL_CHROMA_COEF { 1087 SCL_CHROMA_COEF_FIRST = 0x00000000, 1088 SCL_CHROMA_COEF_SECOND = 0x00000001, 1089 } SCL_CHROMA_COEF; 1090 1091 /* 1092 * SCL_COEF_FILTER_TYPE_SEL enum 1093 */ 1094 1095 typedef enum SCL_COEF_FILTER_TYPE_SEL { 1096 SCL_COEF_LUMA_VERT_FILTER = 0x00000000, 1097 SCL_COEF_LUMA_HORZ_FILTER = 0x00000001, 1098 SCL_COEF_CHROMA_VERT_FILTER = 0x00000002, 1099 SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, 1100 SCL_COEF_SC_VERT_FILTER = 0x00000004, 1101 SCL_COEF_SC_HORZ_FILTER = 0x00000005, 1102 } SCL_COEF_FILTER_TYPE_SEL; 1103 1104 /* 1105 * SCL_COEF_RAM_SEL enum 1106 */ 1107 1108 typedef enum SCL_COEF_RAM_SEL { 1109 SCL_COEF_RAM_SEL_0 = 0x00000000, 1110 SCL_COEF_RAM_SEL_1 = 0x00000001, 1111 } SCL_COEF_RAM_SEL; 1112 1113 /* 1114 * SCL_SHARP_EN enum 1115 */ 1116 1117 typedef enum SCL_SHARP_EN { 1118 SCL_SHARP_DISABLE = 0x00000000, 1119 SCL_SHARP_ENABLE = 0x00000001, 1120 } SCL_SHARP_EN; 1121 1122 /******************************************************* 1123 * CM Enums 1124 *******************************************************/ 1125 1126 /* 1127 * CMC_3DLUT_30BIT_ENUM enum 1128 */ 1129 1130 typedef enum CMC_3DLUT_30BIT_ENUM { 1131 CMC_3DLUT_36BIT = 0x00000000, 1132 CMC_3DLUT_30BIT = 0x00000001, 1133 } CMC_3DLUT_30BIT_ENUM; 1134 1135 /* 1136 * CMC_3DLUT_RAM_SEL enum 1137 */ 1138 1139 typedef enum CMC_3DLUT_RAM_SEL { 1140 CMC_RAM0_ACCESS = 0x00000000, 1141 CMC_RAM1_ACCESS = 0x00000001, 1142 CMC_RAM2_ACCESS = 0x00000002, 1143 CMC_RAM3_ACCESS = 0x00000003, 1144 } CMC_3DLUT_RAM_SEL; 1145 1146 /* 1147 * CMC_3DLUT_SIZE_ENUM enum 1148 */ 1149 1150 typedef enum CMC_3DLUT_SIZE_ENUM { 1151 CMC_3DLUT_17CUBE = 0x00000000, 1152 CMC_3DLUT_9CUBE = 0x00000001, 1153 } CMC_3DLUT_SIZE_ENUM; 1154 1155 /* 1156 * CMC_LUT_2_CONFIG_ENUM enum 1157 */ 1158 1159 typedef enum CMC_LUT_2_CONFIG_ENUM { 1160 CMC_LUT_2CFG_NO_MEMORY = 0x00000000, 1161 CMC_LUT_2CFG_MEMORY_A = 0x00000001, 1162 CMC_LUT_2CFG_MEMORY_B = 0x00000002, 1163 } CMC_LUT_2_CONFIG_ENUM; 1164 1165 /* 1166 * CMC_LUT_2_MODE_ENUM enum 1167 */ 1168 1169 typedef enum CMC_LUT_2_MODE_ENUM { 1170 CMC_LUT_2_MODE_BYPASS = 0x00000000, 1171 CMC_LUT_2_MODE_RAMA_LUT = 0x00000001, 1172 CMC_LUT_2_MODE_RAMB_LUT = 0x00000002, 1173 } CMC_LUT_2_MODE_ENUM; 1174 1175 /* 1176 * CMC_LUT_NUM_SEG enum 1177 */ 1178 1179 typedef enum CMC_LUT_NUM_SEG { 1180 CMC_SEGMENTS_1 = 0x00000000, 1181 CMC_SEGMENTS_2 = 0x00000001, 1182 CMC_SEGMENTS_4 = 0x00000002, 1183 CMC_SEGMENTS_8 = 0x00000003, 1184 CMC_SEGMENTS_16 = 0x00000004, 1185 CMC_SEGMENTS_32 = 0x00000005, 1186 CMC_SEGMENTS_64 = 0x00000006, 1187 CMC_SEGMENTS_128 = 0x00000007, 1188 } CMC_LUT_NUM_SEG; 1189 1190 /* 1191 * CMC_LUT_RAM_SEL enum 1192 */ 1193 1194 typedef enum CMC_LUT_RAM_SEL { 1195 CMC_RAMA_ACCESS = 0x00000000, 1196 CMC_RAMB_ACCESS = 0x00000001, 1197 } CMC_LUT_RAM_SEL; 1198 1199 /* 1200 * CM_BYPASS enum 1201 */ 1202 1203 typedef enum CM_BYPASS { 1204 NON_BYPASS = 0x00000000, 1205 BYPASS_EN = 0x00000001, 1206 } CM_BYPASS; 1207 1208 /* 1209 * CM_COEF_FORMAT_ENUM enum 1210 */ 1211 1212 typedef enum CM_COEF_FORMAT_ENUM { 1213 FIX_S2_13 = 0x00000000, 1214 FIX_S3_12 = 0x00000001, 1215 } CM_COEF_FORMAT_ENUM; 1216 1217 /* 1218 * CM_DATA_SIGNED enum 1219 */ 1220 1221 typedef enum CM_DATA_SIGNED { 1222 UNSIGNED = 0x00000000, 1223 SIGNED = 0x00000001, 1224 } CM_DATA_SIGNED; 1225 1226 /* 1227 * CM_EN enum 1228 */ 1229 1230 typedef enum CM_EN { 1231 CM_DISABLE = 0x00000000, 1232 CM_ENABLE = 0x00000001, 1233 } CM_EN; 1234 1235 /* 1236 * CM_GAMMA_LUT_MODE_ENUM enum 1237 */ 1238 1239 typedef enum CM_GAMMA_LUT_MODE_ENUM { 1240 BYPASS = 0x00000000, 1241 RESERVED_1 = 0x00000001, 1242 RAM_LUT = 0x00000002, 1243 RESERVED_3 = 0x00000003, 1244 } CM_GAMMA_LUT_MODE_ENUM; 1245 1246 /* 1247 * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum 1248 */ 1249 1250 typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM { 1251 ENABLE_PWL = 0x00000000, 1252 DISABLE_PWL = 0x00000001, 1253 } CM_GAMMA_LUT_PWL_DISABLE_ENUM; 1254 1255 /* 1256 * CM_GAMMA_LUT_SEL_ENUM enum 1257 */ 1258 1259 typedef enum CM_GAMMA_LUT_SEL_ENUM { 1260 RAMA = 0x00000000, 1261 RAMB = 0x00000001, 1262 } CM_GAMMA_LUT_SEL_ENUM; 1263 1264 /* 1265 * CM_LUT_2_CONFIG_ENUM enum 1266 */ 1267 1268 typedef enum CM_LUT_2_CONFIG_ENUM { 1269 LUT_2CFG_NO_MEMORY = 0x00000000, 1270 LUT_2CFG_MEMORY_A = 0x00000001, 1271 LUT_2CFG_MEMORY_B = 0x00000002, 1272 } CM_LUT_2_CONFIG_ENUM; 1273 1274 /* 1275 * CM_LUT_2_MODE_ENUM enum 1276 */ 1277 1278 typedef enum CM_LUT_2_MODE_ENUM { 1279 LUT_2_MODE_BYPASS = 0x00000000, 1280 LUT_2_MODE_RAMA_LUT = 0x00000001, 1281 LUT_2_MODE_RAMB_LUT = 0x00000002, 1282 } CM_LUT_2_MODE_ENUM; 1283 1284 /* 1285 * CM_LUT_4_CONFIG_ENUM enum 1286 */ 1287 1288 typedef enum CM_LUT_4_CONFIG_ENUM { 1289 LUT_4CFG_NO_MEMORY = 0x00000000, 1290 LUT_4CFG_ROM_A = 0x00000001, 1291 LUT_4CFG_ROM_B = 0x00000002, 1292 LUT_4CFG_MEMORY_A = 0x00000003, 1293 LUT_4CFG_MEMORY_B = 0x00000004, 1294 } CM_LUT_4_CONFIG_ENUM; 1295 1296 /* 1297 * CM_LUT_4_MODE_ENUM enum 1298 */ 1299 1300 typedef enum CM_LUT_4_MODE_ENUM { 1301 LUT_4_MODE_BYPASS = 0x00000000, 1302 LUT_4_MODE_ROMA_LUT = 0x00000001, 1303 LUT_4_MODE_ROMB_LUT = 0x00000002, 1304 LUT_4_MODE_RAMA_LUT = 0x00000003, 1305 LUT_4_MODE_RAMB_LUT = 0x00000004, 1306 } CM_LUT_4_MODE_ENUM; 1307 1308 /* 1309 * CM_LUT_CONFIG_MODE enum 1310 */ 1311 1312 typedef enum CM_LUT_CONFIG_MODE { 1313 DIFFERENT_RGB = 0x00000000, 1314 ALL_USE_R = 0x00000001, 1315 } CM_LUT_CONFIG_MODE; 1316 1317 /* 1318 * CM_LUT_NUM_SEG enum 1319 */ 1320 1321 typedef enum CM_LUT_NUM_SEG { 1322 SEGMENTS_1 = 0x00000000, 1323 SEGMENTS_2 = 0x00000001, 1324 SEGMENTS_4 = 0x00000002, 1325 SEGMENTS_8 = 0x00000003, 1326 SEGMENTS_16 = 0x00000004, 1327 SEGMENTS_32 = 0x00000005, 1328 SEGMENTS_64 = 0x00000006, 1329 SEGMENTS_128 = 0x00000007, 1330 } CM_LUT_NUM_SEG; 1331 1332 /* 1333 * CM_LUT_RAM_SEL enum 1334 */ 1335 1336 typedef enum CM_LUT_RAM_SEL { 1337 RAMA_ACCESS = 0x00000000, 1338 RAMB_ACCESS = 0x00000001, 1339 } CM_LUT_RAM_SEL; 1340 1341 /* 1342 * CM_LUT_READ_COLOR_SEL enum 1343 */ 1344 1345 typedef enum CM_LUT_READ_COLOR_SEL { 1346 BLUE_LUT = 0x00000000, 1347 GREEN_LUT = 0x00000001, 1348 RED_LUT = 0x00000002, 1349 } CM_LUT_READ_COLOR_SEL; 1350 1351 /* 1352 * CM_LUT_READ_DBG enum 1353 */ 1354 1355 typedef enum CM_LUT_READ_DBG { 1356 DISABLE_DEBUG = 0x00000000, 1357 ENABLE_DEBUG = 0x00000001, 1358 } CM_LUT_READ_DBG; 1359 1360 /* 1361 * CM_PENDING enum 1362 */ 1363 1364 typedef enum CM_PENDING { 1365 CM_NOT_PENDING = 0x00000000, 1366 CM_YES_PENDING = 0x00000001, 1367 } CM_PENDING; 1368 1369 /* 1370 * CM_POST_CSC_MODE_ENUM enum 1371 */ 1372 1373 typedef enum CM_POST_CSC_MODE_ENUM { 1374 BYPASS_POST_CSC = 0x00000000, 1375 COEF_POST_CSC = 0x00000001, 1376 COEF_POST_CSC_B = 0x00000002, 1377 } CM_POST_CSC_MODE_ENUM; 1378 1379 /* 1380 * CM_WRITE_BASE_ONLY enum 1381 */ 1382 1383 typedef enum CM_WRITE_BASE_ONLY { 1384 WRITE_BOTH = 0x00000000, 1385 WRITE_BASE_ONLY = 0x00000001, 1386 } CM_WRITE_BASE_ONLY; 1387 1388 /******************************************************* 1389 * DPP_TOP Enums 1390 *******************************************************/ 1391 1392 /* 1393 * CRC_CUR_SEL enum 1394 */ 1395 1396 typedef enum CRC_CUR_SEL { 1397 CRC_CUR_0 = 0x00000000, 1398 CRC_CUR_1 = 0x00000001, 1399 } CRC_CUR_SEL; 1400 1401 /* 1402 * CRC_INTERLACE_SEL enum 1403 */ 1404 1405 typedef enum CRC_INTERLACE_SEL { 1406 CRC_INTERLACE_0 = 0x00000000, 1407 CRC_INTERLACE_1 = 0x00000001, 1408 CRC_INTERLACE_2 = 0x00000002, 1409 CRC_INTERLACE_3 = 0x00000003, 1410 } CRC_INTERLACE_SEL; 1411 1412 /* 1413 * CRC_IN_PIX_SEL enum 1414 */ 1415 1416 typedef enum CRC_IN_PIX_SEL { 1417 CRC_IN_PIX_0 = 0x00000000, 1418 CRC_IN_PIX_1 = 0x00000001, 1419 CRC_IN_PIX_2 = 0x00000002, 1420 CRC_IN_PIX_3 = 0x00000003, 1421 CRC_IN_PIX_4 = 0x00000004, 1422 CRC_IN_PIX_5 = 0x00000005, 1423 CRC_IN_PIX_6 = 0x00000006, 1424 CRC_IN_PIX_7 = 0x00000007, 1425 } CRC_IN_PIX_SEL; 1426 1427 /* 1428 * CRC_SRC_SEL enum 1429 */ 1430 1431 typedef enum CRC_SRC_SEL { 1432 CRC_SRC_0 = 0x00000000, 1433 CRC_SRC_1 = 0x00000001, 1434 CRC_SRC_2 = 0x00000002, 1435 CRC_SRC_3 = 0x00000003, 1436 } CRC_SRC_SEL; 1437 1438 /* 1439 * CRC_STEREO_SEL enum 1440 */ 1441 1442 typedef enum CRC_STEREO_SEL { 1443 CRC_STEREO_0 = 0x00000000, 1444 CRC_STEREO_1 = 0x00000001, 1445 CRC_STEREO_2 = 0x00000002, 1446 CRC_STEREO_3 = 0x00000003, 1447 } CRC_STEREO_SEL; 1448 1449 /* 1450 * TEST_CLK_SEL enum 1451 */ 1452 1453 typedef enum TEST_CLK_SEL { 1454 TEST_CLK_SEL_0 = 0x00000000, 1455 TEST_CLK_SEL_1 = 0x00000001, 1456 TEST_CLK_SEL_2 = 0x00000002, 1457 TEST_CLK_SEL_3 = 0x00000003, 1458 TEST_CLK_SEL_4 = 0x00000004, 1459 TEST_CLK_SEL_5 = 0x00000005, 1460 TEST_CLK_SEL_6 = 0x00000006, 1461 TEST_CLK_SEL_7 = 0x00000007, 1462 } TEST_CLK_SEL; 1463 1464 /******************************************************* 1465 * DC_PERFMON Enums 1466 *******************************************************/ 1467 1468 /* 1469 * PERFCOUNTER_ACTIVE enum 1470 */ 1471 1472 typedef enum PERFCOUNTER_ACTIVE { 1473 PERFCOUNTER_IS_IDLE = 0x00000000, 1474 PERFCOUNTER_IS_ACTIVE = 0x00000001, 1475 } PERFCOUNTER_ACTIVE; 1476 1477 /* 1478 * PERFCOUNTER_CNT0_STATE enum 1479 */ 1480 1481 typedef enum PERFCOUNTER_CNT0_STATE { 1482 PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, 1483 PERFCOUNTER_CNT0_STATE_START = 0x00000001, 1484 PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, 1485 PERFCOUNTER_CNT0_STATE_HW = 0x00000003, 1486 } PERFCOUNTER_CNT0_STATE; 1487 1488 /* 1489 * PERFCOUNTER_CNT1_STATE enum 1490 */ 1491 1492 typedef enum PERFCOUNTER_CNT1_STATE { 1493 PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, 1494 PERFCOUNTER_CNT1_STATE_START = 0x00000001, 1495 PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, 1496 PERFCOUNTER_CNT1_STATE_HW = 0x00000003, 1497 } PERFCOUNTER_CNT1_STATE; 1498 1499 /* 1500 * PERFCOUNTER_CNT2_STATE enum 1501 */ 1502 1503 typedef enum PERFCOUNTER_CNT2_STATE { 1504 PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, 1505 PERFCOUNTER_CNT2_STATE_START = 0x00000001, 1506 PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, 1507 PERFCOUNTER_CNT2_STATE_HW = 0x00000003, 1508 } PERFCOUNTER_CNT2_STATE; 1509 1510 /* 1511 * PERFCOUNTER_CNT3_STATE enum 1512 */ 1513 1514 typedef enum PERFCOUNTER_CNT3_STATE { 1515 PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, 1516 PERFCOUNTER_CNT3_STATE_START = 0x00000001, 1517 PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, 1518 PERFCOUNTER_CNT3_STATE_HW = 0x00000003, 1519 } PERFCOUNTER_CNT3_STATE; 1520 1521 /* 1522 * PERFCOUNTER_CNT4_STATE enum 1523 */ 1524 1525 typedef enum PERFCOUNTER_CNT4_STATE { 1526 PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, 1527 PERFCOUNTER_CNT4_STATE_START = 0x00000001, 1528 PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, 1529 PERFCOUNTER_CNT4_STATE_HW = 0x00000003, 1530 } PERFCOUNTER_CNT4_STATE; 1531 1532 /* 1533 * PERFCOUNTER_CNT5_STATE enum 1534 */ 1535 1536 typedef enum PERFCOUNTER_CNT5_STATE { 1537 PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, 1538 PERFCOUNTER_CNT5_STATE_START = 0x00000001, 1539 PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, 1540 PERFCOUNTER_CNT5_STATE_HW = 0x00000003, 1541 } PERFCOUNTER_CNT5_STATE; 1542 1543 /* 1544 * PERFCOUNTER_CNT6_STATE enum 1545 */ 1546 1547 typedef enum PERFCOUNTER_CNT6_STATE { 1548 PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, 1549 PERFCOUNTER_CNT6_STATE_START = 0x00000001, 1550 PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, 1551 PERFCOUNTER_CNT6_STATE_HW = 0x00000003, 1552 } PERFCOUNTER_CNT6_STATE; 1553 1554 /* 1555 * PERFCOUNTER_CNT7_STATE enum 1556 */ 1557 1558 typedef enum PERFCOUNTER_CNT7_STATE { 1559 PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, 1560 PERFCOUNTER_CNT7_STATE_START = 0x00000001, 1561 PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, 1562 PERFCOUNTER_CNT7_STATE_HW = 0x00000003, 1563 } PERFCOUNTER_CNT7_STATE; 1564 1565 /* 1566 * PERFCOUNTER_CNTL_SEL enum 1567 */ 1568 1569 typedef enum PERFCOUNTER_CNTL_SEL { 1570 PERFCOUNTER_CNTL_SEL_0 = 0x00000000, 1571 PERFCOUNTER_CNTL_SEL_1 = 0x00000001, 1572 PERFCOUNTER_CNTL_SEL_2 = 0x00000002, 1573 PERFCOUNTER_CNTL_SEL_3 = 0x00000003, 1574 PERFCOUNTER_CNTL_SEL_4 = 0x00000004, 1575 PERFCOUNTER_CNTL_SEL_5 = 0x00000005, 1576 PERFCOUNTER_CNTL_SEL_6 = 0x00000006, 1577 PERFCOUNTER_CNTL_SEL_7 = 0x00000007, 1578 } PERFCOUNTER_CNTL_SEL; 1579 1580 /* 1581 * PERFCOUNTER_CNTOFF_START_DIS enum 1582 */ 1583 1584 typedef enum PERFCOUNTER_CNTOFF_START_DIS { 1585 PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, 1586 PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, 1587 } PERFCOUNTER_CNTOFF_START_DIS; 1588 1589 /* 1590 * PERFCOUNTER_COUNTED_VALUE_TYPE enum 1591 */ 1592 1593 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { 1594 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, 1595 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, 1596 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, 1597 } PERFCOUNTER_COUNTED_VALUE_TYPE; 1598 1599 /* 1600 * PERFCOUNTER_CVALUE_SEL enum 1601 */ 1602 1603 typedef enum PERFCOUNTER_CVALUE_SEL { 1604 PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, 1605 PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, 1606 PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, 1607 PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, 1608 PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, 1609 PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, 1610 PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, 1611 PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, 1612 } PERFCOUNTER_CVALUE_SEL; 1613 1614 /* 1615 * PERFCOUNTER_HW_CNTL_SEL enum 1616 */ 1617 1618 typedef enum PERFCOUNTER_HW_CNTL_SEL { 1619 PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, 1620 PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, 1621 } PERFCOUNTER_HW_CNTL_SEL; 1622 1623 /* 1624 * PERFCOUNTER_HW_STOP1_SEL enum 1625 */ 1626 1627 typedef enum PERFCOUNTER_HW_STOP1_SEL { 1628 PERFCOUNTER_HW_STOP1_0 = 0x00000000, 1629 PERFCOUNTER_HW_STOP1_1 = 0x00000001, 1630 } PERFCOUNTER_HW_STOP1_SEL; 1631 1632 /* 1633 * PERFCOUNTER_HW_STOP2_SEL enum 1634 */ 1635 1636 typedef enum PERFCOUNTER_HW_STOP2_SEL { 1637 PERFCOUNTER_HW_STOP2_0 = 0x00000000, 1638 PERFCOUNTER_HW_STOP2_1 = 0x00000001, 1639 } PERFCOUNTER_HW_STOP2_SEL; 1640 1641 /* 1642 * PERFCOUNTER_INC_MODE enum 1643 */ 1644 1645 typedef enum PERFCOUNTER_INC_MODE { 1646 PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, 1647 PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, 1648 PERFCOUNTER_INC_MODE_LSB = 0x00000002, 1649 PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, 1650 PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, 1651 } PERFCOUNTER_INC_MODE; 1652 1653 /* 1654 * PERFCOUNTER_INT_EN enum 1655 */ 1656 1657 typedef enum PERFCOUNTER_INT_EN { 1658 PERFCOUNTER_INT_DISABLE = 0x00000000, 1659 PERFCOUNTER_INT_ENABLE = 0x00000001, 1660 } PERFCOUNTER_INT_EN; 1661 1662 /* 1663 * PERFCOUNTER_INT_TYPE enum 1664 */ 1665 1666 typedef enum PERFCOUNTER_INT_TYPE { 1667 PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, 1668 PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, 1669 } PERFCOUNTER_INT_TYPE; 1670 1671 /* 1672 * PERFCOUNTER_OFF_MASK enum 1673 */ 1674 1675 typedef enum PERFCOUNTER_OFF_MASK { 1676 PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, 1677 PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, 1678 } PERFCOUNTER_OFF_MASK; 1679 1680 /* 1681 * PERFCOUNTER_RESTART_EN enum 1682 */ 1683 1684 typedef enum PERFCOUNTER_RESTART_EN { 1685 PERFCOUNTER_RESTART_DISABLE = 0x00000000, 1686 PERFCOUNTER_RESTART_ENABLE = 0x00000001, 1687 } PERFCOUNTER_RESTART_EN; 1688 1689 /* 1690 * PERFCOUNTER_RUNEN_MODE enum 1691 */ 1692 1693 typedef enum PERFCOUNTER_RUNEN_MODE { 1694 PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, 1695 PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, 1696 } PERFCOUNTER_RUNEN_MODE; 1697 1698 /* 1699 * PERFCOUNTER_STATE_SEL0 enum 1700 */ 1701 1702 typedef enum PERFCOUNTER_STATE_SEL0 { 1703 PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, 1704 PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, 1705 } PERFCOUNTER_STATE_SEL0; 1706 1707 /* 1708 * PERFCOUNTER_STATE_SEL1 enum 1709 */ 1710 1711 typedef enum PERFCOUNTER_STATE_SEL1 { 1712 PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, 1713 PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, 1714 } PERFCOUNTER_STATE_SEL1; 1715 1716 /* 1717 * PERFCOUNTER_STATE_SEL2 enum 1718 */ 1719 1720 typedef enum PERFCOUNTER_STATE_SEL2 { 1721 PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, 1722 PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, 1723 } PERFCOUNTER_STATE_SEL2; 1724 1725 /* 1726 * PERFCOUNTER_STATE_SEL3 enum 1727 */ 1728 1729 typedef enum PERFCOUNTER_STATE_SEL3 { 1730 PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, 1731 PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, 1732 } PERFCOUNTER_STATE_SEL3; 1733 1734 /* 1735 * PERFCOUNTER_STATE_SEL4 enum 1736 */ 1737 1738 typedef enum PERFCOUNTER_STATE_SEL4 { 1739 PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, 1740 PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, 1741 } PERFCOUNTER_STATE_SEL4; 1742 1743 /* 1744 * PERFCOUNTER_STATE_SEL5 enum 1745 */ 1746 1747 typedef enum PERFCOUNTER_STATE_SEL5 { 1748 PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, 1749 PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, 1750 } PERFCOUNTER_STATE_SEL5; 1751 1752 /* 1753 * PERFCOUNTER_STATE_SEL6 enum 1754 */ 1755 1756 typedef enum PERFCOUNTER_STATE_SEL6 { 1757 PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, 1758 PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, 1759 } PERFCOUNTER_STATE_SEL6; 1760 1761 /* 1762 * PERFCOUNTER_STATE_SEL7 enum 1763 */ 1764 1765 typedef enum PERFCOUNTER_STATE_SEL7 { 1766 PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, 1767 PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, 1768 } PERFCOUNTER_STATE_SEL7; 1769 1770 /* 1771 * PERFMON_CNTOFF_AND_OR enum 1772 */ 1773 1774 typedef enum PERFMON_CNTOFF_AND_OR { 1775 PERFMON_CNTOFF_OR = 0x00000000, 1776 PERFMON_CNTOFF_AND = 0x00000001, 1777 } PERFMON_CNTOFF_AND_OR; 1778 1779 /* 1780 * PERFMON_CNTOFF_INT_EN enum 1781 */ 1782 1783 typedef enum PERFMON_CNTOFF_INT_EN { 1784 PERFMON_CNTOFF_INT_DISABLE = 0x00000000, 1785 PERFMON_CNTOFF_INT_ENABLE = 0x00000001, 1786 } PERFMON_CNTOFF_INT_EN; 1787 1788 /* 1789 * PERFMON_CNTOFF_INT_TYPE enum 1790 */ 1791 1792 typedef enum PERFMON_CNTOFF_INT_TYPE { 1793 PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, 1794 PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, 1795 } PERFMON_CNTOFF_INT_TYPE; 1796 1797 /* 1798 * PERFMON_STATE enum 1799 */ 1800 1801 typedef enum PERFMON_STATE { 1802 PERFMON_STATE_RESET = 0x00000000, 1803 PERFMON_STATE_START = 0x00000001, 1804 PERFMON_STATE_FREEZE = 0x00000002, 1805 PERFMON_STATE_HW = 0x00000003, 1806 } PERFMON_STATE; 1807 1808 /******************************************************* 1809 * HUBP Enums 1810 *******************************************************/ 1811 1812 /* 1813 * BIGK_FRAGMENT_SIZE enum 1814 */ 1815 1816 typedef enum BIGK_FRAGMENT_SIZE { 1817 VM_PG_SIZE_4KB = 0x00000000, 1818 VM_PG_SIZE_8KB = 0x00000001, 1819 VM_PG_SIZE_16KB = 0x00000002, 1820 VM_PG_SIZE_32KB = 0x00000003, 1821 VM_PG_SIZE_64KB = 0x00000004, 1822 VM_PG_SIZE_128KB = 0x00000005, 1823 VM_PG_SIZE_256KB = 0x00000006, 1824 VM_PG_SIZE_512KB = 0x00000007, 1825 VM_PG_SIZE_1MB = 0x00000008, 1826 VM_PG_SIZE_2MB = 0x00000009, 1827 VM_PG_SIZE_4MB = 0x0000000a, 1828 VM_PG_SIZE_8MB = 0x0000000b, 1829 VM_PG_SIZE_16MB = 0x0000000c, 1830 VM_PG_SIZE_32MB = 0x0000000d, 1831 VM_PG_SIZE_64MB = 0x0000000e, 1832 VM_PG_SIZE_128MB = 0x0000000f, 1833 } BIGK_FRAGMENT_SIZE; 1834 1835 /* 1836 * CHUNK_SIZE enum 1837 */ 1838 1839 typedef enum CHUNK_SIZE { 1840 CHUNK_SIZE_1KB = 0x00000000, 1841 CHUNK_SIZE_2KB = 0x00000001, 1842 CHUNK_SIZE_4KB = 0x00000002, 1843 CHUNK_SIZE_8KB = 0x00000003, 1844 CHUNK_SIZE_16KB = 0x00000004, 1845 CHUNK_SIZE_32KB = 0x00000005, 1846 CHUNK_SIZE_64KB = 0x00000006, 1847 } CHUNK_SIZE; 1848 1849 /* 1850 * DPTE_GROUP_SIZE enum 1851 */ 1852 1853 typedef enum DPTE_GROUP_SIZE { 1854 DPTE_GROUP_SIZE_64B = 0x00000000, 1855 DPTE_GROUP_SIZE_128B = 0x00000001, 1856 DPTE_GROUP_SIZE_256B = 0x00000002, 1857 DPTE_GROUP_SIZE_512B = 0x00000003, 1858 DPTE_GROUP_SIZE_1024B = 0x00000004, 1859 DPTE_GROUP_SIZE_2048B = 0x00000005, 1860 } DPTE_GROUP_SIZE; 1861 1862 /* 1863 * FORCE_ONE_ROW_FOR_FRAME enum 1864 */ 1865 1866 typedef enum FORCE_ONE_ROW_FOR_FRAME { 1867 FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000, 1868 FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001, 1869 } FORCE_ONE_ROW_FOR_FRAME; 1870 1871 /* 1872 * HUBP_BLANK_EN enum 1873 */ 1874 1875 typedef enum HUBP_BLANK_EN { 1876 HUBP_BLANK_SW_DEASSERT = 0x00000000, 1877 HUBP_BLANK_SW_ASSERT = 0x00000001, 1878 } HUBP_BLANK_EN; 1879 1880 /* 1881 * HUBP_IN_BLANK enum 1882 */ 1883 1884 typedef enum HUBP_IN_BLANK { 1885 HUBP_IN_ACTIVE = 0x00000000, 1886 HUBP_IN_VBLANK = 0x00000001, 1887 } HUBP_IN_BLANK; 1888 1889 /* 1890 * HUBP_MEASURE_WIN_MODE_DCFCLK enum 1891 */ 1892 1893 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK { 1894 HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000, 1895 HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001, 1896 HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002, 1897 HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003, 1898 } HUBP_MEASURE_WIN_MODE_DCFCLK; 1899 1900 /* 1901 * HUBP_NO_OUTSTANDING_REQ enum 1902 */ 1903 1904 typedef enum HUBP_NO_OUTSTANDING_REQ { 1905 OUTSTANDING_REQ = 0x00000000, 1906 NO_OUTSTANDING_REQ = 0x00000001, 1907 } HUBP_NO_OUTSTANDING_REQ; 1908 1909 /* 1910 * HUBP_SOFT_RESET enum 1911 */ 1912 1913 typedef enum HUBP_SOFT_RESET { 1914 HUBP_SOFT_RESET_ON = 0x00000000, 1915 HUBP_SOFT_RESET_OFF = 0x00000001, 1916 } HUBP_SOFT_RESET; 1917 1918 /* 1919 * HUBP_TTU_DISABLE enum 1920 */ 1921 1922 typedef enum HUBP_TTU_DISABLE { 1923 HUBP_TTU_ENABLED = 0x00000000, 1924 HUBP_TTU_DISABLED = 0x00000001, 1925 } HUBP_TTU_DISABLE; 1926 1927 /* 1928 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum 1929 */ 1930 1931 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC { 1932 VREADY_BEFORE_VSYNC = 0x00000000, 1933 VREADY_AT_OR_AFTER_VSYNC = 0x00000001, 1934 } HUBP_VREADY_AT_OR_AFTER_VSYNC; 1935 1936 /* 1937 * HUBP_VTG_SEL enum 1938 */ 1939 1940 typedef enum HUBP_VTG_SEL { 1941 VTG_SEL_0 = 0x00000000, 1942 VTG_SEL_1 = 0x00000001, 1943 VTG_SEL_2 = 0x00000002, 1944 VTG_SEL_3 = 0x00000003, 1945 VTG_SEL_4 = 0x00000004, 1946 VTG_SEL_5 = 0x00000005, 1947 } HUBP_VTG_SEL; 1948 1949 /* 1950 * H_MIRROR_EN enum 1951 */ 1952 1953 typedef enum H_MIRROR_EN { 1954 HW_MIRRORING_DISABLE = 0x00000000, 1955 HW_MIRRORING_ENABLE = 0x00000001, 1956 } H_MIRROR_EN; 1957 1958 /* 1959 * LEGACY_PIPE_INTERLEAVE enum 1960 */ 1961 1962 typedef enum LEGACY_PIPE_INTERLEAVE { 1963 LEGACY_PIPE_INTERLEAVE_256B = 0x00000000, 1964 LEGACY_PIPE_INTERLEAVE_512B = 0x00000001, 1965 } LEGACY_PIPE_INTERLEAVE; 1966 1967 /* 1968 * META_CHUNK_SIZE enum 1969 */ 1970 1971 typedef enum META_CHUNK_SIZE { 1972 META_CHUNK_SIZE_1KB = 0x00000000, 1973 META_CHUNK_SIZE_2KB = 0x00000001, 1974 META_CHUNK_SIZE_4KB = 0x00000002, 1975 META_CHUNK_SIZE_8KB = 0x00000003, 1976 } META_CHUNK_SIZE; 1977 1978 /* 1979 * META_LINEAR enum 1980 */ 1981 1982 typedef enum META_LINEAR { 1983 META_SURF_TILED = 0x00000000, 1984 META_SURF_LINEAR = 0x00000001, 1985 } META_LINEAR; 1986 1987 /* 1988 * MIN_CHUNK_SIZE enum 1989 */ 1990 1991 typedef enum MIN_CHUNK_SIZE { 1992 NO_MIN_CHUNK_SIZE = 0x00000000, 1993 MIN_CHUNK_SIZE_256B = 0x00000001, 1994 MIN_CHUNK_SIZE_512B = 0x00000002, 1995 MIN_CHUNK_SIZE_1024B = 0x00000003, 1996 } MIN_CHUNK_SIZE; 1997 1998 /* 1999 * MIN_META_CHUNK_SIZE enum 2000 */ 2001 2002 typedef enum MIN_META_CHUNK_SIZE { 2003 NO_MIN_META_CHUNK_SIZE = 0x00000000, 2004 MIN_META_CHUNK_SIZE_64B = 0x00000001, 2005 MIN_META_CHUNK_SIZE_128B = 0x00000002, 2006 MIN_META_CHUNK_SIZE_256B = 0x00000003, 2007 } MIN_META_CHUNK_SIZE; 2008 2009 /* 2010 * PIPE_ALIGNED enum 2011 */ 2012 2013 typedef enum PIPE_ALIGNED { 2014 PIPE_UNALIGNED_SURF = 0x00000000, 2015 PIPE_ALIGNED_SURF = 0x00000001, 2016 } PIPE_ALIGNED; 2017 2018 /* 2019 * PTE_BUFFER_MODE enum 2020 */ 2021 2022 typedef enum PTE_BUFFER_MODE { 2023 PTE_BUFFER_MODE_0 = 0x00000000, 2024 PTE_BUFFER_MODE_1 = 0x00000001, 2025 } PTE_BUFFER_MODE; 2026 2027 /* 2028 * PTE_ROW_HEIGHT_LINEAR enum 2029 */ 2030 2031 typedef enum PTE_ROW_HEIGHT_LINEAR { 2032 PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000, 2033 PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001, 2034 PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002, 2035 PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003, 2036 PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004, 2037 PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005, 2038 PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006, 2039 PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007, 2040 } PTE_ROW_HEIGHT_LINEAR; 2041 2042 /* 2043 * ROTATION_ANGLE enum 2044 */ 2045 2046 typedef enum ROTATION_ANGLE { 2047 ROTATE_0_DEGREES = 0x00000000, 2048 ROTATE_90_DEGREES = 0x00000001, 2049 ROTATE_180_DEGREES = 0x00000002, 2050 ROTATE_270_DEGREES = 0x00000003, 2051 } ROTATION_ANGLE; 2052 2053 /* 2054 * SWATH_HEIGHT enum 2055 */ 2056 2057 typedef enum SWATH_HEIGHT { 2058 SWATH_HEIGHT_1L = 0x00000000, 2059 SWATH_HEIGHT_2L = 0x00000001, 2060 SWATH_HEIGHT_4L = 0x00000002, 2061 SWATH_HEIGHT_8L = 0x00000003, 2062 SWATH_HEIGHT_16L = 0x00000004, 2063 } SWATH_HEIGHT; 2064 2065 /* 2066 * VMPG_SIZE enum 2067 */ 2068 2069 typedef enum VMPG_SIZE { 2070 VMPG_SIZE_4KB = 0x00000000, 2071 VMPG_SIZE_64KB = 0x00000001, 2072 } VMPG_SIZE; 2073 2074 /* 2075 * VM_GROUP_SIZE enum 2076 */ 2077 2078 typedef enum VM_GROUP_SIZE { 2079 VM_GROUP_SIZE_64B = 0x00000000, 2080 VM_GROUP_SIZE_128B = 0x00000001, 2081 VM_GROUP_SIZE_256B = 0x00000002, 2082 VM_GROUP_SIZE_512B = 0x00000003, 2083 VM_GROUP_SIZE_1024B = 0x00000004, 2084 VM_GROUP_SIZE_2048B = 0x00000005, 2085 } VM_GROUP_SIZE; 2086 2087 /******************************************************* 2088 * HUBPREQ Enums 2089 *******************************************************/ 2090 2091 /* 2092 * DFQ_MIN_FREE_ENTRIES enum 2093 */ 2094 2095 typedef enum DFQ_MIN_FREE_ENTRIES { 2096 DFQ_MIN_FREE_ENTRIES_0 = 0x00000000, 2097 DFQ_MIN_FREE_ENTRIES_1 = 0x00000001, 2098 DFQ_MIN_FREE_ENTRIES_2 = 0x00000002, 2099 DFQ_MIN_FREE_ENTRIES_3 = 0x00000003, 2100 DFQ_MIN_FREE_ENTRIES_4 = 0x00000004, 2101 DFQ_MIN_FREE_ENTRIES_5 = 0x00000005, 2102 DFQ_MIN_FREE_ENTRIES_6 = 0x00000006, 2103 DFQ_MIN_FREE_ENTRIES_7 = 0x00000007, 2104 } DFQ_MIN_FREE_ENTRIES; 2105 2106 /* 2107 * DFQ_NUM_ENTRIES enum 2108 */ 2109 2110 typedef enum DFQ_NUM_ENTRIES { 2111 DFQ_NUM_ENTRIES_0 = 0x00000000, 2112 DFQ_NUM_ENTRIES_1 = 0x00000001, 2113 DFQ_NUM_ENTRIES_2 = 0x00000002, 2114 DFQ_NUM_ENTRIES_3 = 0x00000003, 2115 DFQ_NUM_ENTRIES_4 = 0x00000004, 2116 DFQ_NUM_ENTRIES_5 = 0x00000005, 2117 DFQ_NUM_ENTRIES_6 = 0x00000006, 2118 DFQ_NUM_ENTRIES_7 = 0x00000007, 2119 DFQ_NUM_ENTRIES_8 = 0x00000008, 2120 } DFQ_NUM_ENTRIES; 2121 2122 /* 2123 * DFQ_SIZE enum 2124 */ 2125 2126 typedef enum DFQ_SIZE { 2127 DFQ_SIZE_0 = 0x00000000, 2128 DFQ_SIZE_1 = 0x00000001, 2129 DFQ_SIZE_2 = 0x00000002, 2130 DFQ_SIZE_3 = 0x00000003, 2131 DFQ_SIZE_4 = 0x00000004, 2132 DFQ_SIZE_5 = 0x00000005, 2133 DFQ_SIZE_6 = 0x00000006, 2134 DFQ_SIZE_7 = 0x00000007, 2135 } DFQ_SIZE; 2136 2137 /* 2138 * DMDATA_VM_DONE enum 2139 */ 2140 2141 typedef enum DMDATA_VM_DONE { 2142 DMDATA_VM_IS_NOT_DONE = 0x00000000, 2143 DMDATA_VM_IS_DONE = 0x00000001, 2144 } DMDATA_VM_DONE; 2145 2146 /* 2147 * EXPANSION_MODE enum 2148 */ 2149 2150 typedef enum EXPANSION_MODE { 2151 EXPANSION_MODE_ZERO = 0x00000000, 2152 EXPANSION_MODE_CONSERVATIVE = 0x00000001, 2153 EXPANSION_MODE_OPTIMAL = 0x00000002, 2154 } EXPANSION_MODE; 2155 2156 /* 2157 * FLIP_RATE enum 2158 */ 2159 2160 typedef enum FLIP_RATE { 2161 FLIP_RATE_0 = 0x00000000, 2162 FLIP_RATE_1 = 0x00000001, 2163 FLIP_RATE_2 = 0x00000002, 2164 FLIP_RATE_3 = 0x00000003, 2165 FLIP_RATE_4 = 0x00000004, 2166 FLIP_RATE_5 = 0x00000005, 2167 FLIP_RATE_6 = 0x00000006, 2168 FLIP_RATE_7 = 0x00000007, 2169 } FLIP_RATE; 2170 2171 /* 2172 * INT_MASK enum 2173 */ 2174 2175 typedef enum INT_MASK { 2176 INT_DISABLED = 0x00000000, 2177 INT_ENABLED = 0x00000001, 2178 } INT_MASK; 2179 2180 /* 2181 * PIPE_IN_FLUSH_URGENT enum 2182 */ 2183 2184 typedef enum PIPE_IN_FLUSH_URGENT { 2185 PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000, 2186 PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001, 2187 } PIPE_IN_FLUSH_URGENT; 2188 2189 /* 2190 * PRQ_MRQ_FLUSH_URGENT enum 2191 */ 2192 2193 typedef enum PRQ_MRQ_FLUSH_URGENT { 2194 PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000, 2195 PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001, 2196 } PRQ_MRQ_FLUSH_URGENT; 2197 2198 /* 2199 * ROW_TTU_MODE enum 2200 */ 2201 2202 typedef enum ROW_TTU_MODE { 2203 END_OF_ROW_MODE = 0x00000000, 2204 WATERMARK_MODE = 0x00000001, 2205 } ROW_TTU_MODE; 2206 2207 /* 2208 * SURFACE_DCC enum 2209 */ 2210 2211 typedef enum SURFACE_DCC { 2212 SURFACE_IS_NOT_DCC = 0x00000000, 2213 SURFACE_IS_DCC = 0x00000001, 2214 } SURFACE_DCC; 2215 2216 /* 2217 * SURFACE_DCC_IND_128B enum 2218 */ 2219 2220 typedef enum SURFACE_DCC_IND_128B { 2221 SURFACE_DCC_IS_NOT_IND_128B = 0x00000000, 2222 SURFACE_DCC_IS_IND_128B = 0x00000001, 2223 } SURFACE_DCC_IND_128B; 2224 2225 /* 2226 * SURFACE_DCC_IND_64B enum 2227 */ 2228 2229 typedef enum SURFACE_DCC_IND_64B { 2230 SURFACE_DCC_IS_NOT_IND_64B = 0x00000000, 2231 SURFACE_DCC_IS_IND_64B = 0x00000001, 2232 } SURFACE_DCC_IND_64B; 2233 2234 /* 2235 * SURFACE_DCC_IND_BLK enum 2236 */ 2237 2238 typedef enum SURFACE_DCC_IND_BLK { 2239 SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000, 2240 SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001, 2241 SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002, 2242 SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003, 2243 } SURFACE_DCC_IND_BLK; 2244 2245 /* 2246 * SURFACE_FLIP_AWAY_INT_TYPE enum 2247 */ 2248 2249 typedef enum SURFACE_FLIP_AWAY_INT_TYPE { 2250 SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000, 2251 SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001, 2252 } SURFACE_FLIP_AWAY_INT_TYPE; 2253 2254 /* 2255 * SURFACE_FLIP_EXEC_DEBUG_MODE enum 2256 */ 2257 2258 typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE { 2259 SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000, 2260 SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001, 2261 } SURFACE_FLIP_EXEC_DEBUG_MODE; 2262 2263 /* 2264 * SURFACE_FLIP_INT_TYPE enum 2265 */ 2266 2267 typedef enum SURFACE_FLIP_INT_TYPE { 2268 SURFACE_FLIP_INT_LEVEL = 0x00000000, 2269 SURFACE_FLIP_INT_PULSE = 0x00000001, 2270 } SURFACE_FLIP_INT_TYPE; 2271 2272 /* 2273 * SURFACE_FLIP_IN_STEREOSYNC enum 2274 */ 2275 2276 typedef enum SURFACE_FLIP_IN_STEREOSYNC { 2277 SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000, 2278 SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001, 2279 } SURFACE_FLIP_IN_STEREOSYNC; 2280 2281 /* 2282 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum 2283 */ 2284 2285 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC { 2286 FLIP_ANY_FRAME = 0x00000000, 2287 FLIP_LEFT_EYE = 0x00000001, 2288 FLIP_RIGHT_EYE = 0x00000002, 2289 SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003, 2290 } SURFACE_FLIP_MODE_FOR_STEREOSYNC; 2291 2292 /* 2293 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum 2294 */ 2295 2296 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE { 2297 SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000, 2298 SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001, 2299 } SURFACE_FLIP_STEREO_SELECT_DISABLE; 2300 2301 /* 2302 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum 2303 */ 2304 2305 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY { 2306 SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000, 2307 SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001, 2308 } SURFACE_FLIP_STEREO_SELECT_POLARITY; 2309 2310 /* 2311 * SURFACE_FLIP_TYPE enum 2312 */ 2313 2314 typedef enum SURFACE_FLIP_TYPE { 2315 SURFACE_V_FLIP = 0x00000000, 2316 SURFACE_I_FLIP = 0x00000001, 2317 } SURFACE_FLIP_TYPE; 2318 2319 /* 2320 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum 2321 */ 2322 2323 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM { 2324 SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000, 2325 SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001, 2326 SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002, 2327 SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003, 2328 SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004, 2329 SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005, 2330 SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006, 2331 SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007, 2332 SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008, 2333 SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009, 2334 SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a, 2335 SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b, 2336 SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c, 2337 SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d, 2338 SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e, 2339 SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f, 2340 } SURFACE_FLIP_VUPDATE_SKIP_NUM; 2341 2342 /* 2343 * SURFACE_INUSE_RAED_NO_LATCH enum 2344 */ 2345 2346 typedef enum SURFACE_INUSE_RAED_NO_LATCH { 2347 SURFACE_INUSE_IS_LATCHED = 0x00000000, 2348 SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001, 2349 } SURFACE_INUSE_RAED_NO_LATCH; 2350 2351 /* 2352 * SURFACE_TMZ enum 2353 */ 2354 2355 typedef enum SURFACE_TMZ { 2356 SURFACE_IS_NOT_TMZ = 0x00000000, 2357 SURFACE_IS_TMZ = 0x00000001, 2358 } SURFACE_TMZ; 2359 2360 /* 2361 * SURFACE_UPDATE_LOCK enum 2362 */ 2363 2364 typedef enum SURFACE_UPDATE_LOCK { 2365 SURFACE_UPDATE_IS_UNLOCKED = 0x00000000, 2366 SURFACE_UPDATE_IS_LOCKED = 0x00000001, 2367 } SURFACE_UPDATE_LOCK; 2368 2369 /******************************************************* 2370 * HUBPRET Enums 2371 *******************************************************/ 2372 2373 /* 2374 * CROSSBAR_FOR_ALPHA enum 2375 */ 2376 2377 typedef enum CROSSBAR_FOR_ALPHA { 2378 ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000, 2379 Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001, 2380 CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002, 2381 CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003, 2382 } CROSSBAR_FOR_ALPHA; 2383 2384 /* 2385 * CROSSBAR_FOR_CB_B enum 2386 */ 2387 2388 typedef enum CROSSBAR_FOR_CB_B { 2389 ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000, 2390 Y_G_DATA_ONTO_CB_B_PORT = 0x00000001, 2391 CB_B_DATA_ONTO_CB_B_PORT = 0x00000002, 2392 CR_R_DATA_ONTO_CB_B_PORT = 0x00000003, 2393 } CROSSBAR_FOR_CB_B; 2394 2395 /* 2396 * CROSSBAR_FOR_CR_R enum 2397 */ 2398 2399 typedef enum CROSSBAR_FOR_CR_R { 2400 ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000, 2401 Y_G_DATA_ONTO_CR_R_PORT = 0x00000001, 2402 CB_B_DATA_ONTO_CR_R_PORT = 0x00000002, 2403 CR_R_DATA_ONTO_CR_R_PORT = 0x00000003, 2404 } CROSSBAR_FOR_CR_R; 2405 2406 /* 2407 * CROSSBAR_FOR_Y_G enum 2408 */ 2409 2410 typedef enum CROSSBAR_FOR_Y_G { 2411 ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000, 2412 Y_G_DATA_ONTO_Y_G_PORT = 0x00000001, 2413 CB_B_DATA_ONTO_Y_G_PORT = 0x00000002, 2414 CR_R_DATA_ONTO_Y_G_PORT = 0x00000003, 2415 } CROSSBAR_FOR_Y_G; 2416 2417 /* 2418 * DETILE_BUFFER_PACKER_ENABLE enum 2419 */ 2420 2421 typedef enum DETILE_BUFFER_PACKER_ENABLE { 2422 DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000, 2423 DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001, 2424 } DETILE_BUFFER_PACKER_ENABLE; 2425 2426 /* 2427 * MEM_PWR_DIS_MODE enum 2428 */ 2429 2430 typedef enum MEM_PWR_DIS_MODE { 2431 MEM_POWER_DIS_MODE_ENABLE = 0x00000000, 2432 MEM_POWER_DIS_MODE_DISABLE = 0x00000001, 2433 } MEM_PWR_DIS_MODE; 2434 2435 /* 2436 * MEM_PWR_FORCE_MODE enum 2437 */ 2438 2439 typedef enum MEM_PWR_FORCE_MODE { 2440 MEM_POWER_FORCE_MODE_OFF = 0x00000000, 2441 MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001, 2442 MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002, 2443 MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003, 2444 } MEM_PWR_FORCE_MODE; 2445 2446 /* 2447 * MEM_PWR_STATUS enum 2448 */ 2449 2450 typedef enum MEM_PWR_STATUS { 2451 MEM_POWER_STATUS_ON = 0x00000000, 2452 MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001, 2453 MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002, 2454 MEM_POWER_STATUS_SHUT_DOWN = 0x00000003, 2455 } MEM_PWR_STATUS; 2456 2457 /* 2458 * PIPE_INT_MASK_MODE enum 2459 */ 2460 2461 typedef enum PIPE_INT_MASK_MODE { 2462 PIPE_INT_MASK_MODE_DISABLE = 0x00000000, 2463 PIPE_INT_MASK_MODE_ENABLE = 0x00000001, 2464 } PIPE_INT_MASK_MODE; 2465 2466 /* 2467 * PIPE_INT_TYPE_MODE enum 2468 */ 2469 2470 typedef enum PIPE_INT_TYPE_MODE { 2471 PIPE_INT_TYPE_MODE_DISABLE = 0x00000000, 2472 PIPE_INT_TYPE_MODE_ENABLE = 0x00000001, 2473 } PIPE_INT_TYPE_MODE; 2474 2475 /* 2476 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum 2477 */ 2478 2479 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE { 2480 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2481 PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2482 } PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; 2483 2484 /******************************************************* 2485 * CURSOR Enums 2486 *******************************************************/ 2487 2488 /* 2489 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum 2490 */ 2491 2492 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE { 2493 CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2494 CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2495 CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, 2496 } CROB_MEM_PWR_LIGHT_SLEEP_MODE; 2497 2498 /* 2499 * CURSOR_2X_MAGNIFY enum 2500 */ 2501 2502 typedef enum CURSOR_2X_MAGNIFY { 2503 CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000, 2504 CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001, 2505 } CURSOR_2X_MAGNIFY; 2506 2507 /* 2508 * CURSOR_ENABLE enum 2509 */ 2510 2511 typedef enum CURSOR_ENABLE { 2512 CURSOR_IS_DISABLE = 0x00000000, 2513 CURSOR_IS_ENABLE = 0x00000001, 2514 } CURSOR_ENABLE; 2515 2516 /* 2517 * CURSOR_LINES_PER_CHUNK enum 2518 */ 2519 2520 typedef enum CURSOR_LINES_PER_CHUNK { 2521 CURSOR_LINE_PER_CHUNK_1 = 0x00000000, 2522 CURSOR_LINE_PER_CHUNK_2 = 0x00000001, 2523 CURSOR_LINE_PER_CHUNK_4 = 0x00000002, 2524 CURSOR_LINE_PER_CHUNK_8 = 0x00000003, 2525 CURSOR_LINE_PER_CHUNK_16 = 0x00000004, 2526 } CURSOR_LINES_PER_CHUNK; 2527 2528 /* 2529 * CURSOR_MODE enum 2530 */ 2531 2532 typedef enum CURSOR_MODE { 2533 CURSOR_MONO_2BIT = 0x00000000, 2534 CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001, 2535 CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, 2536 CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, 2537 CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004, 2538 CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005, 2539 } CURSOR_MODE; 2540 2541 /* 2542 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum 2543 */ 2544 2545 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN { 2546 CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000, 2547 CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001, 2548 } CURSOR_PERFMON_LATENCY_MEASURE_EN; 2549 2550 /* 2551 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum 2552 */ 2553 2554 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL { 2555 CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000, 2556 CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001, 2557 } CURSOR_PERFMON_LATENCY_MEASURE_SEL; 2558 2559 /* 2560 * CURSOR_PITCH enum 2561 */ 2562 2563 typedef enum CURSOR_PITCH { 2564 CURSOR_PITCH_64_PIXELS = 0x00000000, 2565 CURSOR_PITCH_128_PIXELS = 0x00000001, 2566 CURSOR_PITCH_256_PIXELS = 0x00000002, 2567 } CURSOR_PITCH; 2568 2569 /* 2570 * CURSOR_REQ_MODE enum 2571 */ 2572 2573 typedef enum CURSOR_REQ_MODE { 2574 CURSOR_REQUEST_NORMALLY = 0x00000000, 2575 CURSOR_REQUEST_EARLY = 0x00000001, 2576 } CURSOR_REQ_MODE; 2577 2578 /* 2579 * CURSOR_SNOOP enum 2580 */ 2581 2582 typedef enum CURSOR_SNOOP { 2583 CURSOR_IS_NOT_SNOOP = 0x00000000, 2584 CURSOR_IS_SNOOP = 0x00000001, 2585 } CURSOR_SNOOP; 2586 2587 /* 2588 * CURSOR_STEREO_EN enum 2589 */ 2590 2591 typedef enum CURSOR_STEREO_EN { 2592 CURSOR_STEREO_IS_DISABLED = 0x00000000, 2593 CURSOR_STEREO_IS_ENABLED = 0x00000001, 2594 } CURSOR_STEREO_EN; 2595 2596 /* 2597 * CURSOR_SURFACE_TMZ enum 2598 */ 2599 2600 typedef enum CURSOR_SURFACE_TMZ { 2601 CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000, 2602 CURSOR_SURFACE_IS_TMZ = 0x00000001, 2603 } CURSOR_SURFACE_TMZ; 2604 2605 /* 2606 * CURSOR_SYSTEM enum 2607 */ 2608 2609 typedef enum CURSOR_SYSTEM { 2610 CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000, 2611 CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001, 2612 } CURSOR_SYSTEM; 2613 2614 /* 2615 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum 2616 */ 2617 2618 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS { 2619 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000, 2620 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001, 2621 } CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; 2622 2623 /* 2624 * DMDATA_DONE enum 2625 */ 2626 2627 typedef enum DMDATA_DONE { 2628 DMDATA_NOT_SENT_TO_DIG = 0x00000000, 2629 DMDATA_SENT_TO_DIG = 0x00000001, 2630 } DMDATA_DONE; 2631 2632 /* 2633 * DMDATA_MODE enum 2634 */ 2635 2636 typedef enum DMDATA_MODE { 2637 DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000, 2638 DMDATA_HARDWARE_UPDATE_MODE = 0x00000001, 2639 } DMDATA_MODE; 2640 2641 /* 2642 * DMDATA_QOS_MODE enum 2643 */ 2644 2645 typedef enum DMDATA_QOS_MODE { 2646 DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000, 2647 DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001, 2648 } DMDATA_QOS_MODE; 2649 2650 /* 2651 * DMDATA_REPEAT enum 2652 */ 2653 2654 typedef enum DMDATA_REPEAT { 2655 DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000, 2656 DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001, 2657 } DMDATA_REPEAT; 2658 2659 /* 2660 * DMDATA_UNDERFLOW enum 2661 */ 2662 2663 typedef enum DMDATA_UNDERFLOW { 2664 DMDATA_NOT_UNDERFLOW = 0x00000000, 2665 DMDATA_UNDERFLOWED = 0x00000001, 2666 } DMDATA_UNDERFLOW; 2667 2668 /* 2669 * DMDATA_UNDERFLOW_CLEAR enum 2670 */ 2671 2672 typedef enum DMDATA_UNDERFLOW_CLEAR { 2673 DMDATA_DONT_CLEAR = 0x00000000, 2674 DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001, 2675 } DMDATA_UNDERFLOW_CLEAR; 2676 2677 /* 2678 * DMDATA_UPDATED enum 2679 */ 2680 2681 typedef enum DMDATA_UPDATED { 2682 DMDATA_NOT_UPDATED = 0x00000000, 2683 DMDATA_WAS_UPDATED = 0x00000001, 2684 } DMDATA_UPDATED; 2685 2686 /* 2687 * HUBP_3DLUT_ADDRESSING_MODE enum 2688 */ 2689 2690 typedef enum HUBP_3DLUT_ADDRESSING_MODE { 2691 HUBP_3DLUT_SW_LINEAR = 0x00000000, 2692 HUBP_3DLUT_SIMPLE_LINEAR = 0x00000001, 2693 } HUBP_3DLUT_ADDRESSING_MODE; 2694 2695 /******************************************************* 2696 * HUBBUB_SDPIF Enums 2697 *******************************************************/ 2698 2699 /* 2700 * RESPONSE_STATUS enum 2701 */ 2702 2703 typedef enum RESPONSE_STATUS { 2704 OKAY = 0x00000000, 2705 EXOKAY = 0x00000001, 2706 SLVERR = 0x00000002, 2707 DECERR = 0x00000003, 2708 EARLY = 0x00000004, 2709 OKAY_NODATA = 0x00000005, 2710 PROTVIOL = 0x00000006, 2711 TRANSERR = 0x00000007, 2712 CMPTO = 0x00000008, 2713 CRS = 0x0000000c, 2714 } RESPONSE_STATUS; 2715 2716 /******************************************************* 2717 * HUBBUB_RET_PATH Enums 2718 *******************************************************/ 2719 2720 /* 2721 * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum 2722 */ 2723 2724 typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE { 2725 DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, 2726 DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, 2727 DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, 2728 } DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE; 2729 2730 /* 2731 * DCHUBBUB_MEM_PWR_DIS_MODE enum 2732 */ 2733 2734 typedef enum DCHUBBUB_MEM_PWR_DIS_MODE { 2735 DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000, 2736 DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001, 2737 } DCHUBBUB_MEM_PWR_DIS_MODE; 2738 2739 /* 2740 * DCHUBBUB_MEM_PWR_MODE enum 2741 */ 2742 2743 typedef enum DCHUBBUB_MEM_PWR_MODE { 2744 DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000, 2745 DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001, 2746 DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002, 2747 DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003, 2748 } DCHUBBUB_MEM_PWR_MODE; 2749 2750 /******************************************************* 2751 * MPC_CFG Enums 2752 *******************************************************/ 2753 2754 /* 2755 * MPC_CFG_3DLUT_FL_FORMAT enum 2756 */ 2757 2758 typedef enum MPC_CFG_3DLUT_FL_FORMAT { 2759 MPC_CFG_3DLUT_FL_FORMAT_0 = 0x00000000, 2760 MPC_CFG_3DLUT_FL_FORMAT_1 = 0x00000001, 2761 MPC_CFG_3DLUT_FL_FORMAT_2 = 0x00000002, 2762 } MPC_CFG_3DLUT_FL_FORMAT; 2763 2764 /* 2765 * MPC_CFG_3DLUT_FL_MODE enum 2766 */ 2767 2768 typedef enum MPC_CFG_3DLUT_FL_MODE { 2769 MPC_CFG_3DLUT_FL_MODE_0 = 0x00000000, 2770 MPC_CFG_3DLUT_FL_MODE_1 = 0x00000001, 2771 MPC_CFG_3DLUT_FL_MODE_2 = 0x00000002, 2772 MPC_CFG_3DLUT_FL_MODE_3 = 0x00000003, 2773 } MPC_CFG_3DLUT_FL_MODE; 2774 2775 /* 2776 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum 2777 */ 2778 2779 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET { 2780 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2781 MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2782 } MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; 2783 2784 /* 2785 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum 2786 */ 2787 2788 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET { 2789 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2790 MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2791 } MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; 2792 2793 /* 2794 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum 2795 */ 2796 2797 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET { 2798 MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2799 MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2800 } MPC_CFG_ADR_VUPDATE_LOCK_SET; 2801 2802 /* 2803 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum 2804 */ 2805 2806 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET { 2807 MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2808 MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2809 } MPC_CFG_CFG_VUPDATE_LOCK_SET; 2810 2811 /* 2812 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum 2813 */ 2814 2815 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET { 2816 MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, 2817 MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, 2818 } MPC_CFG_CUR_VUPDATE_LOCK_SET; 2819 2820 /* 2821 * MPC_CFG_MPC_TEST_CLK_SEL enum 2822 */ 2823 2824 typedef enum MPC_CFG_MPC_TEST_CLK_SEL { 2825 MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000, 2826 MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001, 2827 MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002, 2828 MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003, 2829 } MPC_CFG_MPC_TEST_CLK_SEL; 2830 2831 /* 2832 * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum 2833 */ 2834 2835 typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN { 2836 MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, 2837 MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, 2838 } MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN; 2839 2840 /* 2841 * MPC_CRC_CALC_INTERLACE_MODE enum 2842 */ 2843 2844 typedef enum MPC_CRC_CALC_INTERLACE_MODE { 2845 MPC_CRC_INTERLACE_MODE_TOP = 0x00000000, 2846 MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 2847 MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002, 2848 MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003, 2849 } MPC_CRC_CALC_INTERLACE_MODE; 2850 2851 /* 2852 * MPC_CRC_CALC_MODE enum 2853 */ 2854 2855 typedef enum MPC_CRC_CALC_MODE { 2856 MPC_CRC_ONE_SHOT_MODE = 0x00000000, 2857 MPC_CRC_CONTINUOUS_MODE = 0x00000001, 2858 } MPC_CRC_CALC_MODE; 2859 2860 /* 2861 * MPC_CRC_CALC_STEREO_MODE enum 2862 */ 2863 2864 typedef enum MPC_CRC_CALC_STEREO_MODE { 2865 MPC_CRC_STEREO_MODE_LEFT = 0x00000000, 2866 MPC_CRC_STEREO_MODE_RIGHT = 0x00000001, 2867 MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002, 2868 MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003, 2869 } MPC_CRC_CALC_STEREO_MODE; 2870 2871 /* 2872 * MPC_CRC_SOURCE_SELECT enum 2873 */ 2874 2875 typedef enum MPC_CRC_SOURCE_SELECT { 2876 MPC_CRC_SOURCE_SEL_DPP = 0x00000000, 2877 MPC_CRC_SOURCE_SEL_OPP = 0x00000001, 2878 MPC_CRC_SOURCE_SEL_DWB = 0x00000002, 2879 MPC_CRC_SOURCE_SEL_OTHER = 0x00000003, 2880 } MPC_CRC_SOURCE_SELECT; 2881 2882 /******************************************************* 2883 * MPC_OCSC Enums 2884 *******************************************************/ 2885 2886 /* 2887 * MPC_OCSC_COEF_FORMAT enum 2888 */ 2889 2890 typedef enum MPC_OCSC_COEF_FORMAT { 2891 MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000, 2892 MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001, 2893 } MPC_OCSC_COEF_FORMAT; 2894 2895 /* 2896 * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum 2897 */ 2898 2899 typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN { 2900 MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, 2901 MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, 2902 } MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN; 2903 2904 /* 2905 * MPC_OUT_CSC_MODE enum 2906 */ 2907 2908 typedef enum MPC_OUT_CSC_MODE { 2909 MPC_OUT_CSC_MODE_0 = 0x00000000, 2910 MPC_OUT_CSC_MODE_1 = 0x00000001, 2911 MPC_OUT_CSC_MODE_2 = 0x00000002, 2912 MPC_OUT_CSC_MODE_RSV = 0x00000003, 2913 } MPC_OUT_CSC_MODE; 2914 2915 /* 2916 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum 2917 */ 2918 2919 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE { 2920 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000, 2921 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001, 2922 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002, 2923 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003, 2924 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004, 2925 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005, 2926 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006, 2927 MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007, 2928 } MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; 2929 2930 /* 2931 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum 2932 */ 2933 2934 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET { 2935 MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000, 2936 MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001, 2937 } MPC_OUT_RATE_CONTROL_DISABLE_SET; 2938 2939 /******************************************************* 2940 * MPCC Enums 2941 *******************************************************/ 2942 2943 /* 2944 * MPCC_BG_COLOR_BPC enum 2945 */ 2946 2947 typedef enum MPCC_BG_COLOR_BPC { 2948 MPCC_BG_COLOR_BPC_8bit = 0x00000000, 2949 MPCC_BG_COLOR_BPC_9bit = 0x00000001, 2950 MPCC_BG_COLOR_BPC_10bit = 0x00000002, 2951 MPCC_BG_COLOR_BPC_11bit = 0x00000003, 2952 MPCC_BG_COLOR_BPC_12bit = 0x00000004, 2953 } MPCC_BG_COLOR_BPC; 2954 2955 /* 2956 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum 2957 */ 2958 2959 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY { 2960 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, 2961 MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, 2962 } MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; 2963 2964 /* 2965 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum 2966 */ 2967 2968 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE { 2969 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000, 2970 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, 2971 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002, 2972 MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003, 2973 } MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; 2974 2975 /* 2976 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum 2977 */ 2978 2979 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE { 2980 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000, 2981 MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001, 2982 } MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; 2983 2984 /* 2985 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum 2986 */ 2987 2988 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE { 2989 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000, 2990 MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001, 2991 } MPCC_CONTROL_MPCC_BOT_GAIN_MODE; 2992 2993 /* 2994 * MPCC_CONTROL_MPCC_MODE enum 2995 */ 2996 2997 typedef enum MPCC_CONTROL_MPCC_MODE { 2998 MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000, 2999 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001, 3000 MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002, 3001 MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003, 3002 } MPCC_CONTROL_MPCC_MODE; 3003 3004 /* 3005 * MPCC_SM_CONTROL_MPCC_SM_EN enum 3006 */ 3007 3008 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN { 3009 MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000, 3010 MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001, 3011 } MPCC_SM_CONTROL_MPCC_SM_EN; 3012 3013 /* 3014 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum 3015 */ 3016 3017 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT { 3018 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000, 3019 MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001, 3020 } MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; 3021 3022 /* 3023 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum 3024 */ 3025 3026 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL { 3027 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, 3028 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, 3029 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, 3030 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, 3031 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; 3032 3033 /* 3034 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum 3035 */ 3036 3037 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL { 3038 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, 3039 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, 3040 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, 3041 MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, 3042 } MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; 3043 3044 /* 3045 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum 3046 */ 3047 3048 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT { 3049 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000, 3050 MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001, 3051 } MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; 3052 3053 /* 3054 * MPCC_SM_CONTROL_MPCC_SM_MODE enum 3055 */ 3056 3057 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE { 3058 MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000, 3059 MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002, 3060 MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, 3061 MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, 3062 } MPCC_SM_CONTROL_MPCC_SM_MODE; 3063 3064 /******************************************************* 3065 * MPCC_OGAM Enums 3066 *******************************************************/ 3067 3068 /* 3069 * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum 3070 */ 3071 3072 typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM { 3073 MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, 3074 MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, 3075 } MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM; 3076 3077 /* 3078 * MPCC_GAMUT_REMAP_MODE_ENUM enum 3079 */ 3080 3081 typedef enum MPCC_GAMUT_REMAP_MODE_ENUM { 3082 MPCC_GAMUT_REMAP_MODE_0 = 0x00000000, 3083 MPCC_GAMUT_REMAP_MODE_1 = 0x00000001, 3084 MPCC_GAMUT_REMAP_MODE_2 = 0x00000002, 3085 MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003, 3086 } MPCC_GAMUT_REMAP_MODE_ENUM; 3087 3088 /* 3089 * MPCC_OGAM_LUT_2_CONFIG_ENUM enum 3090 */ 3091 3092 typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM { 3093 MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000, 3094 MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001, 3095 MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002, 3096 } MPCC_OGAM_LUT_2_CONFIG_ENUM; 3097 3098 /* 3099 * MPCC_OGAM_LUT_CONFIG_MODE enum 3100 */ 3101 3102 typedef enum MPCC_OGAM_LUT_CONFIG_MODE { 3103 MPCC_OGAM_DIFFERENT_RGB = 0x00000000, 3104 MPCC_OGAM_ALL_USE_R = 0x00000001, 3105 } MPCC_OGAM_LUT_CONFIG_MODE; 3106 3107 /* 3108 * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum 3109 */ 3110 3111 typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM { 3112 MPCC_OGAM_ENABLE_PWL = 0x00000000, 3113 MPCC_OGAM_DISABLE_PWL = 0x00000001, 3114 } MPCC_OGAM_LUT_PWL_DISABLE_ENUM; 3115 3116 /* 3117 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum 3118 */ 3119 3120 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL { 3121 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000, 3122 MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001, 3123 } MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; 3124 3125 /* 3126 * MPCC_OGAM_LUT_RAM_SEL enum 3127 */ 3128 3129 typedef enum MPCC_OGAM_LUT_RAM_SEL { 3130 MPCC_OGAM_RAMA_ACCESS = 0x00000000, 3131 MPCC_OGAM_RAMB_ACCESS = 0x00000001, 3132 } MPCC_OGAM_LUT_RAM_SEL; 3133 3134 /* 3135 * MPCC_OGAM_LUT_READ_COLOR_SEL enum 3136 */ 3137 3138 typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL { 3139 MPCC_OGAM_BLUE_LUT = 0x00000000, 3140 MPCC_OGAM_GREEN_LUT = 0x00000001, 3141 MPCC_OGAM_RED_LUT = 0x00000002, 3142 } MPCC_OGAM_LUT_READ_COLOR_SEL; 3143 3144 /* 3145 * MPCC_OGAM_LUT_READ_DBG enum 3146 */ 3147 3148 typedef enum MPCC_OGAM_LUT_READ_DBG { 3149 MPCC_OGAM_DISABLE_DEBUG = 0x00000000, 3150 MPCC_OGAM_ENABLE_DEBUG = 0x00000001, 3151 } MPCC_OGAM_LUT_READ_DBG; 3152 3153 /* 3154 * MPCC_OGAM_LUT_SEL_ENUM enum 3155 */ 3156 3157 typedef enum MPCC_OGAM_LUT_SEL_ENUM { 3158 MPCC_OGAM_RAMA = 0x00000000, 3159 MPCC_OGAM_RAMB = 0x00000001, 3160 } MPCC_OGAM_LUT_SEL_ENUM; 3161 3162 /* 3163 * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum 3164 */ 3165 3166 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM { 3167 MPCC_OGAM_MODE_0 = 0x00000000, 3168 MPCC_OGAM_MODE_RSV1 = 0x00000001, 3169 MPCC_OGAM_MODE_2 = 0x00000002, 3170 MPCC_OGAM_MODE_RSV = 0x00000003, 3171 } MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM; 3172 3173 /* 3174 * MPCC_OGAM_NUM_SEG enum 3175 */ 3176 3177 typedef enum MPCC_OGAM_NUM_SEG { 3178 MPCC_OGAM_SEGMENTS_1 = 0x00000000, 3179 MPCC_OGAM_SEGMENTS_2 = 0x00000001, 3180 MPCC_OGAM_SEGMENTS_4 = 0x00000002, 3181 MPCC_OGAM_SEGMENTS_8 = 0x00000003, 3182 MPCC_OGAM_SEGMENTS_16 = 0x00000004, 3183 MPCC_OGAM_SEGMENTS_32 = 0x00000005, 3184 MPCC_OGAM_SEGMENTS_64 = 0x00000006, 3185 MPCC_OGAM_SEGMENTS_128 = 0x00000007, 3186 } MPCC_OGAM_NUM_SEG; 3187 3188 /* 3189 * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum 3190 */ 3191 3192 typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN { 3193 MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, 3194 MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, 3195 } MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN; 3196 3197 /******************************************************* 3198 * MPCC_MCM Enums 3199 *******************************************************/ 3200 3201 /* 3202 * MPCC_MCM_3DLUT_30BIT_ENUM enum 3203 */ 3204 3205 typedef enum MPCC_MCM_3DLUT_30BIT_ENUM { 3206 MPCC_MCM_3DLUT_36BIT = 0x00000000, 3207 MPCC_MCM_3DLUT_30BIT = 0x00000001, 3208 } MPCC_MCM_3DLUT_30BIT_ENUM; 3209 3210 /* 3211 * MPCC_MCM_3DLUT_RAM_SEL enum 3212 */ 3213 3214 typedef enum MPCC_MCM_3DLUT_RAM_SEL { 3215 MPCC_MCM_RAM0_ACCESS = 0x00000000, 3216 MPCC_MCM_RAM1_ACCESS = 0x00000001, 3217 MPCC_MCM_RAM2_ACCESS = 0x00000002, 3218 MPCC_MCM_RAM3_ACCESS = 0x00000003, 3219 } MPCC_MCM_3DLUT_RAM_SEL; 3220 3221 /* 3222 * MPCC_MCM_3DLUT_SIZE_ENUM enum 3223 */ 3224 3225 typedef enum MPCC_MCM_3DLUT_SIZE_ENUM { 3226 MPCC_MCM_3DLUT_17CUBE = 0x00000000, 3227 MPCC_MCM_3DLUT_9CUBE = 0x00000001, 3228 } MPCC_MCM_3DLUT_SIZE_ENUM; 3229 3230 /* 3231 * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum 3232 */ 3233 3234 typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM { 3235 MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000, 3236 MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001, 3237 MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002, 3238 MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003, 3239 } MPCC_MCM_GAMMA_LUT_MODE_ENUM; 3240 3241 /* 3242 * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum 3243 */ 3244 3245 typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM { 3246 MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000, 3247 MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001, 3248 } MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM; 3249 3250 /* 3251 * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum 3252 */ 3253 3254 typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM { 3255 MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000, 3256 MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001, 3257 } MPCC_MCM_GAMMA_LUT_SEL_ENUM; 3258 3259 /* 3260 * MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM enum 3261 */ 3262 3263 typedef enum MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM { 3264 MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, 3265 MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, 3266 } MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM; 3267 3268 /* 3269 * MPCC_MCM_GAMUT_REMAP_MODE_ENUM enum 3270 */ 3271 3272 typedef enum MPCC_MCM_GAMUT_REMAP_MODE_ENUM { 3273 MPCC_MCM_GAMUT_REMAP_MODE_0 = 0x00000000, 3274 MPCC_MCM_GAMUT_REMAP_MODE_1 = 0x00000001, 3275 MPCC_MCM_GAMUT_REMAP_MODE_2 = 0x00000002, 3276 MPCC_MCM_GAMUT_REMAP_MODE_RSV = 0x00000003, 3277 } MPCC_MCM_GAMUT_REMAP_MODE_ENUM; 3278 3279 /* 3280 * MPCC_MCM_LUT_2_MODE_ENUM enum 3281 */ 3282 3283 typedef enum MPCC_MCM_LUT_2_MODE_ENUM { 3284 MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000, 3285 MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001, 3286 MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002, 3287 } MPCC_MCM_LUT_2_MODE_ENUM; 3288 3289 /* 3290 * MPCC_MCM_LUT_CONFIG_MODE enum 3291 */ 3292 3293 typedef enum MPCC_MCM_LUT_CONFIG_MODE { 3294 MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000, 3295 MPCC_MCM_LUT_ALL_USE_R = 0x00000001, 3296 } MPCC_MCM_LUT_CONFIG_MODE; 3297 3298 /* 3299 * MPCC_MCM_LUT_NUM_SEG enum 3300 */ 3301 3302 typedef enum MPCC_MCM_LUT_NUM_SEG { 3303 MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000, 3304 MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001, 3305 MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002, 3306 MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003, 3307 MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004, 3308 MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005, 3309 MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006, 3310 MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007, 3311 } MPCC_MCM_LUT_NUM_SEG; 3312 3313 /* 3314 * MPCC_MCM_LUT_RAM_SEL enum 3315 */ 3316 3317 typedef enum MPCC_MCM_LUT_RAM_SEL { 3318 MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000, 3319 MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001, 3320 } MPCC_MCM_LUT_RAM_SEL; 3321 3322 /* 3323 * MPCC_MCM_LUT_READ_COLOR_SEL enum 3324 */ 3325 3326 typedef enum MPCC_MCM_LUT_READ_COLOR_SEL { 3327 MPCC_MCM_LUT_BLUE_LUT = 0x00000000, 3328 MPCC_MCM_LUT_GREEN_LUT = 0x00000001, 3329 MPCC_MCM_LUT_RED_LUT = 0x00000002, 3330 } MPCC_MCM_LUT_READ_COLOR_SEL; 3331 3332 /* 3333 * MPCC_MCM_LUT_READ_DBG enum 3334 */ 3335 3336 typedef enum MPCC_MCM_LUT_READ_DBG { 3337 MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000, 3338 MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001, 3339 } MPCC_MCM_LUT_READ_DBG; 3340 3341 /* 3342 * MPCC_MCM_MEM_PWR_FORCE_ENUM enum 3343 */ 3344 3345 typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM { 3346 MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000, 3347 MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001, 3348 MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002, 3349 MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003, 3350 } MPCC_MCM_MEM_PWR_FORCE_ENUM; 3351 3352 /* 3353 * MPCC_MCM_MEM_PWR_STATE_ENUM enum 3354 */ 3355 3356 typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM { 3357 MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000, 3358 MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001, 3359 MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002, 3360 MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003, 3361 } MPCC_MCM_MEM_PWR_STATE_ENUM; 3362 3363 /******************************************************* 3364 * DPG Enums 3365 *******************************************************/ 3366 3367 /* 3368 * ENUM_DPG_BIT_DEPTH enum 3369 */ 3370 3371 typedef enum ENUM_DPG_BIT_DEPTH { 3372 ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000, 3373 ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001, 3374 ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002, 3375 ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003, 3376 } ENUM_DPG_BIT_DEPTH; 3377 3378 /* 3379 * ENUM_DPG_DYNAMIC_RANGE enum 3380 */ 3381 3382 typedef enum ENUM_DPG_DYNAMIC_RANGE { 3383 ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000, 3384 ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001, 3385 } ENUM_DPG_DYNAMIC_RANGE; 3386 3387 /* 3388 * ENUM_DPG_EN enum 3389 */ 3390 3391 typedef enum ENUM_DPG_EN { 3392 ENUM_DPG_DISABLE = 0x00000000, 3393 ENUM_DPG_ENABLE = 0x00000001, 3394 } ENUM_DPG_EN; 3395 3396 /* 3397 * ENUM_DPG_FIELD_POLARITY enum 3398 */ 3399 3400 typedef enum ENUM_DPG_FIELD_POLARITY { 3401 ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, 3402 ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, 3403 } ENUM_DPG_FIELD_POLARITY; 3404 3405 /* 3406 * ENUM_DPG_MODE enum 3407 */ 3408 3409 typedef enum ENUM_DPG_MODE { 3410 ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000, 3411 ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001, 3412 ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002, 3413 ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003, 3414 ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004, 3415 ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005, 3416 ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006, 3417 ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007, 3418 } ENUM_DPG_MODE; 3419 3420 /******************************************************* 3421 * FMT Enums 3422 *******************************************************/ 3423 3424 /* 3425 * FMTMEM_PWR_DIS_CTRL enum 3426 */ 3427 3428 typedef enum FMTMEM_PWR_DIS_CTRL { 3429 FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 3430 FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 3431 } FMTMEM_PWR_DIS_CTRL; 3432 3433 /* 3434 * FMTMEM_PWR_FORCE_CTRL enum 3435 */ 3436 3437 typedef enum FMTMEM_PWR_FORCE_CTRL { 3438 FMTMEM_NO_FORCE_REQUEST = 0x00000000, 3439 FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 3440 FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 3441 FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 3442 } FMTMEM_PWR_FORCE_CTRL; 3443 3444 /* 3445 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum 3446 */ 3447 3448 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { 3449 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, 3450 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, 3451 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, 3452 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, 3453 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL; 3454 3455 /* 3456 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum 3457 */ 3458 3459 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { 3460 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, 3461 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, 3462 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, 3463 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, 3464 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL; 3465 3466 /* 3467 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum 3468 */ 3469 3470 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { 3471 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, 3472 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, 3473 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, 3474 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, 3475 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL; 3476 3477 /* 3478 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum 3479 */ 3480 3481 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { 3482 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, 3483 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, 3484 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, 3485 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; 3486 3487 /* 3488 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum 3489 */ 3490 3491 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { 3492 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, 3493 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, 3494 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, 3495 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; 3496 3497 /* 3498 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum 3499 */ 3500 3501 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { 3502 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, 3503 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, 3504 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; 3505 3506 /* 3507 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum 3508 */ 3509 3510 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { 3511 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, 3512 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, 3513 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, 3514 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; 3515 3516 /* 3517 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum 3518 */ 3519 3520 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { 3521 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, 3522 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, 3523 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; 3524 3525 /* 3526 * FMT_CLAMP_CNTL_COLOR_FORMAT enum 3527 */ 3528 3529 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { 3530 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, 3531 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, 3532 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, 3533 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, 3534 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, 3535 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, 3536 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, 3537 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, 3538 } FMT_CLAMP_CNTL_COLOR_FORMAT; 3539 3540 /* 3541 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum 3542 */ 3543 3544 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { 3545 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, 3546 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, 3547 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; 3548 3549 /* 3550 * FMT_CONTROL_PIXEL_ENCODING enum 3551 */ 3552 3553 typedef enum FMT_CONTROL_PIXEL_ENCODING { 3554 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, 3555 FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, 3556 FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, 3557 FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, 3558 } FMT_CONTROL_PIXEL_ENCODING; 3559 3560 /* 3561 * FMT_CONTROL_SUBSAMPLING_MODE enum 3562 */ 3563 3564 typedef enum FMT_CONTROL_SUBSAMPLING_MODE { 3565 FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, 3566 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, 3567 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, 3568 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, 3569 } FMT_CONTROL_SUBSAMPLING_MODE; 3570 3571 /* 3572 * FMT_CONTROL_SUBSAMPLING_ORDER enum 3573 */ 3574 3575 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { 3576 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, 3577 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, 3578 } FMT_CONTROL_SUBSAMPLING_ORDER; 3579 3580 /* 3581 * FMT_DEBUG_CNTL_COLOR_SELECT enum 3582 */ 3583 3584 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { 3585 FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000, 3586 FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001, 3587 FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002, 3588 FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003, 3589 } FMT_DEBUG_CNTL_COLOR_SELECT; 3590 3591 /* 3592 * FMT_DYNAMIC_EXP_MODE enum 3593 */ 3594 3595 typedef enum FMT_DYNAMIC_EXP_MODE { 3596 FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, 3597 FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, 3598 } FMT_DYNAMIC_EXP_MODE; 3599 3600 /* 3601 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum 3602 */ 3603 3604 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL { 3605 FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000, 3606 FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001, 3607 } FMT_FRAME_RANDOM_ENABLE_CONTROL; 3608 3609 /* 3610 * FMT_POWER_STATE_ENUM enum 3611 */ 3612 3613 typedef enum FMT_POWER_STATE_ENUM { 3614 FMT_POWER_STATE_ENUM_ON = 0x00000000, 3615 FMT_POWER_STATE_ENUM_LS = 0x00000001, 3616 FMT_POWER_STATE_ENUM_DS = 0x00000002, 3617 FMT_POWER_STATE_ENUM_SD = 0x00000003, 3618 } FMT_POWER_STATE_ENUM; 3619 3620 /* 3621 * FMT_RGB_RANDOM_ENABLE_CONTROL enum 3622 */ 3623 3624 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL { 3625 FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000, 3626 FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001, 3627 } FMT_RGB_RANDOM_ENABLE_CONTROL; 3628 3629 /* 3630 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum 3631 */ 3632 3633 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL { 3634 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000, 3635 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001, 3636 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002, 3637 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003, 3638 } FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; 3639 3640 /* 3641 * FMT_SPATIAL_DITHER_MODE enum 3642 */ 3643 3644 typedef enum FMT_SPATIAL_DITHER_MODE { 3645 FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, 3646 FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, 3647 FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, 3648 FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, 3649 } FMT_SPATIAL_DITHER_MODE; 3650 3651 /* 3652 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum 3653 */ 3654 3655 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL { 3656 FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000, 3657 FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001, 3658 } FMT_STEREOSYNC_OVERRIDE_CONTROL; 3659 3660 /* 3661 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum 3662 */ 3663 3664 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { 3665 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, 3666 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, 3667 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; 3668 3669 /******************************************************* 3670 * OPPBUF Enums 3671 *******************************************************/ 3672 3673 /* 3674 * OPPBUF_DISPLAY_SEGMENTATION enum 3675 */ 3676 3677 typedef enum OPPBUF_DISPLAY_SEGMENTATION { 3678 OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000, 3679 OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001, 3680 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002, 3681 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003, 3682 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004, 3683 } OPPBUF_DISPLAY_SEGMENTATION; 3684 3685 /******************************************************* 3686 * OPP_PIPE Enums 3687 *******************************************************/ 3688 3689 /* 3690 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum 3691 */ 3692 3693 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL { 3694 OPP_PIPE_CLOCK_DISABLE = 0x00000000, 3695 OPP_PIPE_CLOCK_ENABLE = 0x00000001, 3696 } OPP_PIPE_CLOCK_ENABLE_CONTROL; 3697 3698 /* 3699 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum 3700 */ 3701 3702 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL { 3703 OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000, 3704 OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001, 3705 } OPP_PIPE_DIGTIAL_BYPASS_CONTROL; 3706 3707 /******************************************************* 3708 * OPP_PIPE_CRC Enums 3709 *******************************************************/ 3710 3711 /* 3712 * OPP_PIPE_CRC_CONT_EN enum 3713 */ 3714 3715 typedef enum OPP_PIPE_CRC_CONT_EN { 3716 OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000, 3717 OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001, 3718 } OPP_PIPE_CRC_CONT_EN; 3719 3720 /* 3721 * OPP_PIPE_CRC_EN enum 3722 */ 3723 3724 typedef enum OPP_PIPE_CRC_EN { 3725 OPP_PIPE_CRC_DISABLE = 0x00000000, 3726 OPP_PIPE_CRC_ENABLE = 0x00000001, 3727 } OPP_PIPE_CRC_EN; 3728 3729 /* 3730 * OPP_PIPE_CRC_INTERLACE_EN enum 3731 */ 3732 3733 typedef enum OPP_PIPE_CRC_INTERLACE_EN { 3734 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000, 3735 OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001, 3736 } OPP_PIPE_CRC_INTERLACE_EN; 3737 3738 /* 3739 * OPP_PIPE_CRC_INTERLACE_MODE enum 3740 */ 3741 3742 typedef enum OPP_PIPE_CRC_INTERLACE_MODE { 3743 OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000, 3744 OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 3745 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002, 3746 OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003, 3747 } OPP_PIPE_CRC_INTERLACE_MODE; 3748 3749 /* 3750 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum 3751 */ 3752 3753 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING { 3754 OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000, 3755 OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001, 3756 } OPP_PIPE_CRC_ONE_SHOT_PENDING; 3757 3758 /* 3759 * OPP_PIPE_CRC_PIXEL_SELECT enum 3760 */ 3761 3762 typedef enum OPP_PIPE_CRC_PIXEL_SELECT { 3763 OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000, 3764 OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001, 3765 OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002, 3766 OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003, 3767 } OPP_PIPE_CRC_PIXEL_SELECT; 3768 3769 /* 3770 * OPP_PIPE_CRC_SOURCE_SELECT enum 3771 */ 3772 3773 typedef enum OPP_PIPE_CRC_SOURCE_SELECT { 3774 OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000, 3775 OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001, 3776 } OPP_PIPE_CRC_SOURCE_SELECT; 3777 3778 /* 3779 * OPP_PIPE_CRC_STEREO_EN enum 3780 */ 3781 3782 typedef enum OPP_PIPE_CRC_STEREO_EN { 3783 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000, 3784 OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001, 3785 } OPP_PIPE_CRC_STEREO_EN; 3786 3787 /* 3788 * OPP_PIPE_CRC_STEREO_MODE enum 3789 */ 3790 3791 typedef enum OPP_PIPE_CRC_STEREO_MODE { 3792 OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000, 3793 OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001, 3794 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002, 3795 OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003, 3796 } OPP_PIPE_CRC_STEREO_MODE; 3797 3798 /******************************************************* 3799 * OPP_TOP Enums 3800 *******************************************************/ 3801 3802 /* 3803 * OPP_TEST_CLK_SEL_CONTROL enum 3804 */ 3805 3806 typedef enum OPP_TEST_CLK_SEL_CONTROL { 3807 OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000, 3808 OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001, 3809 OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002, 3810 OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003, 3811 OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004, 3812 OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005, 3813 OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006, 3814 OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007, 3815 OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008, 3816 OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009, 3817 OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a, 3818 OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b, 3819 OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c, 3820 OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d, 3821 } OPP_TEST_CLK_SEL_CONTROL; 3822 3823 /* 3824 * OPP_TOP_CLOCK_ENABLE_STATUS enum 3825 */ 3826 3827 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS { 3828 OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000, 3829 OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001, 3830 } OPP_TOP_CLOCK_ENABLE_STATUS; 3831 3832 /* 3833 * OPP_TOP_CLOCK_GATING_CONTROL enum 3834 */ 3835 3836 typedef enum OPP_TOP_CLOCK_GATING_CONTROL { 3837 OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000, 3838 OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001, 3839 } OPP_TOP_CLOCK_GATING_CONTROL; 3840 3841 /******************************************************* 3842 * OTG Enums 3843 *******************************************************/ 3844 3845 /* 3846 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum 3847 */ 3848 3849 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { 3850 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, 3851 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, 3852 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; 3853 3854 /* 3855 * MASTER_UPDATE_LOCK_SEL enum 3856 */ 3857 3858 typedef enum MASTER_UPDATE_LOCK_SEL { 3859 MASTER_UPDATE_LOCK_SEL_0 = 0x00000000, 3860 MASTER_UPDATE_LOCK_SEL_1 = 0x00000001, 3861 MASTER_UPDATE_LOCK_SEL_2 = 0x00000002, 3862 MASTER_UPDATE_LOCK_SEL_3 = 0x00000003, 3863 MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004, 3864 MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005, 3865 } MASTER_UPDATE_LOCK_SEL; 3866 3867 /* 3868 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum 3869 */ 3870 3871 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { 3872 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, 3873 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001, 3874 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002, 3875 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, 3876 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; 3877 3878 /* 3879 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum 3880 */ 3881 3882 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN { 3883 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000, 3884 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001, 3885 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; 3886 3887 /* 3888 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum 3889 */ 3890 3891 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB { 3892 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, 3893 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, 3894 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; 3895 3896 /* 3897 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum 3898 */ 3899 3900 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR { 3901 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, 3902 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, 3903 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; 3904 3905 /* 3906 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum 3907 */ 3908 3909 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE { 3910 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, 3911 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, 3912 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, 3913 OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, 3914 } OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; 3915 3916 /* 3917 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum 3918 */ 3919 3920 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL { 3921 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000, 3922 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, 3923 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002, 3924 OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, 3925 } OTG_CONTROL_OTG_DISABLE_POINT_CNTL; 3926 3927 /* 3928 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum 3929 */ 3930 3931 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL { 3932 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, 3933 OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001, 3934 } OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; 3935 3936 /* 3937 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum 3938 */ 3939 3940 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY { 3941 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, 3942 OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, 3943 } OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; 3944 3945 /* 3946 * OTG_CONTROL_OTG_MASTER_EN enum 3947 */ 3948 3949 typedef enum OTG_CONTROL_OTG_MASTER_EN { 3950 OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000, 3951 OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001, 3952 } OTG_CONTROL_OTG_MASTER_EN; 3953 3954 /* 3955 * OTG_CONTROL_OTG_OUT_MUX enum 3956 */ 3957 3958 typedef enum OTG_CONTROL_OTG_OUT_MUX { 3959 OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000, 3960 OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001, 3961 OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002, 3962 } OTG_CONTROL_OTG_OUT_MUX; 3963 3964 /* 3965 * OTG_CONTROL_OTG_START_POINT_CNTL enum 3966 */ 3967 3968 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL { 3969 OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000, 3970 OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001, 3971 } OTG_CONTROL_OTG_START_POINT_CNTL; 3972 3973 /* 3974 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum 3975 */ 3976 3977 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN { 3978 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, 3979 OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, 3980 } OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; 3981 3982 /* 3983 * OTG_CRC_CNTL_OTG_CRC1_EN enum 3984 */ 3985 3986 typedef enum OTG_CRC_CNTL_OTG_CRC1_EN { 3987 OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000, 3988 OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001, 3989 } OTG_CRC_CNTL_OTG_CRC1_EN; 3990 3991 /* 3992 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum 3993 */ 3994 3995 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN { 3996 OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000, 3997 OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001, 3998 } OTG_CRC_CNTL_OTG_CRC_CONT_EN; 3999 4000 /* 4001 * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum 4002 */ 4003 4004 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE { 4005 OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000, 4006 OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001, 4007 } OTG_CRC_CNTL_OTG_CRC_CONT_MODE; 4008 4009 /* 4010 * OTG_CRC_CNTL_OTG_CRC_EN enum 4011 */ 4012 4013 typedef enum OTG_CRC_CNTL_OTG_CRC_EN { 4014 OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000, 4015 OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001, 4016 } OTG_CRC_CNTL_OTG_CRC_EN; 4017 4018 /* 4019 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum 4020 */ 4021 4022 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE { 4023 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000, 4024 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, 4025 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, 4026 OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, 4027 } OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; 4028 4029 /* 4030 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum 4031 */ 4032 4033 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE { 4034 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000, 4035 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001, 4036 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, 4037 OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, 4038 } OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; 4039 4040 /* 4041 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum 4042 */ 4043 4044 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS { 4045 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, 4046 OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, 4047 } OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; 4048 4049 /* 4050 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum 4051 */ 4052 4053 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT { 4054 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000, 4055 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001, 4056 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002, 4057 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003, 4058 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004, 4059 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005, 4060 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006, 4061 OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007, 4062 } OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; 4063 4064 /* 4065 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum 4066 */ 4067 4068 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT { 4069 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000, 4070 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001, 4071 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002, 4072 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003, 4073 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004, 4074 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005, 4075 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006, 4076 OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007, 4077 } OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; 4078 4079 /* 4080 * OTG_DIG_UPDATE_VCOUNT_MODE enum 4081 */ 4082 4083 typedef enum OTG_DIG_UPDATE_VCOUNT_MODE { 4084 OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000, 4085 OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001, 4086 } OTG_DIG_UPDATE_VCOUNT_MODE; 4087 4088 /* 4089 * OTG_DLPC_CONTROL_OTG_RESYNC_MODE enum 4090 */ 4091 4092 typedef enum OTG_DLPC_CONTROL_OTG_RESYNC_MODE { 4093 OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0 = 0x00000000, 4094 OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1 = 0x00000001, 4095 } OTG_DLPC_CONTROL_OTG_RESYNC_MODE; 4096 4097 /* 4098 * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum 4099 */ 4100 4101 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE { 4102 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, 4103 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, 4104 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002, 4105 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003, 4106 } OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE; 4107 4108 /* 4109 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum 4110 */ 4111 4112 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY { 4113 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000, 4114 OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001, 4115 } OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; 4116 4117 /* 4118 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum 4119 */ 4120 4121 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME { 4122 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000, 4123 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001, 4124 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002, 4125 OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003, 4126 } OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; 4127 4128 /* 4129 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum 4130 */ 4131 4132 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN { 4133 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000, 4134 OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001, 4135 } OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; 4136 4137 /* 4138 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum 4139 */ 4140 4141 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY { 4142 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, 4143 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, 4144 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; 4145 4146 /* 4147 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum 4148 */ 4149 4150 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY { 4151 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, 4152 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, 4153 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; 4154 4155 /* 4156 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum 4157 */ 4158 4159 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT { 4160 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, 4161 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001, 4162 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002, 4163 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003, 4164 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004, 4165 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005, 4166 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006, 4167 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007, 4168 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008, 4169 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009, 4170 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a, 4171 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b, 4172 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c, 4173 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d, 4174 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e, 4175 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f, 4176 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010, 4177 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011, 4178 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012, 4179 OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013, 4180 } OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; 4181 4182 /* 4183 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum 4184 */ 4185 4186 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK { 4187 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, 4188 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, 4189 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; 4190 4191 /* 4192 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum 4193 */ 4194 4195 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR { 4196 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, 4197 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, 4198 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; 4199 4200 /* 4201 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum 4202 */ 4203 4204 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE { 4205 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, 4206 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, 4207 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, 4208 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, 4209 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; 4210 4211 /* 4212 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum 4213 */ 4214 4215 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL { 4216 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, 4217 OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, 4218 } OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; 4219 4220 /* 4221 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum 4222 */ 4223 4224 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL { 4225 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000, 4226 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001, 4227 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002, 4228 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003, 4229 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004, 4230 OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005, 4231 } OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; 4232 4233 /* 4234 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum 4235 */ 4236 4237 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL { 4238 DIG_UPDATE_EYE_SEL_BOTH = 0x00000000, 4239 DIG_UPDATE_EYE_SEL_LEFT = 0x00000001, 4240 DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002, 4241 } OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL; 4242 4243 /* 4244 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum 4245 */ 4246 4247 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL { 4248 DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000, 4249 DIG_UPDATE_FIELD_SEL_TOP = 0x00000001, 4250 DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002, 4251 DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003, 4252 } OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL; 4253 4254 /* 4255 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum 4256 */ 4257 4258 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD { 4259 MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000, 4260 MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001, 4261 MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002, 4262 MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003, 4263 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; 4264 4265 /* 4266 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum 4267 */ 4268 4269 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL { 4270 MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000, 4271 MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001, 4272 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002, 4273 MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003, 4274 } OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; 4275 4276 /* 4277 * OTG_GLOBAL_UPDATE_LOCK_EN enum 4278 */ 4279 4280 typedef enum OTG_GLOBAL_UPDATE_LOCK_EN { 4281 OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000, 4282 OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001, 4283 } OTG_GLOBAL_UPDATE_LOCK_EN; 4284 4285 /* 4286 * OTG_GSL_MASTER_MODE enum 4287 */ 4288 4289 typedef enum OTG_GSL_MASTER_MODE { 4290 OTG_GSL_MASTER_MODE_0 = 0x00000000, 4291 OTG_GSL_MASTER_MODE_1 = 0x00000001, 4292 OTG_GSL_MASTER_MODE_2 = 0x00000002, 4293 OTG_GSL_MASTER_MODE_3 = 0x00000003, 4294 } OTG_GSL_MASTER_MODE; 4295 4296 /* 4297 * OTG_HORZ_REPETITION_COUNT enum 4298 */ 4299 4300 typedef enum OTG_HORZ_REPETITION_COUNT { 4301 OTG_HORZ_REPETITION_COUNT_0 = 0x00000000, 4302 OTG_HORZ_REPETITION_COUNT_1 = 0x00000001, 4303 OTG_HORZ_REPETITION_COUNT_2 = 0x00000002, 4304 OTG_HORZ_REPETITION_COUNT_3 = 0x00000003, 4305 OTG_HORZ_REPETITION_COUNT_4 = 0x00000004, 4306 OTG_HORZ_REPETITION_COUNT_5 = 0x00000005, 4307 OTG_HORZ_REPETITION_COUNT_6 = 0x00000006, 4308 OTG_HORZ_REPETITION_COUNT_7 = 0x00000007, 4309 OTG_HORZ_REPETITION_COUNT_8 = 0x00000008, 4310 OTG_HORZ_REPETITION_COUNT_9 = 0x00000009, 4311 OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a, 4312 OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b, 4313 OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c, 4314 OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d, 4315 OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e, 4316 OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f, 4317 } OTG_HORZ_REPETITION_COUNT; 4318 4319 /* 4320 * OTG_H_SYNC_A_POL enum 4321 */ 4322 4323 typedef enum OTG_H_SYNC_A_POL { 4324 OTG_H_SYNC_A_POL_HIGH = 0x00000000, 4325 OTG_H_SYNC_A_POL_LOW = 0x00000001, 4326 } OTG_H_SYNC_A_POL; 4327 4328 /* 4329 * OTG_H_TIMING_DIV_MODE enum 4330 */ 4331 4332 typedef enum OTG_H_TIMING_DIV_MODE { 4333 OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000, 4334 OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001, 4335 OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002, 4336 OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003, 4337 } OTG_H_TIMING_DIV_MODE; 4338 4339 /* 4340 * OTG_H_TIMING_DIV_MODE_MANUAL enum 4341 */ 4342 4343 typedef enum OTG_H_TIMING_DIV_MODE_MANUAL { 4344 OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000, 4345 OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001, 4346 } OTG_H_TIMING_DIV_MODE_MANUAL; 4347 4348 /* 4349 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum 4350 */ 4351 4352 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE { 4353 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000, 4354 OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001, 4355 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; 4356 4357 /* 4358 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum 4359 */ 4360 4361 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD { 4362 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, 4363 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001, 4364 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002, 4365 OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, 4366 } OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; 4367 4368 /* 4369 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum 4370 */ 4371 4372 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK { 4373 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, 4374 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, 4375 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; 4376 4377 /* 4378 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum 4379 */ 4380 4381 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE { 4382 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, 4383 OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, 4384 } OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; 4385 4386 /* 4387 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum 4388 */ 4389 4390 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK { 4391 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, 4392 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, 4393 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; 4394 4395 /* 4396 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum 4397 */ 4398 4399 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE { 4400 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, 4401 OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, 4402 } OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; 4403 4404 /* 4405 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum 4406 */ 4407 4408 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK { 4409 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, 4410 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, 4411 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; 4412 4413 /* 4414 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum 4415 */ 4416 4417 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE { 4418 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, 4419 OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, 4420 } OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; 4421 4422 /* 4423 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum 4424 */ 4425 4426 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK { 4427 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000, 4428 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001, 4429 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; 4430 4431 /* 4432 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum 4433 */ 4434 4435 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE { 4436 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, 4437 OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, 4438 } OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; 4439 4440 /* 4441 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum 4442 */ 4443 4444 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK { 4445 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000, 4446 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001, 4447 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; 4448 4449 /* 4450 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum 4451 */ 4452 4453 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE { 4454 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000, 4455 OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001, 4456 } OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; 4457 4458 /* 4459 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum 4460 */ 4461 4462 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK { 4463 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000, 4464 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001, 4465 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; 4466 4467 /* 4468 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum 4469 */ 4470 4471 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE { 4472 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000, 4473 OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001, 4474 } OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; 4475 4476 /* 4477 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum 4478 */ 4479 4480 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK { 4481 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, 4482 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, 4483 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; 4484 4485 /* 4486 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum 4487 */ 4488 4489 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE { 4490 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, 4491 OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, 4492 } OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; 4493 4494 /* 4495 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum 4496 */ 4497 4498 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE { 4499 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, 4500 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, 4501 } OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; 4502 4503 /* 4504 * OTG_MASTER_UPDATE_LOCK_DB_EN enum 4505 */ 4506 4507 typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN { 4508 OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000, 4509 OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001, 4510 } OTG_MASTER_UPDATE_LOCK_DB_EN; 4511 4512 /* 4513 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum 4514 */ 4515 4516 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN { 4517 OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000, 4518 OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001, 4519 } OTG_MASTER_UPDATE_LOCK_GSL_EN; 4520 4521 /* 4522 * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum 4523 */ 4524 4525 typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE { 4526 OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000, 4527 OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001, 4528 } OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE; 4529 4530 /* 4531 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum 4532 */ 4533 4534 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL { 4535 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, 4536 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, 4537 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, 4538 OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, 4539 } OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; 4540 4541 /* 4542 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum 4543 */ 4544 4545 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR { 4546 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000, 4547 OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001, 4548 } OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; 4549 4550 /* 4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum 4552 */ 4553 4554 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR { 4555 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000, 4556 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001, 4557 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; 4558 4559 /* 4560 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum 4561 */ 4562 4563 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE { 4564 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000, 4565 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001, 4566 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; 4567 4568 /* 4569 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum 4570 */ 4571 4572 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE { 4573 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000, 4574 OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001, 4575 } OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; 4576 4577 /* 4578 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum 4579 */ 4580 4581 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE { 4582 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, 4583 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, 4584 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; 4585 4586 /* 4587 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum 4588 */ 4589 4590 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE { 4591 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, 4592 OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, 4593 } OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; 4594 4595 /* 4596 * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum 4597 */ 4598 4599 typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL { 4600 OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000, 4601 OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001, 4602 } OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL; 4603 4604 /* 4605 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum 4606 */ 4607 4608 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN { 4609 OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000, 4610 OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001, 4611 } OTG_STEREO_CONTROL_OTG_STEREO_EN; 4612 4613 /* 4614 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum 4615 */ 4616 4617 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY { 4618 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, 4619 OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, 4620 } OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; 4621 4622 /* 4623 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum 4624 */ 4625 4626 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY { 4627 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, 4628 OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, 4629 } OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; 4630 4631 /* 4632 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum 4633 */ 4634 4635 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE { 4636 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, 4637 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, 4638 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, 4639 OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, 4640 } OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; 4641 4642 /* 4643 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum 4644 */ 4645 4646 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR { 4647 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000, 4648 OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001, 4649 } OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; 4650 4651 /* 4652 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum 4653 */ 4654 4655 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT { 4656 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000, 4657 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, 4658 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, 4659 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, 4660 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, 4661 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005, 4662 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006, 4663 OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007, 4664 } OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; 4665 4666 /* 4667 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum 4668 */ 4669 4670 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN { 4671 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, 4672 OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, 4673 } OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; 4674 4675 /* 4676 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum 4677 */ 4678 4679 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT { 4680 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, 4681 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, 4682 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, 4683 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, 4684 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, 4685 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, 4686 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; 4687 4688 /* 4689 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum 4690 */ 4691 4692 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT { 4693 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000, 4694 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001, 4695 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002, 4696 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003, 4697 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004, 4698 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005, 4699 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006, 4700 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, 4701 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, 4702 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, 4703 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, 4704 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, 4705 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, 4706 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, 4707 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e, 4708 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, 4709 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, 4710 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, 4711 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012, 4712 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013, 4713 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014, 4714 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, 4715 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, 4716 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017, 4717 OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018, 4718 } OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; 4719 4720 /* 4721 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum 4722 */ 4723 4724 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL { 4725 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, 4726 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, 4727 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, 4728 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, 4729 } OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; 4730 4731 /* 4732 * OTG_TRIGA_FREQUENCY_SELECT enum 4733 */ 4734 4735 typedef enum OTG_TRIGA_FREQUENCY_SELECT { 4736 OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000, 4737 OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001, 4738 OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002, 4739 OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003, 4740 } OTG_TRIGA_FREQUENCY_SELECT; 4741 4742 /* 4743 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum 4744 */ 4745 4746 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL { 4747 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, 4748 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, 4749 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, 4750 OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, 4751 } OTG_TRIGA_RISING_EDGE_DETECT_CNTL; 4752 4753 /* 4754 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum 4755 */ 4756 4757 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR { 4758 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000, 4759 OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001, 4760 } OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; 4761 4762 /* 4763 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum 4764 */ 4765 4766 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT { 4767 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000, 4768 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, 4769 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, 4770 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, 4771 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, 4772 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005, 4773 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006, 4774 OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007, 4775 } OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; 4776 4777 /* 4778 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum 4779 */ 4780 4781 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN { 4782 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, 4783 OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, 4784 } OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; 4785 4786 /* 4787 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum 4788 */ 4789 4790 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT { 4791 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, 4792 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, 4793 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, 4794 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, 4795 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, 4796 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, 4797 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; 4798 4799 /* 4800 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum 4801 */ 4802 4803 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT { 4804 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000, 4805 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001, 4806 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002, 4807 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003, 4808 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004, 4809 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005, 4810 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006, 4811 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, 4812 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, 4813 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, 4814 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, 4815 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, 4816 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, 4817 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, 4818 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e, 4819 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, 4820 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, 4821 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, 4822 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012, 4823 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013, 4824 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014, 4825 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, 4826 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, 4827 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017, 4828 OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018, 4829 } OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; 4830 4831 /* 4832 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum 4833 */ 4834 4835 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL { 4836 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, 4837 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, 4838 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, 4839 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, 4840 } OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; 4841 4842 /* 4843 * OTG_TRIGB_FREQUENCY_SELECT enum 4844 */ 4845 4846 typedef enum OTG_TRIGB_FREQUENCY_SELECT { 4847 OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000, 4848 OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001, 4849 OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002, 4850 OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003, 4851 } OTG_TRIGB_FREQUENCY_SELECT; 4852 4853 /* 4854 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum 4855 */ 4856 4857 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL { 4858 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, 4859 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, 4860 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, 4861 OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, 4862 } OTG_TRIGB_RISING_EDGE_DETECT_CNTL; 4863 4864 /* 4865 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum 4866 */ 4867 4868 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK { 4869 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000, 4870 OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001, 4871 } OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; 4872 4873 /* 4874 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum 4875 */ 4876 4877 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR { 4878 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, 4879 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, 4880 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; 4881 4882 /* 4883 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum 4884 */ 4885 4886 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE { 4887 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, 4888 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, 4889 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; 4890 4891 /* 4892 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum 4893 */ 4894 4895 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE { 4896 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, 4897 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, 4898 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; 4899 4900 /* 4901 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum 4902 */ 4903 4904 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { 4905 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, 4906 OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, 4907 } OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; 4908 4909 /* 4910 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum 4911 */ 4912 4913 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR { 4914 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, 4915 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, 4916 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; 4917 4918 /* 4919 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum 4920 */ 4921 4922 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE { 4923 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, 4924 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, 4925 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; 4926 4927 /* 4928 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum 4929 */ 4930 4931 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE { 4932 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, 4933 OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, 4934 } OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; 4935 4936 /* 4937 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum 4938 */ 4939 4940 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR { 4941 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, 4942 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, 4943 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; 4944 4945 /* 4946 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum 4947 */ 4948 4949 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE { 4950 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, 4951 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, 4952 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; 4953 4954 /* 4955 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum 4956 */ 4957 4958 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE { 4959 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, 4960 OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, 4961 } OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; 4962 4963 /* 4964 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum 4965 */ 4966 4967 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE { 4968 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, 4969 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, 4970 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, 4971 OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, 4972 } OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; 4973 4974 /* 4975 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum 4976 */ 4977 4978 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR { 4979 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, 4980 OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, 4981 } OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; 4982 4983 /* 4984 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum 4985 */ 4986 4987 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR { 4988 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, 4989 OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, 4990 } OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; 4991 4992 /* 4993 * OTG_VUPDATE_BLOCK_DISABLE enum 4994 */ 4995 4996 typedef enum OTG_VUPDATE_BLOCK_DISABLE { 4997 OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000, 4998 OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001, 4999 } OTG_VUPDATE_BLOCK_DISABLE; 5000 5001 /* 5002 * OTG_V_SYNC_A_POL enum 5003 */ 5004 5005 typedef enum OTG_V_SYNC_A_POL { 5006 OTG_V_SYNC_A_POL_HIGH = 0x00000000, 5007 OTG_V_SYNC_A_POL_LOW = 0x00000001, 5008 } OTG_V_SYNC_A_POL; 5009 5010 /* 5011 * OTG_V_SYNC_MODE enum 5012 */ 5013 5014 typedef enum OTG_V_SYNC_MODE { 5015 OTG_V_SYNC_MODE_HSYNC = 0x00000000, 5016 OTG_V_SYNC_MODE_HBLANK = 0x00000001, 5017 } OTG_V_SYNC_MODE; 5018 5019 /* 5020 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum 5021 */ 5022 5023 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD { 5024 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000, 5025 OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001, 5026 } OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; 5027 5028 /* 5029 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum 5030 */ 5031 5032 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT { 5033 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, 5034 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, 5035 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; 5036 5037 /* 5038 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum 5039 */ 5040 5041 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC { 5042 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, 5043 OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, 5044 } OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; 5045 5046 /* 5047 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum 5048 */ 5049 5050 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL { 5051 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000, 5052 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001, 5053 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; 5054 5055 /* 5056 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum 5057 */ 5058 5059 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL { 5060 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000, 5061 OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001, 5062 } OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; 5063 5064 /* 5065 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum 5066 */ 5067 5068 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK { 5069 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000, 5070 OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001, 5071 } OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK; 5072 5073 /******************************************************* 5074 * OPTC_MISC Enums 5075 *******************************************************/ 5076 5077 /* 5078 * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum 5079 */ 5080 5081 typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL { 5082 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000, 5083 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001, 5084 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002, 5085 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003, 5086 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004, 5087 OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005, 5088 } OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL; 5089 5090 /******************************************************* 5091 * DMCUB Enums 5092 *******************************************************/ 5093 5094 /* 5095 * DC_DMCUB_INT_TYPE enum 5096 */ 5097 5098 typedef enum DC_DMCUB_INT_TYPE { 5099 INT_LEVEL = 0x00000000, 5100 INT_PULSE = 0x00000001, 5101 } DC_DMCUB_INT_TYPE; 5102 5103 /* 5104 * DC_DMCUB_TIMER_WINDOW enum 5105 */ 5106 5107 typedef enum DC_DMCUB_TIMER_WINDOW { 5108 BITS_31_0 = 0x00000000, 5109 BITS_32_1 = 0x00000001, 5110 BITS_33_2 = 0x00000002, 5111 BITS_34_3 = 0x00000003, 5112 BITS_35_4 = 0x00000004, 5113 BITS_36_5 = 0x00000005, 5114 BITS_37_6 = 0x00000006, 5115 BITS_38_7 = 0x00000007, 5116 } DC_DMCUB_TIMER_WINDOW; 5117 5118 /******************************************************* 5119 * RBBMIF Enums 5120 *******************************************************/ 5121 5122 /* 5123 * INVALID_REG_ACCESS_TYPE enum 5124 */ 5125 5126 typedef enum INVALID_REG_ACCESS_TYPE { 5127 REG_UNALLOCATED_ADDR_WRITE = 0x00000000, 5128 REG_UNALLOCATED_ADDR_READ = 0x00000001, 5129 REG_VIRTUAL_WRITE = 0x00000002, 5130 REG_VIRTUAL_READ = 0x00000003, 5131 REG_SECURE_VIOLATE_WRITE = 0x00000004, 5132 REG_SECURE_VIOLATE_READ = 0x00000005, 5133 } INVALID_REG_ACCESS_TYPE; 5134 5135 /******************************************************* 5136 * IHC Enums 5137 *******************************************************/ 5138 5139 /* 5140 * DMU_DC_GPU_TIMER_READ_SELECT enum 5141 */ 5142 5143 typedef enum DMU_DC_GPU_TIMER_READ_SELECT { 5144 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000, 5145 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001, 5146 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002, 5147 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003, 5148 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004, 5149 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005, 5150 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006, 5151 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007, 5152 RESERVED_8 = 0x00000008, 5153 RESERVED_9 = 0x00000009, 5154 RESERVED_10 = 0x0000000a, 5155 RESERVED_11 = 0x0000000b, 5156 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c, 5157 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d, 5158 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e, 5159 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f, 5160 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010, 5161 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011, 5162 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012, 5163 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013, 5164 RESERVED_20 = 0x00000014, 5165 RESERVED_21 = 0x00000015, 5166 RESERVED_22 = 0x00000016, 5167 RESERVED_23 = 0x00000017, 5168 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018, 5169 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019, 5170 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a, 5171 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b, 5172 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c, 5173 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d, 5174 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e, 5175 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f, 5176 RESERVED_32 = 0x00000020, 5177 RESERVED_33 = 0x00000021, 5178 RESERVED_34 = 0x00000022, 5179 RESERVED_35 = 0x00000023, 5180 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024, 5181 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025, 5182 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026, 5183 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027, 5184 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028, 5185 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029, 5186 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a, 5187 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b, 5188 RESERVED_44 = 0x0000002c, 5189 RESERVED_45 = 0x0000002d, 5190 RESERVED_46 = 0x0000002e, 5191 RESERVED_47 = 0x0000002f, 5192 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030, 5193 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031, 5194 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032, 5195 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033, 5196 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034, 5197 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035, 5198 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036, 5199 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037, 5200 RESERVED_56 = 0x00000038, 5201 RESERVED_57 = 0x00000039, 5202 RESERVED_58 = 0x0000003a, 5203 RESERVED_59 = 0x0000003b, 5204 RESERVED_60 = 0x0000003c, 5205 RESERVED_61 = 0x0000003d, 5206 RESERVED_62 = 0x0000003e, 5207 RESERVED_63 = 0x0000003f, 5208 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040, 5209 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041, 5210 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042, 5211 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043, 5212 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044, 5213 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045, 5214 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046, 5215 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047, 5216 RESERVED_72 = 0x00000048, 5217 RESERVED_73 = 0x00000049, 5218 RESERVED_74 = 0x0000004a, 5219 RESERVED_75 = 0x0000004b, 5220 DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c, 5221 DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d, 5222 DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e, 5223 DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f, 5224 DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050, 5225 DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051, 5226 DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052, 5227 DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053, 5228 RESERVED_84 = 0x00000054, 5229 RESERVED_85 = 0x00000055, 5230 RESERVED_86 = 0x00000056, 5231 RESERVED_87 = 0x00000057, 5232 RESERVED_88 = 0x00000058, 5233 RESERVED_89 = 0x00000059, 5234 RESERVED_90 = 0x0000005a, 5235 RESERVED_91 = 0x0000005b, 5236 } DMU_DC_GPU_TIMER_READ_SELECT; 5237 5238 /* 5239 * DMU_DC_GPU_TIMER_START_POSITION enum 5240 */ 5241 5242 typedef enum DMU_DC_GPU_TIMER_START_POSITION { 5243 DMU_GPU_TIMER_START_0_END_27 = 0x00000000, 5244 DMU_GPU_TIMER_START_1_END_28 = 0x00000001, 5245 DMU_GPU_TIMER_START_2_END_29 = 0x00000002, 5246 DMU_GPU_TIMER_START_3_END_30 = 0x00000003, 5247 DMU_GPU_TIMER_START_4_END_31 = 0x00000004, 5248 DMU_GPU_TIMER_START_6_END_33 = 0x00000005, 5249 DMU_GPU_TIMER_START_8_END_35 = 0x00000006, 5250 DMU_GPU_TIMER_START_10_END_37 = 0x00000007, 5251 } DMU_DC_GPU_TIMER_START_POSITION; 5252 5253 /* 5254 * IHC_INTERRUPT_DEST enum 5255 */ 5256 5257 typedef enum IHC_INTERRUPT_DEST { 5258 INTERRUPT_SENT_TO_IH = 0x00000000, 5259 INTERRUPT_SENT_TO_DMCUB = 0x00000001, 5260 } IHC_INTERRUPT_DEST; 5261 5262 /* 5263 * IHC_INTERRUPT_LINE_STATUS enum 5264 */ 5265 5266 typedef enum IHC_INTERRUPT_LINE_STATUS { 5267 INTERRUPT_LINE_NOT_ASSERTED = 0x00000000, 5268 INTERRUPT_LINE_ASSERTED = 0x00000001, 5269 } IHC_INTERRUPT_LINE_STATUS; 5270 5271 /******************************************************* 5272 * DMU_MISC Enums 5273 *******************************************************/ 5274 5275 /* 5276 * DC_SMU_INTERRUPT_ENABLE enum 5277 */ 5278 5279 typedef enum DC_SMU_INTERRUPT_ENABLE { 5280 DISABLE_THE_INTERRUPT = 0x00000000, 5281 ENABLE_THE_INTERRUPT = 0x00000001, 5282 } DC_SMU_INTERRUPT_ENABLE; 5283 5284 /* 5285 * DMU_CLOCK_ON enum 5286 */ 5287 5288 typedef enum DMU_CLOCK_ON { 5289 DMU_CLOCK_STATUS_ON = 0x00000000, 5290 DMU_CLOCK_STATUS_OFF = 0x00000001, 5291 } DMU_CLOCK_ON; 5292 5293 /* 5294 * SMU_INTR enum 5295 */ 5296 5297 typedef enum SMU_INTR { 5298 SMU_MSG_INTR_NOOP = 0x00000000, 5299 SET_SMU_MSG_INTR = 0x00000001, 5300 } SMU_INTR; 5301 5302 /******************************************************* 5303 * DCCG Enums 5304 *******************************************************/ 5305 5306 /* 5307 * ALLOW_SR_ON_TRANS_REQ enum 5308 */ 5309 5310 typedef enum ALLOW_SR_ON_TRANS_REQ { 5311 ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, 5312 ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, 5313 } ALLOW_SR_ON_TRANS_REQ; 5314 5315 /* 5316 * AMCLOCK_ENABLE enum 5317 */ 5318 5319 typedef enum AMCLOCK_ENABLE { 5320 ENABLE_AMCLK0 = 0x00000000, 5321 ENABLE_AMCLK1 = 0x00000001, 5322 } AMCLOCK_ENABLE; 5323 5324 /* 5325 * CLEAR_SMU_INTR enum 5326 */ 5327 5328 typedef enum CLEAR_SMU_INTR { 5329 SMU_INTR_STATUS_NOOP = 0x00000000, 5330 SMU_INTR_STATUS_CLEAR = 0x00000001, 5331 } CLEAR_SMU_INTR; 5332 5333 /* 5334 * CLOCK_BRANCH_SOFT_RESET enum 5335 */ 5336 5337 typedef enum CLOCK_BRANCH_SOFT_RESET { 5338 CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, 5339 CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, 5340 } CLOCK_BRANCH_SOFT_RESET; 5341 5342 /* 5343 * DCCG_AUDIO_DTO0_SOURCE_SEL enum 5344 */ 5345 5346 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { 5347 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000, 5348 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001, 5349 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002, 5350 DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003, 5351 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004, 5352 } DCCG_AUDIO_DTO0_SOURCE_SEL; 5353 5354 /* 5355 * DCCG_AUDIO_DTO2_SOURCE_SEL enum 5356 */ 5357 5358 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { 5359 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, 5360 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001, 5361 } DCCG_AUDIO_DTO2_SOURCE_SEL; 5362 5363 /* 5364 * DCCG_AUDIO_DTO_SEL enum 5365 */ 5366 5367 typedef enum DCCG_AUDIO_DTO_SEL { 5368 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, 5369 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, 5370 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, 5371 } DCCG_AUDIO_DTO_SEL; 5372 5373 /* 5374 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum 5375 */ 5376 5377 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { 5378 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, 5379 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, 5380 } DCCG_AUDIO_DTO_USE_512FBR_DTO; 5381 5382 /* 5383 * DCCG_DBG_BLOCK_SEL enum 5384 */ 5385 5386 typedef enum DCCG_DBG_BLOCK_SEL { 5387 DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000, 5388 DCCG_DBG_BLOCK_SEL_PMON = 0x00000001, 5389 DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002, 5390 } DCCG_DBG_BLOCK_SEL; 5391 5392 /* 5393 * DCCG_DBG_EN enum 5394 */ 5395 5396 typedef enum DCCG_DBG_EN { 5397 DCCG_DBG_EN_DISABLE = 0x00000000, 5398 DCCG_DBG_EN_ENABLE = 0x00000001, 5399 } DCCG_DBG_EN; 5400 5401 /* 5402 * DCCG_DEEP_COLOR_CNTL enum 5403 */ 5404 5405 typedef enum DCCG_DEEP_COLOR_CNTL { 5406 DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, 5407 DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, 5408 DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, 5409 DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, 5410 } DCCG_DEEP_COLOR_CNTL; 5411 5412 /* 5413 * DCCG_FIFO_ERRDET_OVR_EN enum 5414 */ 5415 5416 typedef enum DCCG_FIFO_ERRDET_OVR_EN { 5417 DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, 5418 DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, 5419 } DCCG_FIFO_ERRDET_OVR_EN; 5420 5421 /* 5422 * DCCG_FIFO_ERRDET_RESET enum 5423 */ 5424 5425 typedef enum DCCG_FIFO_ERRDET_RESET { 5426 DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, 5427 DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, 5428 } DCCG_FIFO_ERRDET_RESET; 5429 5430 /* 5431 * DCCG_FIFO_ERRDET_STATE enum 5432 */ 5433 5434 typedef enum DCCG_FIFO_ERRDET_STATE { 5435 DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000, 5436 DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001, 5437 } DCCG_FIFO_ERRDET_STATE; 5438 5439 /* 5440 * DCCG_PERF_MODE_HSYNC enum 5441 */ 5442 5443 typedef enum DCCG_PERF_MODE_HSYNC { 5444 DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, 5445 DCCG_PERF_MODE_HSYNC_START = 0x00000001, 5446 } DCCG_PERF_MODE_HSYNC; 5447 5448 /* 5449 * DCCG_PERF_MODE_VSYNC enum 5450 */ 5451 5452 typedef enum DCCG_PERF_MODE_VSYNC { 5453 DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, 5454 DCCG_PERF_MODE_VSYNC_START = 0x00000001, 5455 } DCCG_PERF_MODE_VSYNC; 5456 5457 /* 5458 * DCCG_PERF_OTG_SELECT enum 5459 */ 5460 5461 typedef enum DCCG_PERF_OTG_SELECT { 5462 DCCG_PERF_SEL_OTG0 = 0x00000000, 5463 DCCG_PERF_SEL_OTG1 = 0x00000001, 5464 DCCG_PERF_SEL_OTG2 = 0x00000002, 5465 DCCG_PERF_SEL_OTG3 = 0x00000003, 5466 DCCG_PERF_SEL_RESERVED = 0x00000004, 5467 } DCCG_PERF_OTG_SELECT; 5468 5469 /* 5470 * DCCG_PERF_RUN enum 5471 */ 5472 5473 typedef enum DCCG_PERF_RUN { 5474 DCCG_PERF_RUN_NOOP = 0x00000000, 5475 DCCG_PERF_RUN_START = 0x00000001, 5476 } DCCG_PERF_RUN; 5477 5478 /* 5479 * DC_MEM_GLOBAL_PWR_REQ_DIS enum 5480 */ 5481 5482 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { 5483 DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, 5484 DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, 5485 } DC_MEM_GLOBAL_PWR_REQ_DIS; 5486 5487 /* 5488 * DIO_FIFO_ERROR enum 5489 */ 5490 5491 typedef enum DIO_FIFO_ERROR { 5492 DIO_FIFO_ERROR_00 = 0x00000000, 5493 DIO_FIFO_ERROR_01 = 0x00000001, 5494 DIO_FIFO_ERROR_10 = 0x00000002, 5495 DIO_FIFO_ERROR_11 = 0x00000003, 5496 } DIO_FIFO_ERROR; 5497 5498 /* 5499 * DISABLE_CLOCK_GATING enum 5500 */ 5501 5502 typedef enum DISABLE_CLOCK_GATING { 5503 CLOCK_GATING_ENABLED = 0x00000000, 5504 CLOCK_GATING_DISABLED = 0x00000001, 5505 } DISABLE_CLOCK_GATING; 5506 5507 /* 5508 * DISABLE_CLOCK_GATING_IN_DCO enum 5509 */ 5510 5511 typedef enum DISABLE_CLOCK_GATING_IN_DCO { 5512 CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, 5513 CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, 5514 } DISABLE_CLOCK_GATING_IN_DCO; 5515 5516 /* 5517 * DISPCLK_CHG_FWD_CORR_DISABLE enum 5518 */ 5519 5520 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { 5521 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, 5522 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, 5523 } DISPCLK_CHG_FWD_CORR_DISABLE; 5524 5525 /* 5526 * DISPCLK_FREQ_RAMP_DONE enum 5527 */ 5528 5529 typedef enum DISPCLK_FREQ_RAMP_DONE { 5530 DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, 5531 DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, 5532 } DISPCLK_FREQ_RAMP_DONE; 5533 5534 /* 5535 * DPREFCLK_SRC_SEL enum 5536 */ 5537 5538 typedef enum DPREFCLK_SRC_SEL { 5539 DPREFCLK_SRC_SEL_CK = 0x00000000, 5540 DPREFCLK_SRC_SEL_P0PLL = 0x00000001, 5541 DPREFCLK_SRC_SEL_P1PLL = 0x00000002, 5542 DPREFCLK_SRC_SEL_P2PLL = 0x00000003, 5543 } DPREFCLK_SRC_SEL; 5544 5545 /* 5546 * DP_DTO_DS_DISABLE enum 5547 */ 5548 5549 typedef enum DP_DTO_DS_DISABLE { 5550 DP_DTO_DESPREAD_DISABLE = 0x00000000, 5551 DP_DTO_DESPREAD_ENABLE = 0x00000001, 5552 } DP_DTO_DS_DISABLE; 5553 5554 /* 5555 * DS_HW_CAL_ENABLE enum 5556 */ 5557 5558 typedef enum DS_HW_CAL_ENABLE { 5559 DS_HW_CAL_DIS = 0x00000000, 5560 DS_HW_CAL_EN = 0x00000001, 5561 } DS_HW_CAL_ENABLE; 5562 5563 /* 5564 * DS_REF_SRC enum 5565 */ 5566 5567 typedef enum DS_REF_SRC { 5568 DS_REF_IS_XTALIN = 0x00000000, 5569 DS_REF_IS_EXT_GENLOCK = 0x00000001, 5570 DS_REF_IS_PCIE = 0x00000002, 5571 } DS_REF_SRC; 5572 5573 /* 5574 * DVO_ENABLE_RST enum 5575 */ 5576 5577 typedef enum DVO_ENABLE_RST { 5578 DVO_ENABLE_RST_DISABLE = 0x00000000, 5579 DVO_ENABLE_RST_ENABLE = 0x00000001, 5580 } DVO_ENABLE_RST; 5581 5582 /* 5583 * ENABLE enum 5584 */ 5585 5586 typedef enum ENABLE { 5587 DISABLE_THE_FEATURE = 0x00000000, 5588 ENABLE_THE_FEATURE = 0x00000001, 5589 } ENABLE; 5590 5591 /* 5592 * ENABLE_CLOCK enum 5593 */ 5594 5595 typedef enum ENABLE_CLOCK { 5596 ENABLE_THE_REFCLK = 0x00000000, 5597 ENABLE_THE_FUNC_CLOCK = 0x00000001, 5598 } ENABLE_CLOCK; 5599 5600 /* 5601 * FORCE_DISABLE_CLOCK enum 5602 */ 5603 5604 typedef enum FORCE_DISABLE_CLOCK { 5605 NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000, 5606 FORCE_THE_CLOCK_DISABLED = 0x00000001, 5607 } FORCE_DISABLE_CLOCK; 5608 5609 /* 5610 * HDMICHARCLK_SRC_SEL enum 5611 */ 5612 5613 typedef enum HDMICHARCLK_SRC_SEL { 5614 HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000, 5615 HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001, 5616 HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002, 5617 HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003, 5618 HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000004, 5619 } HDMICHARCLK_SRC_SEL; 5620 5621 /* 5622 * HDMISTREAMCLK_SRC_SEL enum 5623 */ 5624 5625 typedef enum HDMISTREAMCLK_SRC_SEL { 5626 SEL_DTBCLK_P0 = 0x00000000, 5627 SEL_DTBCLK_P1 = 0x00000001, 5628 SEL_DTBCLK_P2 = 0x00000002, 5629 SEL_DTBCLK_P3 = 0x00000003, 5630 } HDMISTREAMCLK_SRC_SEL; 5631 5632 /* 5633 * JITTER_REMOVE_DISABLE enum 5634 */ 5635 5636 typedef enum JITTER_REMOVE_DISABLE { 5637 ENABLE_JITTER_REMOVAL = 0x00000000, 5638 DISABLE_JITTER_REMOVAL = 0x00000001, 5639 } JITTER_REMOVE_DISABLE; 5640 5641 /* 5642 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum 5643 */ 5644 5645 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { 5646 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, 5647 MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, 5648 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; 5649 5650 /* 5651 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum 5652 */ 5653 5654 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { 5655 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, 5656 MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, 5657 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; 5658 5659 /* 5660 * OTG_ADD_PIXEL enum 5661 */ 5662 5663 typedef enum OTG_ADD_PIXEL { 5664 OTG_ADD_PIXEL_NOOP = 0x00000000, 5665 OTG_ADD_PIXEL_FORCE = 0x00000001, 5666 } OTG_ADD_PIXEL; 5667 5668 /* 5669 * OTG_DROP_PIXEL enum 5670 */ 5671 5672 typedef enum OTG_DROP_PIXEL { 5673 OTG_DROP_PIXEL_NOOP = 0x00000000, 5674 OTG_DROP_PIXEL_FORCE = 0x00000001, 5675 } OTG_DROP_PIXEL; 5676 5677 /* 5678 * PHYSYMCLK_FORCE_EN enum 5679 */ 5680 5681 typedef enum PHYSYMCLK_FORCE_EN { 5682 PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000, 5683 PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001, 5684 } PHYSYMCLK_FORCE_EN; 5685 5686 /* 5687 * PHYSYMCLK_FORCE_SRC_SEL enum 5688 */ 5689 5690 typedef enum PHYSYMCLK_FORCE_SRC_SEL { 5691 PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000, 5692 PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001, 5693 PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002, 5694 } PHYSYMCLK_FORCE_SRC_SEL; 5695 5696 /* 5697 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum 5698 */ 5699 5700 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { 5701 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, 5702 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, 5703 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, 5704 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, 5705 PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004, 5706 } PIPE_PHYPLL_PIXEL_RATE_SOURCE; 5707 5708 /* 5709 * PIPE_PIXEL_RATE_PLL_SOURCE enum 5710 */ 5711 5712 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { 5713 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, 5714 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, 5715 } PIPE_PIXEL_RATE_PLL_SOURCE; 5716 5717 /* 5718 * PIPE_PIXEL_RATE_SOURCE enum 5719 */ 5720 5721 typedef enum PIPE_PIXEL_RATE_SOURCE { 5722 PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, 5723 PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, 5724 PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, 5725 } PIPE_PIXEL_RATE_SOURCE; 5726 5727 /* 5728 * PLL_CFG_IF_SOFT_RESET enum 5729 */ 5730 5731 typedef enum PLL_CFG_IF_SOFT_RESET { 5732 PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, 5733 PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, 5734 } PLL_CFG_IF_SOFT_RESET; 5735 5736 /* 5737 * SYMCLK_FE_SRC enum 5738 */ 5739 5740 typedef enum SYMCLK_FE_SRC { 5741 SYMCLK_FE_SRC_UNIPHYA = 0x00000000, 5742 SYMCLK_FE_SRC_UNIPHYB = 0x00000001, 5743 SYMCLK_FE_SRC_UNIPHYC = 0x00000002, 5744 SYMCLK_FE_SRC_UNIPHYD = 0x00000003, 5745 SYMCLK_FE_SRC_RESERVED = 0x00000004, 5746 } SYMCLK_FE_SRC; 5747 5748 /* 5749 * TEST_CLK_DIV_SEL enum 5750 */ 5751 5752 typedef enum TEST_CLK_DIV_SEL { 5753 NO_DIV = 0x00000000, 5754 DIV_2 = 0x00000001, 5755 DIV_4 = 0x00000002, 5756 DIV_8 = 0x00000003, 5757 } TEST_CLK_DIV_SEL; 5758 5759 /* 5760 * VSYNC_CNT_LATCH_MASK enum 5761 */ 5762 5763 typedef enum VSYNC_CNT_LATCH_MASK { 5764 VSYNC_CNT_LATCH_MASK_0 = 0x00000000, 5765 VSYNC_CNT_LATCH_MASK_1 = 0x00000001, 5766 } VSYNC_CNT_LATCH_MASK; 5767 5768 /* 5769 * VSYNC_CNT_RESET_SEL enum 5770 */ 5771 5772 typedef enum VSYNC_CNT_RESET_SEL { 5773 VSYNC_CNT_RESET_SEL_0 = 0x00000000, 5774 VSYNC_CNT_RESET_SEL_1 = 0x00000001, 5775 } VSYNC_CNT_RESET_SEL; 5776 5777 /* 5778 * XTAL_REF_CLOCK_SOURCE_SEL enum 5779 */ 5780 5781 typedef enum XTAL_REF_CLOCK_SOURCE_SEL { 5782 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, 5783 XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001, 5784 } XTAL_REF_CLOCK_SOURCE_SEL; 5785 5786 /* 5787 * XTAL_REF_SEL enum 5788 */ 5789 5790 typedef enum XTAL_REF_SEL { 5791 XTAL_REF_SEL_1X = 0x00000000, 5792 XTAL_REF_SEL_2X = 0x00000001, 5793 } XTAL_REF_SEL; 5794 5795 /******************************************************* 5796 * DP Enums 5797 *******************************************************/ 5798 5799 /* 5800 * DPHY_8B10B_CUR_DISP enum 5801 */ 5802 5803 typedef enum DPHY_8B10B_CUR_DISP { 5804 DPHY_8B10B_CUR_DISP_ZERO = 0x00000000, 5805 DPHY_8B10B_CUR_DISP_ONE = 0x00000001, 5806 } DPHY_8B10B_CUR_DISP; 5807 5808 /* 5809 * DPHY_8B10B_RESET enum 5810 */ 5811 5812 typedef enum DPHY_8B10B_RESET { 5813 DPHY_8B10B_NOT_RESET = 0x00000000, 5814 DPHY_8B10B_RESETET = 0x00000001, 5815 } DPHY_8B10B_RESET; 5816 5817 /* 5818 * DPHY_ATEST_SEL_LANE0 enum 5819 */ 5820 5821 typedef enum DPHY_ATEST_SEL_LANE0 { 5822 DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, 5823 DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, 5824 } DPHY_ATEST_SEL_LANE0; 5825 5826 /* 5827 * DPHY_ATEST_SEL_LANE1 enum 5828 */ 5829 5830 typedef enum DPHY_ATEST_SEL_LANE1 { 5831 DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, 5832 DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, 5833 } DPHY_ATEST_SEL_LANE1; 5834 5835 /* 5836 * DPHY_ATEST_SEL_LANE2 enum 5837 */ 5838 5839 typedef enum DPHY_ATEST_SEL_LANE2 { 5840 DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, 5841 DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, 5842 } DPHY_ATEST_SEL_LANE2; 5843 5844 /* 5845 * DPHY_ATEST_SEL_LANE3 enum 5846 */ 5847 5848 typedef enum DPHY_ATEST_SEL_LANE3 { 5849 DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, 5850 DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, 5851 } DPHY_ATEST_SEL_LANE3; 5852 5853 /* 5854 * DPHY_BYPASS enum 5855 */ 5856 5857 typedef enum DPHY_BYPASS { 5858 DPHY_8B10B_OUTPUT = 0x00000000, 5859 DPHY_DBG_OUTPUT = 0x00000001, 5860 } DPHY_BYPASS; 5861 5862 /* 5863 * DPHY_CRC_CONT_EN enum 5864 */ 5865 5866 typedef enum DPHY_CRC_CONT_EN { 5867 DPHY_CRC_ONE_SHOT = 0x00000000, 5868 DPHY_CRC_CONTINUOUS = 0x00000001, 5869 } DPHY_CRC_CONT_EN; 5870 5871 /* 5872 * DPHY_CRC_EN enum 5873 */ 5874 5875 typedef enum DPHY_CRC_EN { 5876 DPHY_CRC_DISABLED = 0x00000000, 5877 DPHY_CRC_ENABLED = 0x00000001, 5878 } DPHY_CRC_EN; 5879 5880 /* 5881 * DPHY_CRC_FIELD enum 5882 */ 5883 5884 typedef enum DPHY_CRC_FIELD { 5885 DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000, 5886 DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001, 5887 } DPHY_CRC_FIELD; 5888 5889 /* 5890 * DPHY_CRC_MST_PHASE_ERROR_ACK enum 5891 */ 5892 5893 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { 5894 DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000, 5895 DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001, 5896 } DPHY_CRC_MST_PHASE_ERROR_ACK; 5897 5898 /* 5899 * DPHY_CRC_SEL enum 5900 */ 5901 5902 typedef enum DPHY_CRC_SEL { 5903 DPHY_CRC_LANE0_SELECTED = 0x00000000, 5904 DPHY_CRC_LANE1_SELECTED = 0x00000001, 5905 DPHY_CRC_LANE2_SELECTED = 0x00000002, 5906 DPHY_CRC_LANE3_SELECTED = 0x00000003, 5907 } DPHY_CRC_SEL; 5908 5909 /* 5910 * DPHY_FEC_ENABLE enum 5911 */ 5912 5913 typedef enum DPHY_FEC_ENABLE { 5914 DPHY_FEC_DISABLED = 0x00000000, 5915 DPHY_FEC_ENABLED = 0x00000001, 5916 } DPHY_FEC_ENABLE; 5917 5918 /* 5919 * DPHY_FEC_READY enum 5920 */ 5921 5922 typedef enum DPHY_FEC_READY { 5923 DPHY_FEC_READY_EN = 0x00000000, 5924 DPHY_FEC_READY_DIS = 0x00000001, 5925 } DPHY_FEC_READY; 5926 5927 /* 5928 * DPHY_LOAD_BS_COUNT_START enum 5929 */ 5930 5931 typedef enum DPHY_LOAD_BS_COUNT_START { 5932 DPHY_LOAD_BS_COUNT_STARTED = 0x00000000, 5933 DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001, 5934 } DPHY_LOAD_BS_COUNT_START; 5935 5936 /* 5937 * DPHY_PRBS_EN enum 5938 */ 5939 5940 typedef enum DPHY_PRBS_EN { 5941 DPHY_PRBS_DISABLE = 0x00000000, 5942 DPHY_PRBS_ENABLE = 0x00000001, 5943 } DPHY_PRBS_EN; 5944 5945 /* 5946 * DPHY_PRBS_SEL enum 5947 */ 5948 5949 typedef enum DPHY_PRBS_SEL { 5950 DPHY_PRBS7_SELECTED = 0x00000000, 5951 DPHY_PRBS23_SELECTED = 0x00000001, 5952 DPHY_PRBS11_SELECTED = 0x00000002, 5953 } DPHY_PRBS_SEL; 5954 5955 /* 5956 * DPHY_RX_FAST_TRAINING_CAPABLE enum 5957 */ 5958 5959 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { 5960 DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000, 5961 DPHY_FAST_TRAINING_CAPABLE = 0x00000001, 5962 } DPHY_RX_FAST_TRAINING_CAPABLE; 5963 5964 /* 5965 * DPHY_SKEW_BYPASS enum 5966 */ 5967 5968 typedef enum DPHY_SKEW_BYPASS { 5969 DPHY_WITH_SKEW = 0x00000000, 5970 DPHY_NO_SKEW = 0x00000001, 5971 } DPHY_SKEW_BYPASS; 5972 5973 /* 5974 * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum 5975 */ 5976 5977 typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM { 5978 DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000, 5979 DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001, 5980 } DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM; 5981 5982 /* 5983 * DPHY_SW_FAST_TRAINING_START enum 5984 */ 5985 5986 typedef enum DPHY_SW_FAST_TRAINING_START { 5987 DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000, 5988 DPHY_SW_FAST_TRAINING_STARTED = 0x00000001, 5989 } DPHY_SW_FAST_TRAINING_START; 5990 5991 /* 5992 * DPHY_TRAINING_PATTERN_SEL enum 5993 */ 5994 5995 typedef enum DPHY_TRAINING_PATTERN_SEL { 5996 DPHY_TRAINING_PATTERN_1 = 0x00000000, 5997 DPHY_TRAINING_PATTERN_2 = 0x00000001, 5998 DPHY_TRAINING_PATTERN_3 = 0x00000002, 5999 DPHY_TRAINING_PATTERN_4 = 0x00000003, 6000 } DPHY_TRAINING_PATTERN_SEL; 6001 6002 /* 6003 * DP_COMPONENT_DEPTH enum 6004 */ 6005 6006 typedef enum DP_COMPONENT_DEPTH { 6007 DP_COMPONENT_DEPTH_6BPC = 0x00000000, 6008 DP_COMPONENT_DEPTH_8BPC = 0x00000001, 6009 DP_COMPONENT_DEPTH_10BPC = 0x00000002, 6010 DP_COMPONENT_DEPTH_12BPC = 0x00000003, 6011 DP_COMPONENT_DEPTH_16BPC = 0x00000004, 6012 } DP_COMPONENT_DEPTH; 6013 6014 /* 6015 * DP_COMPRESSED_PIXEL_FORMAT enum 6016 */ 6017 6018 typedef enum DP_COMPRESSED_PIXEL_FORMAT { 6019 DP_DSC_444_S422 = 0x00000000, 6020 DP_DSC_N422_N420 = 0x00000001, 6021 } DP_COMPRESSED_PIXEL_FORMAT; 6022 6023 /* 6024 * DP_DPHY_8B10B_EXT_DISP enum 6025 */ 6026 6027 typedef enum DP_DPHY_8B10B_EXT_DISP { 6028 DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000, 6029 DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001, 6030 } DP_DPHY_8B10B_EXT_DISP; 6031 6032 /* 6033 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum 6034 */ 6035 6036 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { 6037 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000, 6038 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001, 6039 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK; 6040 6041 /* 6042 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum 6043 */ 6044 6045 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { 6046 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000, 6047 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001, 6048 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK; 6049 6050 /* 6051 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum 6052 */ 6053 6054 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { 6055 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000, 6056 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001, 6057 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; 6058 6059 /* 6060 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum 6061 */ 6062 6063 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { 6064 DP_DPHY_HBR2_PASS_THROUGH = 0x00000000, 6065 DP_DPHY_HBR2_PATTERN_1 = 0x00000001, 6066 DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002, 6067 DP_DPHY_HBR2_PATTERN_3 = 0x00000003, 6068 DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006, 6069 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE; 6070 6071 /* 6072 * DP_LINK_TRAINING_COMPLETE enum 6073 */ 6074 6075 typedef enum DP_LINK_TRAINING_COMPLETE { 6076 DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, 6077 DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, 6078 } DP_LINK_TRAINING_COMPLETE; 6079 6080 /* 6081 * DP_LINK_TRAINING_SWITCH_MODE enum 6082 */ 6083 6084 typedef enum DP_LINK_TRAINING_SWITCH_MODE { 6085 DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000, 6086 DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001, 6087 } DP_LINK_TRAINING_SWITCH_MODE; 6088 6089 /* 6090 * DP_ML_PHY_SEQ_MODE enum 6091 */ 6092 6093 typedef enum DP_ML_PHY_SEQ_MODE { 6094 DP_ML_PHY_SEQ_LINE_NUM = 0x00000000, 6095 DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001, 6096 } DP_ML_PHY_SEQ_MODE; 6097 6098 /* 6099 * DP_MSA_V_TIMING_OVERRIDE_EN enum 6100 */ 6101 6102 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { 6103 MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000, 6104 MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001, 6105 } DP_MSA_V_TIMING_OVERRIDE_EN; 6106 6107 /* 6108 * DP_MSE_BLANK_CODE enum 6109 */ 6110 6111 typedef enum DP_MSE_BLANK_CODE { 6112 DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000, 6113 DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001, 6114 } DP_MSE_BLANK_CODE; 6115 6116 /* 6117 * DP_MSE_LINK_LINE enum 6118 */ 6119 6120 typedef enum DP_MSE_LINK_LINE { 6121 DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000, 6122 DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001, 6123 DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002, 6124 DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003, 6125 } DP_MSE_LINK_LINE; 6126 6127 /* 6128 * DP_MSE_TIMESTAMP_MODE enum 6129 */ 6130 6131 typedef enum DP_MSE_TIMESTAMP_MODE { 6132 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000, 6133 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001, 6134 } DP_MSE_TIMESTAMP_MODE; 6135 6136 /* 6137 * DP_MSE_ZERO_ENCODER enum 6138 */ 6139 6140 typedef enum DP_MSE_ZERO_ENCODER { 6141 DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000, 6142 DP_MSE_ZERO_FE_ENCODER = 0x00000001, 6143 } DP_MSE_ZERO_ENCODER; 6144 6145 /* 6146 * DP_MSO_NUM_OF_SST_LINKS enum 6147 */ 6148 6149 typedef enum DP_MSO_NUM_OF_SST_LINKS { 6150 DP_MSO_ONE_SSTLINK = 0x00000000, 6151 DP_MSO_TWO_SSTLINK = 0x00000001, 6152 DP_MSO_FOUR_SSTLINK = 0x00000002, 6153 } DP_MSO_NUM_OF_SST_LINKS; 6154 6155 /* 6156 * DP_PIXEL_ENCODING enum 6157 */ 6158 6159 typedef enum DP_PIXEL_ENCODING { 6160 DP_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000, 6161 DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, 6162 DP_PIXEL_ENCODING_YCBCR420 = 0x00000002, 6163 DP_PIXEL_ENCODING_Y_ONLY = 0x00000003, 6164 } DP_PIXEL_ENCODING; 6165 6166 /* 6167 * DP_PIXEL_ENCODING_TYPE enum 6168 */ 6169 6170 typedef enum DP_PIXEL_ENCODING_TYPE { 6171 DP_PIXEL_ENCODING_UNCOMPRESSED = 0x00000000, 6172 DP_PIXEL_ENCODING_COMPRESSED = 0x00000001, 6173 } DP_PIXEL_ENCODING_TYPE; 6174 6175 /* 6176 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum 6177 */ 6178 6179 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { 6180 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, 6181 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, 6182 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; 6183 6184 /* 6185 * DP_SEC_ASP_PRIORITY enum 6186 */ 6187 6188 typedef enum DP_SEC_ASP_PRIORITY { 6189 DP_SEC_ASP_LOW_PRIORITY = 0x00000000, 6190 DP_SEC_ASP_HIGH_PRIORITY = 0x00000001, 6191 } DP_SEC_ASP_PRIORITY; 6192 6193 /* 6194 * DP_SEC_AUDIO_MUTE enum 6195 */ 6196 6197 typedef enum DP_SEC_AUDIO_MUTE { 6198 DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000, 6199 DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001, 6200 } DP_SEC_AUDIO_MUTE; 6201 6202 /* 6203 * DP_SEC_COLLISION_ACK enum 6204 */ 6205 6206 typedef enum DP_SEC_COLLISION_ACK { 6207 DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000, 6208 DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001, 6209 } DP_SEC_COLLISION_ACK; 6210 6211 /* 6212 * DP_SEC_GSP0_PRIORITY enum 6213 */ 6214 6215 typedef enum DP_SEC_GSP0_PRIORITY { 6216 SEC_GSP0_PRIORITY_LOW = 0x00000000, 6217 SEC_GSP0_PRIORITY_HIGH = 0x00000001, 6218 } DP_SEC_GSP0_PRIORITY; 6219 6220 /* 6221 * DP_SEC_GSP_SEND enum 6222 */ 6223 6224 typedef enum DP_SEC_GSP_SEND { 6225 NOT_SENT = 0x00000000, 6226 FORCE_SENT = 0x00000001, 6227 } DP_SEC_GSP_SEND; 6228 6229 /* 6230 * DP_SEC_GSP_SEND_ANY_LINE enum 6231 */ 6232 6233 typedef enum DP_SEC_GSP_SEND_ANY_LINE { 6234 SEND_AT_LINK_NUMBER = 0x00000000, 6235 SEND_AT_EARLIEST_TIME = 0x00000001, 6236 } DP_SEC_GSP_SEND_ANY_LINE; 6237 6238 /* 6239 * DP_SEC_GSP_SEND_PPS enum 6240 */ 6241 6242 typedef enum DP_SEC_GSP_SEND_PPS { 6243 SEND_NORMAL_PACKET = 0x00000000, 6244 SEND_PPS_PACKET = 0x00000001, 6245 } DP_SEC_GSP_SEND_PPS; 6246 6247 /* 6248 * DP_SEC_LINE_REFERENCE enum 6249 */ 6250 6251 typedef enum DP_SEC_LINE_REFERENCE { 6252 REFER_TO_DP_SOF = 0x00000000, 6253 REFER_TO_OTG_SOF = 0x00000001, 6254 } DP_SEC_LINE_REFERENCE; 6255 6256 /* 6257 * DP_SEC_TIMESTAMP_MODE enum 6258 */ 6259 6260 typedef enum DP_SEC_TIMESTAMP_MODE { 6261 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000, 6262 DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001, 6263 } DP_SEC_TIMESTAMP_MODE; 6264 6265 /* 6266 * DP_STEER_OUTPUT_PIXEL_PER_CYCLE enum 6267 */ 6268 6269 typedef enum DP_STEER_OUTPUT_PIXEL_PER_CYCLE { 6270 DP_STEER_1_PIX_PER_CYCLE = 0x00000000, 6271 DP_STEER_2_PIX_PER_CYCLE = 0x00000001, 6272 DP_STEER_4_PIX_PER_CYCLE = 0x00000002, 6273 DP_STEER_8_PIX_PER_CYCLE = 0x00000003, 6274 } DP_STEER_OUTPUT_PIXEL_PER_CYCLE; 6275 6276 /* 6277 * DP_STEER_OVERFLOW_ACK enum 6278 */ 6279 6280 typedef enum DP_STEER_OVERFLOW_ACK { 6281 DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, 6282 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, 6283 } DP_STEER_OVERFLOW_ACK; 6284 6285 /* 6286 * DP_STEER_OVERFLOW_MASK enum 6287 */ 6288 6289 typedef enum DP_STEER_OVERFLOW_MASK { 6290 DP_STEER_OVERFLOW_MASKED = 0x00000000, 6291 DP_STEER_OVERFLOW_UNMASK = 0x00000001, 6292 } DP_STEER_OVERFLOW_MASK; 6293 6294 /* 6295 * DP_SYNC_POLARITY enum 6296 */ 6297 6298 typedef enum DP_SYNC_POLARITY { 6299 DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000, 6300 DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001, 6301 } DP_SYNC_POLARITY; 6302 6303 /* 6304 * DP_TU_OVERFLOW_ACK enum 6305 */ 6306 6307 typedef enum DP_TU_OVERFLOW_ACK { 6308 DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, 6309 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, 6310 } DP_TU_OVERFLOW_ACK; 6311 6312 /* 6313 * DP_UDI_LANES enum 6314 */ 6315 6316 typedef enum DP_UDI_LANES { 6317 DP_UDI_1_LANE = 0x00000000, 6318 DP_UDI_2_LANES = 0x00000001, 6319 DP_UDI_LANES_RESERVED = 0x00000002, 6320 DP_UDI_4_LANES = 0x00000003, 6321 } DP_UDI_LANES; 6322 6323 /* 6324 * DP_VID_ENHANCED_FRAME_MODE enum 6325 */ 6326 6327 typedef enum DP_VID_ENHANCED_FRAME_MODE { 6328 VID_NORMAL_FRAME_MODE = 0x00000000, 6329 VID_ENHANCED_MODE = 0x00000001, 6330 } DP_VID_ENHANCED_FRAME_MODE; 6331 6332 /* 6333 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum 6334 */ 6335 6336 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { 6337 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, 6338 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, 6339 } DP_VID_M_N_DOUBLE_BUFFER_MODE; 6340 6341 /* 6342 * DP_VID_M_N_GEN_EN enum 6343 */ 6344 6345 typedef enum DP_VID_M_N_GEN_EN { 6346 DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, 6347 DP_VID_M_N_CALC_AUTO = 0x00000001, 6348 } DP_VID_M_N_GEN_EN; 6349 6350 /* 6351 * DP_VID_N_INTERVAL enum 6352 */ 6353 6354 typedef enum DP_VID_N_INTERVAL { 6355 DP_VID_1X_Nvid = 0x00000000, 6356 DP_VID_2X_Nvid = 0x00000001, 6357 DP_VID_4X_Nvid = 0x00000002, 6358 DP_VID_8X_Nvid = 0x00000003, 6359 } DP_VID_N_INTERVAL; 6360 6361 /* 6362 * DP_VID_STREAM_DISABLE_ACK enum 6363 */ 6364 6365 typedef enum DP_VID_STREAM_DISABLE_ACK { 6366 ID_STREAM_DISABLE_NO_ACK = 0x00000000, 6367 ID_STREAM_DISABLE_ACKED = 0x00000001, 6368 } DP_VID_STREAM_DISABLE_ACK; 6369 6370 /* 6371 * DP_VID_STREAM_DISABLE_MASK enum 6372 */ 6373 6374 typedef enum DP_VID_STREAM_DISABLE_MASK { 6375 VID_STREAM_DISABLE_MASKED = 0x00000000, 6376 VID_STREAM_DISABLE_UNMASK = 0x00000001, 6377 } DP_VID_STREAM_DISABLE_MASK; 6378 6379 /* 6380 * DP_VID_STREAM_DIS_DEFER enum 6381 */ 6382 6383 typedef enum DP_VID_STREAM_DIS_DEFER { 6384 DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, 6385 DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, 6386 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, 6387 } DP_VID_STREAM_DIS_DEFER; 6388 6389 /* 6390 * DP_VID_VBID_FIELD_POL enum 6391 */ 6392 6393 typedef enum DP_VID_VBID_FIELD_POL { 6394 DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, 6395 DP_VID_VBID_FIELD_POL_INV = 0x00000001, 6396 } DP_VID_VBID_FIELD_POL; 6397 6398 /* 6399 * FEC_ACTIVE_STATUS enum 6400 */ 6401 6402 typedef enum FEC_ACTIVE_STATUS { 6403 DPHY_FEC_NOT_ACTIVE = 0x00000000, 6404 DPHY_FEC_ACTIVE = 0x00000001, 6405 } FEC_ACTIVE_STATUS; 6406 6407 /******************************************************* 6408 * DIG Enums 6409 *******************************************************/ 6410 6411 /* 6412 * DIG_BE_CNTL_HPD_SELECT enum 6413 */ 6414 6415 typedef enum DIG_BE_CNTL_HPD_SELECT { 6416 DIG_BE_CNTL_HPD1 = 0x00000000, 6417 DIG_BE_CNTL_HPD2 = 0x00000001, 6418 DIG_BE_CNTL_HPD3 = 0x00000002, 6419 DIG_BE_CNTL_HPD4 = 0x00000003, 6420 DIG_BE_CNTL_NO_HPD = 0x00000004, 6421 } DIG_BE_CNTL_HPD_SELECT; 6422 6423 /* 6424 * DIG_BE_CNTL_MODE enum 6425 */ 6426 6427 typedef enum DIG_BE_CNTL_MODE { 6428 DIG_BE_DP_SST_MODE = 0x00000000, 6429 DIG_BE_RESERVED1 = 0x00000001, 6430 DIG_BE_TMDS_DVI_MODE = 0x00000002, 6431 DIG_BE_TMDS_HDMI_MODE = 0x00000003, 6432 DIG_BE_RESERVED4 = 0x00000004, 6433 DIG_BE_DP_MST_MODE = 0x00000005, 6434 DIG_BE_RESERVED2 = 0x00000006, 6435 DIG_BE_RESERVED3 = 0x00000007, 6436 } DIG_BE_CNTL_MODE; 6437 6438 /* 6439 * DIG_DIGITAL_BYPASS_ENABLE enum 6440 */ 6441 6442 typedef enum DIG_DIGITAL_BYPASS_ENABLE { 6443 DIG_DIGITAL_BYPASS_OFF = 0x00000000, 6444 DIG_DIGITAL_BYPASS_ON = 0x00000001, 6445 } DIG_DIGITAL_BYPASS_ENABLE; 6446 6447 /* 6448 * DIG_DIGITAL_BYPASS_SEL enum 6449 */ 6450 6451 typedef enum DIG_DIGITAL_BYPASS_SEL { 6452 DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000, 6453 DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001, 6454 DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002, 6455 DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003, 6456 DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004, 6457 DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005, 6458 DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006, 6459 } DIG_DIGITAL_BYPASS_SEL; 6460 6461 /* 6462 * DIG_FE_CNTL_SOURCE_SELECT enum 6463 */ 6464 6465 typedef enum DIG_FE_CNTL_SOURCE_SELECT { 6466 DIG_FE_SOURCE_FROM_OTG0 = 0x00000000, 6467 DIG_FE_SOURCE_FROM_OTG1 = 0x00000001, 6468 DIG_FE_SOURCE_FROM_OTG2 = 0x00000002, 6469 DIG_FE_SOURCE_FROM_OTG3 = 0x00000003, 6470 DIG_FE_SOURCE_RESERVED = 0x00000004, 6471 } DIG_FE_CNTL_SOURCE_SELECT; 6472 6473 /* 6474 * DIG_FE_CNTL_STEREOSYNC_SELECT enum 6475 */ 6476 6477 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { 6478 DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000, 6479 DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001, 6480 DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002, 6481 DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003, 6482 DIG_FE_STEREOSYNC_RESERVED = 0x00000004, 6483 } DIG_FE_CNTL_STEREOSYNC_SELECT; 6484 6485 /* 6486 * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum 6487 */ 6488 6489 typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX { 6490 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000, 6491 DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001, 6492 } DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX; 6493 6494 /* 6495 * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum 6496 */ 6497 6498 typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL { 6499 DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000, 6500 DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001, 6501 } DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL; 6502 6503 /* 6504 * DIG_FIFO_FORCE_RECAL_AVERAGE enum 6505 */ 6506 6507 typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE { 6508 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000, 6509 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001, 6510 } DIG_FIFO_FORCE_RECAL_AVERAGE; 6511 6512 /* 6513 * DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE enum 6514 */ 6515 6516 typedef enum DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE { 6517 DIG_FIFO_1_PIX_PER_CYCLE = 0x00000000, 6518 DIG_FIFO_2_PIX_PER_CYCLE = 0x00000001, 6519 DIG_FIFO_4_PIX_PER_CYCLE = 0x00000002, 6520 DIG_FIFO_8_PIX_PER_CYCLE = 0x00000003, 6521 } DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE; 6522 6523 /* 6524 * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum 6525 */ 6526 6527 typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR { 6528 DIG_FIFO_NO_ERROR_OCCURRED = 0x00000000, 6529 DIG_FIFO_UNDERFLOW_OCCURRED = 0x00000001, 6530 DIG_FIFO_OVERFLOW_OCCURRED = 0x00000002, 6531 } DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR; 6532 6533 /* 6534 * DIG_FIFO_READ_CLOCK_SRC enum 6535 */ 6536 6537 typedef enum DIG_FIFO_READ_CLOCK_SRC { 6538 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000, 6539 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001, 6540 } DIG_FIFO_READ_CLOCK_SRC; 6541 6542 /* 6543 * DIG_MODE enum 6544 */ 6545 6546 typedef enum DIG_MODE { 6547 DP_SST_MODE = 0x00000000, 6548 RESERVED1 = 0x00000001, 6549 TMDS_DVI_MODE = 0x00000002, 6550 TMDS_HDMI_MODE = 0x00000003, 6551 RESERVED4 = 0x00000004, 6552 DP_MST_MODE = 0x00000005, 6553 RESERVED2 = 0x00000006, 6554 RESERVED3 = 0x00000007, 6555 } DIG_MODE; 6556 6557 /* 6558 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum 6559 */ 6560 6561 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { 6562 DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000, 6563 DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001, 6564 } DIG_OUTPUT_CRC_CNTL_LINK_SEL; 6565 6566 /* 6567 * DIG_OUTPUT_CRC_DATA_SEL enum 6568 */ 6569 6570 typedef enum DIG_OUTPUT_CRC_DATA_SEL { 6571 DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000, 6572 DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001, 6573 DIG_OUTPUT_CRC_FOR_VBI = 0x00000002, 6574 DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003, 6575 } DIG_OUTPUT_CRC_DATA_SEL; 6576 6577 /* 6578 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum 6579 */ 6580 6581 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { 6582 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000, 6583 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001, 6584 } DIG_RANDOM_PATTERN_SEED_RAN_PAT; 6585 6586 /* 6587 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum 6588 */ 6589 6590 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { 6591 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000, 6592 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001, 6593 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN; 6594 6595 /* 6596 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum 6597 */ 6598 6599 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { 6600 DIG_10BIT_TEST_PATTERN = 0x00000000, 6601 DIG_ALTERNATING_TEST_PATTERN = 0x00000001, 6602 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; 6603 6604 /* 6605 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum 6606 */ 6607 6608 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { 6609 DIG_TEST_PATTERN_NORMAL = 0x00000000, 6610 DIG_TEST_PATTERN_RANDOM = 0x00000001, 6611 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; 6612 6613 /* 6614 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum 6615 */ 6616 6617 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { 6618 DIG_RANDOM_PATTERN_ENABLED = 0x00000000, 6619 DIG_RANDOM_PATTERN_RESETED = 0x00000001, 6620 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; 6621 6622 /* 6623 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum 6624 */ 6625 6626 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { 6627 DIG_IN_NORMAL_OPERATION = 0x00000000, 6628 DIG_IN_DEBUG_MODE = 0x00000001, 6629 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; 6630 6631 /* 6632 * HDMI_ACP_SEND enum 6633 */ 6634 6635 typedef enum HDMI_ACP_SEND { 6636 HDMI_ACP_NOT_SEND = 0x00000000, 6637 HDMI_ACP_PKT_SEND = 0x00000001, 6638 } HDMI_ACP_SEND; 6639 6640 /* 6641 * HDMI_ACR_AUDIO_PRIORITY enum 6642 */ 6643 6644 typedef enum HDMI_ACR_AUDIO_PRIORITY { 6645 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, 6646 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, 6647 } HDMI_ACR_AUDIO_PRIORITY; 6648 6649 /* 6650 * HDMI_ACR_CONT enum 6651 */ 6652 6653 typedef enum HDMI_ACR_CONT { 6654 HDMI_ACR_CONT_DISABLE = 0x00000000, 6655 HDMI_ACR_CONT_ENABLE = 0x00000001, 6656 } HDMI_ACR_CONT; 6657 6658 /* 6659 * HDMI_ACR_N_MULTIPLE enum 6660 */ 6661 6662 typedef enum HDMI_ACR_N_MULTIPLE { 6663 HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000, 6664 HDMI_ACR_1_MULTIPLE = 0x00000001, 6665 HDMI_ACR_2_MULTIPLE = 0x00000002, 6666 HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003, 6667 HDMI_ACR_4_MULTIPLE = 0x00000004, 6668 HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005, 6669 HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006, 6670 HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007, 6671 } HDMI_ACR_N_MULTIPLE; 6672 6673 /* 6674 * HDMI_ACR_SELECT enum 6675 */ 6676 6677 typedef enum HDMI_ACR_SELECT { 6678 HDMI_ACR_SELECT_HW = 0x00000000, 6679 HDMI_ACR_SELECT_32K = 0x00000001, 6680 HDMI_ACR_SELECT_44K = 0x00000002, 6681 HDMI_ACR_SELECT_48K = 0x00000003, 6682 } HDMI_ACR_SELECT; 6683 6684 /* 6685 * HDMI_ACR_SEND enum 6686 */ 6687 6688 typedef enum HDMI_ACR_SEND { 6689 HDMI_ACR_NOT_SEND = 0x00000000, 6690 HDMI_ACR_PKT_SEND = 0x00000001, 6691 } HDMI_ACR_SEND; 6692 6693 /* 6694 * HDMI_ACR_SOURCE enum 6695 */ 6696 6697 typedef enum HDMI_ACR_SOURCE { 6698 HDMI_ACR_SOURCE_HW = 0x00000000, 6699 HDMI_ACR_SOURCE_SW = 0x00000001, 6700 } HDMI_ACR_SOURCE; 6701 6702 /* 6703 * HDMI_AUDIO_DELAY_EN enum 6704 */ 6705 6706 typedef enum HDMI_AUDIO_DELAY_EN { 6707 HDMI_AUDIO_DELAY_DISABLE = 0x00000000, 6708 HDMI_AUDIO_DELAY_58CLK = 0x00000001, 6709 HDMI_AUDIO_DELAY_56CLK = 0x00000002, 6710 HDMI_AUDIO_DELAY_RESERVED = 0x00000003, 6711 } HDMI_AUDIO_DELAY_EN; 6712 6713 /* 6714 * HDMI_AUDIO_INFO_CONT enum 6715 */ 6716 6717 typedef enum HDMI_AUDIO_INFO_CONT { 6718 HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000, 6719 HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001, 6720 } HDMI_AUDIO_INFO_CONT; 6721 6722 /* 6723 * HDMI_AUDIO_INFO_SEND enum 6724 */ 6725 6726 typedef enum HDMI_AUDIO_INFO_SEND { 6727 HDMI_AUDIO_INFO_NOT_SEND = 0x00000000, 6728 HDMI_AUDIO_INFO_PKT_SEND = 0x00000001, 6729 } HDMI_AUDIO_INFO_SEND; 6730 6731 /* 6732 * HDMI_CLOCK_CHANNEL_RATE enum 6733 */ 6734 6735 typedef enum HDMI_CLOCK_CHANNEL_RATE { 6736 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000, 6737 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001, 6738 } HDMI_CLOCK_CHANNEL_RATE; 6739 6740 /* 6741 * HDMI_DATA_SCRAMBLE_EN enum 6742 */ 6743 6744 typedef enum HDMI_DATA_SCRAMBLE_EN { 6745 HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000, 6746 HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001, 6747 } HDMI_DATA_SCRAMBLE_EN; 6748 6749 /* 6750 * HDMI_DEEP_COLOR_DEPTH enum 6751 */ 6752 6753 typedef enum HDMI_DEEP_COLOR_DEPTH { 6754 HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000, 6755 HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001, 6756 HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002, 6757 HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003, 6758 } HDMI_DEEP_COLOR_DEPTH; 6759 6760 /* 6761 * HDMI_DEFAULT_PAHSE enum 6762 */ 6763 6764 typedef enum HDMI_DEFAULT_PAHSE { 6765 HDMI_DEFAULT_PHASE_IS_0 = 0x00000000, 6766 HDMI_DEFAULT_PHASE_IS_1 = 0x00000001, 6767 } HDMI_DEFAULT_PAHSE; 6768 6769 /* 6770 * HDMI_ERROR_ACK enum 6771 */ 6772 6773 typedef enum HDMI_ERROR_ACK { 6774 HDMI_ERROR_ACK_INT = 0x00000000, 6775 HDMI_ERROR_NOT_ACK = 0x00000001, 6776 } HDMI_ERROR_ACK; 6777 6778 /* 6779 * HDMI_ERROR_MASK enum 6780 */ 6781 6782 typedef enum HDMI_ERROR_MASK { 6783 HDMI_ERROR_MASK_INT = 0x00000000, 6784 HDMI_ERROR_NOT_MASK = 0x00000001, 6785 } HDMI_ERROR_MASK; 6786 6787 /* 6788 * HDMI_GC_AVMUTE enum 6789 */ 6790 6791 typedef enum HDMI_GC_AVMUTE { 6792 HDMI_GC_AVMUTE_SET = 0x00000000, 6793 HDMI_GC_AVMUTE_UNSET = 0x00000001, 6794 } HDMI_GC_AVMUTE; 6795 6796 /* 6797 * HDMI_GC_AVMUTE_CONT enum 6798 */ 6799 6800 typedef enum HDMI_GC_AVMUTE_CONT { 6801 HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000, 6802 HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001, 6803 } HDMI_GC_AVMUTE_CONT; 6804 6805 /* 6806 * HDMI_GC_CONT enum 6807 */ 6808 6809 typedef enum HDMI_GC_CONT { 6810 HDMI_GC_CONT_DISABLE = 0x00000000, 6811 HDMI_GC_CONT_ENABLE = 0x00000001, 6812 } HDMI_GC_CONT; 6813 6814 /* 6815 * HDMI_GC_SEND enum 6816 */ 6817 6818 typedef enum HDMI_GC_SEND { 6819 HDMI_GC_NOT_SEND = 0x00000000, 6820 HDMI_GC_PKT_SEND = 0x00000001, 6821 } HDMI_GC_SEND; 6822 6823 /* 6824 * HDMI_GENERIC_CONT enum 6825 */ 6826 6827 typedef enum HDMI_GENERIC_CONT { 6828 HDMI_GENERIC_CONT_DISABLE = 0x00000000, 6829 HDMI_GENERIC_CONT_ENABLE = 0x00000001, 6830 } HDMI_GENERIC_CONT; 6831 6832 /* 6833 * HDMI_GENERIC_SEND enum 6834 */ 6835 6836 typedef enum HDMI_GENERIC_SEND { 6837 HDMI_GENERIC_NOT_SEND = 0x00000000, 6838 HDMI_GENERIC_PKT_SEND = 0x00000001, 6839 } HDMI_GENERIC_SEND; 6840 6841 /* 6842 * HDMI_ISRC_CONT enum 6843 */ 6844 6845 typedef enum HDMI_ISRC_CONT { 6846 HDMI_ISRC_CONT_DISABLE = 0x00000000, 6847 HDMI_ISRC_CONT_ENABLE = 0x00000001, 6848 } HDMI_ISRC_CONT; 6849 6850 /* 6851 * HDMI_ISRC_SEND enum 6852 */ 6853 6854 typedef enum HDMI_ISRC_SEND { 6855 HDMI_ISRC_NOT_SEND = 0x00000000, 6856 HDMI_ISRC_PKT_SEND = 0x00000001, 6857 } HDMI_ISRC_SEND; 6858 6859 /* 6860 * HDMI_KEEPOUT_MODE enum 6861 */ 6862 6863 typedef enum HDMI_KEEPOUT_MODE { 6864 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000, 6865 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001, 6866 } HDMI_KEEPOUT_MODE; 6867 6868 /* 6869 * HDMI_METADATA_ENABLE enum 6870 */ 6871 6872 typedef enum HDMI_METADATA_ENABLE { 6873 HDMI_METADATA_NOT_SEND = 0x00000000, 6874 HDMI_METADATA_PKT_SEND = 0x00000001, 6875 } HDMI_METADATA_ENABLE; 6876 6877 /* 6878 * HDMI_MPEG_INFO_CONT enum 6879 */ 6880 6881 typedef enum HDMI_MPEG_INFO_CONT { 6882 HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000, 6883 HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001, 6884 } HDMI_MPEG_INFO_CONT; 6885 6886 /* 6887 * HDMI_MPEG_INFO_SEND enum 6888 */ 6889 6890 typedef enum HDMI_MPEG_INFO_SEND { 6891 HDMI_MPEG_INFO_NOT_SEND = 0x00000000, 6892 HDMI_MPEG_INFO_PKT_SEND = 0x00000001, 6893 } HDMI_MPEG_INFO_SEND; 6894 6895 /* 6896 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum 6897 */ 6898 6899 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { 6900 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000, 6901 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001, 6902 } HDMI_NO_EXTRA_NULL_PACKET_FILLED; 6903 6904 /* 6905 * HDMI_NULL_SEND enum 6906 */ 6907 6908 typedef enum HDMI_NULL_SEND { 6909 HDMI_NULL_NOT_SEND = 0x00000000, 6910 HDMI_NULL_PKT_SEND = 0x00000001, 6911 } HDMI_NULL_SEND; 6912 6913 /* 6914 * HDMI_PACKET_GEN_VERSION enum 6915 */ 6916 6917 typedef enum HDMI_PACKET_GEN_VERSION { 6918 HDMI_PACKET_GEN_VERSION_OLD = 0x00000000, 6919 HDMI_PACKET_GEN_VERSION_NEW = 0x00000001, 6920 } HDMI_PACKET_GEN_VERSION; 6921 6922 /* 6923 * HDMI_PACKET_LINE_REFERENCE enum 6924 */ 6925 6926 typedef enum HDMI_PACKET_LINE_REFERENCE { 6927 HDMI_PKT_LINE_REF_VSYNC = 0x00000000, 6928 HDMI_PKT_LINE_REF_OTGSOF = 0x00000001, 6929 } HDMI_PACKET_LINE_REFERENCE; 6930 6931 /* 6932 * HDMI_PACKING_PHASE_OVERRIDE enum 6933 */ 6934 6935 typedef enum HDMI_PACKING_PHASE_OVERRIDE { 6936 HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000, 6937 HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001, 6938 } HDMI_PACKING_PHASE_OVERRIDE; 6939 6940 /* 6941 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum 6942 */ 6943 6944 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { 6945 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000, 6946 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001, 6947 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; 6948 6949 /* 6950 * TMDS_COLOR_FORMAT enum 6951 */ 6952 6953 typedef enum TMDS_COLOR_FORMAT { 6954 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000, 6955 TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001, 6956 TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002, 6957 TMDS_COLOR_FORMAT_RESERVED = 0x00000003, 6958 } TMDS_COLOR_FORMAT; 6959 6960 /* 6961 * TMDS_CTL0_DATA_INVERT enum 6962 */ 6963 6964 typedef enum TMDS_CTL0_DATA_INVERT { 6965 TMDS_CTL0_DATA_NORMAL = 0x00000000, 6966 TMDS_CTL0_DATA_INVERT_EN = 0x00000001, 6967 } TMDS_CTL0_DATA_INVERT; 6968 6969 /* 6970 * TMDS_CTL0_DATA_MODULATION enum 6971 */ 6972 6973 typedef enum TMDS_CTL0_DATA_MODULATION { 6974 TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000, 6975 TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001, 6976 TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002, 6977 TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003, 6978 } TMDS_CTL0_DATA_MODULATION; 6979 6980 /* 6981 * TMDS_CTL0_DATA_SEL enum 6982 */ 6983 6984 typedef enum TMDS_CTL0_DATA_SEL { 6985 TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000, 6986 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 6987 TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002, 6988 TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003, 6989 TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004, 6990 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005, 6991 TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006, 6992 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007, 6993 } TMDS_CTL0_DATA_SEL; 6994 6995 /* 6996 * TMDS_CTL0_PATTERN_OUT_EN enum 6997 */ 6998 6999 typedef enum TMDS_CTL0_PATTERN_OUT_EN { 7000 TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000, 7001 TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001, 7002 } TMDS_CTL0_PATTERN_OUT_EN; 7003 7004 /* 7005 * TMDS_CTL1_DATA_INVERT enum 7006 */ 7007 7008 typedef enum TMDS_CTL1_DATA_INVERT { 7009 TMDS_CTL1_DATA_NORMAL = 0x00000000, 7010 TMDS_CTL1_DATA_INVERT_EN = 0x00000001, 7011 } TMDS_CTL1_DATA_INVERT; 7012 7013 /* 7014 * TMDS_CTL1_DATA_MODULATION enum 7015 */ 7016 7017 typedef enum TMDS_CTL1_DATA_MODULATION { 7018 TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000, 7019 TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001, 7020 TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002, 7021 TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003, 7022 } TMDS_CTL1_DATA_MODULATION; 7023 7024 /* 7025 * TMDS_CTL1_DATA_SEL enum 7026 */ 7027 7028 typedef enum TMDS_CTL1_DATA_SEL { 7029 TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000, 7030 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 7031 TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002, 7032 TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003, 7033 TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004, 7034 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005, 7035 TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006, 7036 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007, 7037 } TMDS_CTL1_DATA_SEL; 7038 7039 /* 7040 * TMDS_CTL1_PATTERN_OUT_EN enum 7041 */ 7042 7043 typedef enum TMDS_CTL1_PATTERN_OUT_EN { 7044 TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000, 7045 TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001, 7046 } TMDS_CTL1_PATTERN_OUT_EN; 7047 7048 /* 7049 * TMDS_CTL2_DATA_INVERT enum 7050 */ 7051 7052 typedef enum TMDS_CTL2_DATA_INVERT { 7053 TMDS_CTL2_DATA_NORMAL = 0x00000000, 7054 TMDS_CTL2_DATA_INVERT_EN = 0x00000001, 7055 } TMDS_CTL2_DATA_INVERT; 7056 7057 /* 7058 * TMDS_CTL2_DATA_MODULATION enum 7059 */ 7060 7061 typedef enum TMDS_CTL2_DATA_MODULATION { 7062 TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000, 7063 TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001, 7064 TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002, 7065 TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003, 7066 } TMDS_CTL2_DATA_MODULATION; 7067 7068 /* 7069 * TMDS_CTL2_DATA_SEL enum 7070 */ 7071 7072 typedef enum TMDS_CTL2_DATA_SEL { 7073 TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000, 7074 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 7075 TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002, 7076 TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003, 7077 TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004, 7078 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005, 7079 TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006, 7080 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007, 7081 } TMDS_CTL2_DATA_SEL; 7082 7083 /* 7084 * TMDS_CTL2_PATTERN_OUT_EN enum 7085 */ 7086 7087 typedef enum TMDS_CTL2_PATTERN_OUT_EN { 7088 TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000, 7089 TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001, 7090 } TMDS_CTL2_PATTERN_OUT_EN; 7091 7092 /* 7093 * TMDS_CTL3_DATA_INVERT enum 7094 */ 7095 7096 typedef enum TMDS_CTL3_DATA_INVERT { 7097 TMDS_CTL3_DATA_NORMAL = 0x00000000, 7098 TMDS_CTL3_DATA_INVERT_EN = 0x00000001, 7099 } TMDS_CTL3_DATA_INVERT; 7100 7101 /* 7102 * TMDS_CTL3_DATA_MODULATION enum 7103 */ 7104 7105 typedef enum TMDS_CTL3_DATA_MODULATION { 7106 TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000, 7107 TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001, 7108 TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002, 7109 TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003, 7110 } TMDS_CTL3_DATA_MODULATION; 7111 7112 /* 7113 * TMDS_CTL3_DATA_SEL enum 7114 */ 7115 7116 typedef enum TMDS_CTL3_DATA_SEL { 7117 TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000, 7118 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, 7119 TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002, 7120 TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003, 7121 TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004, 7122 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005, 7123 TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006, 7124 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007, 7125 } TMDS_CTL3_DATA_SEL; 7126 7127 /* 7128 * TMDS_CTL3_PATTERN_OUT_EN enum 7129 */ 7130 7131 typedef enum TMDS_CTL3_PATTERN_OUT_EN { 7132 TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000, 7133 TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001, 7134 } TMDS_CTL3_PATTERN_OUT_EN; 7135 7136 /* 7137 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum 7138 */ 7139 7140 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { 7141 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000, 7142 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001, 7143 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL; 7144 7145 /* 7146 * TMDS_PIXEL_ENCODING enum 7147 */ 7148 7149 typedef enum TMDS_PIXEL_ENCODING { 7150 TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000, 7151 TMDS_PIXEL_ENCODING_422 = 0x00000001, 7152 } TMDS_PIXEL_ENCODING; 7153 7154 /* 7155 * TMDS_REG_TEST_OUTPUTA_CNTLA enum 7156 */ 7157 7158 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { 7159 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000, 7160 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001, 7161 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002, 7162 TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003, 7163 } TMDS_REG_TEST_OUTPUTA_CNTLA; 7164 7165 /* 7166 * TMDS_REG_TEST_OUTPUTB_CNTLB enum 7167 */ 7168 7169 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { 7170 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000, 7171 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001, 7172 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002, 7173 TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003, 7174 } TMDS_REG_TEST_OUTPUTB_CNTLB; 7175 7176 /* 7177 * TMDS_STEREOSYNC_CTL_SEL_REG enum 7178 */ 7179 7180 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { 7181 TMDS_STEREOSYNC_CTL0 = 0x00000000, 7182 TMDS_STEREOSYNC_CTL1 = 0x00000001, 7183 TMDS_STEREOSYNC_CTL2 = 0x00000002, 7184 TMDS_STEREOSYNC_CTL3 = 0x00000003, 7185 } TMDS_STEREOSYNC_CTL_SEL_REG; 7186 7187 /* 7188 * TMDS_SYNC_PHASE enum 7189 */ 7190 7191 typedef enum TMDS_SYNC_PHASE { 7192 TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, 7193 TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001, 7194 } TMDS_SYNC_PHASE; 7195 7196 /* 7197 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum 7198 */ 7199 7200 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { 7201 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000, 7202 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001, 7203 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; 7204 7205 /* 7206 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum 7207 */ 7208 7209 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { 7210 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000, 7211 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001, 7212 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; 7213 7214 /* 7215 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum 7216 */ 7217 7218 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { 7219 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000, 7220 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001, 7221 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA; 7222 7223 /* 7224 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum 7225 */ 7226 7227 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { 7228 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000, 7229 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001, 7230 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB; 7231 7232 /* 7233 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum 7234 */ 7235 7236 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { 7237 TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000, 7238 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001, 7239 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; 7240 7241 /* 7242 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum 7243 */ 7244 7245 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { 7246 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000, 7247 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001, 7248 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002, 7249 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003, 7250 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; 7251 7252 /* 7253 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum 7254 */ 7255 7256 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { 7257 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000, 7258 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001, 7259 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; 7260 7261 /* 7262 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum 7263 */ 7264 7265 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { 7266 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000, 7267 TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001, 7268 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; 7269 7270 /* 7271 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum 7272 */ 7273 7274 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { 7275 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000, 7276 TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001, 7277 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; 7278 7279 /* 7280 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum 7281 */ 7282 7283 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { 7284 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000, 7285 TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001, 7286 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; 7287 7288 /* 7289 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum 7290 */ 7291 7292 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { 7293 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7294 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001, 7295 } TMDS_TRANSMITTER_ENABLE_HPD_MASK; 7296 7297 /* 7298 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum 7299 */ 7300 7301 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { 7302 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7303 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001, 7304 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; 7305 7306 /* 7307 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum 7308 */ 7309 7310 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { 7311 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, 7312 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001, 7313 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; 7314 7315 /******************************************************* 7316 * DOUT_I2C Enums 7317 *******************************************************/ 7318 7319 /* 7320 * DOUT_I2C_ACK enum 7321 */ 7322 7323 typedef enum DOUT_I2C_ACK { 7324 DOUT_I2C_NO_ACK = 0x00000000, 7325 DOUT_I2C_ACK_TO_CLEAN = 0x00000001, 7326 } DOUT_I2C_ACK; 7327 7328 /* 7329 * DOUT_I2C_ARBITRATION_ABORT_XFER enum 7330 */ 7331 7332 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { 7333 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000, 7334 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001, 7335 } DOUT_I2C_ARBITRATION_ABORT_XFER; 7336 7337 /* 7338 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum 7339 */ 7340 7341 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { 7342 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000, 7343 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001, 7344 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; 7345 7346 /* 7347 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum 7348 */ 7349 7350 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { 7351 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000, 7352 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001, 7353 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; 7354 7355 /* 7356 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum 7357 */ 7358 7359 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { 7360 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000, 7361 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001, 7362 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002, 7363 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003, 7364 } DOUT_I2C_ARBITRATION_SW_PRIORITY; 7365 7366 /* 7367 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum 7368 */ 7369 7370 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { 7371 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000, 7372 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001, 7373 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; 7374 7375 /* 7376 * DOUT_I2C_CONTROL_DBG_REF_SEL enum 7377 */ 7378 7379 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { 7380 DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000, 7381 DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001, 7382 } DOUT_I2C_CONTROL_DBG_REF_SEL; 7383 7384 /* 7385 * DOUT_I2C_CONTROL_DDC_SELECT enum 7386 */ 7387 7388 typedef enum DOUT_I2C_CONTROL_DDC_SELECT { 7389 DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000, 7390 DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001, 7391 DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002, 7392 DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003, 7393 DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000004, 7394 } DOUT_I2C_CONTROL_DDC_SELECT; 7395 7396 /* 7397 * DOUT_I2C_CONTROL_GO enum 7398 */ 7399 7400 typedef enum DOUT_I2C_CONTROL_GO { 7401 DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000, 7402 DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001, 7403 } DOUT_I2C_CONTROL_GO; 7404 7405 /* 7406 * DOUT_I2C_CONTROL_SEND_RESET enum 7407 */ 7408 7409 typedef enum DOUT_I2C_CONTROL_SEND_RESET { 7410 DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000, 7411 DOUT_I2C_CONTROL__SEND_RESET = 0x00000001, 7412 } DOUT_I2C_CONTROL_SEND_RESET; 7413 7414 /* 7415 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum 7416 */ 7417 7418 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH { 7419 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000, 7420 DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001, 7421 } DOUT_I2C_CONTROL_SEND_RESET_LENGTH; 7422 7423 /* 7424 * DOUT_I2C_CONTROL_SOFT_RESET enum 7425 */ 7426 7427 typedef enum DOUT_I2C_CONTROL_SOFT_RESET { 7428 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000, 7429 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001, 7430 } DOUT_I2C_CONTROL_SOFT_RESET; 7431 7432 /* 7433 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum 7434 */ 7435 7436 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { 7437 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000, 7438 DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001, 7439 } DOUT_I2C_CONTROL_SW_STATUS_RESET; 7440 7441 /* 7442 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum 7443 */ 7444 7445 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { 7446 DOUT_I2C_CONTROL_TRANS0 = 0x00000000, 7447 DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001, 7448 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002, 7449 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003, 7450 } DOUT_I2C_CONTROL_TRANSACTION_COUNT; 7451 7452 /* 7453 * DOUT_I2C_DATA_INDEX_WRITE enum 7454 */ 7455 7456 typedef enum DOUT_I2C_DATA_INDEX_WRITE { 7457 DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000, 7458 DOUT_I2C_DATA__INDEX_WRITE = 0x00000001, 7459 } DOUT_I2C_DATA_INDEX_WRITE; 7460 7461 /* 7462 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum 7463 */ 7464 7465 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { 7466 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, 7467 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001, 7468 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; 7469 7470 /* 7471 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum 7472 */ 7473 7474 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { 7475 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, 7476 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001, 7477 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; 7478 7479 /* 7480 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum 7481 */ 7482 7483 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { 7484 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000, 7485 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001, 7486 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; 7487 7488 /* 7489 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum 7490 */ 7491 7492 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { 7493 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000, 7494 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001, 7495 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; 7496 7497 /* 7498 * DOUT_I2C_DDC_SPEED_THRESHOLD enum 7499 */ 7500 7501 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { 7502 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000, 7503 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001, 7504 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002, 7505 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003, 7506 } DOUT_I2C_DDC_SPEED_THRESHOLD; 7507 7508 /* 7509 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum 7510 */ 7511 7512 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { 7513 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000, 7514 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001, 7515 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; 7516 7517 /* 7518 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum 7519 */ 7520 7521 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { 7522 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000, 7523 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001, 7524 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; 7525 7526 /* 7527 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum 7528 */ 7529 7530 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { 7531 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000, 7532 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001, 7533 } DOUT_I2C_TRANSACTION_STOP_ON_NACK; 7534 7535 /******************************************************* 7536 * DIO_MISC Enums 7537 *******************************************************/ 7538 7539 /* 7540 * CLOCK_GATING_EN enum 7541 */ 7542 7543 typedef enum CLOCK_GATING_EN { 7544 CLOCK_GATING_ENABLE = 0x00000000, 7545 CLOCK_GATING_DISABLE = 0x00000001, 7546 } CLOCK_GATING_EN; 7547 7548 /* 7549 * DAC_MUX_SELECT enum 7550 */ 7551 7552 typedef enum DAC_MUX_SELECT { 7553 DAC_MUX_SELECT_DACA = 0x00000000, 7554 DAC_MUX_SELECT_DACB = 0x00000001, 7555 } DAC_MUX_SELECT; 7556 7557 /* 7558 * DIOMEM_PWR_DIS_CTRL enum 7559 */ 7560 7561 typedef enum DIOMEM_PWR_DIS_CTRL { 7562 DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 7563 DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 7564 } DIOMEM_PWR_DIS_CTRL; 7565 7566 /* 7567 * DIOMEM_PWR_FORCE_CTRL enum 7568 */ 7569 7570 typedef enum DIOMEM_PWR_FORCE_CTRL { 7571 DIOMEM_NO_FORCE_REQUEST = 0x00000000, 7572 DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 7573 DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 7574 DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 7575 } DIOMEM_PWR_FORCE_CTRL; 7576 7577 /* 7578 * DIOMEM_PWR_FORCE_CTRL2 enum 7579 */ 7580 7581 typedef enum DIOMEM_PWR_FORCE_CTRL2 { 7582 DIOMEM_NO_FORCE_REQ = 0x00000000, 7583 DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, 7584 } DIOMEM_PWR_FORCE_CTRL2; 7585 7586 /* 7587 * DIOMEM_PWR_SEL_CTRL enum 7588 */ 7589 7590 typedef enum DIOMEM_PWR_SEL_CTRL { 7591 DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, 7592 DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, 7593 DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, 7594 } DIOMEM_PWR_SEL_CTRL; 7595 7596 /* 7597 * DIOMEM_PWR_SEL_CTRL2 enum 7598 */ 7599 7600 typedef enum DIOMEM_PWR_SEL_CTRL2 { 7601 DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000, 7602 DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, 7603 } DIOMEM_PWR_SEL_CTRL2; 7604 7605 /* 7606 * DIO_CLOCK_GATING_DISABLE enum 7607 */ 7608 7609 typedef enum DIO_CLOCK_GATING_DISABLE { 7610 DIO_CLOCK_GATING_EN = 0x00000000, 7611 DIO_CLOCK_GATING_DIS = 0x00000001, 7612 } DIO_CLOCK_GATING_DISABLE; 7613 7614 /* 7615 * DIO_DBG_BLOCK_SEL enum 7616 */ 7617 7618 typedef enum DIO_DBG_BLOCK_SEL { 7619 DIO_DBG_BLOCK_SEL_DIO = 0x00000000, 7620 DIO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b, 7621 DIO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c, 7622 DIO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d, 7623 DIO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e, 7624 DIO_DBG_BLOCK_SEL_DIGA = 0x00000012, 7625 DIO_DBG_BLOCK_SEL_DIGB = 0x00000013, 7626 DIO_DBG_BLOCK_SEL_DIGC = 0x00000014, 7627 DIO_DBG_BLOCK_SEL_DIGD = 0x00000015, 7628 DIO_DBG_BLOCK_SEL_DPFE_A = 0x00000019, 7629 DIO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a, 7630 DIO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b, 7631 DIO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c, 7632 DIO_DBG_BLOCK_SEL_DPA = 0x00000020, 7633 DIO_DBG_BLOCK_SEL_DPB = 0x00000021, 7634 DIO_DBG_BLOCK_SEL_DPC = 0x00000022, 7635 DIO_DBG_BLOCK_SEL_DPD = 0x00000023, 7636 DIO_DBG_BLOCK_SEL_AUX0 = 0x00000027, 7637 DIO_DBG_BLOCK_SEL_AUX1 = 0x00000028, 7638 DIO_DBG_BLOCK_SEL_AUX2 = 0x00000029, 7639 DIO_DBG_BLOCK_SEL_AUX3 = 0x0000002a, 7640 DIO_DBG_BLOCK_SEL_PERFMON_DIO = 0x0000002d, 7641 DIO_DBG_BLOCK_SEL_RESERVED = 0x0000002e, 7642 } DIO_DBG_BLOCK_SEL; 7643 7644 /* 7645 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum 7646 */ 7647 7648 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE { 7649 DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000, 7650 DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001, 7651 } DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE; 7652 7653 /* 7654 * ENUM_DIO_DCN_ACTIVE_STATUS enum 7655 */ 7656 7657 typedef enum ENUM_DIO_DCN_ACTIVE_STATUS { 7658 ENUM_DCN_NOT_ACTIVE = 0x00000000, 7659 ENUM_DCN_ACTIVE = 0x00000001, 7660 } ENUM_DIO_DCN_ACTIVE_STATUS; 7661 7662 /* 7663 * GENERIC_STEREOSYNC_SEL enum 7664 */ 7665 7666 typedef enum GENERIC_STEREOSYNC_SEL { 7667 GENERIC_STEREOSYNC_SEL_D1 = 0x00000000, 7668 GENERIC_STEREOSYNC_SEL_D2 = 0x00000001, 7669 GENERIC_STEREOSYNC_SEL_D3 = 0x00000002, 7670 GENERIC_STEREOSYNC_SEL_D4 = 0x00000003, 7671 GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000004, 7672 } GENERIC_STEREOSYNC_SEL; 7673 7674 /* 7675 * PM_ASSERT_RESET enum 7676 */ 7677 7678 typedef enum PM_ASSERT_RESET { 7679 PM_ASSERT_RESET_0 = 0x00000000, 7680 PM_ASSERT_RESET_1 = 0x00000001, 7681 } PM_ASSERT_RESET; 7682 7683 /* 7684 * SOFT_RESET enum 7685 */ 7686 7687 typedef enum SOFT_RESET { 7688 SOFT_RESET_0 = 0x00000000, 7689 SOFT_RESET_1 = 0x00000001, 7690 } SOFT_RESET; 7691 7692 /* 7693 * TMDS_MUX_SELECT enum 7694 */ 7695 7696 typedef enum TMDS_MUX_SELECT { 7697 TMDS_MUX_SELECT_B = 0x00000000, 7698 TMDS_MUX_SELECT_G = 0x00000001, 7699 TMDS_MUX_SELECT_R = 0x00000002, 7700 TMDS_MUX_SELECT_RESERVED = 0x00000003, 7701 } TMDS_MUX_SELECT; 7702 7703 /******************************************************* 7704 * DIG_STREAM_MAPPER Enums 7705 *******************************************************/ 7706 7707 /* 7708 * DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET enum 7709 */ 7710 7711 typedef enum DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET { 7712 DIG_STREAM_MAPPER_LINK0 = 0x00000000, 7713 DIG_STREAM_MAPPER_LINK1 = 0x00000001, 7714 DIG_STREAM_MAPPER_LINK2 = 0x00000002, 7715 DIG_STREAM_MAPPER_LINK3 = 0x00000003, 7716 DIG_STREAM_MAPPER_LINK6 = 0x00000004, 7717 } DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET; 7718 7719 /******************************************************* 7720 * DME Enums 7721 *******************************************************/ 7722 7723 /* 7724 * DME_MEM_POWER_STATE_ENUM enum 7725 */ 7726 7727 typedef enum DME_MEM_POWER_STATE_ENUM { 7728 DME_MEM_POWER_STATE_ENUM_ON = 0x00000000, 7729 DME_MEM_POWER_STATE_ENUM_LS = 0x00000001, 7730 DME_MEM_POWER_STATE_ENUM_DS = 0x00000002, 7731 DME_MEM_POWER_STATE_ENUM_SD = 0x00000003, 7732 } DME_MEM_POWER_STATE_ENUM; 7733 7734 /* 7735 * DME_MEM_PWR_DIS_CTRL enum 7736 */ 7737 7738 typedef enum DME_MEM_PWR_DIS_CTRL { 7739 DME_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 7740 DME_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 7741 } DME_MEM_PWR_DIS_CTRL; 7742 7743 /* 7744 * DME_MEM_PWR_FORCE_CTRL enum 7745 */ 7746 7747 typedef enum DME_MEM_PWR_FORCE_CTRL { 7748 DME_MEM_NO_FORCE_REQUEST = 0x00000000, 7749 DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 7750 DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 7751 DME_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 7752 } DME_MEM_PWR_FORCE_CTRL; 7753 7754 /* 7755 * METADATA_HUBP_SEL enum 7756 */ 7757 7758 typedef enum METADATA_HUBP_SEL { 7759 METADATA_HUBP_SEL_0 = 0x00000000, 7760 METADATA_HUBP_SEL_1 = 0x00000001, 7761 METADATA_HUBP_SEL_2 = 0x00000002, 7762 METADATA_HUBP_SEL_3 = 0x00000003, 7763 METADATA_HUBP_SEL_RESERVED = 0x00000004, 7764 } METADATA_HUBP_SEL; 7765 7766 /* 7767 * METADATA_STREAM_TYPE_SEL enum 7768 */ 7769 7770 typedef enum METADATA_STREAM_TYPE_SEL { 7771 METADATA_STREAM_DP = 0x00000000, 7772 METADATA_STREAM_DVE = 0x00000001, 7773 } METADATA_STREAM_TYPE_SEL; 7774 7775 /******************************************************* 7776 * VPG Enums 7777 *******************************************************/ 7778 7779 /* 7780 * VPG_MEM_PWR_DIS_CTRL enum 7781 */ 7782 7783 typedef enum VPG_MEM_PWR_DIS_CTRL { 7784 VPG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 7785 VPG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 7786 } VPG_MEM_PWR_DIS_CTRL; 7787 7788 /* 7789 * VPG_MEM_PWR_FORCE_CTRL enum 7790 */ 7791 7792 typedef enum VPG_MEM_PWR_FORCE_CTRL { 7793 VPG_MEM_NO_FORCE_REQ = 0x00000000, 7794 VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, 7795 } VPG_MEM_PWR_FORCE_CTRL; 7796 7797 /******************************************************* 7798 * AFMT Enums 7799 *******************************************************/ 7800 7801 /* 7802 * AFMT_ACP_TYPE enum 7803 */ 7804 7805 typedef enum AFMT_ACP_TYPE { 7806 ACP_TYPE_GENERIC_AUDIO = 0x00000000, 7807 ACP_TYPE_ICE60958_AUDIO = 0x00000001, 7808 ACP_TYPE_DVD_AUDIO = 0x00000002, 7809 ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, 7810 } AFMT_ACP_TYPE; 7811 7812 /* 7813 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum 7814 */ 7815 7816 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { 7817 AFMT_AUDIO_CRC_CH0_SIG = 0x00000000, 7818 AFMT_AUDIO_CRC_CH1_SIG = 0x00000001, 7819 AFMT_AUDIO_CRC_CH2_SIG = 0x00000002, 7820 AFMT_AUDIO_CRC_CH3_SIG = 0x00000003, 7821 AFMT_AUDIO_CRC_CH4_SIG = 0x00000004, 7822 AFMT_AUDIO_CRC_CH5_SIG = 0x00000005, 7823 AFMT_AUDIO_CRC_CH6_SIG = 0x00000006, 7824 AFMT_AUDIO_CRC_CH7_SIG = 0x00000007, 7825 AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008, 7826 AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009, 7827 AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a, 7828 AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b, 7829 AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c, 7830 AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d, 7831 AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e, 7832 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f, 7833 } AFMT_AUDIO_CRC_CONTROL_CH_SEL; 7834 7835 /* 7836 * AFMT_AUDIO_CRC_CONTROL_CONT enum 7837 */ 7838 7839 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { 7840 AFMT_AUDIO_CRC_ONESHOT = 0x00000000, 7841 AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001, 7842 } AFMT_AUDIO_CRC_CONTROL_CONT; 7843 7844 /* 7845 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum 7846 */ 7847 7848 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { 7849 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000, 7850 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001, 7851 } AFMT_AUDIO_CRC_CONTROL_SOURCE; 7852 7853 /* 7854 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum 7855 */ 7856 7857 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { 7858 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000, 7859 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001, 7860 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; 7861 7862 /* 7863 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum 7864 */ 7865 7866 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { 7867 AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000, 7868 AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001, 7869 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; 7870 7871 /* 7872 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum 7873 */ 7874 7875 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { 7876 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000, 7877 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001, 7878 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; 7879 7880 /* 7881 * AFMT_AUDIO_SRC_CONTROL_SELECT enum 7882 */ 7883 7884 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { 7885 AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000, 7886 AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001, 7887 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002, 7888 AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003, 7889 AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004, 7890 AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005, 7891 } AFMT_AUDIO_SRC_CONTROL_SELECT; 7892 7893 /* 7894 * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum 7895 */ 7896 7897 typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS { 7898 HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000, 7899 HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001, 7900 } AFMT_HDMI_AUDIO_SEND_MAX_PACKETS; 7901 7902 /* 7903 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum 7904 */ 7905 7906 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { 7907 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000, 7908 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, 7909 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; 7910 7911 /* 7912 * AFMT_INTERRUPT_STATUS_CHG_MASK enum 7913 */ 7914 7915 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { 7916 AFMT_INTERRUPT_DISABLE = 0x00000000, 7917 AFMT_INTERRUPT_ENABLE = 0x00000001, 7918 } AFMT_INTERRUPT_STATUS_CHG_MASK; 7919 7920 /* 7921 * AFMT_MEM_PWR_DIS_CTRL enum 7922 */ 7923 7924 typedef enum AFMT_MEM_PWR_DIS_CTRL { 7925 AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 7926 AFMT_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 7927 } AFMT_MEM_PWR_DIS_CTRL; 7928 7929 /* 7930 * AFMT_MEM_PWR_FORCE_CTRL enum 7931 */ 7932 7933 typedef enum AFMT_MEM_PWR_FORCE_CTRL { 7934 AFMT_MEM_NO_FORCE_REQUEST = 0x00000000, 7935 AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 7936 AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 7937 AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 7938 } AFMT_MEM_PWR_FORCE_CTRL; 7939 7940 /* 7941 * AFMT_RAMP_CONTROL0_SIGN enum 7942 */ 7943 7944 typedef enum AFMT_RAMP_CONTROL0_SIGN { 7945 AFMT_RAMP_SIGNED = 0x00000000, 7946 AFMT_RAMP_UNSIGNED = 0x00000001, 7947 } AFMT_RAMP_CONTROL0_SIGN; 7948 7949 /* 7950 * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum 7951 */ 7952 7953 typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE { 7954 AFMT_ACP_SOURCE_FROM_AZALIA = 0x00000000, 7955 AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, 7956 } AFMT_VBI_PACKET_CONTROL_ACP_SOURCE; 7957 7958 /* 7959 * AUDIO_LAYOUT_SELECT enum 7960 */ 7961 7962 typedef enum AUDIO_LAYOUT_SELECT { 7963 AUDIO_LAYOUT_0 = 0x00000000, 7964 AUDIO_LAYOUT_1 = 0x00000001, 7965 } AUDIO_LAYOUT_SELECT; 7966 7967 /******************************************************* 7968 * DCOH_TOP Enums 7969 *******************************************************/ 7970 7971 /* 7972 * DCOH_TEST_CLOCK_MUX_SELECT_ENUM enum 7973 */ 7974 7975 typedef enum DCOH_TEST_CLOCK_MUX_SELECT_ENUM { 7976 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000, 7977 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000001, 7978 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1 = 0x00000002, 7979 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2 = 0x00000003, 7980 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3 = 0x00000004, 7981 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4 = 0x00000005, 7982 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5 = 0x00000006, 7983 DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6 = 0x00000007, 7984 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P = 0x00000008, 7985 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R = 0x00000009, 7986 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1 = 0x0000000a, 7987 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2 = 0x0000000b, 7988 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3 = 0x0000000c, 7989 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4 = 0x0000000d, 7990 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5 = 0x0000000e, 7991 DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6 = 0x0000000f, 7992 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0 = 0x00000010, 7993 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1 = 0x00000011, 7994 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2 = 0x00000012, 7995 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3 = 0x00000013, 7996 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4 = 0x00000014, 7997 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5 = 0x00000015, 7998 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6 = 0x00000016, 7999 DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7 = 0x00000017, 8000 DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK = 0x00000018, 8001 DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK = 0x00000019, 8002 DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK = 0x0000001a, 8003 DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK = 0x0000001b, 8004 DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK = 0x0000001c, 8005 DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK = 0x0000001d, 8006 DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK = 0x0000001e, 8007 } DCOH_TEST_CLOCK_MUX_SELECT_ENUM; 8008 8009 /* 8010 * DCOH_TOP_CLOCK_GATING_DISABLE_ENUM enum 8011 */ 8012 8013 typedef enum DCOH_TOP_CLOCK_GATING_DISABLE_ENUM { 8014 DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000, 8015 DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001, 8016 } DCOH_TOP_CLOCK_GATING_DISABLE_ENUM; 8017 8018 /* 8019 * DCOH_TOP_ENABLE_ENUM enum 8020 */ 8021 8022 typedef enum DCOH_TOP_ENABLE_ENUM { 8023 DCOH_TOP_ENABLE_ENUM_DISABLED = 0x00000000, 8024 DCOH_TOP_ENABLE_ENUM_ENABLED = 0x00000001, 8025 } DCOH_TOP_ENABLE_ENUM; 8026 8027 /******************************************************* 8028 * PHY_MUX Enums 8029 *******************************************************/ 8030 8031 /* 8032 * PHY_MUX_ENABLE_ENUM enum 8033 */ 8034 8035 typedef enum PHY_MUX_ENABLE_ENUM { 8036 PHY_MUX_ENABLE_ENUM_DISABLED = 0x00000000, 8037 PHY_MUX_ENABLE_ENUM_ENABLED = 0x00000001, 8038 } PHY_MUX_ENABLE_ENUM; 8039 8040 /******************************************************* 8041 * DP_AUX Enums 8042 *******************************************************/ 8043 8044 /* 8045 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum 8046 */ 8047 8048 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { 8049 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000, 8050 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001, 8051 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002, 8052 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003, 8053 } DP_AUX_ARB_CONTROL_ARB_PRIORITY; 8054 8055 /* 8056 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum 8057 */ 8058 8059 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { 8060 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000, 8061 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001, 8062 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; 8063 8064 /* 8065 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum 8066 */ 8067 8068 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { 8069 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000, 8070 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001, 8071 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; 8072 8073 /* 8074 * DP_AUX_ARB_STATUS enum 8075 */ 8076 8077 typedef enum DP_AUX_ARB_STATUS { 8078 DP_AUX_IDLE = 0x00000000, 8079 DP_AUX_IN_USE_LS = 0x00000001, 8080 DP_AUX_IN_USE_GTC = 0x00000002, 8081 DP_AUX_IN_USE_SW = 0x00000003, 8082 DP_AUX_IN_USE_PHYWAKE = 0x00000004, 8083 } DP_AUX_ARB_STATUS; 8084 8085 /* 8086 * DP_AUX_CONTROL_HPD_SEL enum 8087 */ 8088 8089 typedef enum DP_AUX_CONTROL_HPD_SEL { 8090 DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000, 8091 DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001, 8092 DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002, 8093 DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003, 8094 DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000004, 8095 } DP_AUX_CONTROL_HPD_SEL; 8096 8097 /* 8098 * DP_AUX_CONTROL_TEST_MODE enum 8099 */ 8100 8101 typedef enum DP_AUX_CONTROL_TEST_MODE { 8102 DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000, 8103 DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001, 8104 } DP_AUX_CONTROL_TEST_MODE; 8105 8106 /* 8107 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum 8108 */ 8109 8110 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { 8111 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000, 8112 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001, 8113 } DP_AUX_DEFINITE_ERR_REACHED_ACK; 8114 8115 /* 8116 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum 8117 */ 8118 8119 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { 8120 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000, 8121 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001, 8122 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; 8123 8124 /* 8125 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum 8126 */ 8127 8128 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { 8129 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000, 8130 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001, 8131 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; 8132 8133 /* 8134 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum 8135 */ 8136 8137 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { 8138 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000, 8139 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001, 8140 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; 8141 8142 /* 8143 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum 8144 */ 8145 8146 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { 8147 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000, 8148 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001, 8149 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002, 8150 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003, 8151 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; 8152 8153 /* 8154 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum 8155 */ 8156 8157 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { 8158 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000, 8159 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001, 8160 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002, 8161 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003, 8162 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; 8163 8164 /* 8165 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum 8166 */ 8167 8168 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { 8169 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000, 8170 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001, 8171 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002, 8172 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003, 8173 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004, 8174 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005, 8175 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006, 8176 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007, 8177 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; 8178 8179 /* 8180 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum 8181 */ 8182 8183 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { 8184 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000, 8185 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001, 8186 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002, 8187 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003, 8188 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004, 8189 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005, 8190 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006, 8191 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007, 8192 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW; 8193 8194 /* 8195 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum 8196 */ 8197 8198 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { 8199 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000, 8200 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001, 8201 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002, 8202 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003, 8203 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004, 8204 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005, 8205 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006, 8206 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007, 8207 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD; 8208 8209 /* 8210 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum 8211 */ 8212 8213 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { 8214 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000, 8215 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001, 8216 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002, 8217 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003, 8218 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004, 8219 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005, 8220 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; 8221 8222 /* 8223 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum 8224 */ 8225 8226 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { 8227 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000, 8228 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001, 8229 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002, 8230 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003, 8231 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; 8232 8233 /* 8234 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum 8235 */ 8236 8237 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { 8238 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000, 8239 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001, 8240 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; 8241 8242 /* 8243 * DP_AUX_ERR_OCCURRED_ACK enum 8244 */ 8245 8246 typedef enum DP_AUX_ERR_OCCURRED_ACK { 8247 DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000, 8248 DP_AUX_ERR_OCCURRED__ACK = 0x00000001, 8249 } DP_AUX_ERR_OCCURRED_ACK; 8250 8251 /* 8252 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum 8253 */ 8254 8255 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { 8256 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000, 8257 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001, 8258 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; 8259 8260 /* 8261 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum 8262 */ 8263 8264 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { 8265 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000, 8266 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001, 8267 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002, 8268 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003, 8269 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; 8270 8271 /* 8272 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum 8273 */ 8274 8275 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { 8276 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000, 8277 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001, 8278 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002, 8279 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003, 8280 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; 8281 8282 /* 8283 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum 8284 */ 8285 8286 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { 8287 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000, 8288 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001, 8289 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002, 8290 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003, 8291 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; 8292 8293 /* 8294 * DP_AUX_INT_ACK enum 8295 */ 8296 8297 typedef enum DP_AUX_INT_ACK { 8298 DP_AUX_INT__NOT_ACK = 0x00000000, 8299 DP_AUX_INT__ACK = 0x00000001, 8300 } DP_AUX_INT_ACK; 8301 8302 /* 8303 * DP_AUX_LS_UPDATE_ACK enum 8304 */ 8305 8306 typedef enum DP_AUX_LS_UPDATE_ACK { 8307 DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000, 8308 DP_AUX_INT_LS_UPDATE_ACK = 0x00000001, 8309 } DP_AUX_LS_UPDATE_ACK; 8310 8311 /* 8312 * DP_AUX_PHY_WAKE_PRIORITY enum 8313 */ 8314 8315 typedef enum DP_AUX_PHY_WAKE_PRIORITY { 8316 DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000, 8317 DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001, 8318 } DP_AUX_PHY_WAKE_PRIORITY; 8319 8320 /* 8321 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum 8322 */ 8323 8324 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { 8325 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000, 8326 DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001, 8327 } DP_AUX_POTENTIAL_ERR_REACHED_ACK; 8328 8329 /* 8330 * DP_AUX_RESET enum 8331 */ 8332 8333 typedef enum DP_AUX_RESET { 8334 DP_AUX_RESET_DEASSERTED = 0x00000000, 8335 DP_AUX_RESET_ASSERTED = 0x00000001, 8336 } DP_AUX_RESET; 8337 8338 /* 8339 * DP_AUX_RESET_DONE enum 8340 */ 8341 8342 typedef enum DP_AUX_RESET_DONE { 8343 DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000, 8344 DP_AUX_RESET_SEQUENCE_DONE = 0x00000001, 8345 } DP_AUX_RESET_DONE; 8346 8347 /* 8348 * DP_AUX_RX_TIMEOUT_LEN_MUL enum 8349 */ 8350 8351 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL { 8352 DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000, 8353 DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001, 8354 DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002, 8355 DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003, 8356 } DP_AUX_RX_TIMEOUT_LEN_MUL; 8357 8358 /* 8359 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum 8360 */ 8361 8362 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { 8363 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000, 8364 DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001, 8365 } DP_AUX_SW_CONTROL_LS_READ_TRIG; 8366 8367 /* 8368 * DP_AUX_SW_CONTROL_SW_GO enum 8369 */ 8370 8371 typedef enum DP_AUX_SW_CONTROL_SW_GO { 8372 DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000, 8373 DP_AUX_SW_CONTROL_SW__GO = 0x00000001, 8374 } DP_AUX_SW_CONTROL_SW_GO; 8375 8376 /* 8377 * DP_AUX_TX_PRECHARGE_LEN_MUL enum 8378 */ 8379 8380 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL { 8381 DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000, 8382 DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001, 8383 DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002, 8384 DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003, 8385 } DP_AUX_TX_PRECHARGE_LEN_MUL; 8386 8387 /******************************************************* 8388 * HPD Enums 8389 *******************************************************/ 8390 8391 /* 8392 * HPD_INT_CONTROL_ACK enum 8393 */ 8394 8395 typedef enum HPD_INT_CONTROL_ACK { 8396 HPD_INT_CONTROL_ACK_0 = 0x00000000, 8397 HPD_INT_CONTROL_ACK_1 = 0x00000001, 8398 } HPD_INT_CONTROL_ACK; 8399 8400 /* 8401 * HPD_INT_CONTROL_POLARITY enum 8402 */ 8403 8404 typedef enum HPD_INT_CONTROL_POLARITY { 8405 HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, 8406 HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, 8407 } HPD_INT_CONTROL_POLARITY; 8408 8409 /* 8410 * HPD_INT_CONTROL_RX_INT_ACK enum 8411 */ 8412 8413 typedef enum HPD_INT_CONTROL_RX_INT_ACK { 8414 HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, 8415 HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, 8416 } HPD_INT_CONTROL_RX_INT_ACK; 8417 8418 /******************************************************* 8419 * HPO_TOP Enums 8420 *******************************************************/ 8421 8422 /* 8423 * HPO_TOP_CLOCK_GATING_DISABLE enum 8424 */ 8425 8426 typedef enum HPO_TOP_CLOCK_GATING_DISABLE { 8427 HPO_TOP_CLOCK_GATING_EN = 0x00000000, 8428 HPO_TOP_CLOCK_GATING_DIS = 0x00000001, 8429 } HPO_TOP_CLOCK_GATING_DISABLE; 8430 8431 /* 8432 * HPO_TOP_TEST_CLK_SEL enum 8433 */ 8434 8435 typedef enum HPO_TOP_TEST_CLK_SEL { 8436 HPO_TOP_PERMANENT_DISPCLK = 0x00000000, 8437 HPO_TOP_REGISTER_GATED_DISPCLK = 0x00000001, 8438 HPO_TOP_PERMANENT_SOCCLK = 0x00000002, 8439 HPO_TOP_TEST_CLOCK_RESERVED = 0x00000003, 8440 HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 0x00000004, 8441 HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 0x00000005, 8442 HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 0x00000006, 8443 HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007, 8444 HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008, 8445 HPO_TOP_PERMANENT_HDMICHARCLK0 = 0x00000009, 8446 HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 0x0000000a, 8447 HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 0x0000000b, 8448 } HPO_TOP_TEST_CLK_SEL; 8449 8450 /******************************************************* 8451 * DP_STREAM_MAPPER Enums 8452 *******************************************************/ 8453 8454 /* 8455 * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum 8456 */ 8457 8458 typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET { 8459 DP_STREAM_MAPPER_LINK0 = 0x00000000, 8460 DP_STREAM_MAPPER_LINK1 = 0x00000001, 8461 DP_STREAM_MAPPER_LINK2 = 0x00000002, 8462 DP_STREAM_MAPPER_LINK3 = 0x00000003, 8463 DP_STREAM_MAPPER_RESERVED = 0x00000004, 8464 } DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET; 8465 8466 /******************************************************* 8467 * DP_STREAM_ENC Enums 8468 *******************************************************/ 8469 8470 /* 8471 * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum 8472 */ 8473 8474 typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR { 8475 DP_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000, 8476 DP_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001, 8477 DP_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002, 8478 } DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; 8479 8480 /* 8481 * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum 8482 */ 8483 8484 typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT { 8485 DP_STREAM_ENC_HARDWARE = 0x00000000, 8486 DP_STREAM_ENC_PROGRAMMABLE = 0x00000001, 8487 } DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT; 8488 8489 /* 8490 * DP_STREAM_ENC_READ_CLOCK_CONTROL enum 8491 */ 8492 8493 typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL { 8494 DP_STREAM_ENC_DCCG = 0x00000000, 8495 DP_STREAM_ENC_DISPLAY_PIPE = 0x00000001, 8496 } DP_STREAM_ENC_READ_CLOCK_CONTROL; 8497 8498 /* 8499 * DP_STREAM_ENC_RESET_CONTROL enum 8500 */ 8501 8502 typedef enum DP_STREAM_ENC_RESET_CONTROL { 8503 DP_STREAM_ENC_NOT_RESET = 0x00000000, 8504 DP_STREAM_ENC_RESET = 0x00000001, 8505 } DP_STREAM_ENC_RESET_CONTROL; 8506 8507 /* 8508 * DP_STREAM_ENC_STREAM_ACTIVE enum 8509 */ 8510 8511 typedef enum DP_STREAM_ENC_STREAM_ACTIVE { 8512 DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000, 8513 DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001, 8514 } DP_STREAM_ENC_STREAM_ACTIVE; 8515 8516 /******************************************************* 8517 * DP_SYM32_ENC Enums 8518 *******************************************************/ 8519 8520 /* 8521 * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum 8522 */ 8523 8524 typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE { 8525 DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0x00000000, 8526 DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 0x00000001, 8527 } ENUM_DP_SYM32_ENC_AUDIO_MUTE; 8528 8529 /* 8530 * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum 8531 */ 8532 8533 typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE { 8534 DP_SYM32_ENC_ONE_SHOT_MODE = 0x00000000, 8535 DP_SYM32_ENC_CONTINUOUS_MODE = 0x00000001, 8536 } ENUM_DP_SYM32_ENC_CONTINUOUS_MODE; 8537 8538 /* 8539 * ENUM_DP_SYM32_ENC_CRC_VALID enum 8540 */ 8541 8542 typedef enum ENUM_DP_SYM32_ENC_CRC_VALID { 8543 DP_SYM32_ENC_CRC_NOT_VALID = 0x00000000, 8544 DP_SYM32_ENC_CRC_VALID = 0x00000001, 8545 } ENUM_DP_SYM32_ENC_CRC_VALID; 8546 8547 /* 8548 * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum 8549 */ 8550 8551 typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH { 8552 DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0x00000000, 8553 DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 0x00000001, 8554 DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 0x00000002, 8555 DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 0x00000003, 8556 } ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH; 8557 8558 /* 8559 * ENUM_DP_SYM32_ENC_ENABLE enum 8560 */ 8561 8562 typedef enum ENUM_DP_SYM32_ENC_ENABLE { 8563 DP_SYM32_ENC_DISABLE = 0x00000000, 8564 DP_SYM32_ENC_ENABLE = 0x00000001, 8565 } ENUM_DP_SYM32_ENC_ENABLE; 8566 8567 /* 8568 * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum 8569 */ 8570 8571 typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED { 8572 DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0x00000000, 8573 DP_SYM32_ENC_GSP_DEADLINE_MISSED = 0x00000001, 8574 } ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED; 8575 8576 /* 8577 * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum 8578 */ 8579 8580 typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION { 8581 DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0x00000000, 8582 DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 0x00000001, 8583 } ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION; 8584 8585 /* 8586 * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum 8587 */ 8588 8589 typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE { 8590 DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0x00000000, 8591 DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 0x00000001, 8592 DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 0x00000002, 8593 DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 0x00000003, 8594 } ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE; 8595 8596 /* 8597 * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum 8598 */ 8599 8600 typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING { 8601 DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0x00000000, 8602 DP_SYM32_ENC_GSP_TRIGGER_PENDING = 0x00000001, 8603 } ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING; 8604 8605 /* 8606 * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum 8607 */ 8608 8609 typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM { 8610 DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0x00000000, 8611 DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 8612 DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 8613 DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 8614 } ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM; 8615 8616 /* 8617 * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum 8618 */ 8619 8620 typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS { 8621 DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0x00000000, 8622 DP_SYM32_ENC_OVERFLOW_OCCURRED = 0x00000001, 8623 } ENUM_DP_SYM32_ENC_OVERFLOW_STATUS; 8624 8625 /* 8626 * ENUM_DP_SYM32_ENC_PENDING enum 8627 */ 8628 8629 typedef enum ENUM_DP_SYM32_ENC_PENDING { 8630 DP_SYM32_ENC_NOT_PENDING = 0x00000000, 8631 DP_SYM32_ENC_PENDING = 0x00000001, 8632 } ENUM_DP_SYM32_ENC_PENDING; 8633 8634 /* 8635 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum 8636 */ 8637 8638 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING { 8639 DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000, 8640 DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 0x00000001, 8641 DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 0x00000002, 8642 DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 0x00000003, 8643 } ENUM_DP_SYM32_ENC_PIXEL_ENCODING; 8644 8645 /* 8646 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum 8647 */ 8648 8649 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE { 8650 DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0x00000000, 8651 DP_SYM32_ENC_COMPRESSED_FORMAT = 0x00000001, 8652 } ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE; 8653 8654 /* 8655 * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum 8656 */ 8657 8658 typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM { 8659 DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0x00000000, 8660 DP_SYM32_ENC_POWER_STATE_ENUM_LS = 0x00000001, 8661 DP_SYM32_ENC_POWER_STATE_ENUM_DS = 0x00000002, 8662 DP_SYM32_ENC_POWER_STATE_ENUM_SD = 0x00000003, 8663 } ENUM_DP_SYM32_ENC_POWER_STATE_ENUM; 8664 8665 /* 8666 * ENUM_DP_SYM32_ENC_RESET enum 8667 */ 8668 8669 typedef enum ENUM_DP_SYM32_ENC_RESET { 8670 DP_SYM32_ENC_NOT_RESET = 0x00000000, 8671 DP_SYM32_ENC_RESET = 0x00000001, 8672 } ENUM_DP_SYM32_ENC_RESET; 8673 8674 /* 8675 * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum 8676 */ 8677 8678 typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY { 8679 DP_SYM32_ENC_SDP_LOW_PRIORITY = 0x00000000, 8680 DP_SYM32_ENC_SDP_HIGH_PRIORITY = 0x00000001, 8681 } ENUM_DP_SYM32_ENC_SDP_PRIORITY; 8682 8683 /* 8684 * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum 8685 */ 8686 8687 typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE { 8688 DP_SYM32_ENC_DP_SOF = 0x00000000, 8689 DP_SYM32_ENC_OTG_SOF = 0x00000001, 8690 } ENUM_DP_SYM32_ENC_SOF_REFERENCE; 8691 8692 /* 8693 * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum 8694 */ 8695 8696 typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER { 8697 DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0x00000000, 8698 DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 0x00000001, 8699 DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 0x00000002, 8700 } ENUM_DP_SYM32_ENC_VID_STREAM_DEFER; 8701 8702 /******************************************************* 8703 * DP_DPHY_SYM32 Enums 8704 *******************************************************/ 8705 8706 /* 8707 * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum 8708 */ 8709 8710 typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT { 8711 DP_DPHY_SYM32_CRC_END_LLCP = 0x00000000, 8712 DP_DPHY_SYM32_CRC_END_PS_ONLY = 0x00000001, 8713 DP_DPHY_SYM32_CRC_END_PS_LT_SR = 0x00000002, 8714 DP_DPHY_SYM32_CRC_END_PS_ANY = 0x00000003, 8715 } ENUM_DP_DPHY_SYM32_CRC_END_EVENT; 8716 8717 /* 8718 * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum 8719 */ 8720 8721 typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT { 8722 DP_DPHY_SYM32_CRC_START_LLCP = 0x00000000, 8723 DP_DPHY_SYM32_CRC_START_PS_ONLY = 0x00000001, 8724 DP_DPHY_SYM32_CRC_START_PS_LT_SR = 0x00000002, 8725 DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 0x00000003, 8726 DP_DPHY_SYM32_CRC_START_TP_START = 0x00000004, 8727 } ENUM_DP_DPHY_SYM32_CRC_START_EVENT; 8728 8729 /* 8730 * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum 8731 */ 8732 8733 typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE { 8734 DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0x00000000, 8735 DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001, 8736 DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 0x00000002, 8737 } ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE; 8738 8739 /* 8740 * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum 8741 */ 8742 8743 typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS { 8744 DP_DPHY_SYM32_CRC_USE_END_EVENT = 0x00000000, 8745 DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 0x00000001, 8746 } ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS; 8747 8748 /* 8749 * ENUM_DP_DPHY_SYM32_ENABLE enum 8750 */ 8751 8752 typedef enum ENUM_DP_DPHY_SYM32_ENABLE { 8753 DP_DPHY_SYM32_DISABLE = 0x00000000, 8754 DP_DPHY_SYM32_ENABLE = 0x00000001, 8755 } ENUM_DP_DPHY_SYM32_ENABLE; 8756 8757 /* 8758 * ENUM_DP_DPHY_SYM32_MODE enum 8759 */ 8760 8761 typedef enum ENUM_DP_DPHY_SYM32_MODE { 8762 DP_DPHY_SYM32_LT_TPS1 = 0x00000000, 8763 DP_DPHY_SYM32_LT_TPS2 = 0x00000001, 8764 DP_DPHY_SYM32_ACTIVE = 0x00000002, 8765 DP_DPHY_SYM32_TEST = 0x00000003, 8766 } ENUM_DP_DPHY_SYM32_MODE; 8767 8768 /* 8769 * ENUM_DP_DPHY_SYM32_NUM_LANES enum 8770 */ 8771 8772 typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES { 8773 DP_DPHY_SYM32_1LANE = 0x00000000, 8774 DP_DPHY_SYM32_2LANE = 0x00000001, 8775 DP_DPHY_SYM32_RESERVED = 0x00000002, 8776 DP_DPHY_SYM32_4LANE = 0x00000003, 8777 } ENUM_DP_DPHY_SYM32_NUM_LANES; 8778 8779 /* 8780 * ENUM_DP_DPHY_SYM32_OUTPUT_MODE enum 8781 */ 8782 8783 typedef enum ENUM_DP_DPHY_SYM32_OUTPUT_MODE { 8784 DP_DPHY_SYM32_OUTPUT_PHY = 0x00000000, 8785 DP_DPHY_SYM32_OUTPUT_DPIA = 0x00000001, 8786 } ENUM_DP_DPHY_SYM32_OUTPUT_MODE; 8787 8788 /* 8789 * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum 8790 */ 8791 8792 typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING { 8793 DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0x00000000, 8794 DP_DPHY_SYM32_RATE_UPDATE_PENDING = 0x00000001, 8795 } ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING; 8796 8797 /* 8798 * ENUM_DP_DPHY_SYM32_RESET enum 8799 */ 8800 8801 typedef enum ENUM_DP_DPHY_SYM32_RESET { 8802 DP_DPHY_SYM32_NOT_RESET = 0x00000000, 8803 DP_DPHY_SYM32_RESET = 0x00000001, 8804 } ENUM_DP_DPHY_SYM32_RESET; 8805 8806 /* 8807 * ENUM_DP_DPHY_SYM32_RESET_STATUS enum 8808 */ 8809 8810 typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS { 8811 DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0x00000000, 8812 DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 0x00000001, 8813 } ENUM_DP_DPHY_SYM32_RESET_STATUS; 8814 8815 /* 8816 * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum 8817 */ 8818 8819 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE { 8820 DP_DPHY_SYM32_SAT_NO_UPDATE = 0x00000000, 8821 DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 0x00000001, 8822 DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 0x00000002, 8823 } ENUM_DP_DPHY_SYM32_SAT_UPDATE; 8824 8825 /* 8826 * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum 8827 */ 8828 8829 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING { 8830 DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0x00000000, 8831 DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001, 8832 DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002, 8833 } ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING; 8834 8835 /* 8836 * ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS enum 8837 */ 8838 8839 typedef enum ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS { 8840 DP_DPHY_SYM32_SCHEDULER_OFF = 0x00000000, 8841 DP_DPHY_SYM32_SCHEDULER_ASLEEP = 0x00000001, 8842 DP_DPHY_SYM32_SCHEDULER_AWAKE = 0x00000002, 8843 } ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS; 8844 8845 /* 8846 * ENUM_DP_DPHY_SYM32_STATUS enum 8847 */ 8848 8849 typedef enum ENUM_DP_DPHY_SYM32_STATUS { 8850 DP_DPHY_SYM32_STATUS_IDLE = 0x00000000, 8851 DP_DPHY_SYM32_STATUS_ENABLED = 0x00000001, 8852 } ENUM_DP_DPHY_SYM32_STATUS; 8853 8854 /* 8855 * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum 8856 */ 8857 8858 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE { 8859 DP_DPHY_SYM32_STREAM_OVR_NONE = 0x00000000, 8860 DP_DPHY_SYM32_STREAM_OVR_REPLACE = 0x00000001, 8861 DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 0x00000002, 8862 } ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE; 8863 8864 /* 8865 * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum 8866 */ 8867 8868 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE { 8869 DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0x00000000, 8870 DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 0x00000001, 8871 } ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE; 8872 8873 /* 8874 * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum 8875 */ 8876 8877 typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL { 8878 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0x00000000, 8879 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 0x00000001, 8880 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 0x00000002, 8881 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 0x00000003, 8882 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 0x00000004, 8883 DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 0x00000005, 8884 } ENUM_DP_DPHY_SYM32_TP_PRBS_SEL; 8885 8886 /* 8887 * ENUM_DP_DPHY_SYM32_TP_SELECT enum 8888 */ 8889 8890 typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT { 8891 DP_DPHY_SYM32_TP_SELECT_TPS1 = 0x00000000, 8892 DP_DPHY_SYM32_TP_SELECT_TPS2 = 0x00000001, 8893 DP_DPHY_SYM32_TP_SELECT_PRBS = 0x00000002, 8894 DP_DPHY_SYM32_TP_SELECT_CUSTOM = 0x00000003, 8895 DP_DPHY_SYM32_TP_SELECT_SQUARE = 0x00000004, 8896 } ENUM_DP_DPHY_SYM32_TP_SELECT; 8897 8898 /******************************************************* 8899 * APG Enums 8900 *******************************************************/ 8901 8902 /* 8903 * APG_AUDIO_CRC_CONTROL_CH_SEL enum 8904 */ 8905 8906 typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL { 8907 APG_AUDIO_CRC_CH0_SIG = 0x00000000, 8908 APG_AUDIO_CRC_CH1_SIG = 0x00000001, 8909 APG_AUDIO_CRC_CH2_SIG = 0x00000002, 8910 APG_AUDIO_CRC_CH3_SIG = 0x00000003, 8911 APG_AUDIO_CRC_CH4_SIG = 0x00000004, 8912 APG_AUDIO_CRC_CH5_SIG = 0x00000005, 8913 APG_AUDIO_CRC_CH6_SIG = 0x00000006, 8914 APG_AUDIO_CRC_CH7_SIG = 0x00000007, 8915 APG_AUDIO_CRC_RESERVED_8 = 0x00000008, 8916 APG_AUDIO_CRC_RESERVED_9 = 0x00000009, 8917 APG_AUDIO_CRC_RESERVED_10 = 0x0000000a, 8918 APG_AUDIO_CRC_RESERVED_11 = 0x0000000b, 8919 APG_AUDIO_CRC_RESERVED_12 = 0x0000000c, 8920 APG_AUDIO_CRC_RESERVED_13 = 0x0000000d, 8921 APG_AUDIO_CRC_RESERVED_14 = 0x0000000e, 8922 APG_AUDIO_CRC_RESERVED_15 = 0x0000000f, 8923 } APG_AUDIO_CRC_CONTROL_CH_SEL; 8924 8925 /* 8926 * APG_AUDIO_CRC_CONTROL_CONT enum 8927 */ 8928 8929 typedef enum APG_AUDIO_CRC_CONTROL_CONT { 8930 APG_AUDIO_CRC_ONESHOT = 0x00000000, 8931 APG_AUDIO_CRC_CONTINUOUS = 0x00000001, 8932 } APG_AUDIO_CRC_CONTROL_CONT; 8933 8934 /* 8935 * APG_DBG_ACP_TYPE enum 8936 */ 8937 8938 typedef enum APG_DBG_ACP_TYPE { 8939 APG_ACP_TYPE_GENERIC_AUDIO = 0x00000000, 8940 APG_ACP_TYPE_ICE60958_AUDIO = 0x00000001, 8941 APG_ACP_TYPE_DVD_AUDIO = 0x00000002, 8942 APG_ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, 8943 } APG_DBG_ACP_TYPE; 8944 8945 /* 8946 * APG_DBG_AUDIO_DTO_BASE enum 8947 */ 8948 8949 typedef enum APG_DBG_AUDIO_DTO_BASE { 8950 BASE_RATE_48KHZ = 0x00000000, 8951 BASE_RATE_44P1KHZ = 0x00000001, 8952 } APG_DBG_AUDIO_DTO_BASE; 8953 8954 /* 8955 * APG_DBG_AUDIO_DTO_DIV enum 8956 */ 8957 8958 typedef enum APG_DBG_AUDIO_DTO_DIV { 8959 DIVISOR_BY1 = 0x00000000, 8960 DIVISOR_BY2_RESERVED = 0x00000001, 8961 DIVISOR_BY3 = 0x00000002, 8962 DIVISOR_BY4_RESERVED = 0x00000003, 8963 DIVISOR_BY5_RESERVED = 0x00000004, 8964 DIVISOR_BY6_RESERVED = 0x00000005, 8965 DIVISOR_BY7_RESERVED = 0x00000006, 8966 DIVISOR_BY8_RESERVED = 0x00000007, 8967 } APG_DBG_AUDIO_DTO_DIV; 8968 8969 /* 8970 * APG_DBG_AUDIO_DTO_MULTI enum 8971 */ 8972 8973 typedef enum APG_DBG_AUDIO_DTO_MULTI { 8974 MULTIPLE_BY1 = 0x00000000, 8975 MULTIPLE_BY2 = 0x00000001, 8976 MULTIPLE_BY3_RESERVED = 0x00000002, 8977 MULTIPLE_BY4 = 0x00000003, 8978 MULTIPLE_RESERVED = 0x00000004, 8979 } APG_DBG_AUDIO_DTO_MULTI; 8980 8981 /* 8982 * APG_DBG_MUX_SEL enum 8983 */ 8984 8985 typedef enum APG_DBG_MUX_SEL { 8986 APG_FUNCTIONAL_MODE = 0x00000000, 8987 APG_DEBUG_AUDIO_MODE = 0x00000001, 8988 } APG_DBG_MUX_SEL; 8989 8990 /* 8991 * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum 8992 */ 8993 8994 typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE { 8995 APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, 8996 APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, 8997 } APG_DP_ASP_CHANNEL_COUNT_OVERRIDE; 8998 8999 /* 9000 * APG_MEM_POWER_STATE enum 9001 */ 9002 9003 typedef enum APG_MEM_POWER_STATE { 9004 APG_MEM_POWER_STATE_ON = 0x00000000, 9005 APG_MEM_POWER_STATE_LS = 0x00000001, 9006 APG_MEM_POWER_STATE_DS = 0x00000002, 9007 APG_MEM_POWER_STATE_SD = 0x00000003, 9008 } APG_MEM_POWER_STATE; 9009 9010 /* 9011 * APG_MEM_PWR_DIS_CTRL enum 9012 */ 9013 9014 typedef enum APG_MEM_PWR_DIS_CTRL { 9015 APG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, 9016 APG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, 9017 } APG_MEM_PWR_DIS_CTRL; 9018 9019 /* 9020 * APG_MEM_PWR_FORCE_CTRL enum 9021 */ 9022 9023 typedef enum APG_MEM_PWR_FORCE_CTRL { 9024 APG_MEM_NO_FORCE_REQUEST = 0x00000000, 9025 APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 9026 APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 9027 APG_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 9028 } APG_MEM_PWR_FORCE_CTRL; 9029 9030 /* 9031 * APG_PACKET_CONTROL_ACP_SOURCE enum 9032 */ 9033 9034 typedef enum APG_PACKET_CONTROL_ACP_SOURCE { 9035 APG_ACP_SOURCE_NO_OVERRIDE = 0x00000000, 9036 APG_ACP_OVERRIDE = 0x00000001, 9037 } APG_PACKET_CONTROL_ACP_SOURCE; 9038 9039 /* 9040 * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum 9041 */ 9042 9043 typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE { 9044 APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0x00000000, 9045 APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 0x00000001, 9046 } APG_PACKET_CONTROL_AUDIO_INFO_SOURCE; 9047 9048 /* 9049 * APG_RAMP_CONTROL_SIGN enum 9050 */ 9051 9052 typedef enum APG_RAMP_CONTROL_SIGN { 9053 APG_RAMP_SIGNED = 0x00000000, 9054 APG_RAMP_UNSIGNED = 0x00000001, 9055 } APG_RAMP_CONTROL_SIGN; 9056 9057 /******************************************************* 9058 * DCIO Enums 9059 *******************************************************/ 9060 9061 /* 9062 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum 9063 */ 9064 9065 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { 9066 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000, 9067 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001, 9068 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002, 9069 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003, 9070 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004, 9071 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005, 9072 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; 9073 9074 /* 9075 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum 9076 */ 9077 9078 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { 9079 DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, 9080 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, 9081 DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002, 9082 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; 9083 9084 /* 9085 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum 9086 */ 9087 9088 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { 9089 DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, 9090 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, 9091 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; 9092 9093 /* 9094 * DCIO_DBG_ASYNC_4BIT_SEL enum 9095 */ 9096 9097 typedef enum DCIO_DBG_ASYNC_4BIT_SEL { 9098 DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000, 9099 DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001, 9100 DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002, 9101 DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003, 9102 DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004, 9103 DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005, 9104 DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006, 9105 DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007, 9106 } DCIO_DBG_ASYNC_4BIT_SEL; 9107 9108 /* 9109 * DCIO_DBG_ASYNC_BLOCK_SEL enum 9110 */ 9111 9112 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL { 9113 DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000, 9114 DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001, 9115 DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002, 9116 DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 0x00000003, 9117 } DCIO_DBG_ASYNC_BLOCK_SEL; 9118 9119 /* 9120 * DCIO_DCRXPHY_SOFT_RESET enum 9121 */ 9122 9123 typedef enum DCIO_DCRXPHY_SOFT_RESET { 9124 DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, 9125 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, 9126 } DCIO_DCRXPHY_SOFT_RESET; 9127 9128 /* 9129 * DCIO_DC_GENERICA_SEL enum 9130 */ 9131 9132 typedef enum DCIO_DC_GENERICA_SEL { 9133 DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, 9134 DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, 9135 DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, 9136 } DCIO_DC_GENERICA_SEL; 9137 9138 /* 9139 * DCIO_DC_GENERICB_SEL enum 9140 */ 9141 9142 typedef enum DCIO_DC_GENERICB_SEL { 9143 DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, 9144 DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, 9145 DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, 9146 } DCIO_DC_GENERICB_SEL; 9147 9148 /* 9149 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum 9150 */ 9151 9152 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { 9153 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, 9154 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, 9155 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, 9156 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, 9157 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, 9158 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, 9159 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006, 9160 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; 9161 9162 /* 9163 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum 9164 */ 9165 9166 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { 9167 DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, 9168 DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, 9169 DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, 9170 DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, 9171 DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, 9172 DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, 9173 DCIO_UNIPHYG_FBDIV_CLK = 0x00000006, 9174 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; 9175 9176 /* 9177 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum 9178 */ 9179 9180 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { 9181 DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, 9182 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, 9183 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, 9184 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, 9185 DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, 9186 DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, 9187 DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006, 9188 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; 9189 9190 /* 9191 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum 9192 */ 9193 9194 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { 9195 DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, 9196 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, 9197 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, 9198 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, 9199 DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, 9200 DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, 9201 DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006, 9202 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; 9203 9204 /* 9205 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum 9206 */ 9207 9208 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { 9209 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000, 9210 DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001, 9211 } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; 9212 9213 /* 9214 * DCIO_DC_GPU_TIMER_READ_SELECT enum 9215 */ 9216 9217 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { 9218 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, 9219 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, 9220 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002, 9221 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003, 9222 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004, 9223 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005, 9224 } DCIO_DC_GPU_TIMER_READ_SELECT; 9225 9226 /* 9227 * DCIO_DC_GPU_TIMER_START_POSITION enum 9228 */ 9229 9230 typedef enum DCIO_DC_GPU_TIMER_START_POSITION { 9231 DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, 9232 DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, 9233 DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, 9234 DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, 9235 DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, 9236 DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, 9237 DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, 9238 DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, 9239 } DCIO_DC_GPU_TIMER_START_POSITION; 9240 9241 /* 9242 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum 9243 */ 9244 9245 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { 9246 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, 9247 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, 9248 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, 9249 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, 9250 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; 9251 9252 /* 9253 * DCIO_DIO_EXT_VSYNC_MASK enum 9254 */ 9255 9256 typedef enum DCIO_DIO_EXT_VSYNC_MASK { 9257 DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, 9258 DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, 9259 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, 9260 DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, 9261 DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, 9262 DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, 9263 DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, 9264 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, 9265 } DCIO_DIO_EXT_VSYNC_MASK; 9266 9267 /* 9268 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum 9269 */ 9270 9271 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX { 9272 DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, 9273 DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001, 9274 DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002, 9275 DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003, 9276 DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004, 9277 DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005, 9278 DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006, 9279 DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, 9280 } DCIO_DIO_OTG_EXT_VSYNC_MUX; 9281 9282 /* 9283 * DCIO_DPCS_INTERRUPT_MASK enum 9284 */ 9285 9286 typedef enum DCIO_DPCS_INTERRUPT_MASK { 9287 DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000, 9288 DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001, 9289 } DCIO_DPCS_INTERRUPT_MASK; 9290 9291 /* 9292 * DCIO_DPCS_INTERRUPT_TYPE enum 9293 */ 9294 9295 typedef enum DCIO_DPCS_INTERRUPT_TYPE { 9296 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, 9297 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, 9298 } DCIO_DPCS_INTERRUPT_TYPE; 9299 9300 /* 9301 * DCIO_GENLK_CLK_GSL_MASK enum 9302 */ 9303 9304 typedef enum DCIO_GENLK_CLK_GSL_MASK { 9305 DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, 9306 DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, 9307 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, 9308 } DCIO_GENLK_CLK_GSL_MASK; 9309 9310 /* 9311 * DCIO_GENLK_VSYNC_GSL_MASK enum 9312 */ 9313 9314 typedef enum DCIO_GENLK_VSYNC_GSL_MASK { 9315 DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, 9316 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, 9317 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, 9318 } DCIO_GENLK_VSYNC_GSL_MASK; 9319 9320 /* 9321 * DCIO_GSL_SEL enum 9322 */ 9323 9324 typedef enum DCIO_GSL_SEL { 9325 DCIO_GSL_SEL_GROUP_0 = 0x00000000, 9326 DCIO_GSL_SEL_GROUP_1 = 0x00000001, 9327 DCIO_GSL_SEL_GROUP_2 = 0x00000002, 9328 } DCIO_GSL_SEL; 9329 9330 /* 9331 * DCIO_PHY_HPO_ENC_SRC_SEL enum 9332 */ 9333 9334 typedef enum DCIO_PHY_HPO_ENC_SRC_SEL { 9335 HPO_SRC0 = 0x00000000, 9336 HPO_SRC_RESERVED = 0x00000001, 9337 } DCIO_PHY_HPO_ENC_SRC_SEL; 9338 9339 /* 9340 * DCIO_SWAPLOCK_A_GSL_MASK enum 9341 */ 9342 9343 typedef enum DCIO_SWAPLOCK_A_GSL_MASK { 9344 DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, 9345 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, 9346 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, 9347 } DCIO_SWAPLOCK_A_GSL_MASK; 9348 9349 /* 9350 * DCIO_SWAPLOCK_B_GSL_MASK enum 9351 */ 9352 9353 typedef enum DCIO_SWAPLOCK_B_GSL_MASK { 9354 DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, 9355 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, 9356 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, 9357 } DCIO_SWAPLOCK_B_GSL_MASK; 9358 9359 /* 9360 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum 9361 */ 9362 9363 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { 9364 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, 9365 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, 9366 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, 9367 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, 9368 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; 9369 9370 /* 9371 * DCIO_UNIPHY_IMPCAL_SEL enum 9372 */ 9373 9374 typedef enum DCIO_UNIPHY_IMPCAL_SEL { 9375 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, 9376 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, 9377 } DCIO_UNIPHY_IMPCAL_SEL; 9378 9379 /* 9380 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum 9381 */ 9382 9383 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { 9384 DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, 9385 DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, 9386 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; 9387 9388 /* 9389 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum 9390 */ 9391 9392 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { 9393 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, 9394 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, 9395 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, 9396 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003, 9397 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; 9398 9399 /******************************************************* 9400 * DCIO_CHIP Enums 9401 *******************************************************/ 9402 9403 /* 9404 * DCIOCHIP_AUX_ALL_PWR_OK enum 9405 */ 9406 9407 typedef enum DCIOCHIP_AUX_ALL_PWR_OK { 9408 DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000, 9409 DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001, 9410 } DCIOCHIP_AUX_ALL_PWR_OK; 9411 9412 /* 9413 * DCIOCHIP_AUX_CSEL0P9 enum 9414 */ 9415 9416 typedef enum DCIOCHIP_AUX_CSEL0P9 { 9417 DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000, 9418 DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001, 9419 } DCIOCHIP_AUX_CSEL0P9; 9420 9421 /* 9422 * DCIOCHIP_AUX_CSEL1P1 enum 9423 */ 9424 9425 typedef enum DCIOCHIP_AUX_CSEL1P1 { 9426 DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000, 9427 DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001, 9428 } DCIOCHIP_AUX_CSEL1P1; 9429 9430 /* 9431 * DCIOCHIP_AUX_FALLSLEWSEL enum 9432 */ 9433 9434 typedef enum DCIOCHIP_AUX_FALLSLEWSEL { 9435 DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000, 9436 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001, 9437 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002, 9438 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003, 9439 } DCIOCHIP_AUX_FALLSLEWSEL; 9440 9441 /* 9442 * DCIOCHIP_AUX_HYS_TUNE enum 9443 */ 9444 9445 typedef enum DCIOCHIP_AUX_HYS_TUNE { 9446 DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000, 9447 DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001, 9448 DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002, 9449 DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003, 9450 } DCIOCHIP_AUX_HYS_TUNE; 9451 9452 /* 9453 * DCIOCHIP_AUX_RECEIVER_SEL enum 9454 */ 9455 9456 typedef enum DCIOCHIP_AUX_RECEIVER_SEL { 9457 DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000, 9458 DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001, 9459 DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002, 9460 DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003, 9461 } DCIOCHIP_AUX_RECEIVER_SEL; 9462 9463 /* 9464 * DCIOCHIP_AUX_RSEL0P9 enum 9465 */ 9466 9467 typedef enum DCIOCHIP_AUX_RSEL0P9 { 9468 DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000, 9469 DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001, 9470 } DCIOCHIP_AUX_RSEL0P9; 9471 9472 /* 9473 * DCIOCHIP_AUX_RSEL1P1 enum 9474 */ 9475 9476 typedef enum DCIOCHIP_AUX_RSEL1P1 { 9477 DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000, 9478 DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001, 9479 } DCIOCHIP_AUX_RSEL1P1; 9480 9481 /* 9482 * DCIOCHIP_AUX_SPIKESEL enum 9483 */ 9484 9485 typedef enum DCIOCHIP_AUX_SPIKESEL { 9486 DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000, 9487 DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001, 9488 } DCIOCHIP_AUX_SPIKESEL; 9489 9490 /* 9491 * DCIOCHIP_AUX_VOD_TUNE enum 9492 */ 9493 9494 typedef enum DCIOCHIP_AUX_VOD_TUNE { 9495 DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000, 9496 DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001, 9497 DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002, 9498 DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003, 9499 } DCIOCHIP_AUX_VOD_TUNE; 9500 9501 /* 9502 * DCIOCHIP_GPIO_MASK_EN enum 9503 */ 9504 9505 typedef enum DCIOCHIP_GPIO_MASK_EN { 9506 DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, 9507 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, 9508 } DCIOCHIP_GPIO_MASK_EN; 9509 9510 /* 9511 * DCIOCHIP_HPD_SEL enum 9512 */ 9513 9514 typedef enum DCIOCHIP_HPD_SEL { 9515 DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, 9516 DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, 9517 } DCIOCHIP_HPD_SEL; 9518 9519 /* 9520 * DCIOCHIP_I2C_COMPSEL enum 9521 */ 9522 9523 typedef enum DCIOCHIP_I2C_COMPSEL { 9524 DCIOCHIP_I2C_REC_SCHMIT = 0x00000000, 9525 DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001, 9526 } DCIOCHIP_I2C_COMPSEL; 9527 9528 /* 9529 * DCIOCHIP_I2C_FALLSLEWSEL enum 9530 */ 9531 9532 typedef enum DCIOCHIP_I2C_FALLSLEWSEL { 9533 DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000, 9534 DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001, 9535 DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002, 9536 DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003, 9537 } DCIOCHIP_I2C_FALLSLEWSEL; 9538 9539 /* 9540 * DCIOCHIP_I2C_RECEIVER_SEL enum 9541 */ 9542 9543 typedef enum DCIOCHIP_I2C_RECEIVER_SEL { 9544 DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000, 9545 DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001, 9546 DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002, 9547 DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003, 9548 } DCIOCHIP_I2C_RECEIVER_SEL; 9549 9550 /* 9551 * DCIOCHIP_I2C_VPH_1V2_EN enum 9552 */ 9553 9554 typedef enum DCIOCHIP_I2C_VPH_1V2_EN { 9555 DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000, 9556 DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001, 9557 } DCIOCHIP_I2C_VPH_1V2_EN; 9558 9559 /* 9560 * DCIOCHIP_INVERT enum 9561 */ 9562 9563 typedef enum DCIOCHIP_INVERT { 9564 DCIOCHIP_POL_NON_INVERT = 0x00000000, 9565 DCIOCHIP_POL_INVERT = 0x00000001, 9566 } DCIOCHIP_INVERT; 9567 9568 /* 9569 * DCIOCHIP_MASK enum 9570 */ 9571 9572 typedef enum DCIOCHIP_MASK { 9573 DCIOCHIP_MASK_DISABLE = 0x00000000, 9574 DCIOCHIP_MASK_ENABLE = 0x00000001, 9575 } DCIOCHIP_MASK; 9576 9577 /* 9578 * DCIOCHIP_PAD_MODE enum 9579 */ 9580 9581 typedef enum DCIOCHIP_PAD_MODE { 9582 DCIOCHIP_PAD_MODE_DDC = 0x00000000, 9583 DCIOCHIP_PAD_MODE_DP = 0x00000001, 9584 } DCIOCHIP_PAD_MODE; 9585 9586 /* 9587 * DCIOCHIP_PD_EN enum 9588 */ 9589 9590 typedef enum DCIOCHIP_PD_EN { 9591 DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, 9592 DCIOCHIP_PD_EN_ALLOW = 0x00000001, 9593 } DCIOCHIP_PD_EN; 9594 9595 /* 9596 * DCIOCHIP_REF_27_SRC_SEL enum 9597 */ 9598 9599 typedef enum DCIOCHIP_REF_27_SRC_SEL { 9600 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, 9601 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, 9602 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, 9603 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, 9604 } DCIOCHIP_REF_27_SRC_SEL; 9605 9606 /******************************************************* 9607 * PWRSEQ Enums 9608 *******************************************************/ 9609 9610 /* 9611 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum 9612 */ 9613 9614 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { 9615 PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, 9616 PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, 9617 } PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; 9618 9619 /* 9620 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum 9621 */ 9622 9623 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN { 9624 PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000, 9625 PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001, 9626 } PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN; 9627 9628 /* 9629 * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum 9630 */ 9631 9632 typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { 9633 PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000, 9634 PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001, 9635 PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002, 9636 PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003, 9637 } PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; 9638 9639 /* 9640 * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum 9641 */ 9642 9643 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN { 9644 PWRSEQ_BL_PWM_DISABLE = 0x00000000, 9645 PWRSEQ_BL_PWM_ENABLE = 0x00000001, 9646 } PWRSEQ_BL_PWM_CNTL_BL_PWM_EN; 9647 9648 /* 9649 * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum 9650 */ 9651 9652 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { 9653 PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, 9654 PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, 9655 } PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; 9656 9657 /* 9658 * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum 9659 */ 9660 9661 typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { 9662 PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, 9663 PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, 9664 } PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; 9665 9666 /* 9667 * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum 9668 */ 9669 9670 typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { 9671 PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, 9672 PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001, 9673 } PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; 9674 9675 /* 9676 * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum 9677 */ 9678 9679 typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK { 9680 PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, 9681 PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, 9682 } PWRSEQ_BL_PWM_GRP1_REG_LOCK; 9683 9684 /* 9685 * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum 9686 */ 9687 9688 typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START { 9689 PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, 9690 PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, 9691 } PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START; 9692 9693 /* 9694 * PWRSEQ_GPIO_MASK_EN enum 9695 */ 9696 9697 typedef enum PWRSEQ_GPIO_MASK_EN { 9698 PWRSEQ_GPIO_MASK_EN_HARDWARE = 0x00000000, 9699 PWRSEQ_GPIO_MASK_EN_SOFTWARE = 0x00000001, 9700 } PWRSEQ_GPIO_MASK_EN; 9701 9702 /* 9703 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum 9704 */ 9705 9706 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON { 9707 PWRSEQ_PANEL_BLON_OFF = 0x00000000, 9708 PWRSEQ_PANEL_BLON_ON = 0x00000001, 9709 } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON; 9710 9711 /* 9712 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum 9713 */ 9714 9715 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL { 9716 PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0x00000000, 9717 PWRSEQ_PANEL_BLON_POL_INVERT = 0x00000001, 9718 } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL; 9719 9720 /* 9721 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum 9722 */ 9723 9724 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON { 9725 PWRSEQ_PANEL_DIGON_OFF = 0x00000000, 9726 PWRSEQ_PANEL_DIGON_ON = 0x00000001, 9727 } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON; 9728 9729 /* 9730 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum 9731 */ 9732 9733 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL { 9734 PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0x00000000, 9735 PWRSEQ_PANEL_DIGON_POL_INVERT = 0x00000001, 9736 } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL; 9737 9738 /* 9739 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum 9740 */ 9741 9742 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL { 9743 PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0x00000000, 9744 PWRSEQ_PANEL_SYNCEN_POL_INVERT = 0x00000001, 9745 } PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL; 9746 9747 /* 9748 * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum 9749 */ 9750 9751 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE { 9752 PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, 9753 PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, 9754 } PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE; 9755 9756 /* 9757 * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum 9758 */ 9759 9760 typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN { 9761 PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, 9762 PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, 9763 } PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN; 9764 9765 /******************************************************* 9766 * AZCONTROLLER Enums 9767 *******************************************************/ 9768 9769 /* 9770 * AZ_CORB_SIZE enum 9771 */ 9772 9773 typedef enum AZ_CORB_SIZE { 9774 AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000, 9775 AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001, 9776 AZ_CORB_SIZE_256ENTRIES = 0x00000002, 9777 AZ_CORB_SIZE_RESERVED = 0x00000003, 9778 } AZ_CORB_SIZE; 9779 9780 /* 9781 * AZ_GLOBAL_CAPABILITIES enum 9782 */ 9783 9784 typedef enum AZ_GLOBAL_CAPABILITIES { 9785 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000, 9786 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001, 9787 } AZ_GLOBAL_CAPABILITIES; 9788 9789 /* 9790 * AZ_RIRB_SIZE enum 9791 */ 9792 9793 typedef enum AZ_RIRB_SIZE { 9794 AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000, 9795 AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001, 9796 AZ_RIRB_SIZE_256ENTRIES = 0x00000002, 9797 AZ_RIRB_SIZE_UNDEFINED = 0x00000003, 9798 } AZ_RIRB_SIZE; 9799 9800 /* 9801 * AZ_RIRB_WRITE_POINTER_RESET enum 9802 */ 9803 9804 typedef enum AZ_RIRB_WRITE_POINTER_RESET { 9805 AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000, 9806 AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001, 9807 } AZ_RIRB_WRITE_POINTER_RESET; 9808 9809 /* 9810 * AZ_STATE_CHANGE_STATUS enum 9811 */ 9812 9813 typedef enum AZ_STATE_CHANGE_STATUS { 9814 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000, 9815 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001, 9816 } AZ_STATE_CHANGE_STATUS; 9817 9818 /* 9819 * CORB_READ_POINTER_RESET enum 9820 */ 9821 9822 typedef enum CORB_READ_POINTER_RESET { 9823 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000, 9824 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001, 9825 } CORB_READ_POINTER_RESET; 9826 9827 /* 9828 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum 9829 */ 9830 9831 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { 9832 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000, 9833 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001, 9834 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; 9835 9836 /* 9837 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum 9838 */ 9839 9840 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { 9841 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000, 9842 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001, 9843 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; 9844 9845 /* 9846 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum 9847 */ 9848 9849 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { 9850 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000, 9851 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001, 9852 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; 9853 9854 /* 9855 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum 9856 */ 9857 9858 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { 9859 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000, 9860 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001, 9861 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS; 9862 9863 /* 9864 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum 9865 */ 9866 9867 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { 9868 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000, 9869 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001, 9870 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; 9871 9872 /* 9873 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum 9874 */ 9875 9876 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { 9877 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000, 9878 ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001, 9879 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; 9880 9881 /* 9882 * GLOBAL_CONTROL_CONTROLLER_RESET enum 9883 */ 9884 9885 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { 9886 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000, 9887 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001, 9888 } GLOBAL_CONTROL_CONTROLLER_RESET; 9889 9890 /* 9891 * GLOBAL_CONTROL_FLUSH_CONTROL enum 9892 */ 9893 9894 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { 9895 FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000, 9896 FLUSH_CONTROL_FLUSH_STARTED = 0x00000001, 9897 } GLOBAL_CONTROL_FLUSH_CONTROL; 9898 9899 /* 9900 * GLOBAL_STATUS_FLUSH_STATUS enum 9901 */ 9902 9903 typedef enum GLOBAL_STATUS_FLUSH_STATUS { 9904 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000, 9905 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001, 9906 } GLOBAL_STATUS_FLUSH_STATUS; 9907 9908 /* 9909 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum 9910 */ 9911 9912 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { 9913 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000, 9914 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001, 9915 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; 9916 9917 /* 9918 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum 9919 */ 9920 9921 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { 9922 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000, 9923 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001, 9924 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; 9925 9926 /* 9927 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum 9928 */ 9929 9930 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { 9931 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, 9932 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, 9933 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; 9934 9935 /* 9936 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum 9937 */ 9938 9939 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { 9940 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, 9941 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, 9942 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; 9943 9944 /* 9945 * STREAM_0_SYNCHRONIZATION enum 9946 */ 9947 9948 typedef enum STREAM_0_SYNCHRONIZATION { 9949 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 9950 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 9951 } STREAM_0_SYNCHRONIZATION; 9952 9953 /* 9954 * STREAM_10_SYNCHRONIZATION enum 9955 */ 9956 9957 typedef enum STREAM_10_SYNCHRONIZATION { 9958 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9959 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9960 } STREAM_10_SYNCHRONIZATION; 9961 9962 /* 9963 * STREAM_11_SYNCHRONIZATION enum 9964 */ 9965 9966 typedef enum STREAM_11_SYNCHRONIZATION { 9967 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9968 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9969 } STREAM_11_SYNCHRONIZATION; 9970 9971 /* 9972 * STREAM_12_SYNCHRONIZATION enum 9973 */ 9974 9975 typedef enum STREAM_12_SYNCHRONIZATION { 9976 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9977 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9978 } STREAM_12_SYNCHRONIZATION; 9979 9980 /* 9981 * STREAM_13_SYNCHRONIZATION enum 9982 */ 9983 9984 typedef enum STREAM_13_SYNCHRONIZATION { 9985 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9986 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9987 } STREAM_13_SYNCHRONIZATION; 9988 9989 /* 9990 * STREAM_14_SYNCHRONIZATION enum 9991 */ 9992 9993 typedef enum STREAM_14_SYNCHRONIZATION { 9994 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 9995 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 9996 } STREAM_14_SYNCHRONIZATION; 9997 9998 /* 9999 * STREAM_15_SYNCHRONIZATION enum 10000 */ 10001 10002 typedef enum STREAM_15_SYNCHRONIZATION { 10003 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10004 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10005 } STREAM_15_SYNCHRONIZATION; 10006 10007 /* 10008 * STREAM_1_SYNCHRONIZATION enum 10009 */ 10010 10011 typedef enum STREAM_1_SYNCHRONIZATION { 10012 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 10013 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 10014 } STREAM_1_SYNCHRONIZATION; 10015 10016 /* 10017 * STREAM_2_SYNCHRONIZATION enum 10018 */ 10019 10020 typedef enum STREAM_2_SYNCHRONIZATION { 10021 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 10022 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 10023 } STREAM_2_SYNCHRONIZATION; 10024 10025 /* 10026 * STREAM_3_SYNCHRONIZATION enum 10027 */ 10028 10029 typedef enum STREAM_3_SYNCHRONIZATION { 10030 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, 10031 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, 10032 } STREAM_3_SYNCHRONIZATION; 10033 10034 /* 10035 * STREAM_4_SYNCHRONIZATION enum 10036 */ 10037 10038 typedef enum STREAM_4_SYNCHRONIZATION { 10039 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10040 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10041 } STREAM_4_SYNCHRONIZATION; 10042 10043 /* 10044 * STREAM_5_SYNCHRONIZATION enum 10045 */ 10046 10047 typedef enum STREAM_5_SYNCHRONIZATION { 10048 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10049 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10050 } STREAM_5_SYNCHRONIZATION; 10051 10052 /* 10053 * STREAM_6_SYNCHRONIZATION enum 10054 */ 10055 10056 typedef enum STREAM_6_SYNCHRONIZATION { 10057 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10058 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10059 } STREAM_6_SYNCHRONIZATION; 10060 10061 /* 10062 * STREAM_7_SYNCHRONIZATION enum 10063 */ 10064 10065 typedef enum STREAM_7_SYNCHRONIZATION { 10066 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10067 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10068 } STREAM_7_SYNCHRONIZATION; 10069 10070 /* 10071 * STREAM_8_SYNCHRONIZATION enum 10072 */ 10073 10074 typedef enum STREAM_8_SYNCHRONIZATION { 10075 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10076 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10077 } STREAM_8_SYNCHRONIZATION; 10078 10079 /* 10080 * STREAM_9_SYNCHRONIZATION enum 10081 */ 10082 10083 typedef enum STREAM_9_SYNCHRONIZATION { 10084 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, 10085 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, 10086 } STREAM_9_SYNCHRONIZATION; 10087 10088 /******************************************************* 10089 * AZENDPOINT Enums 10090 *******************************************************/ 10091 10092 /* 10093 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum 10094 */ 10095 10096 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 10097 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 10098 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 10099 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 10100 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 10101 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 10102 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 10103 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 10104 10105 /* 10106 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum 10107 */ 10108 10109 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 10110 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 10111 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 10112 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 10113 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 10114 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 10115 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 10116 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 10117 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 10118 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, 10119 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 10120 10121 /* 10122 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum 10123 */ 10124 10125 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 10126 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 10127 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 10128 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 10129 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 10130 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 10131 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 10132 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 10133 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 10134 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 10135 10136 /* 10137 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum 10138 */ 10139 10140 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 10141 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 10142 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 10143 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 10144 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 10145 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 10146 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 10147 10148 /* 10149 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum 10150 */ 10151 10152 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 10153 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 10154 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 10155 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 10156 10157 /* 10158 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum 10159 */ 10160 10161 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 10162 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, 10163 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, 10164 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 10165 10166 /* 10167 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum 10168 */ 10169 10170 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { 10171 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000, 10172 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001, 10173 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; 10174 10175 /* 10176 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum 10177 */ 10178 10179 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { 10180 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000, 10181 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001, 10182 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; 10183 10184 /* 10185 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum 10186 */ 10187 10188 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 10189 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, 10190 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, 10191 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 10192 10193 /* 10194 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum 10195 */ 10196 10197 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { 10198 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000, 10199 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001, 10200 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; 10201 10202 /* 10203 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum 10204 */ 10205 10206 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { 10207 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000, 10208 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001, 10209 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; 10210 10211 /* 10212 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum 10213 */ 10214 10215 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { 10216 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000, 10217 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001, 10218 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; 10219 10220 /* 10221 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum 10222 */ 10223 10224 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { 10225 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000, 10226 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001, 10227 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; 10228 10229 /* 10230 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum 10231 */ 10232 10233 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { 10234 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000, 10235 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001, 10236 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; 10237 10238 /* 10239 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum 10240 */ 10241 10242 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { 10243 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000, 10244 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001, 10245 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; 10246 10247 /* 10248 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum 10249 */ 10250 10251 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE { 10252 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000, 10253 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001, 10254 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002, 10255 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003, 10256 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004, 10257 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005, 10258 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006, 10259 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007, 10260 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008, 10261 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009, 10262 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a, 10263 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b, 10264 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c, 10265 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d, 10266 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e, 10267 AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f, 10268 } AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE; 10269 10270 /* 10271 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum 10272 */ 10273 10274 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { 10275 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000, 10276 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001, 10277 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; 10278 10279 /* 10280 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum 10281 */ 10282 10283 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { 10284 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000, 10285 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001, 10286 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; 10287 10288 /* 10289 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum 10290 */ 10291 10292 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 10293 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, 10294 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, 10295 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 10296 10297 /* 10298 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum 10299 */ 10300 10301 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { 10302 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000, 10303 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001, 10304 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; 10305 10306 /* 10307 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum 10308 */ 10309 10310 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 10311 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, 10312 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, 10313 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 10314 10315 /* 10316 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum 10317 */ 10318 10319 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { 10320 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000, 10321 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001, 10322 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; 10323 10324 /* 10325 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum 10326 */ 10327 10328 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 10329 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, 10330 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, 10331 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 10332 10333 /* 10334 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum 10335 */ 10336 10337 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { 10338 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000, 10339 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001, 10340 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; 10341 10342 /* 10343 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum 10344 */ 10345 10346 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 10347 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, 10348 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, 10349 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 10350 10351 /* 10352 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum 10353 */ 10354 10355 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 10356 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, 10357 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, 10358 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 10359 10360 /* 10361 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum 10362 */ 10363 10364 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 10365 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, 10366 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, 10367 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 10368 10369 /* 10370 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum 10371 */ 10372 10373 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { 10374 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000, 10375 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001, 10376 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; 10377 10378 /******************************************************* 10379 * AZF0CONTROLLER Enums 10380 *******************************************************/ 10381 10382 /* 10383 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum 10384 */ 10385 10386 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET { 10387 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000, 10388 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001, 10389 } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; 10390 10391 /* 10392 * MEM_PWR_DIS_CTRL enum 10393 */ 10394 10395 typedef enum MEM_PWR_DIS_CTRL { 10396 ENABLE_MEM_PWR_CTRL = 0x00000000, 10397 DISABLE_MEM_PWR_CTRL = 0x00000001, 10398 } MEM_PWR_DIS_CTRL; 10399 10400 /* 10401 * MEM_PWR_FORCE_CTRL enum 10402 */ 10403 10404 typedef enum MEM_PWR_FORCE_CTRL { 10405 NO_FORCE_REQUEST = 0x00000000, 10406 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 10407 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 10408 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 10409 } MEM_PWR_FORCE_CTRL; 10410 10411 /* 10412 * MEM_PWR_FORCE_CTRL2 enum 10413 */ 10414 10415 typedef enum MEM_PWR_FORCE_CTRL2 { 10416 NO_FORCE_REQ = 0x00000000, 10417 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 10418 } MEM_PWR_FORCE_CTRL2; 10419 10420 /* 10421 * MEM_PWR_SEL_CTRL enum 10422 */ 10423 10424 typedef enum MEM_PWR_SEL_CTRL { 10425 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, 10426 DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, 10427 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, 10428 } MEM_PWR_SEL_CTRL; 10429 10430 /* 10431 * MEM_PWR_SEL_CTRL2 enum 10432 */ 10433 10434 typedef enum MEM_PWR_SEL_CTRL2 { 10435 DYNAMIC_DEEP_SLEEP_EN = 0x00000000, 10436 DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, 10437 } MEM_PWR_SEL_CTRL2; 10438 10439 /******************************************************* 10440 * AZF0ROOT Enums 10441 *******************************************************/ 10442 10443 /* 10444 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum 10445 */ 10446 10447 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { 10448 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000, 10449 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001, 10450 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002, 10451 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003, 10452 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004, 10453 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005, 10454 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006, 10455 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007, 10456 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; 10457 10458 /* 10459 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum 10460 */ 10461 10462 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { 10463 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000, 10464 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001, 10465 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002, 10466 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003, 10467 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004, 10468 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005, 10469 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006, 10470 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007, 10471 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; 10472 10473 /******************************************************* 10474 * AZINPUTENDPOINT Enums 10475 *******************************************************/ 10476 10477 /* 10478 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum 10479 */ 10480 10481 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 10482 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 10483 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 10484 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 10485 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 10486 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 10487 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 10488 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 10489 10490 /* 10491 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum 10492 */ 10493 10494 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 10495 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 10496 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 10497 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 10498 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 10499 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 10500 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 10501 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 10502 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 10503 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, 10504 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 10505 10506 /* 10507 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum 10508 */ 10509 10510 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 10511 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 10512 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 10513 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 10514 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 10515 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 10516 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 10517 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 10518 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 10519 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 10520 10521 /* 10522 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum 10523 */ 10524 10525 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 10526 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 10527 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 10528 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 10529 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 10530 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 10531 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 10532 10533 /* 10534 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum 10535 */ 10536 10537 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 10538 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 10539 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 10540 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 10541 10542 /* 10543 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum 10544 */ 10545 10546 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 10547 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, 10548 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, 10549 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 10550 10551 /* 10552 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum 10553 */ 10554 10555 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 10556 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, 10557 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, 10558 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 10559 10560 /* 10561 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum 10562 */ 10563 10564 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { 10565 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000, 10566 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001, 10567 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; 10568 10569 /* 10570 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum 10571 */ 10572 10573 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 10574 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, 10575 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, 10576 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 10577 10578 /* 10579 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum 10580 */ 10581 10582 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { 10583 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000, 10584 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001, 10585 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; 10586 10587 /* 10588 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum 10589 */ 10590 10591 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 10592 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, 10593 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, 10594 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 10595 10596 /* 10597 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum 10598 */ 10599 10600 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { 10601 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000, 10602 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001, 10603 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; 10604 10605 /* 10606 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum 10607 */ 10608 10609 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 10610 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, 10611 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, 10612 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 10613 10614 /* 10615 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum 10616 */ 10617 10618 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { 10619 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000, 10620 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001, 10621 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; 10622 10623 /* 10624 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum 10625 */ 10626 10627 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 10628 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, 10629 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, 10630 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 10631 10632 /* 10633 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum 10634 */ 10635 10636 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 10637 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, 10638 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, 10639 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 10640 10641 /* 10642 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum 10643 */ 10644 10645 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { 10646 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000, 10647 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001, 10648 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; 10649 10650 /******************************************************* 10651 * AZROOT Enums 10652 *******************************************************/ 10653 10654 /* 10655 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum 10656 */ 10657 10658 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { 10659 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000, 10660 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001, 10661 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; 10662 10663 /******************************************************* 10664 * AZF0STREAM Enums 10665 *******************************************************/ 10666 10667 /* 10668 * AZ_LATENCY_COUNTER_CONTROL enum 10669 */ 10670 10671 typedef enum AZ_LATENCY_COUNTER_CONTROL { 10672 AZ_LATENCY_COUNTER_NO_RESET = 0x00000000, 10673 AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001, 10674 } AZ_LATENCY_COUNTER_CONTROL; 10675 10676 /******************************************************* 10677 * AZSTREAM Enums 10678 *******************************************************/ 10679 10680 /* 10681 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum 10682 */ 10683 10684 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { 10685 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000, 10686 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001, 10687 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; 10688 10689 /* 10690 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum 10691 */ 10692 10693 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { 10694 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000, 10695 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001, 10696 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; 10697 10698 /* 10699 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum 10700 */ 10701 10702 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { 10703 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000, 10704 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001, 10705 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; 10706 10707 /* 10708 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum 10709 */ 10710 10711 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { 10712 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000, 10713 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001, 10714 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; 10715 10716 /* 10717 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum 10718 */ 10719 10720 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { 10721 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000, 10722 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001, 10723 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; 10724 10725 /* 10726 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum 10727 */ 10728 10729 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { 10730 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000, 10731 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001, 10732 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; 10733 10734 /* 10735 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum 10736 */ 10737 10738 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { 10739 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000, 10740 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001, 10741 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; 10742 10743 /* 10744 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum 10745 */ 10746 10747 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { 10748 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000, 10749 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001, 10750 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; 10751 10752 /* 10753 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum 10754 */ 10755 10756 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { 10757 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000, 10758 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001, 10759 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; 10760 10761 /* 10762 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum 10763 */ 10764 10765 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { 10766 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, 10767 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, 10768 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, 10769 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, 10770 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, 10771 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, 10772 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; 10773 10774 /* 10775 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum 10776 */ 10777 10778 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { 10779 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, 10780 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, 10781 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, 10782 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, 10783 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, 10784 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, 10785 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, 10786 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, 10787 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008, 10788 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009, 10789 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a, 10790 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b, 10791 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c, 10792 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d, 10793 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e, 10794 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f, 10795 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; 10796 10797 /* 10798 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum 10799 */ 10800 10801 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { 10802 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, 10803 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, 10804 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, 10805 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, 10806 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, 10807 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, 10808 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, 10809 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, 10810 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; 10811 10812 /* 10813 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum 10814 */ 10815 10816 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { 10817 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, 10818 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, 10819 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, 10820 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, 10821 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, 10822 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; 10823 10824 /* 10825 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum 10826 */ 10827 10828 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { 10829 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, 10830 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, 10831 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; 10832 10833 /******************************************************* 10834 * AZF0ENDPOINT Enums 10835 *******************************************************/ 10836 10837 /* 10838 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10839 */ 10840 10841 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10842 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10843 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 10844 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10845 10846 /* 10847 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum 10848 */ 10849 10850 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 10851 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, 10852 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, 10853 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 10854 10855 /* 10856 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10857 */ 10858 10859 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10860 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10861 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10862 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10863 10864 /* 10865 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 10866 */ 10867 10868 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 10869 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 10870 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 10871 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 10872 10873 /* 10874 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum 10875 */ 10876 10877 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 10878 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, 10879 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001, 10880 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 10881 10882 /* 10883 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 10884 */ 10885 10886 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 10887 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 10888 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 10889 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 10890 10891 /* 10892 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 10893 */ 10894 10895 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 10896 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 10897 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 10898 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 10899 10900 /* 10901 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 10902 */ 10903 10904 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 10905 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 10906 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 10907 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 10908 10909 /* 10910 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 10911 */ 10912 10913 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 10914 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 10915 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 10916 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 10917 10918 /* 10919 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 10920 */ 10921 10922 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 10923 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, 10924 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 10925 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 10926 10927 /* 10928 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 10929 */ 10930 10931 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 10932 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 10933 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 10934 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 10935 10936 /* 10937 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 10938 */ 10939 10940 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 10941 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 10942 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 10943 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 10944 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 10945 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 10946 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 10947 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 10948 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 10949 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, 10950 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 10951 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 10952 10953 /* 10954 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 10955 */ 10956 10957 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 10958 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 10959 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 10960 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 10961 10962 /* 10963 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum 10964 */ 10965 10966 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 10967 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, 10968 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, 10969 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 10970 10971 /* 10972 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum 10973 */ 10974 10975 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 10976 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000, 10977 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001, 10978 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 10979 10980 /* 10981 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 10982 */ 10983 10984 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 10985 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 10986 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 10987 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 10988 10989 /* 10990 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 10991 */ 10992 10993 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 10994 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 10995 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 10996 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 10997 10998 /* 10999 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 11000 */ 11001 11002 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 11003 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 11004 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 11005 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 11006 11007 /* 11008 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 11009 */ 11010 11011 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 11012 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000, 11013 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 11014 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 11015 11016 /* 11017 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 11018 */ 11019 11020 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 11021 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 11022 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 11023 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 11024 11025 /* 11026 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 11027 */ 11028 11029 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 11030 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 11031 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 11032 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 11033 11034 /* 11035 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 11036 */ 11037 11038 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 11039 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 11040 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 11041 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 11042 11043 /* 11044 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 11045 */ 11046 11047 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 11048 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, 11049 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 11050 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 11051 11052 /* 11053 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 11054 */ 11055 11056 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 11057 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 11058 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 11059 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 11060 11061 /* 11062 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 11063 */ 11064 11065 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 11066 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 11067 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 11068 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 11069 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 11070 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 11071 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 11072 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 11073 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 11074 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, 11075 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 11076 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 11077 11078 /* 11079 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 11080 */ 11081 11082 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 11083 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 11084 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 11085 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 11086 11087 /* 11088 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum 11089 */ 11090 11091 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 11092 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000, 11093 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, 11094 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 11095 11096 /* 11097 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum 11098 */ 11099 11100 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 11101 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000, 11102 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001, 11103 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 11104 11105 /* 11106 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum 11107 */ 11108 11109 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 11110 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, 11111 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, 11112 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 11113 11114 /* 11115 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum 11116 */ 11117 11118 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 11119 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, 11120 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, 11121 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 11122 11123 /* 11124 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum 11125 */ 11126 11127 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 11128 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, 11129 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, 11130 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 11131 11132 /* 11133 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum 11134 */ 11135 11136 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 11137 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000, 11138 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001, 11139 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 11140 11141 /* 11142 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum 11143 */ 11144 11145 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 11146 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, 11147 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, 11148 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 11149 11150 /* 11151 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum 11152 */ 11153 11154 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 11155 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, 11156 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, 11157 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 11158 11159 /******************************************************* 11160 * AZF0INPUTENDPOINT Enums 11161 *******************************************************/ 11162 11163 /* 11164 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 11165 */ 11166 11167 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 11168 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 11169 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001, 11170 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 11171 11172 /* 11173 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum 11174 */ 11175 11176 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 11177 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, 11178 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, 11179 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 11180 11181 /* 11182 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 11183 */ 11184 11185 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 11186 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 11187 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 11188 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 11189 11190 /* 11191 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 11192 */ 11193 11194 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 11195 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000, 11196 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001, 11197 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 11198 11199 /* 11200 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum 11201 */ 11202 11203 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 11204 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, 11205 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001, 11206 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 11207 11208 /* 11209 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 11210 */ 11211 11212 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 11213 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 11214 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 11215 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 11216 11217 /* 11218 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 11219 */ 11220 11221 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 11222 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, 11223 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, 11224 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 11225 11226 /* 11227 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 11228 */ 11229 11230 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 11231 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 11232 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 11233 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 11234 11235 /* 11236 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 11237 */ 11238 11239 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 11240 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 11241 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 11242 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 11243 11244 /* 11245 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 11246 */ 11247 11248 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 11249 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000, 11250 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001, 11251 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 11252 11253 /* 11254 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 11255 */ 11256 11257 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 11258 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000, 11259 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 11260 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 11261 11262 /* 11263 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 11264 */ 11265 11266 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 11267 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 11268 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 11269 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 11270 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 11271 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 11272 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 11273 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 11274 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 11275 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, 11276 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 11277 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 11278 11279 /* 11280 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 11281 */ 11282 11283 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 11284 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 11285 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 11286 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 11287 11288 /* 11289 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum 11290 */ 11291 11292 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 11293 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000, 11294 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001, 11295 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 11296 11297 /* 11298 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum 11299 */ 11300 11301 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 11302 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, 11303 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, 11304 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 11305 11306 /* 11307 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum 11308 */ 11309 11310 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 11311 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, 11312 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, 11313 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 11314 11315 /* 11316 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum 11317 */ 11318 11319 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 11320 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, 11321 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, 11322 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 11323 11324 /* 11325 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum 11326 */ 11327 11328 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 11329 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, 11330 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, 11331 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 11332 11333 /* 11334 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum 11335 */ 11336 11337 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 11338 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000, 11339 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001, 11340 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 11341 11342 /* 11343 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum 11344 */ 11345 11346 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 11347 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, 11348 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, 11349 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 11350 11351 /* 11352 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum 11353 */ 11354 11355 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 11356 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, 11357 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, 11358 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 11359 11360 /* 11361 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum 11362 */ 11363 11364 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 11365 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000, 11366 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001, 11367 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 11368 11369 /* 11370 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum 11371 */ 11372 11373 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 11374 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, 11375 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, 11376 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 11377 11378 /* 11379 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum 11380 */ 11381 11382 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 11383 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, 11384 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, 11385 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, 11386 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, 11387 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, 11388 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, 11389 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, 11390 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, 11391 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, 11392 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, 11393 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 11394 11395 /* 11396 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum 11397 */ 11398 11399 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 11400 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, 11401 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, 11402 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 11403 11404 /* 11405 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum 11406 */ 11407 11408 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 11409 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000, 11410 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, 11411 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 11412 11413 /* 11414 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum 11415 */ 11416 11417 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { 11418 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000, 11419 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001, 11420 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; 11421 11422 /* 11423 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum 11424 */ 11425 11426 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 11427 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000, 11428 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001, 11429 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 11430 11431 /* 11432 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum 11433 */ 11434 11435 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { 11436 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000, 11437 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001, 11438 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; 11439 11440 /* 11441 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum 11442 */ 11443 11444 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 11445 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, 11446 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, 11447 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 11448 11449 /* 11450 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum 11451 */ 11452 11453 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 11454 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, 11455 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, 11456 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 11457 11458 /* 11459 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum 11460 */ 11461 11462 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 11463 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, 11464 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, 11465 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 11466 11467 /* 11468 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum 11469 */ 11470 11471 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 11472 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000, 11473 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001, 11474 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 11475 11476 /* 11477 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum 11478 */ 11479 11480 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 11481 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, 11482 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, 11483 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 11484 11485 /* 11486 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum 11487 */ 11488 11489 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 11490 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, 11491 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, 11492 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 11493 11494 /******************************************************* 11495 * DSCC Enums 11496 *******************************************************/ 11497 11498 /* 11499 * DSCC_BITS_PER_COMPONENT_ENUM enum 11500 */ 11501 11502 typedef enum DSCC_BITS_PER_COMPONENT_ENUM { 11503 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, 11504 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, 11505 DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, 11506 } DSCC_BITS_PER_COMPONENT_ENUM; 11507 11508 /* 11509 * DSCC_DSC_VERSION_MAJOR_ENUM enum 11510 */ 11511 11512 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM { 11513 DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001, 11514 } DSCC_DSC_VERSION_MAJOR_ENUM; 11515 11516 /* 11517 * DSCC_DSC_VERSION_MINOR_ENUM enum 11518 */ 11519 11520 typedef enum DSCC_DSC_VERSION_MINOR_ENUM { 11521 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001, 11522 DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002, 11523 } DSCC_DSC_VERSION_MINOR_ENUM; 11524 11525 /* 11526 * DSCC_ENABLE_ENUM enum 11527 */ 11528 11529 typedef enum DSCC_ENABLE_ENUM { 11530 DSCC_ENABLE_ENUM_DISABLED = 0x00000000, 11531 DSCC_ENABLE_ENUM_ENABLED = 0x00000001, 11532 } DSCC_ENABLE_ENUM; 11533 11534 /* 11535 * DSCC_ICH_RESET_ENUM enum 11536 */ 11537 11538 typedef enum DSCC_ICH_RESET_ENUM { 11539 DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001, 11540 DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002, 11541 DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004, 11542 DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008, 11543 } DSCC_ICH_RESET_ENUM; 11544 11545 /* 11546 * DSCC_LINEBUF_DEPTH_ENUM enum 11547 */ 11548 11549 typedef enum DSCC_LINEBUF_DEPTH_ENUM { 11550 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008, 11551 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009, 11552 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a, 11553 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b, 11554 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c, 11555 DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d, 11556 } DSCC_LINEBUF_DEPTH_ENUM; 11557 11558 /* 11559 * DSCC_MEM_PWR_DIS_ENUM enum 11560 */ 11561 11562 typedef enum DSCC_MEM_PWR_DIS_ENUM { 11563 DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000, 11564 DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001, 11565 } DSCC_MEM_PWR_DIS_ENUM; 11566 11567 /* 11568 * DSCC_MEM_PWR_FORCE_ENUM enum 11569 */ 11570 11571 typedef enum DSCC_MEM_PWR_FORCE_ENUM { 11572 DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000, 11573 DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 11574 DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 11575 DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, 11576 } DSCC_MEM_PWR_FORCE_ENUM; 11577 11578 /* 11579 * POWER_STATE_ENUM enum 11580 */ 11581 11582 typedef enum POWER_STATE_ENUM { 11583 POWER_STATE_ENUM_ON = 0x00000000, 11584 POWER_STATE_ENUM_LS = 0x00000001, 11585 POWER_STATE_ENUM_DS = 0x00000002, 11586 POWER_STATE_ENUM_SD = 0x00000003, 11587 } POWER_STATE_ENUM; 11588 11589 /******************************************************* 11590 * DSCCIF Enums 11591 *******************************************************/ 11592 11593 /* 11594 * DSCCIF_BITS_PER_COMPONENT_ENUM enum 11595 */ 11596 11597 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM { 11598 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, 11599 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, 11600 DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, 11601 } DSCCIF_BITS_PER_COMPONENT_ENUM; 11602 11603 /* 11604 * DSCCIF_ENABLE_ENUM enum 11605 */ 11606 11607 typedef enum DSCCIF_ENABLE_ENUM { 11608 DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000, 11609 DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001, 11610 } DSCCIF_ENABLE_ENUM; 11611 11612 /* 11613 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum 11614 */ 11615 11616 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM { 11617 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000, 11618 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001, 11619 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002, 11620 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003, 11621 DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004, 11622 } DSCCIF_INPUT_PIXEL_FORMAT_ENUM; 11623 11624 /******************************************************* 11625 * DSC_TOP Enums 11626 *******************************************************/ 11627 11628 /* 11629 * CLOCK_GATING_DISABLE_ENUM enum 11630 */ 11631 11632 typedef enum CLOCK_GATING_DISABLE_ENUM { 11633 CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000, 11634 CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001, 11635 } CLOCK_GATING_DISABLE_ENUM; 11636 11637 /* 11638 * ENABLE_ENUM enum 11639 */ 11640 11641 typedef enum ENABLE_ENUM { 11642 ENABLE_ENUM_DISABLED = 0x00000000, 11643 ENABLE_ENUM_ENABLED = 0x00000001, 11644 } ENABLE_ENUM; 11645 11646 /* 11647 * TEST_CLOCK_MUX_SELECT_ENUM enum 11648 */ 11649 11650 typedef enum TEST_CLOCK_MUX_SELECT_ENUM { 11651 TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000, 11652 TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001, 11653 TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002, 11654 TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003, 11655 TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004, 11656 TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005, 11657 TEST_CLOCK_MUX_SELECT_DSCCLK_D = 0x00000006, 11658 } TEST_CLOCK_MUX_SELECT_ENUM; 11659 11660 /******************************************************* 11661 * DWB_TOP Enums 11662 *******************************************************/ 11663 11664 /* 11665 * DWB_CRC_CONT_EN_ENUM enum 11666 */ 11667 11668 typedef enum DWB_CRC_CONT_EN_ENUM { 11669 DWB_CRC_CONT_EN_ONE_SHOT = 0x00000000, 11670 DWB_CRC_CONT_EN_CONT = 0x00000001, 11671 } DWB_CRC_CONT_EN_ENUM; 11672 11673 /* 11674 * DWB_CRC_SRC_SEL_ENUM enum 11675 */ 11676 11677 typedef enum DWB_CRC_SRC_SEL_ENUM { 11678 DWB_CRC_SRC_SEL_DWB_IN = 0x00000000, 11679 DWB_CRC_SRC_SEL_OGAM_OUT = 0x00000001, 11680 DWB_CRC_SRC_SEL_DWB_OUT = 0x00000002, 11681 } DWB_CRC_SRC_SEL_ENUM; 11682 11683 /* 11684 * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum 11685 */ 11686 11687 typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM { 11688 DWB_DATA_OVERFLOW_INT_TYPE_0 = 0x00000000, 11689 DWB_DATA_OVERFLOW_INT_TYPE_1 = 0x00000001, 11690 } DWB_DATA_OVERFLOW_INT_TYPE_ENUM; 11691 11692 /* 11693 * DWB_DATA_OVERFLOW_TYPE_ENUM enum 11694 */ 11695 11696 typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM { 11697 DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0x00000000, 11698 DWB_DATA_OVERFLOW_TYPE_BUFFER = 0x00000001, 11699 DWB_DATA_OVERFLOW_TYPE_VUPDATE = 0x00000002, 11700 DWB_DATA_OVERFLOW_TYPE_VREADY = 0x00000003, 11701 } DWB_DATA_OVERFLOW_TYPE_ENUM; 11702 11703 /* 11704 * DWB_DEBUG_SEL_ENUM enum 11705 */ 11706 11707 typedef enum DWB_DEBUG_SEL_ENUM { 11708 DWB_DEBUG_SEL_FC = 0x00000000, 11709 DWB_DEBUG_SEL_RESERVED = 0x00000001, 11710 DWB_DEBUG_SEL_DWBCP = 0x00000002, 11711 DWB_DEBUG_SEL_PERFMON = 0x00000003, 11712 } DWB_DEBUG_SEL_ENUM; 11713 11714 /* 11715 * DWB_MEM_PWR_FORCE_ENUM enum 11716 */ 11717 11718 typedef enum DWB_MEM_PWR_FORCE_ENUM { 11719 DWB_MEM_PWR_FORCE_DIS = 0x00000000, 11720 DWB_MEM_PWR_FORCE_LS = 0x00000001, 11721 DWB_MEM_PWR_FORCE_DS = 0x00000002, 11722 DWB_MEM_PWR_FORCE_SD = 0x00000003, 11723 } DWB_MEM_PWR_FORCE_ENUM; 11724 11725 /* 11726 * DWB_MEM_PWR_STATE_ENUM enum 11727 */ 11728 11729 typedef enum DWB_MEM_PWR_STATE_ENUM { 11730 DWB_MEM_PWR_STATE_ON = 0x00000000, 11731 DWB_MEM_PWR_STATE_LS = 0x00000001, 11732 DWB_MEM_PWR_STATE_DS = 0x00000002, 11733 DWB_MEM_PWR_STATE_SD = 0x00000003, 11734 } DWB_MEM_PWR_STATE_ENUM; 11735 11736 /* 11737 * DWB_TEST_CLK_SEL_ENUM enum 11738 */ 11739 11740 typedef enum DWB_TEST_CLK_SEL_ENUM { 11741 DWB_TEST_CLK_SEL_R = 0x00000000, 11742 DWB_TEST_CLK_SEL_G = 0x00000001, 11743 DWB_TEST_CLK_SEL_P = 0x00000002, 11744 } DWB_TEST_CLK_SEL_ENUM; 11745 11746 /* 11747 * FC_EYE_SELECTION_ENUM enum 11748 */ 11749 11750 typedef enum FC_EYE_SELECTION_ENUM { 11751 FC_EYE_SELECTION_STEREO_DIS = 0x00000000, 11752 FC_EYE_SELECTION_LEFT_EYE = 0x00000001, 11753 FC_EYE_SELECTION_RIGHT_EYE = 0x00000002, 11754 } FC_EYE_SELECTION_ENUM; 11755 11756 /* 11757 * FC_FRAME_CAPTURE_RATE_ENUM enum 11758 */ 11759 11760 typedef enum FC_FRAME_CAPTURE_RATE_ENUM { 11761 FC_FRAME_CAPTURE_RATE_FULL = 0x00000000, 11762 FC_FRAME_CAPTURE_RATE_HALF = 0x00000001, 11763 FC_FRAME_CAPTURE_RATE_THIRD = 0x00000002, 11764 FC_FRAME_CAPTURE_RATE_QUARTER = 0x00000003, 11765 } FC_FRAME_CAPTURE_RATE_ENUM; 11766 11767 /* 11768 * FC_STEREO_EYE_POLARITY_ENUM enum 11769 */ 11770 11771 typedef enum FC_STEREO_EYE_POLARITY_ENUM { 11772 FC_STEREO_EYE_POLARITY_LEFT = 0x00000000, 11773 FC_STEREO_EYE_POLARITY_RIGHT = 0x00000001, 11774 } FC_STEREO_EYE_POLARITY_ENUM; 11775 11776 /******************************************************* 11777 * DWBCP Enums 11778 *******************************************************/ 11779 11780 /* 11781 * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum 11782 */ 11783 11784 typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM { 11785 DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, 11786 DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, 11787 } DWB_GAMUT_REMAP_COEF_FORMAT_ENUM; 11788 11789 /* 11790 * DWB_GAMUT_REMAP_MODE_ENUM enum 11791 */ 11792 11793 typedef enum DWB_GAMUT_REMAP_MODE_ENUM { 11794 DWB_GAMUT_REMAP_MODE_BYPASS = 0x00000000, 11795 DWB_GAMUT_REMAP_MODE_COEF_A = 0x00000001, 11796 DWB_GAMUT_REMAP_MODE_COEF_B = 0x00000002, 11797 DWB_GAMUT_REMAP_MODE_RESERVED = 0x00000003, 11798 } DWB_GAMUT_REMAP_MODE_ENUM; 11799 11800 /* 11801 * DWB_LUT_NUM_SEG enum 11802 */ 11803 11804 typedef enum DWB_LUT_NUM_SEG { 11805 DWB_SEGMENTS_1 = 0x00000000, 11806 DWB_SEGMENTS_2 = 0x00000001, 11807 DWB_SEGMENTS_4 = 0x00000002, 11808 DWB_SEGMENTS_8 = 0x00000003, 11809 DWB_SEGMENTS_16 = 0x00000004, 11810 DWB_SEGMENTS_32 = 0x00000005, 11811 DWB_SEGMENTS_64 = 0x00000006, 11812 DWB_SEGMENTS_128 = 0x00000007, 11813 } DWB_LUT_NUM_SEG; 11814 11815 /* 11816 * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum 11817 */ 11818 11819 typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM { 11820 DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0x00000000, 11821 DWB_OGAM_LUT_CONFIG_MODE_SAME = 0x00000001, 11822 } DWB_OGAM_LUT_CONFIG_MODE_ENUM; 11823 11824 /* 11825 * DWB_OGAM_LUT_HOST_SEL_ENUM enum 11826 */ 11827 11828 typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM { 11829 DWB_OGAM_LUT_HOST_SEL_RAMA = 0x00000000, 11830 DWB_OGAM_LUT_HOST_SEL_RAMB = 0x00000001, 11831 } DWB_OGAM_LUT_HOST_SEL_ENUM; 11832 11833 /* 11834 * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum 11835 */ 11836 11837 typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM { 11838 DWB_OGAM_LUT_READ_COLOR_SEL_B = 0x00000000, 11839 DWB_OGAM_LUT_READ_COLOR_SEL_G = 0x00000001, 11840 DWB_OGAM_LUT_READ_COLOR_SEL_R = 0x00000002, 11841 DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 0x00000003, 11842 } DWB_OGAM_LUT_READ_COLOR_SEL_ENUM; 11843 11844 /* 11845 * DWB_OGAM_LUT_READ_DBG_ENUM enum 11846 */ 11847 11848 typedef enum DWB_OGAM_LUT_READ_DBG_ENUM { 11849 DWB_OGAM_LUT_READ_DBG_DISABLE = 0x00000000, 11850 DWB_OGAM_LUT_READ_DBG_ENABLE = 0x00000001, 11851 } DWB_OGAM_LUT_READ_DBG_ENUM; 11852 11853 /* 11854 * DWB_OGAM_MODE_ENUM enum 11855 */ 11856 11857 typedef enum DWB_OGAM_MODE_ENUM { 11858 DWB_OGAM_MODE_BYPASS = 0x00000000, 11859 DWB_OGAM_MODE_RESERVED = 0x00000001, 11860 DWB_OGAM_MODE_RAM_LUT_ENABLED = 0x00000002, 11861 } DWB_OGAM_MODE_ENUM; 11862 11863 /* 11864 * DWB_OGAM_PWL_DISABLE_ENUM enum 11865 */ 11866 11867 typedef enum DWB_OGAM_PWL_DISABLE_ENUM { 11868 DWB_OGAM_PWL_DISABLE_FALSE = 0x00000000, 11869 DWB_OGAM_PWL_DISABLE_TRUE = 0x00000001, 11870 } DWB_OGAM_PWL_DISABLE_ENUM; 11871 11872 /* 11873 * DWB_OGAM_SELECT_ENUM enum 11874 */ 11875 11876 typedef enum DWB_OGAM_SELECT_ENUM { 11877 DWB_OGAM_SELECT_A = 0x00000000, 11878 DWB_OGAM_SELECT_B = 0x00000001, 11879 } DWB_OGAM_SELECT_ENUM; 11880 11881 /******************************************************* 11882 * RDPCSTX Enums 11883 *******************************************************/ 11884 11885 /* 11886 * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum 11887 */ 11888 11889 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN { 11890 RDPCS_EXT_REFCLK_DISABLE = 0x00000000, 11891 RDPCS_EXT_REFCLK_ENABLE = 0x00000001, 11892 } RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN; 11893 11894 /* 11895 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON enum 11896 */ 11897 11898 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON { 11899 RDPCS_OCLACLK_CLOCK_OFF = 0x00000000, 11900 RDPCS_OCLACLK_CLOCK_ON = 0x00000001, 11901 } RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON; 11902 11903 /* 11904 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN enum 11905 */ 11906 11907 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN { 11908 RDPCS_OCLACLK_DISABLE = 0x00000000, 11909 RDPCS_OCLACLK_ENABLE = 0x00000001, 11910 } RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN; 11911 11912 /* 11913 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS enum 11914 */ 11915 11916 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS { 11917 RDPCS_OCLACLK_GATE_ENABLE = 0x00000000, 11918 RDPCS_OCLACLK_GATE_DISABLE = 0x00000001, 11919 } RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS; 11920 11921 /* 11922 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum 11923 */ 11924 11925 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON { 11926 RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000, 11927 RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001, 11928 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON; 11929 11930 /* 11931 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum 11932 */ 11933 11934 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN { 11935 RDPCS_SRAMCLK_DISABLE = 0x00000000, 11936 RDPCS_SRAMCLK_ENABLE = 0x00000001, 11937 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN; 11938 11939 /* 11940 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum 11941 */ 11942 11943 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS { 11944 RDPCS_SRAMCLK_GATE_ENABLE = 0x00000000, 11945 RDPCS_SRAMCLK_GATE_DISABLE = 0x00000001, 11946 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS; 11947 11948 /* 11949 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum 11950 */ 11951 11952 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS { 11953 RDPCS_SRAMCLK_NOT_PASS = 0x00000000, 11954 RDPCS_SRAMCLK_PASS = 0x00000001, 11955 } RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS; 11956 11957 /* 11958 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON enum 11959 */ 11960 11961 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON { 11962 RDPCS_TX_CLK_CLOCK_OFF = 0x00000000, 11963 RDPCS_TX_CLK_CLOCK_ON = 0x00000001, 11964 } RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON; 11965 11966 /* 11967 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN enum 11968 */ 11969 11970 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN { 11971 RDPCS_TX_CLK_DISABLE = 0x00000000, 11972 RDPCS_TX_CLK_ENABLE = 0x00000001, 11973 } RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN; 11974 11975 /* 11976 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS enum 11977 */ 11978 11979 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS { 11980 RDPCS_TX_CLK_GATE_ENABLE = 0x00000000, 11981 RDPCS_TX_CLK_GATE_DISABLE = 0x00000001, 11982 } RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS; 11983 11984 /* 11985 * RDPCSTX_CLOCK_CNTL_TX_CLK_EN enum 11986 */ 11987 11988 typedef enum RDPCSTX_CLOCK_CNTL_TX_CLK_EN { 11989 RDPCS_EXT_REFCLK_EN_DISABLE = 0x00000000, 11990 RDPCS_EXT_REFCLK_EN_ENABLE = 0x00000001, 11991 } RDPCSTX_CLOCK_CNTL_TX_CLK_EN; 11992 11993 /* 11994 * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum 11995 */ 11996 11997 typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET { 11998 RDPCS_CBUS_SOFT_RESET_DISABLE = 0x00000000, 11999 RDPCS_CBUS_SOFT_RESET_ENABLE = 0x00000001, 12000 } RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET; 12001 12002 /* 12003 * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum 12004 */ 12005 12006 typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET { 12007 RDPCS_SRAM_SRAM_RESET_DISABLE = 0x00000000, 12008 RDPCS_SRAM_SRAM_RESET_ENABLE = 0x00000001, 12009 } RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET; 12010 12011 /* 12012 * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum 12013 */ 12014 12015 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN { 12016 RDPCS_TX_FIFO_DISABLE = 0x00000000, 12017 RDPCS_TX_FIFO_ENABLE = 0x00000001, 12018 } RDPCSTX_CNTL_RDPCS_TX_FIFO_EN; 12019 12020 /* 12021 * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum 12022 */ 12023 12024 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN { 12025 RDPCS_TX_FIFO_LANE_DISABLE = 0x00000000, 12026 RDPCS_TX_FIFO_LANE_ENABLE = 0x00000001, 12027 } RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN; 12028 12029 /* 12030 * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum 12031 */ 12032 12033 typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET { 12034 RDPCS_TX_SOFT_RESET_DISABLE = 0x00000000, 12035 RDPCS_TX_SOFT_RESET_ENABLE = 0x00000001, 12036 } RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET; 12037 12038 /* 12039 * RDPCSTX_FIFO_EMPTY enum 12040 */ 12041 12042 typedef enum RDPCSTX_FIFO_EMPTY { 12043 RDPCSTX_FIFO_NOT_EMPTY = 0x00000000, 12044 RDPCSTX_FIFO_IS_EMPTY = 0x00000001, 12045 } RDPCSTX_FIFO_EMPTY; 12046 12047 /* 12048 * RDPCSTX_FIFO_FULL enum 12049 */ 12050 12051 typedef enum RDPCSTX_FIFO_FULL { 12052 RDPCSTX_FIFO_NOT_FULL = 0x00000000, 12053 RDPCSTX_FIFO_IS_FULL = 0x00000001, 12054 } RDPCSTX_FIFO_FULL; 12055 12056 /* 12057 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum 12058 */ 12059 12060 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE { 12061 RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0x00000000, 12062 RDPCS_DPALT_4LANE_TOGGLE_4LANE = 0x00000001, 12063 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE; 12064 12065 /* 12066 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum 12067 */ 12068 12069 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK { 12070 RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000, 12071 RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001, 12072 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK; 12073 12074 /* 12075 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum 12076 */ 12077 12078 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE { 12079 RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000, 12080 RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001, 12081 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE; 12082 12083 /* 12084 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum 12085 */ 12086 12087 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK { 12088 RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000, 12089 RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001, 12090 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK; 12091 12092 /* 12093 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum 12094 */ 12095 12096 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK { 12097 RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000, 12098 RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001, 12099 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK; 12100 12101 /* 12102 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum 12103 */ 12104 12105 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK { 12106 RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0x00000000, 12107 RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 0x00000001, 12108 } RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK; 12109 12110 /* 12111 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum 12112 */ 12113 12114 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL { 12115 RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0x00000000, 12116 RDPCS_PHY_CR_MUX_SEL_FOR_DC = 0x00000001, 12117 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL; 12118 12119 /* 12120 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum 12121 */ 12122 12123 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL { 12124 RDPCS_PHY_CR_PARA_SEL_JTAG = 0x00000000, 12125 RDPCS_PHY_CR_PARA_SEL_CR = 0x00000001, 12126 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL; 12127 12128 /* 12129 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum 12130 */ 12131 12132 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE { 12133 RDPCS_PHY_REF_RANGE_0 = 0x00000000, 12134 RDPCS_PHY_REF_RANGE_1 = 0x00000001, 12135 RDPCS_PHY_REF_RANGE_2 = 0x00000002, 12136 RDPCS_PHY_REF_RANGE_3 = 0x00000003, 12137 RDPCS_PHY_REF_RANGE_4 = 0x00000004, 12138 RDPCS_PHY_REF_RANGE_5 = 0x00000005, 12139 RDPCS_PHY_REF_RANGE_6 = 0x00000006, 12140 RDPCS_PHY_REF_RANGE_7 = 0x00000007, 12141 } RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE; 12142 12143 /* 12144 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum 12145 */ 12146 12147 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE { 12148 RDPCS_SRAM_EXT_LD_NOT_DONE = 0x00000000, 12149 RDPCS_SRAM_EXT_LD_DONE = 0x00000001, 12150 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE; 12151 12152 /* 12153 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum 12154 */ 12155 12156 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE { 12157 RDPCS_SRAM_INIT_NOT_DONE = 0x00000000, 12158 RDPCS_SRAM_INIT_DONE = 0x00000001, 12159 } RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE; 12160 12161 /* 12162 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum 12163 */ 12164 12165 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV { 12166 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000, 12167 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001, 12168 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002, 12169 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003, 12170 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004, 12171 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV; 12172 12173 /* 12174 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum 12175 */ 12176 12177 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV { 12178 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000, 12179 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001, 12180 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002, 12181 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003, 12182 } RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV; 12183 12184 /* 12185 * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum 12186 */ 12187 12188 typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV { 12189 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000, 12190 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001, 12191 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002, 12192 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003, 12193 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004, 12194 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005, 12195 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006, 12196 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007, 12197 } RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV; 12198 12199 /* 12200 * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum 12201 */ 12202 12203 typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL { 12204 RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0x00000000, 12205 RDPCS_PHY_DP_TX_TERM_CTRL_52 = 0x00000001, 12206 RDPCS_PHY_DP_TX_TERM_CTRL_50 = 0x00000002, 12207 RDPCS_PHY_DP_TX_TERM_CTRL_48 = 0x00000003, 12208 RDPCS_PHY_DP_TX_TERM_CTRL_46 = 0x00000004, 12209 RDPCS_PHY_DP_TX_TERM_CTRL_44 = 0x00000005, 12210 RDPCS_PHY_DP_TX_TERM_CTRL_42 = 0x00000006, 12211 RDPCS_PHY_DP_TX_TERM_CTRL_40 = 0x00000007, 12212 } RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL; 12213 12214 /* 12215 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum 12216 */ 12217 12218 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT { 12219 RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000, 12220 RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001, 12221 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT; 12222 12223 /* 12224 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum 12225 */ 12226 12227 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE { 12228 RDPCS_PHY_DP_TX_RATE = 0x00000000, 12229 RDPCS_PHY_DP_TX_RATE_DIV2 = 0x00000001, 12230 RDPCS_PHY_DP_TX_RATE_DIV4 = 0x00000002, 12231 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE; 12232 12233 /* 12234 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum 12235 */ 12236 12237 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH { 12238 RDPCS_PHY_DP_TX_WIDTH_8 = 0x00000000, 12239 RDPCS_PHY_DP_TX_WIDTH_10 = 0x00000001, 12240 RDPCS_PHY_DP_TX_WIDTH_16 = 0x00000002, 12241 RDPCS_PHY_DP_TX_WIDTH_20 = 0x00000003, 12242 } RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH; 12243 12244 /* 12245 * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum 12246 */ 12247 12248 typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE { 12249 RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000, 12250 RRDPCS_PHY_DP_TX_PSTATE_HOLD = 0x00000001, 12251 RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002, 12252 RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003, 12253 } RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE; 12254 12255 /* 12256 * RDPCSTX_PHY_REF_ALT_CLK_EN enum 12257 */ 12258 12259 typedef enum RDPCSTX_PHY_REF_ALT_CLK_EN { 12260 RDPCS_PHY_REF_ALT_CLK_DISABLE = 0x00000000, 12261 RDPCS_PHY_REF_ALT_CLK_ENABLE = 0x00000001, 12262 } RDPCSTX_PHY_REF_ALT_CLK_EN; 12263 12264 /* 12265 * RDPCSTX_TX_FIFO_DISABLED_MASK enum 12266 */ 12267 12268 typedef enum RDPCSTX_TX_FIFO_DISABLED_MASK { 12269 RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE = 0x00000000, 12270 RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE = 0x00000001, 12271 } RDPCSTX_TX_FIFO_DISABLED_MASK; 12272 12273 /* 12274 * RDPCS_DBG_OCLA_SEL enum 12275 */ 12276 12277 typedef enum RDPCS_DBG_OCLA_SEL { 12278 RDPCS_DBG_OCLA_SEL_MON_OUT_7_0 = 0x00000000, 12279 RDPCS_DBG_OCLA_SEL_MON_OUT_15_8 = 0x00000001, 12280 RDPCS_DBG_OCLA_SEL_MON_OUT_23_16 = 0x00000002, 12281 RDPCS_DBG_OCLA_SEL_MON_OUT_31_24 = 0x00000003, 12282 RDPCS_DBG_OCLA_SEL_MON_OUT_39_32 = 0x00000004, 12283 RDPCS_DBG_OCLA_SEL_MON_OUT_47_40 = 0x00000005, 12284 RDPCS_DBG_OCLA_SEL_MON_OUT_55_48 = 0x00000006, 12285 RDPCS_DBG_OCLA_SEL_MON_OUT_63_56 = 0x00000007, 12286 } RDPCS_DBG_OCLA_SEL; 12287 12288 /* 12289 * RDPCS_TEST_CLK_SEL enum 12290 */ 12291 12292 typedef enum RDPCS_TEST_CLK_SEL { 12293 RDPCS_TEST_CLK_SEL_NONE = 0x00000000, 12294 RDPCS_TEST_CLK_SEL_CFGCLK = 0x00000001, 12295 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002, 12296 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003, 12297 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004, 12298 RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005, 12299 RDPCS_TEST_CLK_SEL_SRAMCLK = 0x00000006, 12300 RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007, 12301 RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008, 12302 RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009, 12303 RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a, 12304 RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b, 12305 RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c, 12306 RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d, 12307 RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e, 12308 RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f, 12309 RDPCS_TEST_CLK_SEL_dtb_out0 = 0x00000010, 12310 RDPCS_TEST_CLK_SEL_dtb_out1 = 0x00000011, 12311 } RDPCS_TEST_CLK_SEL; 12312 12313 /* 12314 * RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB enum 12315 */ 12316 12317 typedef enum RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB { 12318 RDPCS_LANE_PACK_FROM_MSB_DISABLE = 0x00000000, 12319 RDPCS_LANE_PACK_FROM_MSB_ENABLE = 0x00000001, 12320 } RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB; 12321 12322 /* 12323 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum 12324 */ 12325 12326 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE { 12327 RDPCS_MEM_PWR_NO_FORCE = 0x00000000, 12328 RDPCS_MEM_PWR_LIGHT_SLEEP = 0x00000001, 12329 RDPCS_MEM_PWR_DEEP_SLEEP = 0x00000002, 12330 RDPCS_MEM_PWR_SHUT_DOWN = 0x00000003, 12331 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE; 12332 12333 /* 12334 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum 12335 */ 12336 12337 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE { 12338 RDPCS_MEM_PWR_PWR_STATE_ON = 0x00000000, 12339 RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001, 12340 RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002, 12341 RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003, 12342 } RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE; 12343 12344 /* 12345 * RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum 12346 */ 12347 12348 typedef enum RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK { 12349 RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000, 12350 RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE = 0x00000001, 12351 } RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK; 12352 12353 /******************************************************* 12354 * RLC Enums 12355 *******************************************************/ 12356 12357 /* 12358 * RLC_DOORBELL_MODE enum 12359 */ 12360 12361 typedef enum RLC_DOORBELL_MODE { 12362 RLC_DOORBELL_MODE_DISABLE = 0x00000000, 12363 RLC_DOORBELL_MODE_ENABLE = 0x00000001, 12364 RLC_DOORBELL_MODE_ENABLE_PF = 0x00000002, 12365 RLC_DOORBELL_MODE_ENABLE_PF_VF = 0x00000003, 12366 } RLC_DOORBELL_MODE; 12367 12368 /* 12369 * RLC_PERFCOUNTER_SEL enum 12370 */ 12371 12372 typedef enum RLC_PERFCOUNTER_SEL { 12373 RLC_PERF_SEL_POWER_FEATURE_0 = 0x00000000, 12374 RLC_PERF_SEL_POWER_FEATURE_1 = 0x00000001, 12375 RLC_PERF_SEL_CP_INTERRUPT = 0x00000002, 12376 RLC_PERF_SEL_GRBM_INTERRUPT = 0x00000003, 12377 RLC_PERF_SEL_SPM_INTERRUPT = 0x00000004, 12378 RLC_PERF_SEL_IH_INTERRUPT = 0x00000005, 12379 RLC_PERF_SEL_SERDES_COMMAND_WRITE = 0x00000006, 12380 } RLC_PERFCOUNTER_SEL; 12381 12382 /* 12383 * RLC_PERFMON_STATE enum 12384 */ 12385 12386 typedef enum RLC_PERFMON_STATE { 12387 RLC_PERFMON_STATE_RESET = 0x00000000, 12388 RLC_PERFMON_STATE_ENABLE = 0x00000001, 12389 RLC_PERFMON_STATE_DISABLE = 0x00000002, 12390 RLC_PERFMON_STATE_RESERVED_3 = 0x00000003, 12391 RLC_PERFMON_STATE_RESERVED_4 = 0x00000004, 12392 RLC_PERFMON_STATE_RESERVED_5 = 0x00000005, 12393 RLC_PERFMON_STATE_RESERVED_6 = 0x00000006, 12394 RLC_PERFMON_STATE_ROLLOVER = 0x00000007, 12395 } RLC_PERFMON_STATE; 12396 12397 /* 12398 * RSPM_CMD enum 12399 */ 12400 12401 typedef enum RSPM_CMD { 12402 RSPM_CMD_INVALID = 0x00000000, 12403 RSPM_CMD_IDLE = 0x00000001, 12404 RSPM_CMD_CALIBRATE = 0x00000002, 12405 RSPM_CMD_SPM_RESET = 0x00000003, 12406 RSPM_CMD_SPM_START = 0x00000004, 12407 RSPM_CMD_SPM_STOP = 0x00000005, 12408 RSPM_CMD_PERF_RESET = 0x00000006, 12409 RSPM_CMD_PERF_SAMPLE = 0x00000007, 12410 RSPM_CMD_PROF_START = 0x00000008, 12411 RSPM_CMD_PROF_STOP = 0x00000009, 12412 RSPM_CMD_FORCE_SAMPLE = 0x0000000a, 12413 } RSPM_CMD; 12414 12415 /******************************************************* 12416 * COMP Enums 12417 *******************************************************/ 12418 12419 /* 12420 * CSCNTL_TYPE enum 12421 */ 12422 12423 typedef enum CSCNTL_TYPE { 12424 CSCNTL_TYPE_TG = 0x00000000, 12425 CSCNTL_TYPE_STATE = 0x00000001, 12426 CSCNTL_TYPE_EVENT = 0x00000002, 12427 CSCNTL_TYPE_PRIVATE = 0x00000003, 12428 } CSCNTL_TYPE; 12429 12430 /* 12431 * CSDATA_TYPE enum 12432 */ 12433 12434 typedef enum CSDATA_TYPE { 12435 CSDATA_TYPE_TG = 0x00000000, 12436 CSDATA_TYPE_STATE = 0x00000001, 12437 CSDATA_TYPE_EVENT = 0x00000002, 12438 CSDATA_TYPE_PRIVATE = 0x00000003, 12439 } CSDATA_TYPE; 12440 12441 /* 12442 * CSDATA_TYPE_WIDTH value 12443 */ 12444 12445 #define CSDATA_TYPE_WIDTH 0x00000002 12446 12447 /* 12448 * CSDATA_ADDR_WIDTH value 12449 */ 12450 12451 #define CSDATA_ADDR_WIDTH 0x00000007 12452 12453 /* 12454 * CSDATA_DATA_WIDTH value 12455 */ 12456 12457 #define CSDATA_DATA_WIDTH 0x00000020 12458 12459 /* 12460 * CSCNTL_TYPE_WIDTH value 12461 */ 12462 12463 #define CSCNTL_TYPE_WIDTH 0x00000002 12464 12465 /* 12466 * CSCNTL_ADDR_WIDTH value 12467 */ 12468 12469 #define CSCNTL_ADDR_WIDTH 0x00000007 12470 12471 /* 12472 * CSCNTL_DATA_WIDTH value 12473 */ 12474 12475 #define CSCNTL_DATA_WIDTH 0x00000020 12476 12477 /******************************************************* 12478 * GE Enums 12479 *******************************************************/ 12480 12481 /* 12482 * GE1_PERFCOUNT_SELECT enum 12483 */ 12484 12485 typedef enum GE1_PERFCOUNT_SELECT { 12486 ge1_assembler_busy = 0x00000000, 12487 ge1_assembler_stalled = 0x00000001, 12488 ge1_dma_busy = 0x00000002, 12489 ge1_dma_lat_bin_0 = 0x00000003, 12490 ge1_dma_lat_bin_1 = 0x00000004, 12491 ge1_dma_lat_bin_2 = 0x00000005, 12492 ge1_dma_lat_bin_3 = 0x00000006, 12493 ge1_dma_lat_bin_4 = 0x00000007, 12494 ge1_dma_lat_bin_5 = 0x00000008, 12495 ge1_dma_lat_bin_6 = 0x00000009, 12496 ge1_dma_lat_bin_7 = 0x0000000a, 12497 ge1_dma_return_cl0 = 0x0000000b, 12498 ge1_dma_return_cl1 = 0x0000000c, 12499 ge1_dma_utcl1_consecutive_retry_event = 0x0000000d, 12500 ge1_dma_utcl1_request_event = 0x0000000e, 12501 ge1_dma_utcl1_retry_event = 0x0000000f, 12502 ge1_dma_utcl1_stall_event = 0x00000010, 12503 ge1_dma_utcl1_stall_utcl2_event = 0x00000011, 12504 ge1_dma_utcl1_translation_hit_event = 0x00000012, 12505 ge1_dma_utcl1_translation_miss_event = 0x00000013, 12506 ge1_assembler_dma_starved = 0x00000014, 12507 ge1_rbiu_di_fifo_stalled_p0 = 0x00000015, 12508 ge1_rbiu_di_fifo_starved_p0 = 0x00000016, 12509 ge1_rbiu_dr_fifo_stalled_p0 = 0x00000017, 12510 ge1_rbiu_dr_fifo_starved_p0 = 0x00000018, 12511 ge1_sclk_reg_vld = 0x00000019, 12512 ge1_stat_busy = 0x0000001a, 12513 ge1_stat_no_dma_busy = 0x0000001b, 12514 ge1_pipe0_to_pipe1 = 0x0000001c, 12515 ge1_pipe1_to_pipe0 = 0x0000001d, 12516 ge1_dma_return_size_cl0 = 0x0000001e, 12517 ge1_dma_return_size_cl1 = 0x0000001f, 12518 ge1_small_draws_one_instance = 0x00000020, 12519 ge1_sclk_input_vld = 0x00000021, 12520 ge1_prim_group_limit_hit = 0x00000022, 12521 ge1_unopt_multi_instance_draws = 0x00000023, 12522 ge1_rbiu_di_fifo_stalled_p1 = 0x00000024, 12523 ge1_rbiu_di_fifo_starved_p1 = 0x00000025, 12524 ge1_rbiu_dr_fifo_stalled_p1 = 0x00000026, 12525 ge1_rbiu_dr_fifo_starved_p1 = 0x00000027, 12526 } GE1_PERFCOUNT_SELECT; 12527 12528 /* 12529 * GE2_DIST_PERFCOUNT_SELECT enum 12530 */ 12531 12532 typedef enum GE2_DIST_PERFCOUNT_SELECT { 12533 ge_dist_hs_done = 0x00000000, 12534 ge_dist_hs_done_latency_se0 = 0x00000001, 12535 ge_dist_hs_done_latency_se1 = 0x00000002, 12536 ge_dist_hs_done_latency_se2 = 0x00000003, 12537 ge_dist_hs_done_latency_se3 = 0x00000004, 12538 ge_dist_hs_done_latency_se4 = 0x00000005, 12539 ge_dist_hs_done_latency_se5 = 0x00000006, 12540 ge_dist_hs_done_latency_se6 = 0x00000007, 12541 ge_dist_hs_done_latency_se7 = 0x00000008, 12542 ge_dist_inside_tf_bin_0 = 0x00000009, 12543 ge_dist_inside_tf_bin_1 = 0x0000000a, 12544 ge_dist_inside_tf_bin_2 = 0x0000000b, 12545 ge_dist_inside_tf_bin_3 = 0x0000000c, 12546 ge_dist_inside_tf_bin_4 = 0x0000000d, 12547 ge_dist_inside_tf_bin_5 = 0x0000000e, 12548 ge_dist_inside_tf_bin_6 = 0x0000000f, 12549 ge_dist_inside_tf_bin_7 = 0x00000010, 12550 ge_dist_inside_tf_bin_8 = 0x00000011, 12551 ge_dist_null_patch = 0x00000012, 12552 ge_dist_sclk_core_vld = 0x00000013, 12553 ge_dist_sclk_wd_te11_vld = 0x00000014, 12554 ge_dist_tfreq_lat_bin_0 = 0x00000015, 12555 ge_dist_tfreq_lat_bin_1 = 0x00000016, 12556 ge_dist_tfreq_lat_bin_2 = 0x00000017, 12557 ge_dist_tfreq_lat_bin_3 = 0x00000018, 12558 ge_dist_tfreq_lat_bin_4 = 0x00000019, 12559 ge_dist_tfreq_lat_bin_5 = 0x0000001a, 12560 ge_dist_tfreq_lat_bin_6 = 0x0000001b, 12561 ge_dist_tfreq_lat_bin_7 = 0x0000001c, 12562 ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d, 12563 ge_dist_tfreq_utcl1_request_event = 0x0000001e, 12564 ge_dist_tfreq_utcl1_retry_event = 0x0000001f, 12565 ge_dist_tfreq_utcl1_stall_event = 0x00000020, 12566 ge_dist_tfreq_utcl1_stall_utcl2_event = 0x00000021, 12567 ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022, 12568 ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023, 12569 ge_dist_pc_feorder_fifo_full = 0x00000024, 12570 ge_dist_pc_ge_manager_busy = 0x00000025, 12571 ge_dist_sclk_input_vld = 0x00000026, 12572 ge_dist_wd_te11_busy = 0x00000027, 12573 ge_dist_te11_starved = 0x00000028, 12574 ge_dist_switch_mode_stall = 0x00000029, 12575 ge_all_tf_eq = 0x0000002a, 12576 ge_all_tf2 = 0x0000002b, 12577 ge_all_tf3 = 0x0000002c, 12578 ge_all_tf4 = 0x0000002d, 12579 ge_all_tf5 = 0x0000002e, 12580 ge_all_tf6 = 0x0000002f, 12581 ge_se0_te11_starved_on_hs_done = 0x00000030, 12582 ge_se1_te11_starved_on_hs_done = 0x00000031, 12583 ge_se2_te11_starved_on_hs_done = 0x00000032, 12584 ge_se3_te11_starved_on_hs_done = 0x00000033, 12585 ge_se4_te11_starved_on_hs_done = 0x00000034, 12586 ge_se5_te11_starved_on_hs_done = 0x00000035, 12587 ge_se6_te11_starved_on_hs_done = 0x00000036, 12588 ge_se7_te11_starved_on_hs_done = 0x00000037, 12589 ge_dist_op_fifo_full_starve = 0x00000038, 12590 ge_dist_hs_done_se0 = 0x00000039, 12591 ge_dist_hs_done_se1 = 0x0000003a, 12592 ge_dist_hs_done_se2 = 0x0000003b, 12593 ge_dist_hs_done_se3 = 0x0000003c, 12594 ge_dist_hs_done_se4 = 0x0000003d, 12595 ge_dist_hs_done_se5 = 0x0000003e, 12596 ge_dist_hs_done_se6 = 0x0000003f, 12597 ge_dist_hs_done_se7 = 0x00000040, 12598 ge_dist_hs_done_latency = 0x00000041, 12599 ge_dist_distributer_busy = 0x00000042, 12600 ge_tf_ret_data_stalling_hs_done = 0x00000043, 12601 ge_num_of_no_dist_patches = 0x00000044, 12602 ge_num_of_donut_dist_patches = 0x00000045, 12603 ge_num_of_patch_dist_patches = 0x00000046, 12604 ge_num_of_se_switches_due_to_patch_accum = 0x00000047, 12605 ge_num_of_se_switches_due_to_donut = 0x00000048, 12606 ge_num_of_se_switches_due_to_trap = 0x00000049, 12607 ge_num_of_hs_dealloc_events = 0x0000004a, 12608 ge_agm_gcr_req = 0x0000004b, 12609 ge_agm_gcr_tag_stall = 0x0000004c, 12610 ge_agm_gcr_crd_stall = 0x0000004d, 12611 ge_agm_gcr_stall = 0x0000004e, 12612 ge_agm_gcr_latency = 0x0000004f, 12613 ge_distclk_vld = 0x00000050, 12614 ge_dist_indx_fifos_full_and_empty = 0x00000051, 12615 ge_hs_done_all_tf0_se0 = 0x00000052, 12616 ge_hs_done_all_tf0_se1 = 0x00000053, 12617 ge_hs_done_all_tf0_se2 = 0x00000054, 12618 ge_hs_done_all_tf0_se3 = 0x00000055, 12619 ge_hs_done_all_tf0_se4 = 0x00000056, 12620 ge_hs_done_all_tf0_se5 = 0x00000057, 12621 ge_hs_done_all_tf0_se6 = 0x00000058, 12622 ge_hs_done_all_tf0_se7 = 0x00000059, 12623 ge_hs_done_all_tf1_se0 = 0x0000005a, 12624 ge_hs_done_all_tf1_se1 = 0x0000005b, 12625 ge_hs_done_all_tf1_se2 = 0x0000005c, 12626 ge_hs_done_all_tf1_se3 = 0x0000005d, 12627 ge_hs_done_all_tf1_se4 = 0x0000005e, 12628 ge_hs_done_all_tf1_se5 = 0x0000005f, 12629 ge_hs_done_all_tf1_se6 = 0x00000060, 12630 ge_hs_done_all_tf1_se7 = 0x00000061, 12631 ge_agm_gcr_req_outstanding = 0x00000062, 12632 ge_agm_gcr_req_amount = 0x00000063, 12633 ge_agm_gcr_combine = 0x00000064, 12634 } GE2_DIST_PERFCOUNT_SELECT; 12635 12636 /* 12637 * GE2_SE_PERFCOUNT_SELECT enum 12638 */ 12639 12640 typedef enum GE2_SE_PERFCOUNT_SELECT { 12641 ge_se_ds_prims = 0x00000000, 12642 ge_se_es_thread_groups = 0x00000001, 12643 ge_se_esvert_stalled_gsprim = 0x00000002, 12644 ge_se_hs_tfm_stall = 0x00000003, 12645 ge_se_hs_tgs_active_high_water_mark = 0x00000004, 12646 ge_se_hs_thread_groups = 0x00000005, 12647 ge_se_reused_es_indices = 0x00000006, 12648 ge_se_sclk_ngg_vld = 0x00000007, 12649 ge_se_sclk_te11_vld = 0x00000008, 12650 ge_se_spi_esvert_eov = 0x00000009, 12651 ge_se_spi_esvert_stalled = 0x0000000a, 12652 ge_se_spi_esvert_starved_busy = 0x0000000b, 12653 ge_se_spi_esvert_valid = 0x0000000c, 12654 ge_se_spi_gsprim_cont = 0x0000000d, 12655 ge_se_spi_gsprim_eov = 0x0000000e, 12656 ge_se_spi_gsprim_stalled = 0x0000000f, 12657 ge_se_spi_gsprim_starved_busy = 0x00000010, 12658 ge_se_spi_gsprim_valid = 0x00000011, 12659 ge_se_spi_gssubgrp_is_event = 0x00000012, 12660 ge_se_spi_gssubgrp_send = 0x00000013, 12661 ge_se_spi_hsvert_eov = 0x00000014, 12662 ge_se_spi_hsvert_stalled = 0x00000015, 12663 ge_se_spi_hsvert_starved_busy = 0x00000016, 12664 ge_se_spi_hsvert_valid = 0x00000017, 12665 ge_se_spi_hsgrp_is_event = 0x00000018, 12666 ge_se_spi_hsgrp_send = 0x00000019, 12667 ge_se_spi_lsvert_eov = 0x0000001a, 12668 ge_se_spi_lsvert_stalled = 0x0000001b, 12669 ge_se_spi_lsvert_starved_busy = 0x0000001c, 12670 ge_se_spi_lsvert_valid = 0x0000001d, 12671 ge_se_spi_hsvert_fifo_full_stall = 0x0000001e, 12672 ge_se_spi_tgrp_fifo_stall = 0x0000001f, 12673 ge_spi_hsgrp_spi_stall = 0x00000020, 12674 ge_se_spi_gssubgrp_event_window_active = 0x00000021, 12675 ge_se_hs_input_stall = 0x00000022, 12676 ge_se_sending_vert_or_prim = 0x00000023, 12677 ge_se_sclk_input_vld = 0x00000024, 12678 ge_spi_lswave_fifo_full_stall = 0x00000025, 12679 ge_spi_hswave_fifo_full_stall = 0x00000026, 12680 ge_hs_tif_stall = 0x00000027, 12681 ge_csb_spi_bp = 0x00000028, 12682 ge_ngg_starving_for_wave_id = 0x00000029, 12683 ge_pa0_csb_eop = 0x0000002a, 12684 ge_ngg_starved_idle = 0x0000002b, 12685 ge_gsprim_send = 0x0000002c, 12686 ge_esvert_send = 0x0000002d, 12687 ge_ngg_starved_after_work = 0x0000002e, 12688 ge_ngg_subgrp_fifo_stall = 0x0000002f, 12689 ge_ngg_ord_id_req_stall = 0x00000030, 12690 ge_ngg_indx_bus_stall = 0x00000031, 12691 ge_hs_stall_tfmm_fifo_full = 0x00000032, 12692 ge_gs_issue_rtr_stalled = 0x00000033, 12693 ge_gsprim_stalled_esvert = 0x00000034, 12694 ge_gsthread_stalled = 0x00000035, 12695 ge_ngg_attr_grp_alloc = 0x00000036, 12696 ge_ngg_attr_discard_alloc = 0x00000037, 12697 ge_ngg_pc_space_not_avail = 0x00000038, 12698 ge_ngg_agm_req_stall = 0x00000039, 12699 ge_ngg_spi_esvert_partial_eov = 0x0000003a, 12700 ge_ngg_spi_gsprim_partial_eov = 0x0000003b, 12701 ge_spi_gsgrp_valid = 0x0000003c, 12702 ge_ngg_attr_grp_latency = 0x0000003d, 12703 ge_ngg_reuse_prim_limit_hit = 0x0000003e, 12704 ge_ngg_reuse_vert_limit_hit = 0x0000003f, 12705 ge_te11_con_stall = 0x00000040, 12706 ge_te11_compactor_starved = 0x00000041, 12707 ge_ngg_stall_tess_off_tess_on = 0x00000042, 12708 ge_ngg_stall_tess_on_tess_off = 0x00000043, 12709 ge_merged_lses_vert_stalled = 0x00000044, 12710 ge_merged_hsgs_vert_stalled = 0x00000045, 12711 ge_merged_hsgs_grp_stalled = 0x00000046, 12712 ge_merge_lses_fifo_blocked = 0x00000047, 12713 ge_merge_hsgs_fifo_blocked = 0x00000048, 12714 ge_merge_lses_vert_switch = 0x00000049, 12715 ge_merge_hsgs_vert_switch = 0x0000004a, 12716 ge_merge_hsgs_grp_switch = 0x0000004b, 12717 ge_merge_gsgrp_rdy_pending_verts = 0x0000004c, 12718 ge_merge_hsgrp_rdy_pending_verts = 0x0000004d, 12719 ge_se_ds_cache_hits = 0x0000004e, 12720 ge_se_api_vs_verts = 0x0000004f, 12721 ge_se_api_ds_verts = 0x00000050, 12722 ge_se_combined_busy = 0x00000051, 12723 ge_spi_lsvert_send = 0x00000052, 12724 ge_spi_hsvert_send = 0x00000053, 12725 ge_ngg_attr_grp_wasted = 0x00000054, 12726 ge_spi_gssubgrp_stalled = 0x00000055, 12727 ge_ngg_attr_null_dealloc = 0x00000056, 12728 ge_ngg_busy_base = 0x00000057, 12729 } GE2_SE_PERFCOUNT_SELECT; 12730 12731 /* 12732 * VGT_DETECT_ONE enum 12733 */ 12734 12735 typedef enum VGT_DETECT_ONE { 12736 ENABLE_TF1_OPT = 0x00000000, 12737 DISABLE_TF1_OPT = 0x00000001, 12738 } VGT_DETECT_ONE; 12739 12740 /* 12741 * VGT_DETECT_ZERO enum 12742 */ 12743 12744 typedef enum VGT_DETECT_ZERO { 12745 ENABLE_TF0_OPT = 0x00000000, 12746 DISABLE_TF0_OPT = 0x00000001, 12747 } VGT_DETECT_ZERO; 12748 12749 /* 12750 * VGT_DIST_MODE enum 12751 */ 12752 12753 typedef enum VGT_DIST_MODE { 12754 NO_DIST = 0x00000000, 12755 PATCHES = 0x00000001, 12756 DONUTS = 0x00000002, 12757 TRAPEZOIDS = 0x00000003, 12758 } VGT_DIST_MODE; 12759 12760 /* 12761 * VGT_DI_INDEX_SIZE enum 12762 */ 12763 12764 typedef enum VGT_DI_INDEX_SIZE { 12765 DI_INDEX_SIZE_16_BIT = 0x00000000, 12766 DI_INDEX_SIZE_32_BIT = 0x00000001, 12767 DI_INDEX_SIZE_8_BIT = 0x00000002, 12768 } VGT_DI_INDEX_SIZE; 12769 12770 /* 12771 * VGT_DI_PRIM_TYPE enum 12772 */ 12773 12774 typedef enum VGT_DI_PRIM_TYPE { 12775 DI_PT_NONE = 0x00000000, 12776 DI_PT_POINTLIST = 0x00000001, 12777 DI_PT_LINELIST = 0x00000002, 12778 DI_PT_LINESTRIP = 0x00000003, 12779 DI_PT_TRILIST = 0x00000004, 12780 DI_PT_TRIFAN = 0x00000005, 12781 DI_PT_TRISTRIP = 0x00000006, 12782 DI_PT_2D_RECTANGLE = 0x00000007, 12783 DI_PT_UNUSED_1 = 0x00000008, 12784 DI_PT_PATCH = 0x00000009, 12785 DI_PT_LINELIST_ADJ = 0x0000000a, 12786 DI_PT_LINESTRIP_ADJ = 0x0000000b, 12787 DI_PT_TRILIST_ADJ = 0x0000000c, 12788 DI_PT_TRISTRIP_ADJ = 0x0000000d, 12789 DI_PT_UNUSED_3 = 0x0000000e, 12790 DI_PT_UNUSED_4 = 0x0000000f, 12791 DI_PT_UNUSED_5 = 0x00000010, 12792 DI_PT_RECTLIST = 0x00000011, 12793 DI_PT_LINELOOP = 0x00000012, 12794 DI_PT_QUADLIST = 0x00000013, 12795 DI_PT_QUADSTRIP = 0x00000014, 12796 DI_PT_POLYGON = 0x00000015, 12797 } VGT_DI_PRIM_TYPE; 12798 12799 /* 12800 * VGT_DI_SOURCE_SELECT enum 12801 */ 12802 12803 typedef enum VGT_DI_SOURCE_SELECT { 12804 DI_SRC_SEL_DMA = 0x00000000, 12805 DI_SRC_SEL_IMMEDIATE = 0x00000001, 12806 DI_SRC_SEL_AUTO_INDEX = 0x00000002, 12807 DI_SRC_SEL_RESERVED = 0x00000003, 12808 } VGT_DI_SOURCE_SELECT; 12809 12810 /* 12811 * VGT_DMA_BUF_TYPE enum 12812 */ 12813 12814 typedef enum VGT_DMA_BUF_TYPE { 12815 VGT_DMA_BUF_MEM = 0x00000000, 12816 VGT_DMA_BUF_RING = 0x00000001, 12817 VGT_DMA_BUF_SETUP = 0x00000002, 12818 VGT_DMA_PTR_UPDATE = 0x00000003, 12819 } VGT_DMA_BUF_TYPE; 12820 12821 /* 12822 * VGT_DMA_SWAP_MODE enum 12823 */ 12824 12825 typedef enum VGT_DMA_SWAP_MODE { 12826 VGT_DMA_SWAP_NONE = 0x00000000, 12827 VGT_DMA_SWAP_16_BIT = 0x00000001, 12828 VGT_DMA_SWAP_32_BIT = 0x00000002, 12829 VGT_DMA_SWAP_WORD = 0x00000003, 12830 } VGT_DMA_SWAP_MODE; 12831 12832 /* 12833 * VGT_EVENT_TYPE enum 12834 */ 12835 12836 typedef enum VGT_EVENT_TYPE { 12837 Reserved_0x00 = 0x00000000, 12838 SAMPLE_STREAMOUTSTATS1 = 0x00000001, 12839 SAMPLE_STREAMOUTSTATS2 = 0x00000002, 12840 SAMPLE_STREAMOUTSTATS3 = 0x00000003, 12841 CACHE_FLUSH_TS = 0x00000004, 12842 CONTEXT_DONE = 0x00000005, 12843 CACHE_FLUSH = 0x00000006, 12844 CS_PARTIAL_FLUSH = 0x00000007, 12845 VGT_STREAMOUT_SYNC = 0x00000008, 12846 EVENT_STATE_CHANGE = 0x00000009, 12847 VGT_STREAMOUT_RESET = 0x0000000a, 12848 END_OF_PIPE_INCR_DE = 0x0000000b, 12849 END_OF_PIPE_IB_END = 0x0000000c, 12850 RST_PIX_CNT = 0x0000000d, 12851 BREAK_BATCH = 0x0000000e, 12852 VS_PARTIAL_FLUSH = 0x0000000f, 12853 PS_PARTIAL_FLUSH = 0x00000010, 12854 FLUSH_HS_OUTPUT = 0x00000011, 12855 FLUSH_DFSM = 0x00000012, 12856 RESET_TO_LOWEST_VGT = 0x00000013, 12857 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, 12858 WAIT_SYNC = 0x00000015, 12859 CACHE_FLUSH_AND_INV_EVENT = 0x00000016, 12860 PERFCOUNTER_START = 0x00000017, 12861 PERFCOUNTER_STOP = 0x00000018, 12862 PIPELINESTAT_START = 0x00000019, 12863 PIPELINESTAT_STOP = 0x0000001a, 12864 PERFCOUNTER_SAMPLE = 0x0000001b, 12865 FLUSH_ES_OUTPUT = 0x0000001c, 12866 BIN_CONF_OVERRIDE_CHECK = 0x0000001d, 12867 SAMPLE_PIPELINESTAT = 0x0000001e, 12868 SO_VGTSTREAMOUT_FLUSH = 0x0000001f, 12869 SAMPLE_STREAMOUTSTATS = 0x00000020, 12870 RESET_VTX_CNT = 0x00000021, 12871 BLOCK_CONTEXT_DONE = 0x00000022, 12872 CS_CONTEXT_DONE = 0x00000023, 12873 VGT_FLUSH = 0x00000024, 12874 TGID_ROLLOVER = 0x00000025, 12875 SQ_NON_EVENT = 0x00000026, 12876 SC_SEND_DB_VPZ = 0x00000027, 12877 BOTTOM_OF_PIPE_TS = 0x00000028, 12878 FLUSH_SX_TS = 0x00000029, 12879 DB_CACHE_FLUSH_AND_INV = 0x0000002a, 12880 FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, 12881 FLUSH_AND_INV_DB_META = 0x0000002c, 12882 FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, 12883 FLUSH_AND_INV_CB_META = 0x0000002e, 12884 CS_DONE = 0x0000002f, 12885 PS_DONE = 0x00000030, 12886 FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, 12887 SX_CB_RAT_ACK_REQUEST = 0x00000032, 12888 THREAD_TRACE_START = 0x00000033, 12889 THREAD_TRACE_STOP = 0x00000034, 12890 THREAD_TRACE_MARKER = 0x00000035, 12891 THREAD_TRACE_DRAW = 0x00000036, 12892 THREAD_TRACE_FINISH = 0x00000037, 12893 PIXEL_PIPE_STAT_CONTROL = 0x00000038, 12894 PIXEL_PIPE_STAT_DUMP = 0x00000039, 12895 PIXEL_PIPE_STAT_RESET = 0x0000003a, 12896 CONTEXT_SUSPEND = 0x0000003b, 12897 OFFCHIP_HS_DEALLOC = 0x0000003c, 12898 ENABLE_NGG_PIPELINE = 0x0000003d, 12899 ENABLE_PIPELINE_NOT_USED = 0x0000003e, 12900 DRAW_DONE = 0x0000003f, 12901 } VGT_EVENT_TYPE; 12902 12903 /* 12904 * VGT_GROUP_CONV_SEL enum 12905 */ 12906 12907 typedef enum VGT_GROUP_CONV_SEL { 12908 VGT_GRP_INDEX_16 = 0x00000000, 12909 VGT_GRP_INDEX_32 = 0x00000001, 12910 VGT_GRP_UINT_16 = 0x00000002, 12911 VGT_GRP_UINT_32 = 0x00000003, 12912 VGT_GRP_SINT_16 = 0x00000004, 12913 VGT_GRP_SINT_32 = 0x00000005, 12914 VGT_GRP_FLOAT_32 = 0x00000006, 12915 VGT_GRP_AUTO_PRIM = 0x00000007, 12916 VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, 12917 } VGT_GROUP_CONV_SEL; 12918 12919 /* 12920 * VGT_GS_MODE_TYPE enum 12921 */ 12922 12923 typedef enum VGT_GS_MODE_TYPE { 12924 GS_OFF = 0x00000000, 12925 GS_SCENARIO_A = 0x00000001, 12926 GS_SCENARIO_B = 0x00000002, 12927 GS_SCENARIO_G = 0x00000003, 12928 GS_SCENARIO_C = 0x00000004, 12929 SPRITE_EN = 0x00000005, 12930 } VGT_GS_MODE_TYPE; 12931 12932 /* 12933 * VGT_GS_OUTPRIM_TYPE enum 12934 */ 12935 12936 typedef enum VGT_GS_OUTPRIM_TYPE { 12937 POINTLIST = 0x00000000, 12938 LINESTRIP = 0x00000001, 12939 TRISTRIP = 0x00000002, 12940 RECT_2D = 0x00000003, 12941 RECTLIST = 0x00000004, 12942 } VGT_GS_OUTPRIM_TYPE; 12943 12944 /* 12945 * VGT_INDEX_TYPE_MODE enum 12946 */ 12947 12948 typedef enum VGT_INDEX_TYPE_MODE { 12949 VGT_INDEX_16 = 0x00000000, 12950 VGT_INDEX_32 = 0x00000001, 12951 VGT_INDEX_8 = 0x00000002, 12952 } VGT_INDEX_TYPE_MODE; 12953 12954 /* 12955 * VGT_OUTPATH_SELECT enum 12956 */ 12957 12958 typedef enum VGT_OUTPATH_SELECT { 12959 VGT_OUTPATH_VTX_REUSE = 0x00000000, 12960 VGT_OUTPATH_GS_BLOCK = 0x00000001, 12961 VGT_OUTPATH_HS_BLOCK = 0x00000002, 12962 VGT_OUTPATH_PRIM_GEN = 0x00000003, 12963 VGT_OUTPATH_TE_PRIM_GEN = 0x00000004, 12964 VGT_OUTPATH_TE_GS_BLOCK = 0x00000005, 12965 VGT_OUTPATH_TE_OUTPUT = 0x00000006, 12966 } VGT_OUTPATH_SELECT; 12967 12968 /* 12969 * VGT_OUT_PRIM_TYPE enum 12970 */ 12971 12972 typedef enum VGT_OUT_PRIM_TYPE { 12973 VGT_OUT_POINT = 0x00000000, 12974 VGT_OUT_LINE = 0x00000001, 12975 VGT_OUT_TRI = 0x00000002, 12976 VGT_OUT_2D_RECT = 0x00000003, 12977 VGT_OUT_RECT_V0 = 0x00000004, 12978 VGT_OUT_DUMMY_1 = 0x00000005, 12979 VGT_OUT_DUMMY_2 = 0x00000006, 12980 VGT_OUT_DUMMY_3 = 0x00000007, 12981 VGT_OUT_PATCH = 0x00000008, 12982 VGT_OUT_LINE_ADJ = 0x00000009, 12983 VGT_OUT_TRI_ADJ = 0x0000000a, 12984 } VGT_OUT_PRIM_TYPE; 12985 12986 /* 12987 * VGT_RDREQ_POLICY enum 12988 */ 12989 12990 typedef enum VGT_RDREQ_POLICY { 12991 VGT_POLICY_LRU = 0x00000000, 12992 VGT_POLICY_STREAM = 0x00000001, 12993 VGT_POLICY_BYPASS = 0x00000002, 12994 } VGT_RDREQ_POLICY; 12995 12996 /* 12997 * VGT_SPEC_DATA_READ enum 12998 */ 12999 13000 typedef enum VGT_SPEC_DATA_READ { 13001 VGT_SPEC_DATA_READ_AUTO = 0x00000000, 13002 VGT_SPEC_DATA_READ_FORCE_ON = 0x00000001, 13003 VGT_SPEC_DATA_READ_FORCE_OFF = 0x00000002, 13004 } VGT_SPEC_DATA_READ; 13005 13006 /* 13007 * VGT_STAGES_GS_EN enum 13008 */ 13009 13010 typedef enum VGT_STAGES_GS_EN { 13011 GS_STAGE_OFF = 0x00000000, 13012 GS_STAGE_ON = 0x00000001, 13013 } VGT_STAGES_GS_EN; 13014 13015 /* 13016 * VGT_STAGES_HS_EN enum 13017 */ 13018 13019 typedef enum VGT_STAGES_HS_EN { 13020 HS_STAGE_OFF = 0x00000000, 13021 HS_STAGE_ON = 0x00000001, 13022 } VGT_STAGES_HS_EN; 13023 13024 /* 13025 * VGT_TEMPORAL enum 13026 */ 13027 13028 typedef enum VGT_TEMPORAL { 13029 VGT_TEMPORAL_NORMAL = 0x00000000, 13030 VGT_TEMPORAL_HIGH_PRIORITY = 0x00000001, 13031 VGT_TEMPORAL_STREAM = 0x00000002, 13032 VGT_TEMPORAL_DISCARD = 0x00000003, 13033 } VGT_TEMPORAL; 13034 13035 /* 13036 * VGT_TESS_PARTITION enum 13037 */ 13038 13039 typedef enum VGT_TESS_PARTITION { 13040 PART_INTEGER = 0x00000000, 13041 PART_POW2 = 0x00000001, 13042 PART_FRAC_ODD = 0x00000002, 13043 PART_FRAC_EVEN = 0x00000003, 13044 } VGT_TESS_PARTITION; 13045 13046 /* 13047 * VGT_TESS_TOPOLOGY enum 13048 */ 13049 13050 typedef enum VGT_TESS_TOPOLOGY { 13051 OUTPUT_POINT = 0x00000000, 13052 OUTPUT_LINE = 0x00000001, 13053 OUTPUT_TRIANGLE_CW = 0x00000002, 13054 OUTPUT_TRIANGLE_CCW = 0x00000003, 13055 } VGT_TESS_TOPOLOGY; 13056 13057 /* 13058 * VGT_TESS_TYPE enum 13059 */ 13060 13061 typedef enum VGT_TESS_TYPE { 13062 TESS_ISOLINE = 0x00000000, 13063 TESS_TRIANGLE = 0x00000001, 13064 TESS_QUAD = 0x00000002, 13065 } VGT_TESS_TYPE; 13066 13067 /* 13068 * WD_IA_DRAW_REG_XFER enum 13069 */ 13070 13071 typedef enum WD_IA_DRAW_REG_XFER { 13072 WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000000, 13073 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, 13074 WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE = 0x00000002, 13075 WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003, 13076 WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE = 0x00000004, 13077 WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL = 0x00000005, 13078 WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 0x00000006, 13079 WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 0x00000007, 13080 WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 0x00000008, 13081 WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 0x00000009, 13082 WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 0x0000000a, 13083 WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL = 0x0000000b, 13084 WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL = 0x0000000c, 13085 WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET = 0x0000000d, 13086 WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN = 0x0000000e, 13087 WD_IA_DRAW_REG_XFER_GE_USER_VGPR1 = 0x0000000f, 13088 WD_IA_DRAW_REG_XFER_GE_USER_VGPR2 = 0x00000010, 13089 WD_IA_DRAW_REG_XFER_GE_USER_VGPR3 = 0x00000011, 13090 WD_IA_DRAW_REG_XFER_GE_VRS_RATE = 0x00000012, 13091 WD_IA_DRAW_REG_XFER_GE_PC_ALLOC = 0x00000013, 13092 WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS = 0x00000014, 13093 WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE = 0x00000015, 13094 } WD_IA_DRAW_REG_XFER; 13095 13096 /* 13097 * WD_IA_DRAW_SOURCE enum 13098 */ 13099 13100 typedef enum WD_IA_DRAW_SOURCE { 13101 WD_IA_DRAW_SOURCE_DMA = 0x00000000, 13102 WD_IA_DRAW_SOURCE_IMMD = 0x00000001, 13103 WD_IA_DRAW_SOURCE_AUTO = 0x00000002, 13104 WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, 13105 } WD_IA_DRAW_SOURCE; 13106 13107 /* 13108 * WD_IA_DRAW_TYPE enum 13109 */ 13110 13111 typedef enum WD_IA_DRAW_TYPE { 13112 WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, 13113 WD_IA_DRAW_TYPE_INDX_OFF = 0x00000001, 13114 WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, 13115 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, 13116 WD_IA_DRAW_TYPE_REG_XFER = 0x00000004, 13117 WD_IA_DRAW_TYPE_MIN_INDX = 0x00000005, 13118 WD_IA_DRAW_TYPE_MAX_INDX = 0x00000006, 13119 WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, 13120 } WD_IA_DRAW_TYPE; 13121 13122 /* 13123 * GS_THREADID_SIZE value 13124 */ 13125 13126 #define GSTHREADID_SIZE 0x00000002 13127 13128 /******************************************************* 13129 * CH Enums 13130 *******************************************************/ 13131 13132 /* 13133 * CHA_PERF_SEL enum 13134 */ 13135 13136 typedef enum CHA_PERF_SEL { 13137 CHA_PERF_SEL_BUSY = 0x00000000, 13138 CHA_PERF_SEL_STALL_CHC0 = 0x00000001, 13139 CHA_PERF_SEL_STALL_CHC1 = 0x00000002, 13140 CHA_PERF_SEL_STALL_CHC2 = 0x00000003, 13141 CHA_PERF_SEL_STALL_CHC3 = 0x00000004, 13142 CHA_PERF_SEL_REQUEST_CHC0 = 0x00000005, 13143 CHA_PERF_SEL_REQUEST_CHC1 = 0x00000006, 13144 CHA_PERF_SEL_REQUEST_CHC2 = 0x00000007, 13145 CHA_PERF_SEL_REQUEST_CHC3 = 0x00000008, 13146 CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x00000009, 13147 CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000a, 13148 CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000b, 13149 CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000c, 13150 CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x0000000d, 13151 CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x0000000e, 13152 CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x0000000f, 13153 CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000010, 13154 CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000011, 13155 CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000012, 13156 CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000013, 13157 CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000014, 13158 CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x00000015, 13159 CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x00000016, 13160 CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x00000017, 13161 CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x00000018, 13162 CHA_PERF_SEL_ARB_REQUESTS = 0x00000019, 13163 CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x0000001a, 13164 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x0000001b, 13165 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x0000001c, 13166 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x0000001d, 13167 CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x0000001e, 13168 CHA_PERF_SEL_CYCLE = 0x0000001f, 13169 } CHA_PERF_SEL; 13170 13171 /* 13172 * CHC_PERF_SEL enum 13173 */ 13174 13175 typedef enum CHC_PERF_SEL { 13176 CHC_PERF_SEL_CYCLE = 0x00000000, 13177 CHC_PERF_SEL_BUSY = 0x00000001, 13178 CHC_PERF_SEL_STARVE = 0x00000002, 13179 CHC_PERF_SEL_ARB_RET_LEVEL = 0x00000003, 13180 CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, 13181 CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, 13182 CHC_PERF_SEL_REQ = 0x00000006, 13183 CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, 13184 CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, 13185 CHC_PERF_SEL_REQ_NOP_ACK = 0x00000009, 13186 CHC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, 13187 CHC_PERF_SEL_REQ_READ = 0x0000000b, 13188 CHC_PERF_SEL_REQ_READ_128B = 0x0000000c, 13189 CHC_PERF_SEL_REQ_READ_32B = 0x0000000d, 13190 CHC_PERF_SEL_REQ_READ_64B = 0x0000000e, 13191 CHC_PERF_SEL_REQ_WRITE = 0x0000000f, 13192 CHC_PERF_SEL_REQ_WRITE_32B = 0x00000010, 13193 CHC_PERF_SEL_REQ_WRITE_64B = 0x00000011, 13194 CHC_PERF_SEL_STALL_GL2_GL1 = 0x00000012, 13195 CHC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, 13196 CHC_PERF_SEL_REQ_CLIENT0 = 0x00000014, 13197 CHC_PERF_SEL_REQ_CLIENT1 = 0x00000015, 13198 CHC_PERF_SEL_REQ_CLIENT2 = 0x00000016, 13199 CHC_PERF_SEL_REQ_CLIENT3 = 0x00000017, 13200 CHC_PERF_SEL_REQ_CLIENT4 = 0x00000018, 13201 CHC_PERF_SEL_REQ_CLIENT5 = 0x00000019, 13202 CHC_PERF_SEL_REQ_CLIENT6 = 0x0000001a, 13203 CHC_PERF_SEL_REQ_CLIENT7 = 0x0000001b, 13204 CHC_PERF_SEL_REQ_CLIENT8 = 0x0000001c, 13205 CHC_PERF_SEL_REQ_CLIENT9 = 0x0000001d, 13206 CHC_PERF_SEL_REQ_CLIENT10 = 0x0000001e, 13207 CHC_PERF_SEL_REQ_CLIENT11 = 0x0000001f, 13208 CHC_PERF_SEL_REQ_CLIENT12 = 0x00000020, 13209 CHC_PERF_SEL_REQ_CLIENT13 = 0x00000021, 13210 CHC_PERF_SEL_REQ_CLIENT14 = 0x00000022, 13211 CHC_PERF_SEL_REQ_CLIENT15 = 0x00000023, 13212 CHC_PERF_SEL_REQ_CLIENT16 = 0x00000024, 13213 CHC_PERF_SEL_REQ_CLIENT17 = 0x00000025, 13214 CHC_PERF_SEL_REQ_CLIENT18 = 0x00000026, 13215 CHC_PERF_SEL_REQ_CLIENT19 = 0x00000027, 13216 CHC_PERF_SEL_REQ_CLIENT20 = 0x00000028, 13217 CHC_PERF_SEL_REQ_CLIENT21 = 0x00000029, 13218 CHC_PERF_SEL_REQ_CLIENT22 = 0x0000002a, 13219 CHC_PERF_SEL_REQ_CLIENT23 = 0x0000002b, 13220 } CHC_PERF_SEL; 13221 13222 /******************************************************* 13223 * GRBM Enums 13224 *******************************************************/ 13225 13226 /* 13227 * GRBM_PERF_SEL enum 13228 */ 13229 13230 typedef enum GRBM_PERF_SEL { 13231 GRBM_PERF_SEL_COUNT = 0x00000000, 13232 GRBM_PERF_SEL_USER_DEFINED = 0x00000001, 13233 GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, 13234 GRBM_PERF_SEL_CP_BUSY = 0x00000003, 13235 GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, 13236 GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, 13237 GRBM_PERF_SEL_CB_BUSY = 0x00000006, 13238 GRBM_PERF_SEL_DB_BUSY = 0x00000007, 13239 GRBM_PERF_SEL_PA_BUSY = 0x00000008, 13240 GRBM_PERF_SEL_SC_BUSY = 0x00000009, 13241 GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, 13242 GRBM_PERF_SEL_SX_BUSY = 0x0000000c, 13243 GRBM_PERF_SEL_TA_BUSY = 0x0000000d, 13244 GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, 13245 GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, 13246 GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, 13247 GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, 13248 GRBM_PERF_SEL_TCP_BUSY = 0x0000001c, 13249 GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, 13250 GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, 13251 GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, 13252 GRBM_PERF_SEL_GE_BUSY = 0x00000020, 13253 GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021, 13254 GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, 13255 GRBM_PERF_SEL_EA_BUSY = 0x00000023, 13256 GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027, 13257 GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028, 13258 GRBM_PERF_SEL_SDMA_BUSY = 0x00000029, 13259 GRBM_PERF_SEL_CH_BUSY = 0x0000002a, 13260 GRBM_PERF_SEL_PMM_BUSY = 0x0000002c, 13261 GRBM_PERF_SEL_GUS_BUSY = 0x0000002d, 13262 GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e, 13263 GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 0x0000002f, 13264 GRBM_PERF_SEL_GL1XCC_BUSY = 0x00000030, 13265 GRBM_PERF_SEL_PC_BUSY = 0x00000031, 13266 } GRBM_PERF_SEL; 13267 13268 /******************************************************* 13269 * CP Enums 13270 *******************************************************/ 13271 13272 /* 13273 * CPC_LATENCY_STATS_SEL enum 13274 */ 13275 13276 typedef enum CPC_LATENCY_STATS_SEL { 13277 CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 13278 CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 13279 CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 13280 CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 13281 CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 13282 CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 13283 CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006, 13284 CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007, 13285 CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008, 13286 } CPC_LATENCY_STATS_SEL; 13287 13288 /* 13289 * CPC_PERFCOUNT_SEL enum 13290 */ 13291 13292 typedef enum CPC_PERFCOUNT_SEL { 13293 CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, 13294 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, 13295 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, 13296 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, 13297 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, 13298 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, 13299 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, 13300 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ = 0x00000009, 13301 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE = 0x0000000a, 13302 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, 13303 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, 13304 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, 13305 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, 13306 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, 13307 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, 13308 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ = 0x00000011, 13309 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE = 0x00000012, 13310 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, 13311 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, 13312 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, 13313 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, 13314 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, 13315 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, 13316 CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019, 13317 CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a, 13318 CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b, 13319 CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c, 13320 CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d, 13321 CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e, 13322 CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f, 13323 CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020, 13324 CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021, 13325 CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022, 13326 CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023, 13327 CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024, 13328 CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025, 13329 CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026, 13330 CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027, 13331 CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028, 13332 CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029, 13333 CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a, 13334 CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b, 13335 CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c, 13336 CPC_PERF_SEL_MES_THREAD0 = 0x0000002d, 13337 CPC_PERF_SEL_MES_THREAD1 = 0x0000002e, 13338 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002f, 13339 CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000030, 13340 CPC_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000031, 13341 CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000032, 13342 CPC_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000033, 13343 CPC_PERF_SEL_MEC_THREAD0 = 0x00000034, 13344 CPC_PERF_SEL_MEC_THREAD1 = 0x00000035, 13345 CPC_PERF_SEL_MEC_THREAD2 = 0x00000036, 13346 CPC_PERF_SEL_MEC_THREAD3 = 0x00000037, 13347 } CPC_PERFCOUNT_SEL; 13348 13349 /* 13350 * CPF_LATENCY_STATS_SEL enum 13351 */ 13352 13353 typedef enum CPF_LATENCY_STATS_SEL { 13354 CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 13355 CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 13356 CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 13357 CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 13358 CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 13359 CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 13360 CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006, 13361 CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007, 13362 CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008, 13363 CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009, 13364 CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a, 13365 CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b, 13366 } CPF_LATENCY_STATS_SEL; 13367 13368 /* 13369 * CPF_PERFCOUNTWINDOW_SEL enum 13370 */ 13371 13372 typedef enum CPF_PERFCOUNTWINDOW_SEL { 13373 CPF_PERFWINDOW_SEL_CSF = 0x00000000, 13374 CPF_PERFWINDOW_SEL_HQD1 = 0x00000001, 13375 CPF_PERFWINDOW_SEL_HQD2 = 0x00000002, 13376 CPF_PERFWINDOW_SEL_RDMA = 0x00000003, 13377 CPF_PERFWINDOW_SEL_RWPP = 0x00000004, 13378 } CPF_PERFCOUNTWINDOW_SEL; 13379 13380 /* 13381 * CPF_PERFCOUNT_SEL enum 13382 */ 13383 13384 typedef enum CPF_PERFCOUNT_SEL { 13385 CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, 13386 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, 13387 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, 13388 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, 13389 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, 13390 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, 13391 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007, 13392 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, 13393 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, 13394 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, 13395 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, 13396 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, 13397 CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x0000000f, 13398 CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000010, 13399 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, 13400 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, 13401 CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013, 13402 CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014, 13403 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015, 13404 CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016, 13405 CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017, 13406 CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018, 13407 CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019, 13408 CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a, 13409 CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b, 13410 CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c, 13411 CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d, 13412 CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e, 13413 CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f, 13414 CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020, 13415 CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021, 13416 CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022, 13417 CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023, 13418 CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024, 13419 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025, 13420 CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026, 13421 CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027, 13422 CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 0x00000028, 13423 CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 0x00000029, 13424 CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 0x0000002a, 13425 CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 0x0000002b, 13426 } CPF_PERFCOUNT_SEL; 13427 13428 /* 13429 * CPF_SCRATCH_REG_ATOMIC_OP enum 13430 */ 13431 13432 typedef enum CPF_SCRATCH_REG_ATOMIC_OP { 13433 CPF_SCRATCH_REG_ATOMIC_ADD = 0x00000000, 13434 CPF_SCRATCH_REG_ATOMIC_SUB = 0x00000001, 13435 CPF_SCRATCH_REG_ATOMIC_OR = 0x00000002, 13436 CPF_SCRATCH_REG_ATOMIC_AND = 0x00000003, 13437 CPF_SCRATCH_REG_ATOMIC_NOT = 0x00000004, 13438 CPF_SCRATCH_REG_ATOMIC_MIN = 0x00000005, 13439 CPF_SCRATCH_REG_ATOMIC_MAX = 0x00000006, 13440 CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 0x00000007, 13441 } CPF_SCRATCH_REG_ATOMIC_OP; 13442 13443 /* 13444 * CPG_LATENCY_STATS_SEL enum 13445 */ 13446 13447 typedef enum CPG_LATENCY_STATS_SEL { 13448 CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, 13449 CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, 13450 CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, 13451 CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, 13452 CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, 13453 CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, 13454 CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006, 13455 CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007, 13456 CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008, 13457 CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009, 13458 CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a, 13459 CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b, 13460 CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c, 13461 CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d, 13462 CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e, 13463 CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f, 13464 CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010, 13465 CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011, 13466 } CPG_LATENCY_STATS_SEL; 13467 13468 /* 13469 * CPG_PERFCOUNTWINDOW_SEL enum 13470 */ 13471 13472 typedef enum CPG_PERFCOUNTWINDOW_SEL { 13473 CPG_PERFWINDOW_SEL_PFP = 0x00000000, 13474 CPG_PERFWINDOW_SEL_ME = 0x00000001, 13475 CPG_PERFWINDOW_SEL_CE = 0x00000002, 13476 CPG_PERFWINDOW_SEL_MES = 0x00000003, 13477 CPG_PERFWINDOW_SEL_MEC1 = 0x00000004, 13478 CPG_PERFWINDOW_SEL_MEC2 = 0x00000005, 13479 CPG_PERFWINDOW_SEL_DFY = 0x00000006, 13480 CPG_PERFWINDOW_SEL_DMA = 0x00000007, 13481 CPG_PERFWINDOW_SEL_SHADOW = 0x00000008, 13482 CPG_PERFWINDOW_SEL_RB = 0x00000009, 13483 CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a, 13484 CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b, 13485 CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c, 13486 CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d, 13487 CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e, 13488 CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f, 13489 CPG_PERFWINDOW_SEL_MEMWR = 0x00000010, 13490 CPG_PERFWINDOW_SEL_MEMRD = 0x00000011, 13491 CPG_PERFWINDOW_SEL_VGT0 = 0x00000012, 13492 CPG_PERFWINDOW_SEL_VGT1 = 0x00000013, 13493 CPG_PERFWINDOW_SEL_APPEND = 0x00000014, 13494 CPG_PERFWINDOW_SEL_QURD = 0x00000015, 13495 CPG_PERFWINDOW_SEL_DDID = 0x00000016, 13496 CPG_PERFWINDOW_SEL_SR = 0x00000017, 13497 CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018, 13498 CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019, 13499 CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a, 13500 CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b, 13501 CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c, 13502 CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d, 13503 CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e, 13504 } CPG_PERFCOUNTWINDOW_SEL; 13505 13506 /* 13507 * CPG_PERFCOUNT_SEL enum 13508 */ 13509 13510 typedef enum CPG_PERFCOUNT_SEL { 13511 CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, 13512 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, 13513 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, 13514 CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, 13515 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, 13516 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, 13517 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, 13518 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, 13519 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, 13520 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, 13521 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, 13522 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, 13523 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, 13524 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, 13525 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, 13526 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, 13527 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, 13528 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, 13529 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, 13530 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, 13531 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, 13532 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, 13533 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, 13534 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, 13535 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, 13536 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, 13537 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, 13538 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, 13539 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, 13540 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, 13541 CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022, 13542 CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023, 13543 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, 13544 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, 13545 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, 13546 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, 13547 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, 13548 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, 13549 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, 13550 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, 13551 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, 13552 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, 13553 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, 13554 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, 13555 CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031, 13556 CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032, 13557 CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033, 13558 CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034, 13559 CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035, 13560 CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036, 13561 CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037, 13562 CPG_PERF_SEL_CPG_TCIU_STALL = 0x00000038, 13563 CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039, 13564 CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a, 13565 CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b, 13566 CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c, 13567 CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d, 13568 CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e, 13569 CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f, 13570 CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040, 13571 CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041, 13572 CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042, 13573 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043, 13574 CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044, 13575 CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045, 13576 CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046, 13577 CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047, 13578 CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048, 13579 CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049, 13580 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a, 13581 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b, 13582 CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c, 13583 CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d, 13584 CPG_PERF_SEL_DMA_BUSY = 0x0000004e, 13585 CPG_PERF_SEL_DMA_STARVED = 0x0000004f, 13586 CPG_PERF_SEL_DMA_STALLED = 0x00000050, 13587 CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051, 13588 CPG_PERF_SEL_PFP_PWS_STALLED0 = 0x00000052, 13589 CPG_PERF_SEL_ME_PWS_STALLED0 = 0x00000053, 13590 CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0 = 0x00000054, 13591 CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0 = 0x00000055, 13592 CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0 = 0x00000056, 13593 CPG_PERF_SEL_PFP_PWS_STALLED1 = 0x00000057, 13594 CPG_PERF_SEL_ME_PWS_STALLED1 = 0x00000058, 13595 CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1 = 0x00000059, 13596 CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1 = 0x0000005a, 13597 CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1 = 0x0000005b, 13598 } CPG_PERFCOUNT_SEL; 13599 13600 /* 13601 * CP_ALPHA_TAG_RAM_SEL enum 13602 */ 13603 13604 typedef enum CP_ALPHA_TAG_RAM_SEL { 13605 CPG_TAG_RAM = 0x00000000, 13606 CPC_TAG_RAM = 0x00000001, 13607 CPF_TAG_RAM = 0x00000002, 13608 RSV_TAG_RAM = 0x00000003, 13609 } CP_ALPHA_TAG_RAM_SEL; 13610 13611 /* 13612 * CP_DDID_CNTL_MODE enum 13613 */ 13614 13615 typedef enum CP_DDID_CNTL_MODE { 13616 STALL = 0x00000000, 13617 OVERRUN = 0x00000001, 13618 } CP_DDID_CNTL_MODE; 13619 13620 /* 13621 * CP_DDID_CNTL_SIZE enum 13622 */ 13623 13624 typedef enum CP_DDID_CNTL_SIZE { 13625 SIZE_8K = 0x00000000, 13626 SIZE_16K = 0x00000001, 13627 } CP_DDID_CNTL_SIZE; 13628 13629 /* 13630 * CP_DDID_CNTL_VMID_SEL enum 13631 */ 13632 13633 typedef enum CP_DDID_CNTL_VMID_SEL { 13634 DDID_VMID_PIPE = 0x00000000, 13635 DDID_VMID_CNTL = 0x00000001, 13636 } CP_DDID_CNTL_VMID_SEL; 13637 13638 /* 13639 * CP_ME_ID enum 13640 */ 13641 13642 typedef enum CP_ME_ID { 13643 ME_ID0 = 0x00000000, 13644 ME_ID1 = 0x00000001, 13645 ME_ID2 = 0x00000002, 13646 ME_ID3 = 0x00000003, 13647 } CP_ME_ID; 13648 13649 /* 13650 * CP_PIPE_ID enum 13651 */ 13652 13653 typedef enum CP_PIPE_ID { 13654 PIPE_ID0 = 0x00000000, 13655 PIPE_ID1 = 0x00000001, 13656 PIPE_ID2 = 0x00000002, 13657 PIPE_ID3 = 0x00000003, 13658 } CP_PIPE_ID; 13659 13660 /* 13661 * CP_RING_ID enum 13662 */ 13663 13664 typedef enum CP_RING_ID { 13665 RINGID0 = 0x00000000, 13666 RINGID1 = 0x00000001, 13667 RINGID2 = 0x00000002, 13668 RINGID3 = 0x00000003, 13669 } CP_RING_ID; 13670 13671 /* 13672 * IQ_RETRY_TYPE value 13673 */ 13674 13675 #define IQ_QUEUE_SLEEP 0x00000000 13676 #define IQ_OFFLOAD_RETRY 0x00000001 13677 #define IQ_SCH_WAVE_MSG 0x00000002 13678 #define IQ_DEQUEUE_RETRY 0x00000004 13679 13680 /* 13681 * IQ_INTR_TYPE value 13682 */ 13683 13684 #define IQ_INTR_TYPE_PQ 0x00000000 13685 #define IQ_INTR_TYPE_IB 0x00000001 13686 #define IQ_INTR_TYPE_MQD 0x00000002 13687 13688 /* 13689 * VMID_SIZE value 13690 */ 13691 13692 #define VMID_SZ 0x00000004 13693 13694 /* 13695 * CONFIG_SPACE value 13696 */ 13697 13698 #define CONFIG_SPACE_START 0x00002000 13699 #define CONFIG_SPACE_END 0x00009fff 13700 13701 /* 13702 * CONFIG_SPACE1 valu 13703 */ 13704 13705 #define CONFIG_SPACE1_START 0x00002000 13706 #define CONFIG_SPACE1_END 0x00002bff 13707 13708 /* 13709 * CONFIG_SPACE2 value 13710 */ 13711 13712 #define CONFIG_SPACE2_START 0x00003000 13713 #define CONFIG_SPACE2_END 0x00009fff 13714 13715 /* 13716 * UCONFIG_SPACE value 13717 */ 13718 13719 #define UCONFIG_SPACE_START 0x0000c000 13720 #define UCONFIG_SPACE_END 0x0000ffff 13721 13722 /* 13723 * PERSISTENT_SPACE value 13724 */ 13725 13726 #define PERSISTENT_SPACE_START 0x00002c00 13727 #define PERSISTENT_SPACE_END 0x00002fff 13728 13729 /* 13730 * CONTEXT_SPACE value 13731 */ 13732 13733 #define CONTEXT_SPACE_START 0x0000a000 13734 #define CONTEXT_SPACE_END 0x0000a3ff 13735 13736 /******************************************************* 13737 * GCR Enums 13738 *******************************************************/ 13739 13740 /* 13741 * GCRPerfSel enum 13742 */ 13743 13744 typedef enum GCRPerfSel { 13745 GCR_PERF_SEL_NONE = 0x00000000, 13746 GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001, 13747 GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002, 13748 GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003, 13749 GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004, 13750 GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005, 13751 GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006, 13752 GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007, 13753 GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008, 13754 GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009, 13755 GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a, 13756 GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b, 13757 GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c, 13758 GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d, 13759 GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e, 13760 GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f, 13761 GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ = 0x00000010, 13762 GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011, 13763 GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012, 13764 GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013, 13765 GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014, 13766 GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015, 13767 GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016, 13768 GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017, 13769 GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018, 13770 GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019, 13771 GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a, 13772 GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b, 13773 GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c, 13774 GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d, 13775 GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e, 13776 GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f, 13777 GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ = 0x00000020, 13778 GCR_PERF_SEL_CPC_ALL_REQ = 0x00000021, 13779 GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000022, 13780 GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000023, 13781 GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000024, 13782 GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000025, 13783 GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000026, 13784 GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000027, 13785 GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000028, 13786 GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000029, 13787 GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000002a, 13788 GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000002b, 13789 GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000002c, 13790 GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000002d, 13791 GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000002e, 13792 GCR_PERF_SEL_CPC_TCP_REQ = 0x0000002f, 13793 GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ = 0x00000030, 13794 GCR_PERF_SEL_CPG_ALL_REQ = 0x00000031, 13795 GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000032, 13796 GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000033, 13797 GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000034, 13798 GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000035, 13799 GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000036, 13800 GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000037, 13801 GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000038, 13802 GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000039, 13803 GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000003a, 13804 GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000003b, 13805 GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000003c, 13806 GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000003d, 13807 GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000003e, 13808 GCR_PERF_SEL_CPG_TCP_REQ = 0x0000003f, 13809 GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ = 0x00000040, 13810 GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041, 13811 GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042, 13812 GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043, 13813 GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044, 13814 GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045, 13815 GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046, 13816 GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047, 13817 GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048, 13818 GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049, 13819 GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a, 13820 GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b, 13821 GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c, 13822 GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d, 13823 GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e, 13824 GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f, 13825 GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ = 0x00000050, 13826 GCR_PERF_SEL_VIRT_REQ = 0x00000051, 13827 GCR_PERF_SEL_PHY_REQ = 0x00000052, 13828 GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053, 13829 GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054, 13830 GCR_PERF_SEL_ALL_REQ = 0x00000055, 13831 GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056, 13832 GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057, 13833 GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058, 13834 GCR_PERF_SEL_UTCL2_REQ = 0x00000059, 13835 GCR_PERF_SEL_UTCL2_RET = 0x0000005a, 13836 GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b, 13837 GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c, 13838 GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d, 13839 GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH = 0x0000005e, 13840 GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING = 0x0000005f, 13841 GCR_PERF_SEL_PMM_NUM_INTERRUPT = 0x00000060, 13842 GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS = 0x00000061, 13843 GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND = 0x00000062, 13844 GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH = 0x00000063, 13845 GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH = 0x00000064, 13846 GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT = 0x00000065, 13847 GCR_PERF_SEL_PMM_ALOG_INTERRUPT = 0x00000066, 13848 GCR_PERF_SEL_PMM_MAM_FLUSH_REQ = 0x00000067, 13849 GCR_PERF_SEL_PMM_MAM_FLUSH_RESP = 0x00000068, 13850 GCR_PERF_SEL_PMM_RLC_CGCG_REQ = 0x00000069, 13851 GCR_PERF_SEL_PMM_RLC_CGCG_RESP = 0x0000006a, 13852 GCR_PERF_SEL_RLC_ALL_REQ = 0x0000006b, 13853 GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 0x0000006c, 13854 GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 0x0000006d, 13855 GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 0x0000006e, 13856 GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 0x0000006f, 13857 GCR_PERF_SEL_RLC_GL2_ALL_REQ = 0x00000070, 13858 GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 0x00000071, 13859 GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 0x00000072, 13860 GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 0x00000073, 13861 GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 0x00000074, 13862 GCR_PERF_SEL_RLC_GL1_ALL_REQ = 0x00000075, 13863 GCR_PERF_SEL_RLC_METADATA_REQ = 0x00000076, 13864 GCR_PERF_SEL_RLC_SQC_DATA_REQ = 0x00000077, 13865 GCR_PERF_SEL_RLC_SQC_INST_REQ = 0x00000078, 13866 GCR_PERF_SEL_RLC_TCP_REQ = 0x00000079, 13867 GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ = 0x0000007a, 13868 GCR_PERF_SEL_PM_ALL_REQ = 0x0000007b, 13869 GCR_PERF_SEL_PM_GL2_RANGE_REQ = 0x0000007c, 13870 GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 0x0000007d, 13871 GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 0x0000007e, 13872 GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 0x0000007f, 13873 GCR_PERF_SEL_PM_GL2_ALL_REQ = 0x00000080, 13874 GCR_PERF_SEL_PM_GL1_RANGE_REQ = 0x00000081, 13875 GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 0x00000082, 13876 GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 0x00000083, 13877 GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 0x00000084, 13878 GCR_PERF_SEL_PM_GL1_ALL_REQ = 0x00000085, 13879 GCR_PERF_SEL_PM_METADATA_REQ = 0x00000086, 13880 GCR_PERF_SEL_PM_SQC_DATA_REQ = 0x00000087, 13881 GCR_PERF_SEL_PM_SQC_INST_REQ = 0x00000088, 13882 GCR_PERF_SEL_PM_TCP_REQ = 0x00000089, 13883 GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ = 0x0000008a, 13884 GCR_PERF_SEL_PIO_ALL_REQ = 0x0000008b, 13885 GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 0x0000008c, 13886 GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 0x0000008d, 13887 GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 0x0000008e, 13888 GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 0x0000008f, 13889 GCR_PERF_SEL_PIO_GL2_ALL_REQ = 0x00000090, 13890 GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 0x00000091, 13891 GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 0x00000092, 13892 GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 0x00000093, 13893 GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 0x00000094, 13894 GCR_PERF_SEL_PIO_GL1_ALL_REQ = 0x00000095, 13895 GCR_PERF_SEL_PIO_METADATA_REQ = 0x00000096, 13896 GCR_PERF_SEL_PIO_SQC_DATA_REQ = 0x00000097, 13897 GCR_PERF_SEL_PIO_SQC_INST_REQ = 0x00000098, 13898 GCR_PERF_SEL_PIO_TCP_REQ = 0x00000099, 13899 GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ = 0x0000009a, 13900 } GCRPerfSel; 13901 13902 /******************************************************* 13903 * GC_EA_CPWD Enums 13904 *******************************************************/ 13905 13906 /* 13907 * GC_EA_CPWD_PERFCOUNT_SEL enum 13908 */ 13909 13910 typedef enum GC_EA_CPWD_PERFCOUNT_SEL { 13911 GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT = 0x00000000, 13912 GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD = 0x00000001, 13913 GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 0x00000002, 13914 GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 0x00000003, 13915 GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0 = 0x00000004, 13916 GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0 = 0x00000005, 13917 GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1 = 0x00000006, 13918 GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1 = 0x00000007, 13919 GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD = 0x00000008, 13920 GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 0x00000009, 13921 GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 0x0000000a, 13922 GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0 = 0x0000000b, 13923 GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0 = 0x0000000c, 13924 GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1 = 0x0000000d, 13925 GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1 = 0x0000000e, 13926 GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD = 0x0000000f, 13927 GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP = 0x00000010, 13928 GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 0x00000011, 13929 GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0 = 0x00000012, 13930 GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0 = 0x00000013, 13931 GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1 = 0x00000014, 13932 GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1 = 0x00000015, 13933 GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD = 0x00000016, 13934 GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP = 0x00000017, 13935 GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 0x00000018, 13936 GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0 = 0x00000019, 13937 GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0 = 0x0000001a, 13938 GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1 = 0x0000001b, 13939 GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1 = 0x0000001c, 13940 GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP = 0x0000001d, 13941 GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ = 0x0000001e, 13942 GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ = 0x0000001f, 13943 GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ = 0x00000020, 13944 GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ = 0x00000021, 13945 GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ = 0x00000022, 13946 GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0 = 0x00000023, 13947 GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0 = 0x00000024, 13948 GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1 = 0x00000025, 13949 GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1 = 0x00000026, 13950 GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP = 0x00000027, 13951 GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 0x00000028, 13952 GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ = 0x00000029, 13953 GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ = 0x0000002a, 13954 GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ = 0x0000002b, 13955 GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ = 0x0000002c, 13956 GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ = 0x0000002d, 13957 GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0 = 0x0000002e, 13958 GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0 = 0x0000002f, 13959 GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1 = 0x00000030, 13960 GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1 = 0x00000031, 13961 GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC = 0x00000032, 13962 GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC = 0x00000033, 13963 GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC = 0x00000034, 13964 GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC = 0x00000035, 13965 GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ = 0x00000036, 13966 GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ = 0x00000037, 13967 GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ = 0x00000038, 13968 GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ = 0x00000039, 13969 GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0 = 0x0000003a, 13970 GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0 = 0x0000003b, 13971 GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1 = 0x0000003c, 13972 GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1 = 0x0000003d, 13973 GC_EA_CPWD_PERF_SEL_SARB_BUSY = 0x0000003e, 13974 GC_EA_CPWD_PERF_SEL_SARB_STALLED = 0x0000003f, 13975 GC_EA_CPWD_PERF_SEL_SARB_STARVING = 0x00000040, 13976 GC_EA_CPWD_PERF_SEL_SARB_IDLE = 0x00000041, 13977 GC_EA_CPWD_PERF_SEL_RRET_VLD = 0x00000042, 13978 GC_EA_CPWD_PERF_SEL_WRET_VLD = 0x00000043, 13979 GC_EA_CPWD_PERF_SEL_PRB_REQ = 0x00000044, 13980 GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT = 0x00000045, 13981 GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD = 0x00000046, 13982 GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT = 0x00000047, 13983 GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY = 0x00000048, 13984 GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT = 0x00000049, 13985 GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 0x0000004a, 13986 GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED = 0x0000004b, 13987 GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING = 0x0000004c, 13988 GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ = 0x0000004d, 13989 GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ = 0x0000004e, 13990 GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ = 0x0000004f, 13991 GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ = 0x00000050, 13992 GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 0x00000051, 13993 GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 0x00000052, 13994 GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000053, 13995 GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000054, 13996 GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000055, 13997 GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000056, 13998 GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT = 0x00000057, 13999 GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD = 0x00000058, 14000 GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ = 0x00000059, 14001 GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 0x0000005a, 14002 GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 0x0000005b, 14003 GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ = 0x0000005c, 14004 GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP = 0x0000005d, 14005 GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 0x0000005e, 14006 GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 0x0000005f, 14007 GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING = 0x00000060, 14008 GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT = 0x00000061, 14009 } GC_EA_CPWD_PERFCOUNT_SEL; 14010 14011 /******************************************************* 14012 * GC_VML2PERFS Enums 14013 *******************************************************/ 14014 14015 /* 14016 * GCVML2_SPM_PERF_SEL enum 14017 */ 14018 14019 typedef enum GCVML2_SPM_PERF_SEL { 14020 GCVML2_SPM_PERF_SEL_EVENT_0 = 0x00000000, 14021 GCVML2_SPM_PERF_SEL_EVENT_1 = 0x00000001, 14022 GCVML2_SPM_PERF_SEL_EVENT_2 = 0x00000002, 14023 GCVML2_SPM_PERF_SEL_EVENT_3 = 0x00000003, 14024 GCVML2_SPM_PERF_SEL_EVENT_4 = 0x00000004, 14025 GCVML2_SPM_PERF_SEL_EVENT_5 = 0x00000005, 14026 GCVML2_SPM_PERF_SEL_EVENT_6 = 0x00000006, 14027 GCVML2_SPM_PERF_SEL_EVENT_7 = 0x00000007, 14028 GCVML2_SPM_PERF_SEL_EVENT_8 = 0x00000008, 14029 GCVML2_SPM_PERF_SEL_EVENT_9 = 0x00000009, 14030 GCVML2_SPM_PERF_SEL_EVENT_10 = 0x0000000a, 14031 GCVML2_SPM_PERF_SEL_EVENT_11 = 0x0000000b, 14032 GCVML2_SPM_PERF_SEL_EVENT_12 = 0x0000000c, 14033 GCVML2_SPM_PERF_SEL_EVENT_13 = 0x0000000d, 14034 GCVML2_SPM_PERF_SEL_EVENT_14 = 0x0000000e, 14035 GCVML2_SPM_PERF_SEL_EVENT_15 = 0x0000000f, 14036 GCVML2_SPM_PERF_SEL_EVENT_16 = 0x00000010, 14037 GCVML2_SPM_PERF_SEL_EVENT_17 = 0x00000011, 14038 GCVML2_SPM_PERF_SEL_EVENT_18 = 0x00000012, 14039 GCVML2_SPM_PERF_SEL_EVENT_19 = 0x00000013, 14040 GCVML2_SPM_PERF_SEL_EVENT_20 = 0x00000014, 14041 GCVML2_SPM_PERF_SEL_EVENT_21 = 0x00000015, 14042 GCVML2_SPM_PERF_SEL_EVENT_22 = 0x00000016, 14043 GCVML2_SPM_PERF_SEL_EVENT_23 = 0x00000017, 14044 GCVML2_SPM_PERF_SEL_EVENT_24 = 0x00000018, 14045 GCVML2_SPM_PERF_SEL_EVENT_25 = 0x00000019, 14046 GCVML2_SPM_PERF_SEL_EVENT_26 = 0x0000001a, 14047 GCVML2_SPM_PERF_SEL_EVENT_27 = 0x0000001b, 14048 GCVML2_SPM_PERF_SEL_EVENT_28 = 0x0000001c, 14049 GCVML2_SPM_PERF_SEL_EVENT_29 = 0x0000001d, 14050 GCVML2_SPM_PERF_SEL_EVENT_30 = 0x0000001e, 14051 GCVML2_SPM_PERF_SEL_EVENT_31 = 0x0000001f, 14052 GCVML2_SPM_PERF_SEL_EVENT_32 = 0x00000020, 14053 GCVML2_SPM_PERF_SEL_EVENT_33 = 0x00000021, 14054 GCVML2_SPM_PERF_SEL_EVENT_34 = 0x00000022, 14055 GCVML2_SPM_PERF_SEL_EVENT_35 = 0x00000023, 14056 GCVML2_SPM_PERF_SEL_EVENT_36 = 0x00000024, 14057 GCVML2_SPM_PERF_SEL_EVENT_37 = 0x00000025, 14058 GCVML2_SPM_PERF_SEL_EVENT_38 = 0x00000026, 14059 GCVML2_SPM_PERF_SEL_EVENT_39 = 0x00000027, 14060 GCVML2_SPM_PERF_SEL_EVENT_40 = 0x00000028, 14061 GCVML2_SPM_PERF_SEL_EVENT_41 = 0x00000029, 14062 GCVML2_SPM_PERF_SEL_EVENT_42 = 0x0000002a, 14063 GCVML2_SPM_PERF_SEL_EVENT_43 = 0x0000002b, 14064 GCVML2_SPM_PERF_SEL_EVENT_44 = 0x0000002c, 14065 GCVML2_SPM_PERF_SEL_EVENT_45 = 0x0000002d, 14066 GCVML2_SPM_PERF_SEL_EVENT_46 = 0x0000002e, 14067 GCVML2_SPM_PERF_SEL_EVENT_47 = 0x0000002f, 14068 GCVML2_SPM_PERF_SEL_EVENT_48 = 0x00000030, 14069 GCVML2_SPM_PERF_SEL_EVENT_49 = 0x00000031, 14070 GCVML2_SPM_PERF_SEL_EVENT_50 = 0x00000032, 14071 GCVML2_SPM_PERF_SEL_EVENT_51 = 0x00000033, 14072 GCVML2_SPM_PERF_SEL_EVENT_52 = 0x00000034, 14073 GCVML2_SPM_PERF_SEL_EVENT_53 = 0x00000035, 14074 GCVML2_SPM_PERF_SEL_EVENT_54 = 0x00000036, 14075 GCVML2_SPM_PERF_SEL_EVENT_55 = 0x00000037, 14076 GCVML2_SPM_PERF_SEL_EVENT_56 = 0x00000038, 14077 GCVML2_SPM_PERF_SEL_EVENT_57 = 0x00000039, 14078 GCVML2_SPM_PERF_SEL_EVENT_58 = 0x0000003a, 14079 GCVML2_SPM_PERF_SEL_EVENT_59 = 0x0000003b, 14080 GCVML2_SPM_PERF_SEL_EVENT_60 = 0x0000003c, 14081 GCVML2_SPM_PERF_SEL_EVENT_61 = 0x0000003d, 14082 GCVML2_SPM_PERF_SEL_EVENT_62 = 0x0000003e, 14083 GCVML2_SPM_PERF_SEL_EVENT_63 = 0x0000003f, 14084 GCVML2_SPM_PERF_SEL_EVENT_64 = 0x00000040, 14085 GCVML2_SPM_PERF_SEL_EVENT_65 = 0x00000041, 14086 GCVML2_SPM_PERF_SEL_EVENT_66 = 0x00000042, 14087 GCVML2_SPM_PERF_SEL_EVENT_67 = 0x00000043, 14088 GCVML2_SPM_PERF_SEL_EVENT_68 = 0x00000044, 14089 GCVML2_SPM_PERF_SEL_EVENT_69 = 0x00000045, 14090 GCVML2_SPM_PERF_SEL_EVENT_70 = 0x00000046, 14091 GCVML2_SPM_PERF_SEL_EVENT_71 = 0x00000047, 14092 GCVML2_SPM_PERF_SEL_EVENT_72 = 0x00000048, 14093 GCVML2_SPM_PERF_SEL_EVENT_73 = 0x00000049, 14094 GCVML2_SPM_PERF_SEL_EVENT_74 = 0x0000004a, 14095 GCVML2_SPM_PERF_SEL_EVENT_75 = 0x0000004b, 14096 GCVML2_SPM_PERF_SEL_EVENT_76 = 0x0000004c, 14097 GCVML2_SPM_PERF_SEL_EVENT_77 = 0x0000004d, 14098 GCVML2_SPM_PERF_SEL_EVENT_78 = 0x0000004e, 14099 GCVML2_SPM_PERF_SEL_EVENT_79 = 0x0000004f, 14100 GCVML2_SPM_PERF_SEL_EVENT_80 = 0x00000050, 14101 GCVML2_SPM_PERF_SEL_EVENT_81 = 0x00000051, 14102 GCVML2_SPM_PERF_SEL_EVENT_82 = 0x00000052, 14103 GCVML2_SPM_PERF_SEL_EVENT_83 = 0x00000053, 14104 GCVML2_SPM_PERF_SEL_EVENT_84 = 0x00000054, 14105 GCVML2_SPM_PERF_SEL_EVENT_85 = 0x00000055, 14106 GCVML2_SPM_PERF_SEL_EVENT_86 = 0x00000056, 14107 GCVML2_SPM_PERF_SEL_EVENT_87 = 0x00000057, 14108 GCVML2_SPM_PERF_SEL_EVENT_88 = 0x00000058, 14109 GCVML2_SPM_PERF_SEL_EVENT_89 = 0x00000059, 14110 GCVML2_SPM_PERF_SEL_EVENT_90 = 0x0000005a, 14111 } GCVML2_SPM_PERF_SEL; 14112 14113 /******************************************************* 14114 * GC_VML2PL Enums 14115 *******************************************************/ 14116 14117 /* 14118 * GCUTCL2_PERF_SEL enum 14119 */ 14120 14121 typedef enum GCUTCL2_PERF_SEL { 14122 GCUTCL2_PERF_SEL_EVENT_0 = 0x00000000, 14123 GCUTCL2_PERF_SEL_EVENT_1 = 0x00000001, 14124 GCUTCL2_PERF_SEL_EVENT_2 = 0x00000002, 14125 GCUTCL2_PERF_SEL_EVENT_3 = 0x00000003, 14126 GCUTCL2_PERF_SEL_EVENT_4 = 0x00000004, 14127 GCUTCL2_PERF_SEL_EVENT_5 = 0x00000005, 14128 GCUTCL2_PERF_SEL_EVENT_6 = 0x00000006, 14129 GCUTCL2_PERF_SEL_EVENT_7 = 0x00000007, 14130 GCUTCL2_PERF_SEL_EVENT_8 = 0x00000008, 14131 GCUTCL2_PERF_SEL_EVENT_9 = 0x00000009, 14132 GCUTCL2_PERF_SEL_EVENT_10 = 0x0000000a, 14133 GCUTCL2_PERF_SEL_EVENT_11 = 0x0000000b, 14134 GCUTCL2_PERF_SEL_EVENT_12 = 0x0000000c, 14135 GCUTCL2_PERF_SEL_EVENT_13 = 0x0000000d, 14136 GCUTCL2_PERF_SEL_EVENT_14 = 0x0000000e, 14137 GCUTCL2_PERF_SEL_EVENT_15 = 0x0000000f, 14138 GCUTCL2_PERF_SEL_EVENT_16 = 0x00000010, 14139 GCUTCL2_PERF_SEL_EVENT_17 = 0x00000011, 14140 GCUTCL2_PERF_SEL_EVENT_18 = 0x00000012, 14141 GCUTCL2_PERF_SEL_EVENT_19 = 0x00000013, 14142 GCUTCL2_PERF_SEL_EVENT_20 = 0x00000014, 14143 GCUTCL2_PERF_SEL_EVENT_21 = 0x00000015, 14144 GCUTCL2_PERF_SEL_EVENT_22 = 0x00000016, 14145 GCUTCL2_PERF_SEL_EVENT_23 = 0x00000017, 14146 GCUTCL2_PERF_SEL_EVENT_24 = 0x00000018, 14147 GCUTCL2_PERF_SEL_EVENT_25 = 0x00000019, 14148 GCUTCL2_PERF_SEL_EVENT_26 = 0x0000001a, 14149 GCUTCL2_PERF_SEL_EVENT_27 = 0x0000001b, 14150 GCUTCL2_PERF_SEL_EVENT_28 = 0x0000001c, 14151 GCUTCL2_PERF_SEL_EVENT_29 = 0x0000001d, 14152 GCUTCL2_PERF_SEL_EVENT_30 = 0x0000001e, 14153 GCUTCL2_PERF_SEL_EVENT_31 = 0x0000001f, 14154 GCUTCL2_PERF_SEL_EVENT_32 = 0x00000020, 14155 GCUTCL2_PERF_SEL_EVENT_33 = 0x00000021, 14156 GCUTCL2_PERF_SEL_EVENT_34 = 0x00000022, 14157 GCUTCL2_PERF_SEL_EVENT_35 = 0x00000023, 14158 GCUTCL2_PERF_SEL_EVENT_36 = 0x00000024, 14159 } GCUTCL2_PERF_SEL; 14160 14161 /* 14162 * GCVML2_PERF_SEL enum 14163 */ 14164 14165 typedef enum GCVML2_PERF_SEL { 14166 GCVML2_PERF_SEL_EVENT_0 = 0x00000000, 14167 GCVML2_PERF_SEL_EVENT_1 = 0x00000001, 14168 GCVML2_PERF_SEL_EVENT_2 = 0x00000002, 14169 GCVML2_PERF_SEL_EVENT_3 = 0x00000003, 14170 GCVML2_PERF_SEL_EVENT_4 = 0x00000004, 14171 GCVML2_PERF_SEL_EVENT_5 = 0x00000005, 14172 GCVML2_PERF_SEL_EVENT_6 = 0x00000006, 14173 GCVML2_PERF_SEL_EVENT_7 = 0x00000007, 14174 GCVML2_PERF_SEL_EVENT_8 = 0x00000008, 14175 GCVML2_PERF_SEL_EVENT_9 = 0x00000009, 14176 GCVML2_PERF_SEL_EVENT_10 = 0x0000000a, 14177 GCVML2_PERF_SEL_EVENT_11 = 0x0000000b, 14178 GCVML2_PERF_SEL_EVENT_12 = 0x0000000c, 14179 GCVML2_PERF_SEL_EVENT_13 = 0x0000000d, 14180 GCVML2_PERF_SEL_EVENT_14 = 0x0000000e, 14181 GCVML2_PERF_SEL_EVENT_15 = 0x0000000f, 14182 GCVML2_PERF_SEL_EVENT_16 = 0x00000010, 14183 GCVML2_PERF_SEL_EVENT_17 = 0x00000011, 14184 GCVML2_PERF_SEL_EVENT_18 = 0x00000012, 14185 GCVML2_PERF_SEL_EVENT_19 = 0x00000013, 14186 GCVML2_PERF_SEL_EVENT_20 = 0x00000014, 14187 GCVML2_PERF_SEL_EVENT_21 = 0x00000015, 14188 GCVML2_PERF_SEL_EVENT_22 = 0x00000016, 14189 GCVML2_PERF_SEL_EVENT_23 = 0x00000017, 14190 GCVML2_PERF_SEL_EVENT_24 = 0x00000018, 14191 GCVML2_PERF_SEL_EVENT_25 = 0x00000019, 14192 GCVML2_PERF_SEL_EVENT_26 = 0x0000001a, 14193 GCVML2_PERF_SEL_EVENT_27 = 0x0000001b, 14194 GCVML2_PERF_SEL_EVENT_28 = 0x0000001c, 14195 GCVML2_PERF_SEL_EVENT_29 = 0x0000001d, 14196 GCVML2_PERF_SEL_EVENT_30 = 0x0000001e, 14197 GCVML2_PERF_SEL_EVENT_31 = 0x0000001f, 14198 GCVML2_PERF_SEL_EVENT_32 = 0x00000020, 14199 GCVML2_PERF_SEL_EVENT_33 = 0x00000021, 14200 GCVML2_PERF_SEL_EVENT_34 = 0x00000022, 14201 GCVML2_PERF_SEL_EVENT_35 = 0x00000023, 14202 GCVML2_PERF_SEL_EVENT_36 = 0x00000024, 14203 GCVML2_PERF_SEL_EVENT_37 = 0x00000025, 14204 GCVML2_PERF_SEL_EVENT_38 = 0x00000026, 14205 GCVML2_PERF_SEL_EVENT_39 = 0x00000027, 14206 GCVML2_PERF_SEL_EVENT_40 = 0x00000028, 14207 GCVML2_PERF_SEL_EVENT_41 = 0x00000029, 14208 GCVML2_PERF_SEL_EVENT_42 = 0x0000002a, 14209 GCVML2_PERF_SEL_EVENT_43 = 0x0000002b, 14210 GCVML2_PERF_SEL_EVENT_44 = 0x0000002c, 14211 GCVML2_PERF_SEL_EVENT_45 = 0x0000002d, 14212 GCVML2_PERF_SEL_EVENT_46 = 0x0000002e, 14213 GCVML2_PERF_SEL_EVENT_47 = 0x0000002f, 14214 GCVML2_PERF_SEL_EVENT_48 = 0x00000030, 14215 GCVML2_PERF_SEL_EVENT_49 = 0x00000031, 14216 GCVML2_PERF_SEL_EVENT_50 = 0x00000032, 14217 GCVML2_PERF_SEL_EVENT_51 = 0x00000033, 14218 GCVML2_PERF_SEL_EVENT_52 = 0x00000034, 14219 GCVML2_PERF_SEL_EVENT_53 = 0x00000035, 14220 GCVML2_PERF_SEL_EVENT_54 = 0x00000036, 14221 GCVML2_PERF_SEL_EVENT_55 = 0x00000037, 14222 GCVML2_PERF_SEL_EVENT_56 = 0x00000038, 14223 GCVML2_PERF_SEL_EVENT_57 = 0x00000039, 14224 GCVML2_PERF_SEL_EVENT_58 = 0x0000003a, 14225 GCVML2_PERF_SEL_EVENT_59 = 0x0000003b, 14226 GCVML2_PERF_SEL_EVENT_60 = 0x0000003c, 14227 GCVML2_PERF_SEL_EVENT_61 = 0x0000003d, 14228 GCVML2_PERF_SEL_EVENT_62 = 0x0000003e, 14229 GCVML2_PERF_SEL_EVENT_63 = 0x0000003f, 14230 GCVML2_PERF_SEL_EVENT_64 = 0x00000040, 14231 GCVML2_PERF_SEL_EVENT_65 = 0x00000041, 14232 GCVML2_PERF_SEL_EVENT_66 = 0x00000042, 14233 GCVML2_PERF_SEL_EVENT_67 = 0x00000043, 14234 GCVML2_PERF_SEL_EVENT_68 = 0x00000044, 14235 GCVML2_PERF_SEL_EVENT_69 = 0x00000045, 14236 GCVML2_PERF_SEL_EVENT_70 = 0x00000046, 14237 GCVML2_PERF_SEL_EVENT_71 = 0x00000047, 14238 GCVML2_PERF_SEL_EVENT_72 = 0x00000048, 14239 GCVML2_PERF_SEL_EVENT_73 = 0x00000049, 14240 GCVML2_PERF_SEL_EVENT_74 = 0x0000004a, 14241 GCVML2_PERF_SEL_EVENT_75 = 0x0000004b, 14242 GCVML2_PERF_SEL_EVENT_76 = 0x0000004c, 14243 GCVML2_PERF_SEL_EVENT_77 = 0x0000004d, 14244 GCVML2_PERF_SEL_EVENT_78 = 0x0000004e, 14245 GCVML2_PERF_SEL_EVENT_79 = 0x0000004f, 14246 GCVML2_PERF_SEL_EVENT_80 = 0x00000050, 14247 GCVML2_PERF_SEL_EVENT_81 = 0x00000051, 14248 GCVML2_PERF_SEL_EVENT_82 = 0x00000052, 14249 GCVML2_PERF_SEL_EVENT_83 = 0x00000053, 14250 GCVML2_PERF_SEL_EVENT_84 = 0x00000054, 14251 GCVML2_PERF_SEL_EVENT_85 = 0x00000055, 14252 GCVML2_PERF_SEL_EVENT_86 = 0x00000056, 14253 GCVML2_PERF_SEL_EVENT_87 = 0x00000057, 14254 GCVML2_PERF_SEL_EVENT_88 = 0x00000058, 14255 GCVML2_PERF_SEL_EVENT_89 = 0x00000059, 14256 GCVML2_PERF_SEL_EVENT_90 = 0x0000005a, 14257 } GCVML2_PERF_SEL; 14258 14259 /******************************************************* 14260 * CB Enums 14261 *******************************************************/ 14262 14263 /* 14264 * BlendOp enum 14265 */ 14266 14267 typedef enum BlendOp { 14268 BLEND_ZERO = 0x00000000, 14269 BLEND_ONE = 0x00000001, 14270 BLEND_SRC_COLOR = 0x00000002, 14271 BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, 14272 BLEND_SRC_ALPHA = 0x00000004, 14273 BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, 14274 BLEND_DST_ALPHA = 0x00000006, 14275 BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, 14276 BLEND_DST_COLOR = 0x00000008, 14277 BLEND_ONE_MINUS_DST_COLOR = 0x00000009, 14278 BLEND_SRC_ALPHA_SATURATE = 0x0000000a, 14279 BLEND_CONSTANT_COLOR = 0x0000000b, 14280 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000c, 14281 BLEND_SRC1_COLOR = 0x0000000d, 14282 BLEND_INV_SRC1_COLOR = 0x0000000e, 14283 BLEND_SRC1_ALPHA = 0x0000000f, 14284 BLEND_INV_SRC1_ALPHA = 0x00000010, 14285 BLEND_CONSTANT_ALPHA = 0x00000011, 14286 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000012, 14287 } BlendOp; 14288 14289 /* 14290 * BlendOpt enum 14291 */ 14292 14293 typedef enum BlendOpt { 14294 FORCE_OPT_AUTO = 0x00000000, 14295 FORCE_OPT_DISABLE = 0x00000001, 14296 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, 14297 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, 14298 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, 14299 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, 14300 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, 14301 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, 14302 } BlendOpt; 14303 14304 /* 14305 * CBMode enum 14306 */ 14307 14308 typedef enum CBMode { 14309 CB_DISABLE = 0x00000000, 14310 CB_NORMAL = 0x00000001, 14311 CB_ELIMINATE_FAST_CLEAR = 0x00000002, 14312 CB_DCC_DECOMPRESS = 0x00000003, 14313 CB_RESERVED = 0x00000004, 14314 } CBMode; 14315 14316 /* 14317 * CBPerfClearFilterSel enum 14318 */ 14319 14320 typedef enum CBPerfClearFilterSel { 14321 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, 14322 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, 14323 } CBPerfClearFilterSel; 14324 14325 /* 14326 * CBPerfOpFilterSel enum 14327 */ 14328 14329 typedef enum CBPerfOpFilterSel { 14330 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, 14331 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, 14332 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, 14333 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, 14334 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, 14335 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, 14336 } CBPerfOpFilterSel; 14337 14338 /* 14339 * CBPerfSel enum 14340 */ 14341 14342 typedef enum CBPerfSel { 14343 CB_PERF_SEL_BUSY = 0x00000001, 14344 CB_PERF_SEL_DRAWN_BUSY = 0x00000002, 14345 CB_PERF_SEL_DRAWN_PIXEL = 0x00000003, 14346 CB_PERF_SEL_DRAWN_QUAD = 0x00000004, 14347 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000005, 14348 CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 0x0000000f, 14349 CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 0x00000010, 14350 CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 0x00000011, 14351 CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 0x00000012, 14352 CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST = 0x00000015, 14353 CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT = 0x00000016, 14354 CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST = 0x00000017, 14355 CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES = 0x00000018, 14356 CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN = 0x00000019, 14357 CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT = 0x0000001a, 14358 CB_PERF_SEL_EVENT = 0x00000032, 14359 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000033, 14360 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000034, 14361 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000035, 14362 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000036, 14363 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000037, 14364 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000038, 14365 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000039, 14366 CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 0x0000003a, 14367 CB_PERF_SEL_STATIC_CLOCK_EN = 0x0000003c, 14368 CB_PERF_SEL_PERFMON_CLOCK_EN = 0x0000003d, 14369 CB_PERF_SEL_BLEND_CLOCK_EN = 0x0000003e, 14370 CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 0x0000003f, 14371 CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 0x00000040, 14372 CB_PERF_SEL_GRBM_CLOCK_EN = 0x00000041, 14373 CB_PERF_SEL_MEMARB_CLOCK_EN = 0x00000042, 14374 CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 0x00000043, 14375 CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 0x00000044, 14376 CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 0x00000045, 14377 CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 0x00000046, 14378 CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 0x00000047, 14379 CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 0x00000048, 14380 CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 0x00000049, 14381 CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x0000004a, 14382 CB_PERF_SEL_EVENTS_CLK_EN = 0x0000004b, 14383 CB_PERF_SEL_CC_TAG_HIT = 0x00000050, 14384 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000051, 14385 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000052, 14386 CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 0x00000053, 14387 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000058, 14388 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000059, 14389 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x0000005a, 14390 CB_PERF_SEL_CC_CACHE_STALL = 0x0000005b, 14391 CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000005c, 14392 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000005d, 14393 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000005e, 14394 CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED = 0x0000005f, 14395 CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED = 0x00000060, 14396 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000061, 14397 CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL = 0x00000062, 14398 CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC = 0x00000063, 14399 CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC = 0x00000064, 14400 CB_PERF_SEL_CCC_FREE_WAYS_PANIC = 0x00000065, 14401 CB_PERF_SEL_CCC_SKID_FIFO_FULL = 0x00000066, 14402 CB_PERF_SEL_CCC_SKID_FIFO_STALL = 0x00000067, 14403 CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL = 0x00000068, 14404 CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL = 0x00000069, 14405 CB_PERF_SEL_CCC_FREE_WAYS_STALL = 0x0000006a, 14406 CB_PERF_SEL_BE_SRCFIFO_FULL = 0x0000006e, 14407 CB_PERF_SEL_BE_RDLATFIFO_FULL = 0x0000006f, 14408 CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000070, 14409 CB_PERF_SEL_CC_QUADFRAG_VALID_READY = 0x00000071, 14410 CB_PERF_SEL_CC_QUADFRAG_VALID_READYB = 0x00000072, 14411 CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY = 0x00000073, 14412 CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB = 0x00000074, 14413 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY = 0x00000076, 14414 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB = 0x00000077, 14415 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY = 0x00000078, 14416 CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB = 0x00000079, 14417 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x00000096, 14418 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x00000097, 14419 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x00000098, 14420 CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000b4, 14421 CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000b5, 14422 CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000b6, 14423 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000b7, 14424 CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 0x000000b8, 14425 CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS = 0x000000b9, 14426 CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE = 0x000000ba, 14427 CB_PERF_SEL_BLEND_RAW_HAZARD_STALL = 0x000000bb, 14428 CB_PERF_SEL_BE_CS_FILLRATE_1X2 = 0x000000be, 14429 CB_PERF_SEL_BE_CS_FILLRATE_2X1 = 0x000000bf, 14430 CB_PERF_SEL_BE_CS_FILLRATE_2X2 = 0x000000c0, 14431 CB_PERF_SEL_FORMAT_IS_32_R = 0x000000fa, 14432 CB_PERF_SEL_FORMAT_IS_32_AR = 0x000000fb, 14433 CB_PERF_SEL_FORMAT_IS_32_GR = 0x000000fc, 14434 CB_PERF_SEL_FORMAT_IS_32_ABGR = 0x000000fd, 14435 CB_PERF_SEL_FORMAT_IS_FP16_ABGR = 0x000000fe, 14436 CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR = 0x000000ff, 14437 CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR = 0x00000100, 14438 CB_PERF_SEL_FORMAT_IS_32BPP_8PIX = 0x00000101, 14439 CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX = 0x00000102, 14440 CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX = 0x00000103, 14441 CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX = 0x00000104, 14442 CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT = 0x00000105, 14443 CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS = 0x00000106, 14444 CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS = 0x00000107, 14445 CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS = 0x00000108, 14446 CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS = 0x00000109, 14447 CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS = 0x0000010a, 14448 CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS = 0x0000010b, 14449 CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST = 0x0000010c, 14450 CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS = 0x0000010d, 14451 CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS = 0x0000010e, 14452 CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x0000010f, 14453 CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE = 0x00000110, 14454 CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x00000111, 14455 CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x00000112, 14456 CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x00000113, 14457 CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x00000114, 14458 CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x00000115, 14459 CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x00000116, 14460 CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x00000117, 14461 CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x00000118, 14462 CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x00000119, 14463 CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x0000011a, 14464 CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x0000011b, 14465 CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x0000011c, 14466 CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x0000011d, 14467 CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x0000011e, 14468 CB_PERF_SEL_EXPORT_READS_FRAGMENT_0 = 0x0000011f, 14469 CB_PERF_SEL_EXPORT_READS_FRAGMENT_1 = 0x00000120, 14470 CB_PERF_SEL_EXPORT_READS_FRAGMENT_2 = 0x00000121, 14471 CB_PERF_SEL_EXPORT_READS_FRAGMENT_3 = 0x00000122, 14472 CB_PERF_SEL_EXPORT_READS_FRAGMENT_4 = 0x00000123, 14473 CB_PERF_SEL_EXPORT_READS_FRAGMENT_5 = 0x00000124, 14474 CB_PERF_SEL_EXPORT_READS_FRAGMENT_6 = 0x00000125, 14475 CB_PERF_SEL_EXPORT_READS_FRAGMENT_7 = 0x00000126, 14476 CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT = 0x00000127, 14477 CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS = 0x00000128, 14478 CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS = 0x00000129, 14479 CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS = 0x0000012a, 14480 CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS = 0x0000012b, 14481 CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS = 0x0000012c, 14482 CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS = 0x0000012d, 14483 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0 = 0x0000012e, 14484 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1 = 0x0000012f, 14485 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2 = 0x00000130, 14486 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3 = 0x00000131, 14487 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4 = 0x00000132, 14488 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5 = 0x00000133, 14489 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6 = 0x00000134, 14490 CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7 = 0x00000135, 14491 CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID = 0x00000136, 14492 CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL = 0x00000137, 14493 CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK = 0x00000138, 14494 CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000139, 14495 } CBPerfSel; 14496 14497 /* 14498 * CombFunc enum 14499 */ 14500 14501 typedef enum CombFunc { 14502 COMB_DST_PLUS_SRC = 0x00000000, 14503 COMB_SRC_MINUS_DST = 0x00000001, 14504 COMB_MIN_DST_SRC = 0x00000002, 14505 COMB_MAX_DST_SRC = 0x00000003, 14506 COMB_DST_MINUS_SRC = 0x00000004, 14507 } CombFunc; 14508 14509 /* 14510 * MemArbMode enum 14511 */ 14512 14513 typedef enum MemArbMode { 14514 MEM_ARB_MODE_FIXED = 0x00000000, 14515 MEM_ARB_MODE_AGE = 0x00000001, 14516 MEM_ARB_MODE_WEIGHT = 0x00000002, 14517 MEM_ARB_MODE_BOTH = 0x00000003, 14518 } MemArbMode; 14519 14520 /******************************************************* 14521 * PH Enums 14522 *******************************************************/ 14523 14524 /* 14525 * PH_PERFCNT_SEL enum 14526 */ 14527 14528 typedef enum PH_PERFCNT_SEL { 14529 PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0x00000000, 14530 PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001, 14531 PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002, 14532 PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003, 14533 PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 0x00000004, 14534 PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005, 14535 PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006, 14536 PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007, 14537 PH_PERF_SEL_SC0_ARB_BUSY = 0x00000008, 14538 PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 0x00000009, 14539 PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a, 14540 PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 0x0000000b, 14541 PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c, 14542 PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 0x0000000d, 14543 PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e, 14544 PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f, 14545 PH_PERF_SEL_SC0_SEND = 0x00000010, 14546 PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011, 14547 PH_PERF_SEL_SC0_CREDIT_AT_MAX = 0x00000012, 14548 PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013, 14549 PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014, 14550 PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015, 14551 PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016, 14552 PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017, 14553 PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 0x00000018, 14554 PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 0x00000019, 14555 PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 0x0000001a, 14556 PH_PERF_SEL_SC0_PA0_FIFO_FULL = 0x0000001b, 14557 PH_PERF_SEL_SC0_PA0_NULL_WE = 0x0000001c, 14558 PH_PERF_SEL_SC0_PA0_EVENT_WE = 0x0000001d, 14559 PH_PERF_SEL_SC0_PA0_FPOV_WE = 0x0000001e, 14560 PH_PERF_SEL_SC0_PA0_FPOP_WE = 0x0000001f, 14561 PH_PERF_SEL_SC0_PA0_EOP_WE = 0x00000020, 14562 PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021, 14563 PH_PERF_SEL_SC0_PA0_EOPG_WE = 0x00000022, 14564 PH_PERF_SEL_SC0_PA0_DEALLOC_WE = 0x00000023, 14565 PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 0x00000024, 14566 PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 0x00000025, 14567 PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 0x00000026, 14568 PH_PERF_SEL_SC0_PA1_FIFO_FULL = 0x00000027, 14569 PH_PERF_SEL_SC0_PA1_NULL_WE = 0x00000028, 14570 PH_PERF_SEL_SC0_PA1_EVENT_WE = 0x00000029, 14571 PH_PERF_SEL_SC0_PA1_FPOV_WE = 0x0000002a, 14572 PH_PERF_SEL_SC0_PA1_FPOP_WE = 0x0000002b, 14573 PH_PERF_SEL_SC0_PA1_EOP_WE = 0x0000002c, 14574 PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d, 14575 PH_PERF_SEL_SC0_PA1_EOPG_WE = 0x0000002e, 14576 PH_PERF_SEL_SC0_PA1_DEALLOC_WE = 0x0000002f, 14577 PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 0x00000030, 14578 PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 0x00000031, 14579 PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 0x00000032, 14580 PH_PERF_SEL_SC0_PA2_FIFO_FULL = 0x00000033, 14581 PH_PERF_SEL_SC0_PA2_NULL_WE = 0x00000034, 14582 PH_PERF_SEL_SC0_PA2_EVENT_WE = 0x00000035, 14583 PH_PERF_SEL_SC0_PA2_FPOV_WE = 0x00000036, 14584 PH_PERF_SEL_SC0_PA2_FPOP_WE = 0x00000037, 14585 PH_PERF_SEL_SC0_PA2_EOP_WE = 0x00000038, 14586 PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039, 14587 PH_PERF_SEL_SC0_PA2_EOPG_WE = 0x0000003a, 14588 PH_PERF_SEL_SC0_PA2_DEALLOC_WE = 0x0000003b, 14589 PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 0x0000003c, 14590 PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 0x0000003d, 14591 PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 0x0000003e, 14592 PH_PERF_SEL_SC0_PA3_FIFO_FULL = 0x0000003f, 14593 PH_PERF_SEL_SC0_PA3_NULL_WE = 0x00000040, 14594 PH_PERF_SEL_SC0_PA3_EVENT_WE = 0x00000041, 14595 PH_PERF_SEL_SC0_PA3_FPOV_WE = 0x00000042, 14596 PH_PERF_SEL_SC0_PA3_FPOP_WE = 0x00000043, 14597 PH_PERF_SEL_SC0_PA3_EOP_WE = 0x00000044, 14598 PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045, 14599 PH_PERF_SEL_SC0_PA3_EOPG_WE = 0x00000046, 14600 PH_PERF_SEL_SC0_PA3_DEALLOC_WE = 0x00000047, 14601 PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 0x00000048, 14602 PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 0x00000049, 14603 PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 0x0000004a, 14604 PH_PERF_SEL_SC0_PA4_FIFO_FULL = 0x0000004b, 14605 PH_PERF_SEL_SC0_PA4_NULL_WE = 0x0000004c, 14606 PH_PERF_SEL_SC0_PA4_EVENT_WE = 0x0000004d, 14607 PH_PERF_SEL_SC0_PA4_FPOV_WE = 0x0000004e, 14608 PH_PERF_SEL_SC0_PA4_FPOP_WE = 0x0000004f, 14609 PH_PERF_SEL_SC0_PA4_EOP_WE = 0x00000050, 14610 PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051, 14611 PH_PERF_SEL_SC0_PA4_EOPG_WE = 0x00000052, 14612 PH_PERF_SEL_SC0_PA4_DEALLOC_WE = 0x00000053, 14613 PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 0x00000054, 14614 PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 0x00000055, 14615 PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 0x00000056, 14616 PH_PERF_SEL_SC0_PA5_FIFO_FULL = 0x00000057, 14617 PH_PERF_SEL_SC0_PA5_NULL_WE = 0x00000058, 14618 PH_PERF_SEL_SC0_PA5_EVENT_WE = 0x00000059, 14619 PH_PERF_SEL_SC0_PA5_FPOV_WE = 0x0000005a, 14620 PH_PERF_SEL_SC0_PA5_FPOP_WE = 0x0000005b, 14621 PH_PERF_SEL_SC0_PA5_EOP_WE = 0x0000005c, 14622 PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d, 14623 PH_PERF_SEL_SC0_PA5_EOPG_WE = 0x0000005e, 14624 PH_PERF_SEL_SC0_PA5_DEALLOC_WE = 0x0000005f, 14625 PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 0x00000060, 14626 PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 0x00000061, 14627 PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 0x00000062, 14628 PH_PERF_SEL_SC0_PA6_FIFO_FULL = 0x00000063, 14629 PH_PERF_SEL_SC0_PA6_NULL_WE = 0x00000064, 14630 PH_PERF_SEL_SC0_PA6_EVENT_WE = 0x00000065, 14631 PH_PERF_SEL_SC0_PA6_FPOV_WE = 0x00000066, 14632 PH_PERF_SEL_SC0_PA6_FPOP_WE = 0x00000067, 14633 PH_PERF_SEL_SC0_PA6_EOP_WE = 0x00000068, 14634 PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069, 14635 PH_PERF_SEL_SC0_PA6_EOPG_WE = 0x0000006a, 14636 PH_PERF_SEL_SC0_PA6_DEALLOC_WE = 0x0000006b, 14637 PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 0x0000006c, 14638 PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 0x0000006d, 14639 PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 0x0000006e, 14640 PH_PERF_SEL_SC0_PA7_FIFO_FULL = 0x0000006f, 14641 PH_PERF_SEL_SC0_PA7_NULL_WE = 0x00000070, 14642 PH_PERF_SEL_SC0_PA7_EVENT_WE = 0x00000071, 14643 PH_PERF_SEL_SC0_PA7_FPOV_WE = 0x00000072, 14644 PH_PERF_SEL_SC0_PA7_FPOP_WE = 0x00000073, 14645 PH_PERF_SEL_SC0_PA7_EOP_WE = 0x00000074, 14646 PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075, 14647 PH_PERF_SEL_SC0_PA7_EOPG_WE = 0x00000076, 14648 PH_PERF_SEL_SC0_PA7_DEALLOC_WE = 0x00000077, 14649 PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 0x00000078, 14650 PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079, 14651 PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a, 14652 PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b, 14653 PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c, 14654 PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d, 14655 PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e, 14656 PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f, 14657 PH_PERF_SEL_SC1_ARB_BUSY = 0x00000080, 14658 PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 0x00000081, 14659 PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082, 14660 PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 0x00000083, 14661 PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084, 14662 PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 0x00000085, 14663 PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086, 14664 PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 0x00000087, 14665 PH_PERF_SEL_SC1_SEND = 0x00000088, 14666 PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089, 14667 PH_PERF_SEL_SC1_CREDIT_AT_MAX = 0x0000008a, 14668 PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b, 14669 PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c, 14670 PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d, 14671 PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e, 14672 PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f, 14673 PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 0x00000090, 14674 PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 0x00000091, 14675 PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 0x00000092, 14676 PH_PERF_SEL_SC1_PA0_FIFO_FULL = 0x00000093, 14677 PH_PERF_SEL_SC1_PA0_NULL_WE = 0x00000094, 14678 PH_PERF_SEL_SC1_PA0_EVENT_WE = 0x00000095, 14679 PH_PERF_SEL_SC1_PA0_FPOV_WE = 0x00000096, 14680 PH_PERF_SEL_SC1_PA0_FPOP_WE = 0x00000097, 14681 PH_PERF_SEL_SC1_PA0_EOP_WE = 0x00000098, 14682 PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099, 14683 PH_PERF_SEL_SC1_PA0_EOPG_WE = 0x0000009a, 14684 PH_PERF_SEL_SC1_PA0_DEALLOC_WE = 0x0000009b, 14685 PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 0x0000009c, 14686 PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 0x0000009d, 14687 PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 0x0000009e, 14688 PH_PERF_SEL_SC1_PA1_FIFO_FULL = 0x0000009f, 14689 PH_PERF_SEL_SC1_PA1_NULL_WE = 0x000000a0, 14690 PH_PERF_SEL_SC1_PA1_EVENT_WE = 0x000000a1, 14691 PH_PERF_SEL_SC1_PA1_FPOV_WE = 0x000000a2, 14692 PH_PERF_SEL_SC1_PA1_FPOP_WE = 0x000000a3, 14693 PH_PERF_SEL_SC1_PA1_EOP_WE = 0x000000a4, 14694 PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5, 14695 PH_PERF_SEL_SC1_PA1_EOPG_WE = 0x000000a6, 14696 PH_PERF_SEL_SC1_PA1_DEALLOC_WE = 0x000000a7, 14697 PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 0x000000a8, 14698 PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 0x000000a9, 14699 PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 0x000000aa, 14700 PH_PERF_SEL_SC1_PA2_FIFO_FULL = 0x000000ab, 14701 PH_PERF_SEL_SC1_PA2_NULL_WE = 0x000000ac, 14702 PH_PERF_SEL_SC1_PA2_EVENT_WE = 0x000000ad, 14703 PH_PERF_SEL_SC1_PA2_FPOV_WE = 0x000000ae, 14704 PH_PERF_SEL_SC1_PA2_FPOP_WE = 0x000000af, 14705 PH_PERF_SEL_SC1_PA2_EOP_WE = 0x000000b0, 14706 PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1, 14707 PH_PERF_SEL_SC1_PA2_EOPG_WE = 0x000000b2, 14708 PH_PERF_SEL_SC1_PA2_DEALLOC_WE = 0x000000b3, 14709 PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 0x000000b4, 14710 PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 0x000000b5, 14711 PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 0x000000b6, 14712 PH_PERF_SEL_SC1_PA3_FIFO_FULL = 0x000000b7, 14713 PH_PERF_SEL_SC1_PA3_NULL_WE = 0x000000b8, 14714 PH_PERF_SEL_SC1_PA3_EVENT_WE = 0x000000b9, 14715 PH_PERF_SEL_SC1_PA3_FPOV_WE = 0x000000ba, 14716 PH_PERF_SEL_SC1_PA3_FPOP_WE = 0x000000bb, 14717 PH_PERF_SEL_SC1_PA3_EOP_WE = 0x000000bc, 14718 PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd, 14719 PH_PERF_SEL_SC1_PA3_EOPG_WE = 0x000000be, 14720 PH_PERF_SEL_SC1_PA3_DEALLOC_WE = 0x000000bf, 14721 PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 0x000000c0, 14722 PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 0x000000c1, 14723 PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 0x000000c2, 14724 PH_PERF_SEL_SC1_PA4_FIFO_FULL = 0x000000c3, 14725 PH_PERF_SEL_SC1_PA4_NULL_WE = 0x000000c4, 14726 PH_PERF_SEL_SC1_PA4_EVENT_WE = 0x000000c5, 14727 PH_PERF_SEL_SC1_PA4_FPOV_WE = 0x000000c6, 14728 PH_PERF_SEL_SC1_PA4_FPOP_WE = 0x000000c7, 14729 PH_PERF_SEL_SC1_PA4_EOP_WE = 0x000000c8, 14730 PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9, 14731 PH_PERF_SEL_SC1_PA4_EOPG_WE = 0x000000ca, 14732 PH_PERF_SEL_SC1_PA4_DEALLOC_WE = 0x000000cb, 14733 PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 0x000000cc, 14734 PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 0x000000cd, 14735 PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 0x000000ce, 14736 PH_PERF_SEL_SC1_PA5_FIFO_FULL = 0x000000cf, 14737 PH_PERF_SEL_SC1_PA5_NULL_WE = 0x000000d0, 14738 PH_PERF_SEL_SC1_PA5_EVENT_WE = 0x000000d1, 14739 PH_PERF_SEL_SC1_PA5_FPOV_WE = 0x000000d2, 14740 PH_PERF_SEL_SC1_PA5_FPOP_WE = 0x000000d3, 14741 PH_PERF_SEL_SC1_PA5_EOP_WE = 0x000000d4, 14742 PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5, 14743 PH_PERF_SEL_SC1_PA5_EOPG_WE = 0x000000d6, 14744 PH_PERF_SEL_SC1_PA5_DEALLOC_WE = 0x000000d7, 14745 PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 0x000000d8, 14746 PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 0x000000d9, 14747 PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 0x000000da, 14748 PH_PERF_SEL_SC1_PA6_FIFO_FULL = 0x000000db, 14749 PH_PERF_SEL_SC1_PA6_NULL_WE = 0x000000dc, 14750 PH_PERF_SEL_SC1_PA6_EVENT_WE = 0x000000dd, 14751 PH_PERF_SEL_SC1_PA6_FPOV_WE = 0x000000de, 14752 PH_PERF_SEL_SC1_PA6_FPOP_WE = 0x000000df, 14753 PH_PERF_SEL_SC1_PA6_EOP_WE = 0x000000e0, 14754 PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1, 14755 PH_PERF_SEL_SC1_PA6_EOPG_WE = 0x000000e2, 14756 PH_PERF_SEL_SC1_PA6_DEALLOC_WE = 0x000000e3, 14757 PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 0x000000e4, 14758 PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 0x000000e5, 14759 PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 0x000000e6, 14760 PH_PERF_SEL_SC1_PA7_FIFO_FULL = 0x000000e7, 14761 PH_PERF_SEL_SC1_PA7_NULL_WE = 0x000000e8, 14762 PH_PERF_SEL_SC1_PA7_EVENT_WE = 0x000000e9, 14763 PH_PERF_SEL_SC1_PA7_FPOV_WE = 0x000000ea, 14764 PH_PERF_SEL_SC1_PA7_FPOP_WE = 0x000000eb, 14765 PH_PERF_SEL_SC1_PA7_EOP_WE = 0x000000ec, 14766 PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed, 14767 PH_PERF_SEL_SC1_PA7_EOPG_WE = 0x000000ee, 14768 PH_PERF_SEL_SC1_PA7_DEALLOC_WE = 0x000000ef, 14769 PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 0x000000f0, 14770 PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1, 14771 PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2, 14772 PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3, 14773 PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4, 14774 PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5, 14775 PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6, 14776 PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7, 14777 PH_PERF_SEL_SC2_ARB_BUSY = 0x000000f8, 14778 PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 0x000000f9, 14779 PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa, 14780 PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 0x000000fb, 14781 PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc, 14782 PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 0x000000fd, 14783 PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe, 14784 PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff, 14785 PH_PERF_SEL_SC2_SEND = 0x00000100, 14786 PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101, 14787 PH_PERF_SEL_SC2_CREDIT_AT_MAX = 0x00000102, 14788 PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103, 14789 PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104, 14790 PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105, 14791 PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106, 14792 PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107, 14793 PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 0x00000108, 14794 PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 0x00000109, 14795 PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 0x0000010a, 14796 PH_PERF_SEL_SC2_PA0_FIFO_FULL = 0x0000010b, 14797 PH_PERF_SEL_SC2_PA0_NULL_WE = 0x0000010c, 14798 PH_PERF_SEL_SC2_PA0_EVENT_WE = 0x0000010d, 14799 PH_PERF_SEL_SC2_PA0_FPOV_WE = 0x0000010e, 14800 PH_PERF_SEL_SC2_PA0_FPOP_WE = 0x0000010f, 14801 PH_PERF_SEL_SC2_PA0_EOP_WE = 0x00000110, 14802 PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111, 14803 PH_PERF_SEL_SC2_PA0_EOPG_WE = 0x00000112, 14804 PH_PERF_SEL_SC2_PA0_DEALLOC_WE = 0x00000113, 14805 PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 0x00000114, 14806 PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 0x00000115, 14807 PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 0x00000116, 14808 PH_PERF_SEL_SC2_PA1_FIFO_FULL = 0x00000117, 14809 PH_PERF_SEL_SC2_PA1_NULL_WE = 0x00000118, 14810 PH_PERF_SEL_SC2_PA1_EVENT_WE = 0x00000119, 14811 PH_PERF_SEL_SC2_PA1_FPOV_WE = 0x0000011a, 14812 PH_PERF_SEL_SC2_PA1_FPOP_WE = 0x0000011b, 14813 PH_PERF_SEL_SC2_PA1_EOP_WE = 0x0000011c, 14814 PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d, 14815 PH_PERF_SEL_SC2_PA1_EOPG_WE = 0x0000011e, 14816 PH_PERF_SEL_SC2_PA1_DEALLOC_WE = 0x0000011f, 14817 PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 0x00000120, 14818 PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 0x00000121, 14819 PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 0x00000122, 14820 PH_PERF_SEL_SC2_PA2_FIFO_FULL = 0x00000123, 14821 PH_PERF_SEL_SC2_PA2_NULL_WE = 0x00000124, 14822 PH_PERF_SEL_SC2_PA2_EVENT_WE = 0x00000125, 14823 PH_PERF_SEL_SC2_PA2_FPOV_WE = 0x00000126, 14824 PH_PERF_SEL_SC2_PA2_FPOP_WE = 0x00000127, 14825 PH_PERF_SEL_SC2_PA2_EOP_WE = 0x00000128, 14826 PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129, 14827 PH_PERF_SEL_SC2_PA2_EOPG_WE = 0x0000012a, 14828 PH_PERF_SEL_SC2_PA2_DEALLOC_WE = 0x0000012b, 14829 PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 0x0000012c, 14830 PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 0x0000012d, 14831 PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 0x0000012e, 14832 PH_PERF_SEL_SC2_PA3_FIFO_FULL = 0x0000012f, 14833 PH_PERF_SEL_SC2_PA3_NULL_WE = 0x00000130, 14834 PH_PERF_SEL_SC2_PA3_EVENT_WE = 0x00000131, 14835 PH_PERF_SEL_SC2_PA3_FPOV_WE = 0x00000132, 14836 PH_PERF_SEL_SC2_PA3_FPOP_WE = 0x00000133, 14837 PH_PERF_SEL_SC2_PA3_EOP_WE = 0x00000134, 14838 PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135, 14839 PH_PERF_SEL_SC2_PA3_EOPG_WE = 0x00000136, 14840 PH_PERF_SEL_SC2_PA3_DEALLOC_WE = 0x00000137, 14841 PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 0x00000138, 14842 PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 0x00000139, 14843 PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 0x0000013a, 14844 PH_PERF_SEL_SC2_PA4_FIFO_FULL = 0x0000013b, 14845 PH_PERF_SEL_SC2_PA4_NULL_WE = 0x0000013c, 14846 PH_PERF_SEL_SC2_PA4_EVENT_WE = 0x0000013d, 14847 PH_PERF_SEL_SC2_PA4_FPOV_WE = 0x0000013e, 14848 PH_PERF_SEL_SC2_PA4_FPOP_WE = 0x0000013f, 14849 PH_PERF_SEL_SC2_PA4_EOP_WE = 0x00000140, 14850 PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141, 14851 PH_PERF_SEL_SC2_PA4_EOPG_WE = 0x00000142, 14852 PH_PERF_SEL_SC2_PA4_DEALLOC_WE = 0x00000143, 14853 PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 0x00000144, 14854 PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 0x00000145, 14855 PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 0x00000146, 14856 PH_PERF_SEL_SC2_PA5_FIFO_FULL = 0x00000147, 14857 PH_PERF_SEL_SC2_PA5_NULL_WE = 0x00000148, 14858 PH_PERF_SEL_SC2_PA5_EVENT_WE = 0x00000149, 14859 PH_PERF_SEL_SC2_PA5_FPOV_WE = 0x0000014a, 14860 PH_PERF_SEL_SC2_PA5_FPOP_WE = 0x0000014b, 14861 PH_PERF_SEL_SC2_PA5_EOP_WE = 0x0000014c, 14862 PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d, 14863 PH_PERF_SEL_SC2_PA5_EOPG_WE = 0x0000014e, 14864 PH_PERF_SEL_SC2_PA5_DEALLOC_WE = 0x0000014f, 14865 PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 0x00000150, 14866 PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 0x00000151, 14867 PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 0x00000152, 14868 PH_PERF_SEL_SC2_PA6_FIFO_FULL = 0x00000153, 14869 PH_PERF_SEL_SC2_PA6_NULL_WE = 0x00000154, 14870 PH_PERF_SEL_SC2_PA6_EVENT_WE = 0x00000155, 14871 PH_PERF_SEL_SC2_PA6_FPOV_WE = 0x00000156, 14872 PH_PERF_SEL_SC2_PA6_FPOP_WE = 0x00000157, 14873 PH_PERF_SEL_SC2_PA6_EOP_WE = 0x00000158, 14874 PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159, 14875 PH_PERF_SEL_SC2_PA6_EOPG_WE = 0x0000015a, 14876 PH_PERF_SEL_SC2_PA6_DEALLOC_WE = 0x0000015b, 14877 PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 0x0000015c, 14878 PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 0x0000015d, 14879 PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 0x0000015e, 14880 PH_PERF_SEL_SC2_PA7_FIFO_FULL = 0x0000015f, 14881 PH_PERF_SEL_SC2_PA7_NULL_WE = 0x00000160, 14882 PH_PERF_SEL_SC2_PA7_EVENT_WE = 0x00000161, 14883 PH_PERF_SEL_SC2_PA7_FPOV_WE = 0x00000162, 14884 PH_PERF_SEL_SC2_PA7_FPOP_WE = 0x00000163, 14885 PH_PERF_SEL_SC2_PA7_EOP_WE = 0x00000164, 14886 PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165, 14887 PH_PERF_SEL_SC2_PA7_EOPG_WE = 0x00000166, 14888 PH_PERF_SEL_SC2_PA7_DEALLOC_WE = 0x00000167, 14889 PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 0x00000168, 14890 PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169, 14891 PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a, 14892 PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b, 14893 PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c, 14894 PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d, 14895 PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e, 14896 PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f, 14897 PH_PERF_SEL_SC3_ARB_BUSY = 0x00000170, 14898 PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 0x00000171, 14899 PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172, 14900 PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 0x00000173, 14901 PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174, 14902 PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 0x00000175, 14903 PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176, 14904 PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 0x00000177, 14905 PH_PERF_SEL_SC3_SEND = 0x00000178, 14906 PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179, 14907 PH_PERF_SEL_SC3_CREDIT_AT_MAX = 0x0000017a, 14908 PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b, 14909 PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c, 14910 PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d, 14911 PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e, 14912 PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f, 14913 PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 0x00000180, 14914 PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 0x00000181, 14915 PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 0x00000182, 14916 PH_PERF_SEL_SC3_PA0_FIFO_FULL = 0x00000183, 14917 PH_PERF_SEL_SC3_PA0_NULL_WE = 0x00000184, 14918 PH_PERF_SEL_SC3_PA0_EVENT_WE = 0x00000185, 14919 PH_PERF_SEL_SC3_PA0_FPOV_WE = 0x00000186, 14920 PH_PERF_SEL_SC3_PA0_FPOP_WE = 0x00000187, 14921 PH_PERF_SEL_SC3_PA0_EOP_WE = 0x00000188, 14922 PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189, 14923 PH_PERF_SEL_SC3_PA0_EOPG_WE = 0x0000018a, 14924 PH_PERF_SEL_SC3_PA0_DEALLOC_WE = 0x0000018b, 14925 PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 0x0000018c, 14926 PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 0x0000018d, 14927 PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 0x0000018e, 14928 PH_PERF_SEL_SC3_PA1_FIFO_FULL = 0x0000018f, 14929 PH_PERF_SEL_SC3_PA1_NULL_WE = 0x00000190, 14930 PH_PERF_SEL_SC3_PA1_EVENT_WE = 0x00000191, 14931 PH_PERF_SEL_SC3_PA1_FPOV_WE = 0x00000192, 14932 PH_PERF_SEL_SC3_PA1_FPOP_WE = 0x00000193, 14933 PH_PERF_SEL_SC3_PA1_EOP_WE = 0x00000194, 14934 PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195, 14935 PH_PERF_SEL_SC3_PA1_EOPG_WE = 0x00000196, 14936 PH_PERF_SEL_SC3_PA1_DEALLOC_WE = 0x00000197, 14937 PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 0x00000198, 14938 PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 0x00000199, 14939 PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 0x0000019a, 14940 PH_PERF_SEL_SC3_PA2_FIFO_FULL = 0x0000019b, 14941 PH_PERF_SEL_SC3_PA2_NULL_WE = 0x0000019c, 14942 PH_PERF_SEL_SC3_PA2_EVENT_WE = 0x0000019d, 14943 PH_PERF_SEL_SC3_PA2_FPOV_WE = 0x0000019e, 14944 PH_PERF_SEL_SC3_PA2_FPOP_WE = 0x0000019f, 14945 PH_PERF_SEL_SC3_PA2_EOP_WE = 0x000001a0, 14946 PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1, 14947 PH_PERF_SEL_SC3_PA2_EOPG_WE = 0x000001a2, 14948 PH_PERF_SEL_SC3_PA2_DEALLOC_WE = 0x000001a3, 14949 PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 0x000001a4, 14950 PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 0x000001a5, 14951 PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 0x000001a6, 14952 PH_PERF_SEL_SC3_PA3_FIFO_FULL = 0x000001a7, 14953 PH_PERF_SEL_SC3_PA3_NULL_WE = 0x000001a8, 14954 PH_PERF_SEL_SC3_PA3_EVENT_WE = 0x000001a9, 14955 PH_PERF_SEL_SC3_PA3_FPOV_WE = 0x000001aa, 14956 PH_PERF_SEL_SC3_PA3_FPOP_WE = 0x000001ab, 14957 PH_PERF_SEL_SC3_PA3_EOP_WE = 0x000001ac, 14958 PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad, 14959 PH_PERF_SEL_SC3_PA3_EOPG_WE = 0x000001ae, 14960 PH_PERF_SEL_SC3_PA3_DEALLOC_WE = 0x000001af, 14961 PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 0x000001b0, 14962 PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 0x000001b1, 14963 PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 0x000001b2, 14964 PH_PERF_SEL_SC3_PA4_FIFO_FULL = 0x000001b3, 14965 PH_PERF_SEL_SC3_PA4_NULL_WE = 0x000001b4, 14966 PH_PERF_SEL_SC3_PA4_EVENT_WE = 0x000001b5, 14967 PH_PERF_SEL_SC3_PA4_FPOV_WE = 0x000001b6, 14968 PH_PERF_SEL_SC3_PA4_FPOP_WE = 0x000001b7, 14969 PH_PERF_SEL_SC3_PA4_EOP_WE = 0x000001b8, 14970 PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9, 14971 PH_PERF_SEL_SC3_PA4_EOPG_WE = 0x000001ba, 14972 PH_PERF_SEL_SC3_PA4_DEALLOC_WE = 0x000001bb, 14973 PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 0x000001bc, 14974 PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 0x000001bd, 14975 PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 0x000001be, 14976 PH_PERF_SEL_SC3_PA5_FIFO_FULL = 0x000001bf, 14977 PH_PERF_SEL_SC3_PA5_NULL_WE = 0x000001c0, 14978 PH_PERF_SEL_SC3_PA5_EVENT_WE = 0x000001c1, 14979 PH_PERF_SEL_SC3_PA5_FPOV_WE = 0x000001c2, 14980 PH_PERF_SEL_SC3_PA5_FPOP_WE = 0x000001c3, 14981 PH_PERF_SEL_SC3_PA5_EOP_WE = 0x000001c4, 14982 PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5, 14983 PH_PERF_SEL_SC3_PA5_EOPG_WE = 0x000001c6, 14984 PH_PERF_SEL_SC3_PA5_DEALLOC_WE = 0x000001c7, 14985 PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 0x000001c8, 14986 PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 0x000001c9, 14987 PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 0x000001ca, 14988 PH_PERF_SEL_SC3_PA6_FIFO_FULL = 0x000001cb, 14989 PH_PERF_SEL_SC3_PA6_NULL_WE = 0x000001cc, 14990 PH_PERF_SEL_SC3_PA6_EVENT_WE = 0x000001cd, 14991 PH_PERF_SEL_SC3_PA6_FPOV_WE = 0x000001ce, 14992 PH_PERF_SEL_SC3_PA6_FPOP_WE = 0x000001cf, 14993 PH_PERF_SEL_SC3_PA6_EOP_WE = 0x000001d0, 14994 PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1, 14995 PH_PERF_SEL_SC3_PA6_EOPG_WE = 0x000001d2, 14996 PH_PERF_SEL_SC3_PA6_DEALLOC_WE = 0x000001d3, 14997 PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 0x000001d4, 14998 PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 0x000001d5, 14999 PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 0x000001d6, 15000 PH_PERF_SEL_SC3_PA7_FIFO_FULL = 0x000001d7, 15001 PH_PERF_SEL_SC3_PA7_NULL_WE = 0x000001d8, 15002 PH_PERF_SEL_SC3_PA7_EVENT_WE = 0x000001d9, 15003 PH_PERF_SEL_SC3_PA7_FPOV_WE = 0x000001da, 15004 PH_PERF_SEL_SC3_PA7_FPOP_WE = 0x000001db, 15005 PH_PERF_SEL_SC3_PA7_EOP_WE = 0x000001dc, 15006 PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd, 15007 PH_PERF_SEL_SC3_PA7_EOPG_WE = 0x000001de, 15008 PH_PERF_SEL_SC3_PA7_DEALLOC_WE = 0x000001df, 15009 PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 0x000001e0, 15010 PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1, 15011 PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2, 15012 PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3, 15013 PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4, 15014 PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5, 15015 PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6, 15016 PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7, 15017 PH_PERF_SEL_SC4_ARB_BUSY = 0x000001e8, 15018 PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 0x000001e9, 15019 PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea, 15020 PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 0x000001eb, 15021 PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec, 15022 PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 0x000001ed, 15023 PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee, 15024 PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef, 15025 PH_PERF_SEL_SC4_SEND = 0x000001f0, 15026 PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1, 15027 PH_PERF_SEL_SC4_CREDIT_AT_MAX = 0x000001f2, 15028 PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3, 15029 PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4, 15030 PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5, 15031 PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6, 15032 PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7, 15033 PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 0x000001f8, 15034 PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 0x000001f9, 15035 PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 0x000001fa, 15036 PH_PERF_SEL_SC4_PA0_FIFO_FULL = 0x000001fb, 15037 PH_PERF_SEL_SC4_PA0_NULL_WE = 0x000001fc, 15038 PH_PERF_SEL_SC4_PA0_EVENT_WE = 0x000001fd, 15039 PH_PERF_SEL_SC4_PA0_FPOV_WE = 0x000001fe, 15040 PH_PERF_SEL_SC4_PA0_FPOP_WE = 0x000001ff, 15041 PH_PERF_SEL_SC4_PA0_EOP_WE = 0x00000200, 15042 PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201, 15043 PH_PERF_SEL_SC4_PA0_EOPG_WE = 0x00000202, 15044 PH_PERF_SEL_SC4_PA0_DEALLOC_WE = 0x00000203, 15045 PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 0x00000204, 15046 PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 0x00000205, 15047 PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 0x00000206, 15048 PH_PERF_SEL_SC4_PA1_FIFO_FULL = 0x00000207, 15049 PH_PERF_SEL_SC4_PA1_NULL_WE = 0x00000208, 15050 PH_PERF_SEL_SC4_PA1_EVENT_WE = 0x00000209, 15051 PH_PERF_SEL_SC4_PA1_FPOV_WE = 0x0000020a, 15052 PH_PERF_SEL_SC4_PA1_FPOP_WE = 0x0000020b, 15053 PH_PERF_SEL_SC4_PA1_EOP_WE = 0x0000020c, 15054 PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d, 15055 PH_PERF_SEL_SC4_PA1_EOPG_WE = 0x0000020e, 15056 PH_PERF_SEL_SC4_PA1_DEALLOC_WE = 0x0000020f, 15057 PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 0x00000210, 15058 PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 0x00000211, 15059 PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 0x00000212, 15060 PH_PERF_SEL_SC4_PA2_FIFO_FULL = 0x00000213, 15061 PH_PERF_SEL_SC4_PA2_NULL_WE = 0x00000214, 15062 PH_PERF_SEL_SC4_PA2_EVENT_WE = 0x00000215, 15063 PH_PERF_SEL_SC4_PA2_FPOV_WE = 0x00000216, 15064 PH_PERF_SEL_SC4_PA2_FPOP_WE = 0x00000217, 15065 PH_PERF_SEL_SC4_PA2_EOP_WE = 0x00000218, 15066 PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219, 15067 PH_PERF_SEL_SC4_PA2_EOPG_WE = 0x0000021a, 15068 PH_PERF_SEL_SC4_PA2_DEALLOC_WE = 0x0000021b, 15069 PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 0x0000021c, 15070 PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 0x0000021d, 15071 PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 0x0000021e, 15072 PH_PERF_SEL_SC4_PA3_FIFO_FULL = 0x0000021f, 15073 PH_PERF_SEL_SC4_PA3_NULL_WE = 0x00000220, 15074 PH_PERF_SEL_SC4_PA3_EVENT_WE = 0x00000221, 15075 PH_PERF_SEL_SC4_PA3_FPOV_WE = 0x00000222, 15076 PH_PERF_SEL_SC4_PA3_FPOP_WE = 0x00000223, 15077 PH_PERF_SEL_SC4_PA3_EOP_WE = 0x00000224, 15078 PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225, 15079 PH_PERF_SEL_SC4_PA3_EOPG_WE = 0x00000226, 15080 PH_PERF_SEL_SC4_PA3_DEALLOC_WE = 0x00000227, 15081 PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 0x00000228, 15082 PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 0x00000229, 15083 PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 0x0000022a, 15084 PH_PERF_SEL_SC4_PA4_FIFO_FULL = 0x0000022b, 15085 PH_PERF_SEL_SC4_PA4_NULL_WE = 0x0000022c, 15086 PH_PERF_SEL_SC4_PA4_EVENT_WE = 0x0000022d, 15087 PH_PERF_SEL_SC4_PA4_FPOV_WE = 0x0000022e, 15088 PH_PERF_SEL_SC4_PA4_FPOP_WE = 0x0000022f, 15089 PH_PERF_SEL_SC4_PA4_EOP_WE = 0x00000230, 15090 PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231, 15091 PH_PERF_SEL_SC4_PA4_EOPG_WE = 0x00000232, 15092 PH_PERF_SEL_SC4_PA4_DEALLOC_WE = 0x00000233, 15093 PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 0x00000234, 15094 PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 0x00000235, 15095 PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 0x00000236, 15096 PH_PERF_SEL_SC4_PA5_FIFO_FULL = 0x00000237, 15097 PH_PERF_SEL_SC4_PA5_NULL_WE = 0x00000238, 15098 PH_PERF_SEL_SC4_PA5_EVENT_WE = 0x00000239, 15099 PH_PERF_SEL_SC4_PA5_FPOV_WE = 0x0000023a, 15100 PH_PERF_SEL_SC4_PA5_FPOP_WE = 0x0000023b, 15101 PH_PERF_SEL_SC4_PA5_EOP_WE = 0x0000023c, 15102 PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d, 15103 PH_PERF_SEL_SC4_PA5_EOPG_WE = 0x0000023e, 15104 PH_PERF_SEL_SC4_PA5_DEALLOC_WE = 0x0000023f, 15105 PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 0x00000240, 15106 PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 0x00000241, 15107 PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 0x00000242, 15108 PH_PERF_SEL_SC4_PA6_FIFO_FULL = 0x00000243, 15109 PH_PERF_SEL_SC4_PA6_NULL_WE = 0x00000244, 15110 PH_PERF_SEL_SC4_PA6_EVENT_WE = 0x00000245, 15111 PH_PERF_SEL_SC4_PA6_FPOV_WE = 0x00000246, 15112 PH_PERF_SEL_SC4_PA6_FPOP_WE = 0x00000247, 15113 PH_PERF_SEL_SC4_PA6_EOP_WE = 0x00000248, 15114 PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249, 15115 PH_PERF_SEL_SC4_PA6_EOPG_WE = 0x0000024a, 15116 PH_PERF_SEL_SC4_PA6_DEALLOC_WE = 0x0000024b, 15117 PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 0x0000024c, 15118 PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 0x0000024d, 15119 PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 0x0000024e, 15120 PH_PERF_SEL_SC4_PA7_FIFO_FULL = 0x0000024f, 15121 PH_PERF_SEL_SC4_PA7_NULL_WE = 0x00000250, 15122 PH_PERF_SEL_SC4_PA7_EVENT_WE = 0x00000251, 15123 PH_PERF_SEL_SC4_PA7_FPOV_WE = 0x00000252, 15124 PH_PERF_SEL_SC4_PA7_FPOP_WE = 0x00000253, 15125 PH_PERF_SEL_SC4_PA7_EOP_WE = 0x00000254, 15126 PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255, 15127 PH_PERF_SEL_SC4_PA7_EOPG_WE = 0x00000256, 15128 PH_PERF_SEL_SC4_PA7_DEALLOC_WE = 0x00000257, 15129 PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 0x00000258, 15130 PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259, 15131 PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a, 15132 PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b, 15133 PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c, 15134 PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d, 15135 PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e, 15136 PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f, 15137 PH_PERF_SEL_SC5_ARB_BUSY = 0x00000260, 15138 PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 0x00000261, 15139 PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262, 15140 PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 0x00000263, 15141 PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264, 15142 PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 0x00000265, 15143 PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266, 15144 PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 0x00000267, 15145 PH_PERF_SEL_SC5_SEND = 0x00000268, 15146 PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269, 15147 PH_PERF_SEL_SC5_CREDIT_AT_MAX = 0x0000026a, 15148 PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b, 15149 PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c, 15150 PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d, 15151 PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e, 15152 PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f, 15153 PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 0x00000270, 15154 PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 0x00000271, 15155 PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 0x00000272, 15156 PH_PERF_SEL_SC5_PA0_FIFO_FULL = 0x00000273, 15157 PH_PERF_SEL_SC5_PA0_NULL_WE = 0x00000274, 15158 PH_PERF_SEL_SC5_PA0_EVENT_WE = 0x00000275, 15159 PH_PERF_SEL_SC5_PA0_FPOV_WE = 0x00000276, 15160 PH_PERF_SEL_SC5_PA0_FPOP_WE = 0x00000277, 15161 PH_PERF_SEL_SC5_PA0_EOP_WE = 0x00000278, 15162 PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279, 15163 PH_PERF_SEL_SC5_PA0_EOPG_WE = 0x0000027a, 15164 PH_PERF_SEL_SC5_PA0_DEALLOC_WE = 0x0000027b, 15165 PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 0x0000027c, 15166 PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 0x0000027d, 15167 PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 0x0000027e, 15168 PH_PERF_SEL_SC5_PA1_FIFO_FULL = 0x0000027f, 15169 PH_PERF_SEL_SC5_PA1_NULL_WE = 0x00000280, 15170 PH_PERF_SEL_SC5_PA1_EVENT_WE = 0x00000281, 15171 PH_PERF_SEL_SC5_PA1_FPOV_WE = 0x00000282, 15172 PH_PERF_SEL_SC5_PA1_FPOP_WE = 0x00000283, 15173 PH_PERF_SEL_SC5_PA1_EOP_WE = 0x00000284, 15174 PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285, 15175 PH_PERF_SEL_SC5_PA1_EOPG_WE = 0x00000286, 15176 PH_PERF_SEL_SC5_PA1_DEALLOC_WE = 0x00000287, 15177 PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 0x00000288, 15178 PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 0x00000289, 15179 PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 0x0000028a, 15180 PH_PERF_SEL_SC5_PA2_FIFO_FULL = 0x0000028b, 15181 PH_PERF_SEL_SC5_PA2_NULL_WE = 0x0000028c, 15182 PH_PERF_SEL_SC5_PA2_EVENT_WE = 0x0000028d, 15183 PH_PERF_SEL_SC5_PA2_FPOV_WE = 0x0000028e, 15184 PH_PERF_SEL_SC5_PA2_FPOP_WE = 0x0000028f, 15185 PH_PERF_SEL_SC5_PA2_EOP_WE = 0x00000290, 15186 PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291, 15187 PH_PERF_SEL_SC5_PA2_EOPG_WE = 0x00000292, 15188 PH_PERF_SEL_SC5_PA2_DEALLOC_WE = 0x00000293, 15189 PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 0x00000294, 15190 PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 0x00000295, 15191 PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 0x00000296, 15192 PH_PERF_SEL_SC5_PA3_FIFO_FULL = 0x00000297, 15193 PH_PERF_SEL_SC5_PA3_NULL_WE = 0x00000298, 15194 PH_PERF_SEL_SC5_PA3_EVENT_WE = 0x00000299, 15195 PH_PERF_SEL_SC5_PA3_FPOV_WE = 0x0000029a, 15196 PH_PERF_SEL_SC5_PA3_FPOP_WE = 0x0000029b, 15197 PH_PERF_SEL_SC5_PA3_EOP_WE = 0x0000029c, 15198 PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d, 15199 PH_PERF_SEL_SC5_PA3_EOPG_WE = 0x0000029e, 15200 PH_PERF_SEL_SC5_PA3_DEALLOC_WE = 0x0000029f, 15201 PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 0x000002a0, 15202 PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 0x000002a1, 15203 PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 0x000002a2, 15204 PH_PERF_SEL_SC5_PA4_FIFO_FULL = 0x000002a3, 15205 PH_PERF_SEL_SC5_PA4_NULL_WE = 0x000002a4, 15206 PH_PERF_SEL_SC5_PA4_EVENT_WE = 0x000002a5, 15207 PH_PERF_SEL_SC5_PA4_FPOV_WE = 0x000002a6, 15208 PH_PERF_SEL_SC5_PA4_FPOP_WE = 0x000002a7, 15209 PH_PERF_SEL_SC5_PA4_EOP_WE = 0x000002a8, 15210 PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9, 15211 PH_PERF_SEL_SC5_PA4_EOPG_WE = 0x000002aa, 15212 PH_PERF_SEL_SC5_PA4_DEALLOC_WE = 0x000002ab, 15213 PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 0x000002ac, 15214 PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 0x000002ad, 15215 PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 0x000002ae, 15216 PH_PERF_SEL_SC5_PA5_FIFO_FULL = 0x000002af, 15217 PH_PERF_SEL_SC5_PA5_NULL_WE = 0x000002b0, 15218 PH_PERF_SEL_SC5_PA5_EVENT_WE = 0x000002b1, 15219 PH_PERF_SEL_SC5_PA5_FPOV_WE = 0x000002b2, 15220 PH_PERF_SEL_SC5_PA5_FPOP_WE = 0x000002b3, 15221 PH_PERF_SEL_SC5_PA5_EOP_WE = 0x000002b4, 15222 PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5, 15223 PH_PERF_SEL_SC5_PA5_EOPG_WE = 0x000002b6, 15224 PH_PERF_SEL_SC5_PA5_DEALLOC_WE = 0x000002b7, 15225 PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 0x000002b8, 15226 PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 0x000002b9, 15227 PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 0x000002ba, 15228 PH_PERF_SEL_SC5_PA6_FIFO_FULL = 0x000002bb, 15229 PH_PERF_SEL_SC5_PA6_NULL_WE = 0x000002bc, 15230 PH_PERF_SEL_SC5_PA6_EVENT_WE = 0x000002bd, 15231 PH_PERF_SEL_SC5_PA6_FPOV_WE = 0x000002be, 15232 PH_PERF_SEL_SC5_PA6_FPOP_WE = 0x000002bf, 15233 PH_PERF_SEL_SC5_PA6_EOP_WE = 0x000002c0, 15234 PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1, 15235 PH_PERF_SEL_SC5_PA6_EOPG_WE = 0x000002c2, 15236 PH_PERF_SEL_SC5_PA6_DEALLOC_WE = 0x000002c3, 15237 PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 0x000002c4, 15238 PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 0x000002c5, 15239 PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 0x000002c6, 15240 PH_PERF_SEL_SC5_PA7_FIFO_FULL = 0x000002c7, 15241 PH_PERF_SEL_SC5_PA7_NULL_WE = 0x000002c8, 15242 PH_PERF_SEL_SC5_PA7_EVENT_WE = 0x000002c9, 15243 PH_PERF_SEL_SC5_PA7_FPOV_WE = 0x000002ca, 15244 PH_PERF_SEL_SC5_PA7_FPOP_WE = 0x000002cb, 15245 PH_PERF_SEL_SC5_PA7_EOP_WE = 0x000002cc, 15246 PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd, 15247 PH_PERF_SEL_SC5_PA7_EOPG_WE = 0x000002ce, 15248 PH_PERF_SEL_SC5_PA7_DEALLOC_WE = 0x000002cf, 15249 PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 0x000002d0, 15250 PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1, 15251 PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2, 15252 PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3, 15253 PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4, 15254 PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5, 15255 PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6, 15256 PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7, 15257 PH_PERF_SEL_SC6_ARB_BUSY = 0x000002d8, 15258 PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 0x000002d9, 15259 PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da, 15260 PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 0x000002db, 15261 PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc, 15262 PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 0x000002dd, 15263 PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de, 15264 PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 0x000002df, 15265 PH_PERF_SEL_SC6_SEND = 0x000002e0, 15266 PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1, 15267 PH_PERF_SEL_SC6_CREDIT_AT_MAX = 0x000002e2, 15268 PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3, 15269 PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4, 15270 PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5, 15271 PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6, 15272 PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7, 15273 PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 0x000002e8, 15274 PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 0x000002e9, 15275 PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 0x000002ea, 15276 PH_PERF_SEL_SC6_PA0_FIFO_FULL = 0x000002eb, 15277 PH_PERF_SEL_SC6_PA0_NULL_WE = 0x000002ec, 15278 PH_PERF_SEL_SC6_PA0_EVENT_WE = 0x000002ed, 15279 PH_PERF_SEL_SC6_PA0_FPOV_WE = 0x000002ee, 15280 PH_PERF_SEL_SC6_PA0_FPOP_WE = 0x000002ef, 15281 PH_PERF_SEL_SC6_PA0_EOP_WE = 0x000002f0, 15282 PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1, 15283 PH_PERF_SEL_SC6_PA0_EOPG_WE = 0x000002f2, 15284 PH_PERF_SEL_SC6_PA0_DEALLOC_WE = 0x000002f3, 15285 PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 0x000002f4, 15286 PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 0x000002f5, 15287 PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 0x000002f6, 15288 PH_PERF_SEL_SC6_PA1_FIFO_FULL = 0x000002f7, 15289 PH_PERF_SEL_SC6_PA1_NULL_WE = 0x000002f8, 15290 PH_PERF_SEL_SC6_PA1_EVENT_WE = 0x000002f9, 15291 PH_PERF_SEL_SC6_PA1_FPOV_WE = 0x000002fa, 15292 PH_PERF_SEL_SC6_PA1_FPOP_WE = 0x000002fb, 15293 PH_PERF_SEL_SC6_PA1_EOP_WE = 0x000002fc, 15294 PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd, 15295 PH_PERF_SEL_SC6_PA1_EOPG_WE = 0x000002fe, 15296 PH_PERF_SEL_SC6_PA1_DEALLOC_WE = 0x000002ff, 15297 PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 0x00000300, 15298 PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 0x00000301, 15299 PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 0x00000302, 15300 PH_PERF_SEL_SC6_PA2_FIFO_FULL = 0x00000303, 15301 PH_PERF_SEL_SC6_PA2_NULL_WE = 0x00000304, 15302 PH_PERF_SEL_SC6_PA2_EVENT_WE = 0x00000305, 15303 PH_PERF_SEL_SC6_PA2_FPOV_WE = 0x00000306, 15304 PH_PERF_SEL_SC6_PA2_FPOP_WE = 0x00000307, 15305 PH_PERF_SEL_SC6_PA2_EOP_WE = 0x00000308, 15306 PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309, 15307 PH_PERF_SEL_SC6_PA2_EOPG_WE = 0x0000030a, 15308 PH_PERF_SEL_SC6_PA2_DEALLOC_WE = 0x0000030b, 15309 PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 0x0000030c, 15310 PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 0x0000030d, 15311 PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 0x0000030e, 15312 PH_PERF_SEL_SC6_PA3_FIFO_FULL = 0x0000030f, 15313 PH_PERF_SEL_SC6_PA3_NULL_WE = 0x00000310, 15314 PH_PERF_SEL_SC6_PA3_EVENT_WE = 0x00000311, 15315 PH_PERF_SEL_SC6_PA3_FPOV_WE = 0x00000312, 15316 PH_PERF_SEL_SC6_PA3_FPOP_WE = 0x00000313, 15317 PH_PERF_SEL_SC6_PA3_EOP_WE = 0x00000314, 15318 PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315, 15319 PH_PERF_SEL_SC6_PA3_EOPG_WE = 0x00000316, 15320 PH_PERF_SEL_SC6_PA3_DEALLOC_WE = 0x00000317, 15321 PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 0x00000318, 15322 PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 0x00000319, 15323 PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 0x0000031a, 15324 PH_PERF_SEL_SC6_PA4_FIFO_FULL = 0x0000031b, 15325 PH_PERF_SEL_SC6_PA4_NULL_WE = 0x0000031c, 15326 PH_PERF_SEL_SC6_PA4_EVENT_WE = 0x0000031d, 15327 PH_PERF_SEL_SC6_PA4_FPOV_WE = 0x0000031e, 15328 PH_PERF_SEL_SC6_PA4_FPOP_WE = 0x0000031f, 15329 PH_PERF_SEL_SC6_PA4_EOP_WE = 0x00000320, 15330 PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321, 15331 PH_PERF_SEL_SC6_PA4_EOPG_WE = 0x00000322, 15332 PH_PERF_SEL_SC6_PA4_DEALLOC_WE = 0x00000323, 15333 PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 0x00000324, 15334 PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 0x00000325, 15335 PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 0x00000326, 15336 PH_PERF_SEL_SC6_PA5_FIFO_FULL = 0x00000327, 15337 PH_PERF_SEL_SC6_PA5_NULL_WE = 0x00000328, 15338 PH_PERF_SEL_SC6_PA5_EVENT_WE = 0x00000329, 15339 PH_PERF_SEL_SC6_PA5_FPOV_WE = 0x0000032a, 15340 PH_PERF_SEL_SC6_PA5_FPOP_WE = 0x0000032b, 15341 PH_PERF_SEL_SC6_PA5_EOP_WE = 0x0000032c, 15342 PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d, 15343 PH_PERF_SEL_SC6_PA5_EOPG_WE = 0x0000032e, 15344 PH_PERF_SEL_SC6_PA5_DEALLOC_WE = 0x0000032f, 15345 PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 0x00000330, 15346 PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 0x00000331, 15347 PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 0x00000332, 15348 PH_PERF_SEL_SC6_PA6_FIFO_FULL = 0x00000333, 15349 PH_PERF_SEL_SC6_PA6_NULL_WE = 0x00000334, 15350 PH_PERF_SEL_SC6_PA6_EVENT_WE = 0x00000335, 15351 PH_PERF_SEL_SC6_PA6_FPOV_WE = 0x00000336, 15352 PH_PERF_SEL_SC6_PA6_FPOP_WE = 0x00000337, 15353 PH_PERF_SEL_SC6_PA6_EOP_WE = 0x00000338, 15354 PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339, 15355 PH_PERF_SEL_SC6_PA6_EOPG_WE = 0x0000033a, 15356 PH_PERF_SEL_SC6_PA6_DEALLOC_WE = 0x0000033b, 15357 PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 0x0000033c, 15358 PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 0x0000033d, 15359 PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 0x0000033e, 15360 PH_PERF_SEL_SC6_PA7_FIFO_FULL = 0x0000033f, 15361 PH_PERF_SEL_SC6_PA7_NULL_WE = 0x00000340, 15362 PH_PERF_SEL_SC6_PA7_EVENT_WE = 0x00000341, 15363 PH_PERF_SEL_SC6_PA7_FPOV_WE = 0x00000342, 15364 PH_PERF_SEL_SC6_PA7_FPOP_WE = 0x00000343, 15365 PH_PERF_SEL_SC6_PA7_EOP_WE = 0x00000344, 15366 PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345, 15367 PH_PERF_SEL_SC6_PA7_EOPG_WE = 0x00000346, 15368 PH_PERF_SEL_SC6_PA7_DEALLOC_WE = 0x00000347, 15369 PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 0x00000348, 15370 PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349, 15371 PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a, 15372 PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b, 15373 PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c, 15374 PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d, 15375 PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e, 15376 PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f, 15377 PH_PERF_SEL_SC7_ARB_BUSY = 0x00000350, 15378 PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 0x00000351, 15379 PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352, 15380 PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 0x00000353, 15381 PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354, 15382 PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 0x00000355, 15383 PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356, 15384 PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 0x00000357, 15385 PH_PERF_SEL_SC7_SEND = 0x00000358, 15386 PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359, 15387 PH_PERF_SEL_SC7_CREDIT_AT_MAX = 0x0000035a, 15388 PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b, 15389 PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c, 15390 PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d, 15391 PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e, 15392 PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f, 15393 PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 0x00000360, 15394 PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 0x00000361, 15395 PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 0x00000362, 15396 PH_PERF_SEL_SC7_PA0_FIFO_FULL = 0x00000363, 15397 PH_PERF_SEL_SC7_PA0_NULL_WE = 0x00000364, 15398 PH_PERF_SEL_SC7_PA0_EVENT_WE = 0x00000365, 15399 PH_PERF_SEL_SC7_PA0_FPOV_WE = 0x00000366, 15400 PH_PERF_SEL_SC7_PA0_FPOP_WE = 0x00000367, 15401 PH_PERF_SEL_SC7_PA0_EOP_WE = 0x00000368, 15402 PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369, 15403 PH_PERF_SEL_SC7_PA0_EOPG_WE = 0x0000036a, 15404 PH_PERF_SEL_SC7_PA0_DEALLOC_WE = 0x0000036b, 15405 PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 0x0000036c, 15406 PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 0x0000036d, 15407 PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 0x0000036e, 15408 PH_PERF_SEL_SC7_PA1_FIFO_FULL = 0x0000036f, 15409 PH_PERF_SEL_SC7_PA1_NULL_WE = 0x00000370, 15410 PH_PERF_SEL_SC7_PA1_EVENT_WE = 0x00000371, 15411 PH_PERF_SEL_SC7_PA1_FPOV_WE = 0x00000372, 15412 PH_PERF_SEL_SC7_PA1_FPOP_WE = 0x00000373, 15413 PH_PERF_SEL_SC7_PA1_EOP_WE = 0x00000374, 15414 PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375, 15415 PH_PERF_SEL_SC7_PA1_EOPG_WE = 0x00000376, 15416 PH_PERF_SEL_SC7_PA1_DEALLOC_WE = 0x00000377, 15417 PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 0x00000378, 15418 PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 0x00000379, 15419 PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 0x0000037a, 15420 PH_PERF_SEL_SC7_PA2_FIFO_FULL = 0x0000037b, 15421 PH_PERF_SEL_SC7_PA2_NULL_WE = 0x0000037c, 15422 PH_PERF_SEL_SC7_PA2_EVENT_WE = 0x0000037d, 15423 PH_PERF_SEL_SC7_PA2_FPOV_WE = 0x0000037e, 15424 PH_PERF_SEL_SC7_PA2_FPOP_WE = 0x0000037f, 15425 PH_PERF_SEL_SC7_PA2_EOP_WE = 0x00000380, 15426 PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381, 15427 PH_PERF_SEL_SC7_PA2_EOPG_WE = 0x00000382, 15428 PH_PERF_SEL_SC7_PA2_DEALLOC_WE = 0x00000383, 15429 PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 0x00000384, 15430 PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 0x00000385, 15431 PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 0x00000386, 15432 PH_PERF_SEL_SC7_PA3_FIFO_FULL = 0x00000387, 15433 PH_PERF_SEL_SC7_PA3_NULL_WE = 0x00000388, 15434 PH_PERF_SEL_SC7_PA3_EVENT_WE = 0x00000389, 15435 PH_PERF_SEL_SC7_PA3_FPOV_WE = 0x0000038a, 15436 PH_PERF_SEL_SC7_PA3_FPOP_WE = 0x0000038b, 15437 PH_PERF_SEL_SC7_PA3_EOP_WE = 0x0000038c, 15438 PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d, 15439 PH_PERF_SEL_SC7_PA3_EOPG_WE = 0x0000038e, 15440 PH_PERF_SEL_SC7_PA3_DEALLOC_WE = 0x0000038f, 15441 PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 0x00000390, 15442 PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 0x00000391, 15443 PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 0x00000392, 15444 PH_PERF_SEL_SC7_PA4_FIFO_FULL = 0x00000393, 15445 PH_PERF_SEL_SC7_PA4_NULL_WE = 0x00000394, 15446 PH_PERF_SEL_SC7_PA4_EVENT_WE = 0x00000395, 15447 PH_PERF_SEL_SC7_PA4_FPOV_WE = 0x00000396, 15448 PH_PERF_SEL_SC7_PA4_FPOP_WE = 0x00000397, 15449 PH_PERF_SEL_SC7_PA4_EOP_WE = 0x00000398, 15450 PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399, 15451 PH_PERF_SEL_SC7_PA4_EOPG_WE = 0x0000039a, 15452 PH_PERF_SEL_SC7_PA4_DEALLOC_WE = 0x0000039b, 15453 PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 0x0000039c, 15454 PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 0x0000039d, 15455 PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 0x0000039e, 15456 PH_PERF_SEL_SC7_PA5_FIFO_FULL = 0x0000039f, 15457 PH_PERF_SEL_SC7_PA5_NULL_WE = 0x000003a0, 15458 PH_PERF_SEL_SC7_PA5_EVENT_WE = 0x000003a1, 15459 PH_PERF_SEL_SC7_PA5_FPOV_WE = 0x000003a2, 15460 PH_PERF_SEL_SC7_PA5_FPOP_WE = 0x000003a3, 15461 PH_PERF_SEL_SC7_PA5_EOP_WE = 0x000003a4, 15462 PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5, 15463 PH_PERF_SEL_SC7_PA5_EOPG_WE = 0x000003a6, 15464 PH_PERF_SEL_SC7_PA5_DEALLOC_WE = 0x000003a7, 15465 PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 0x000003a8, 15466 PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 0x000003a9, 15467 PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 0x000003aa, 15468 PH_PERF_SEL_SC7_PA6_FIFO_FULL = 0x000003ab, 15469 PH_PERF_SEL_SC7_PA6_NULL_WE = 0x000003ac, 15470 PH_PERF_SEL_SC7_PA6_EVENT_WE = 0x000003ad, 15471 PH_PERF_SEL_SC7_PA6_FPOV_WE = 0x000003ae, 15472 PH_PERF_SEL_SC7_PA6_FPOP_WE = 0x000003af, 15473 PH_PERF_SEL_SC7_PA6_EOP_WE = 0x000003b0, 15474 PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1, 15475 PH_PERF_SEL_SC7_PA6_EOPG_WE = 0x000003b2, 15476 PH_PERF_SEL_SC7_PA6_DEALLOC_WE = 0x000003b3, 15477 PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 0x000003b4, 15478 PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 0x000003b5, 15479 PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 0x000003b6, 15480 PH_PERF_SEL_SC7_PA7_FIFO_FULL = 0x000003b7, 15481 PH_PERF_SEL_SC7_PA7_NULL_WE = 0x000003b8, 15482 PH_PERF_SEL_SC7_PA7_EVENT_WE = 0x000003b9, 15483 PH_PERF_SEL_SC7_PA7_FPOV_WE = 0x000003ba, 15484 PH_PERF_SEL_SC7_PA7_FPOP_WE = 0x000003bb, 15485 PH_PERF_SEL_SC7_PA7_EOP_WE = 0x000003bc, 15486 PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd, 15487 PH_PERF_SEL_SC7_PA7_EOPG_WE = 0x000003be, 15488 PH_PERF_SEL_SC7_PA7_DEALLOC_WE = 0x000003bf, 15489 PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 0x000003c0, 15490 PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 0x000003c1, 15491 PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 0x000003c2, 15492 PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 0x000003c3, 15493 PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 0x000003c4, 15494 PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 0x000003c5, 15495 PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 0x000003c6, 15496 PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 0x000003c7, 15497 PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 0x000003c8, 15498 PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 0x000003c9, 15499 PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 0x000003ca, 15500 PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 0x000003cb, 15501 PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 0x000003cc, 15502 PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 0x000003cd, 15503 PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 0x000003ce, 15504 PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 0x000003cf, 15505 PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0, 15506 PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1, 15507 PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2, 15508 PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3, 15509 PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4, 15510 PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5, 15511 PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6, 15512 PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7, 15513 PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8, 15514 PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9, 15515 PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da, 15516 PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db, 15517 PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc, 15518 PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd, 15519 PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de, 15520 PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df, 15521 PH_PERF_SC0_FIFO_STATUS_0 = 0x000003e0, 15522 PH_PERF_SC0_FIFO_STATUS_1 = 0x000003e1, 15523 PH_PERF_SC0_FIFO_STATUS_2 = 0x000003e2, 15524 PH_PERF_SC0_FIFO_STATUS_3 = 0x000003e3, 15525 PH_PERF_SC1_FIFO_STATUS_0 = 0x000003e4, 15526 PH_PERF_SC1_FIFO_STATUS_1 = 0x000003e5, 15527 PH_PERF_SC1_FIFO_STATUS_2 = 0x000003e6, 15528 PH_PERF_SC1_FIFO_STATUS_3 = 0x000003e7, 15529 PH_PERF_SC2_FIFO_STATUS_0 = 0x000003e8, 15530 PH_PERF_SC2_FIFO_STATUS_1 = 0x000003e9, 15531 PH_PERF_SC2_FIFO_STATUS_2 = 0x000003ea, 15532 PH_PERF_SC2_FIFO_STATUS_3 = 0x000003eb, 15533 PH_PERF_SC3_FIFO_STATUS_0 = 0x000003ec, 15534 PH_PERF_SC3_FIFO_STATUS_1 = 0x000003ed, 15535 PH_PERF_SC3_FIFO_STATUS_2 = 0x000003ee, 15536 PH_PERF_SC3_FIFO_STATUS_3 = 0x000003ef, 15537 PH_PERF_SC4_FIFO_STATUS_0 = 0x000003f0, 15538 PH_PERF_SC4_FIFO_STATUS_1 = 0x000003f1, 15539 PH_PERF_SC4_FIFO_STATUS_2 = 0x000003f2, 15540 PH_PERF_SC4_FIFO_STATUS_3 = 0x000003f3, 15541 PH_PERF_SC5_FIFO_STATUS_0 = 0x000003f4, 15542 PH_PERF_SC5_FIFO_STATUS_1 = 0x000003f5, 15543 PH_PERF_SC5_FIFO_STATUS_2 = 0x000003f6, 15544 PH_PERF_SC5_FIFO_STATUS_3 = 0x000003f7, 15545 PH_PERF_SC6_FIFO_STATUS_0 = 0x000003f8, 15546 PH_PERF_SC6_FIFO_STATUS_1 = 0x000003f9, 15547 PH_PERF_SC6_FIFO_STATUS_2 = 0x000003fa, 15548 PH_PERF_SC6_FIFO_STATUS_3 = 0x000003fb, 15549 PH_PERF_SC7_FIFO_STATUS_0 = 0x000003fc, 15550 PH_PERF_SC7_FIFO_STATUS_1 = 0x000003fd, 15551 PH_PERF_SC7_FIFO_STATUS_2 = 0x000003fe, 15552 PH_PERF_SC7_FIFO_STATUS_3 = 0x000003ff, 15553 } PH_PERFCNT_SEL; 15554 15555 /* 15556 * PhSPIstatusMode enum 15557 */ 15558 15559 typedef enum PhSPIstatusMode { 15560 PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0x00000000, 15561 PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001, 15562 PH_SPI_MODE_DISABLED = 0x00000002, 15563 } PhSPIstatusMode; 15564 15565 /******************************************************* 15566 * SC Enums 15567 *******************************************************/ 15568 15569 /* 15570 * BinEventCntl enum 15571 */ 15572 15573 typedef enum BinEventCntl { 15574 BINNER_BREAK_BATCH = 0x00000000, 15575 BINNER_PIPELINE = 0x00000001, 15576 BINNER_DROP = 0x00000002, 15577 BINNER_PIPELINE_BREAK = 0x00000003, 15578 } BinEventCntl; 15579 15580 /* 15581 * BinMapMode enum 15582 */ 15583 15584 typedef enum BinMapMode { 15585 BIN_MAP_MODE_NONE = 0x00000000, 15586 BIN_MAP_MODE_RTA_INDEX = 0x00000001, 15587 BIN_MAP_MODE_POPS = 0x00000002, 15588 } BinMapMode; 15589 15590 /* 15591 * BinSizeExtend enum 15592 */ 15593 15594 typedef enum BinSizeExtend { 15595 BIN_SIZE_32_PIXELS = 0x00000000, 15596 BIN_SIZE_64_PIXELS = 0x00000001, 15597 BIN_SIZE_128_PIXELS = 0x00000002, 15598 BIN_SIZE_256_PIXELS = 0x00000003, 15599 BIN_SIZE_512_PIXELS = 0x00000004, 15600 } BinSizeExtend; 15601 15602 /* 15603 * BinningMode enum 15604 */ 15605 15606 typedef enum BinningMode { 15607 BINNING_ALLOWED = 0x00000000, 15608 FORCE_BINNING_ON = 0x00000001, 15609 BINNING_ONE_PRIM_PER_BATCH = 0x00000002, 15610 BINNING_DISABLED = 0x00000003, 15611 } BinningMode; 15612 15613 /* 15614 * PkrMap enum 15615 */ 15616 15617 typedef enum PkrMap { 15618 RASTER_CONFIG_PKR_MAP_0 = 0x00000000, 15619 RASTER_CONFIG_PKR_MAP_1 = 0x00000001, 15620 RASTER_CONFIG_PKR_MAP_2 = 0x00000002, 15621 RASTER_CONFIG_PKR_MAP_3 = 0x00000003, 15622 } PkrMap; 15623 15624 /* 15625 * PkrXsel enum 15626 */ 15627 15628 typedef enum PkrXsel { 15629 RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, 15630 RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, 15631 RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, 15632 RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, 15633 } PkrXsel; 15634 15635 /* 15636 * PkrXsel2 enum 15637 */ 15638 15639 typedef enum PkrXsel2 { 15640 RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, 15641 RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, 15642 RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, 15643 RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, 15644 } PkrXsel2; 15645 15646 /* 15647 * PkrYsel enum 15648 */ 15649 15650 typedef enum PkrYsel { 15651 RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, 15652 RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, 15653 RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, 15654 RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, 15655 } PkrYsel; 15656 15657 /* 15658 * RbMap enum 15659 */ 15660 15661 typedef enum RbMap { 15662 RASTER_CONFIG_RB_MAP_0 = 0x00000000, 15663 RASTER_CONFIG_RB_MAP_1 = 0x00000001, 15664 RASTER_CONFIG_RB_MAP_2 = 0x00000002, 15665 RASTER_CONFIG_RB_MAP_3 = 0x00000003, 15666 } RbMap; 15667 15668 /* 15669 * RbXsel enum 15670 */ 15671 15672 typedef enum RbXsel { 15673 RASTER_CONFIG_RB_XSEL_0 = 0x00000000, 15674 RASTER_CONFIG_RB_XSEL_1 = 0x00000001, 15675 } RbXsel; 15676 15677 /* 15678 * RbXsel2 enum 15679 */ 15680 15681 typedef enum RbXsel2 { 15682 RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, 15683 RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, 15684 RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, 15685 RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, 15686 } RbXsel2; 15687 15688 /* 15689 * RbYsel enum 15690 */ 15691 15692 typedef enum RbYsel { 15693 RASTER_CONFIG_RB_YSEL_0 = 0x00000000, 15694 RASTER_CONFIG_RB_YSEL_1 = 0x00000001, 15695 } RbYsel; 15696 15697 /* 15698 * SC_PERFCNT_SEL enum 15699 */ 15700 15701 typedef enum SC_PERFCNT_SEL { 15702 SC_SRPS_WINDOW_VALID = 0x00000000, 15703 SC_PSSW_WINDOW_VALID = 0x00000001, 15704 SC_TPQZ_WINDOW_VALID = 0x00000002, 15705 SC_QZQP_WINDOW_VALID = 0x00000003, 15706 SC_TRPK_WINDOW_VALID = 0x00000004, 15707 SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, 15708 SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, 15709 SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, 15710 SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, 15711 SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, 15712 SC_STARVED_BY_PA = 0x0000000a, 15713 SC_STALLED_BY_PRIMFIFO = 0x0000000b, 15714 SC_STALLED_BY_DB_TILE = 0x0000000c, 15715 SC_STARVED_BY_DB_TILE = 0x0000000d, 15716 SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, 15717 SC_STALLED_BY_TILEFIFO = 0x0000000f, 15718 SC_STALLED_BY_DB_QUAD = 0x00000010, 15719 SC_STARVED_BY_DB_QUAD = 0x00000011, 15720 SC_STALLED_BY_QUADFIFO = 0x00000012, 15721 SC_STALLED_BY_BCI = 0x00000013, 15722 SC_STALLED_BY_SPI = 0x00000014, 15723 SC_SCISSOR_DISCARD = 0x00000015, 15724 SC_BB_DISCARD = 0x00000016, 15725 SC_SUPERTILE_COUNT = 0x00000017, 15726 SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, 15727 SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, 15728 SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, 15729 SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, 15730 SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, 15731 SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, 15732 SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, 15733 SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, 15734 SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, 15735 SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, 15736 SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, 15737 SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, 15738 SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, 15739 SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, 15740 SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, 15741 SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, 15742 SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, 15743 SC_TILE_PER_PRIM_H0 = 0x00000029, 15744 SC_TILE_PER_PRIM_H1 = 0x0000002a, 15745 SC_TILE_PER_PRIM_H2 = 0x0000002b, 15746 SC_TILE_PER_PRIM_H3 = 0x0000002c, 15747 SC_TILE_PER_PRIM_H4 = 0x0000002d, 15748 SC_TILE_PER_PRIM_H5 = 0x0000002e, 15749 SC_TILE_PER_PRIM_H6 = 0x0000002f, 15750 SC_TILE_PER_PRIM_H7 = 0x00000030, 15751 SC_TILE_PER_PRIM_H8 = 0x00000031, 15752 SC_TILE_PER_PRIM_H9 = 0x00000032, 15753 SC_TILE_PER_PRIM_H10 = 0x00000033, 15754 SC_TILE_PER_PRIM_H11 = 0x00000034, 15755 SC_TILE_PER_PRIM_H12 = 0x00000035, 15756 SC_TILE_PER_PRIM_H13 = 0x00000036, 15757 SC_TILE_PER_PRIM_H14 = 0x00000037, 15758 SC_TILE_PER_PRIM_H15 = 0x00000038, 15759 SC_TILE_PER_PRIM_H16 = 0x00000039, 15760 SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, 15761 SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, 15762 SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, 15763 SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, 15764 SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, 15765 SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, 15766 SC_TILE_PER_SUPERTILE_H6 = 0x00000040, 15767 SC_TILE_PER_SUPERTILE_H7 = 0x00000041, 15768 SC_TILE_PER_SUPERTILE_H8 = 0x00000042, 15769 SC_TILE_PER_SUPERTILE_H9 = 0x00000043, 15770 SC_TILE_PER_SUPERTILE_H10 = 0x00000044, 15771 SC_TILE_PER_SUPERTILE_H11 = 0x00000045, 15772 SC_TILE_PER_SUPERTILE_H12 = 0x00000046, 15773 SC_TILE_PER_SUPERTILE_H13 = 0x00000047, 15774 SC_TILE_PER_SUPERTILE_H14 = 0x00000048, 15775 SC_TILE_PER_SUPERTILE_H15 = 0x00000049, 15776 SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, 15777 SC_TILE_PICKED_H1 = 0x0000004b, 15778 SC_PERF_SEL_RESERVED_76 = 0x0000004c, 15779 SC_PERF_SEL_RESERVED_77 = 0x0000004d, 15780 SC_PERF_SEL_RESERVED_78 = 0x0000004e, 15781 SC_QZ0_TILE_COUNT = 0x0000004f, 15782 SC_PERF_SEL_RESERVED_80 = 0x00000050, 15783 SC_PERF_SEL_RESERVED_81 = 0x00000051, 15784 SC_PERF_SEL_RESERVED_82 = 0x00000052, 15785 SC_QZ0_TILE_COVERED_COUNT = 0x00000053, 15786 SC_PERF_SEL_RESERVED_84 = 0x00000054, 15787 SC_PERF_SEL_RESERVED_85 = 0x00000055, 15788 SC_PERF_SEL_RESERVED_86 = 0x00000056, 15789 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, 15790 SC_PERF_SEL_RESERVED_88 = 0x00000058, 15791 SC_PERF_SEL_RESERVED_89 = 0x00000059, 15792 SC_PERF_SEL_RESERVED_90 = 0x0000005a, 15793 SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, 15794 SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, 15795 SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, 15796 SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, 15797 SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, 15798 SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, 15799 SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, 15800 SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, 15801 SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, 15802 SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, 15803 SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, 15804 SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, 15805 SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, 15806 SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, 15807 SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, 15808 SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, 15809 SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, 15810 SC_PERF_SEL_RESERVED_108 = 0x0000006c, 15811 SC_PERF_SEL_RESERVED_109 = 0x0000006d, 15812 SC_PERF_SEL_RESERVED_110 = 0x0000006e, 15813 SC_PERF_SEL_RESERVED_111 = 0x0000006f, 15814 SC_PERF_SEL_RESERVED_112 = 0x00000070, 15815 SC_PERF_SEL_RESERVED_113 = 0x00000071, 15816 SC_PERF_SEL_RESERVED_114 = 0x00000072, 15817 SC_PERF_SEL_RESERVED_115 = 0x00000073, 15818 SC_PERF_SEL_RESERVED_116 = 0x00000074, 15819 SC_PERF_SEL_RESERVED_117 = 0x00000075, 15820 SC_PERF_SEL_RESERVED_118 = 0x00000076, 15821 SC_PERF_SEL_RESERVED_119 = 0x00000077, 15822 SC_PERF_SEL_RESERVED_120 = 0x00000078, 15823 SC_PERF_SEL_RESERVED_121 = 0x00000079, 15824 SC_PERF_SEL_RESERVED_122 = 0x0000007a, 15825 SC_PERF_SEL_RESERVED_123 = 0x0000007b, 15826 SC_PERF_SEL_RESERVED_124 = 0x0000007c, 15827 SC_PERF_SEL_RESERVED_125 = 0x0000007d, 15828 SC_PERF_SEL_RESERVED_126 = 0x0000007e, 15829 SC_PERF_SEL_RESERVED_127 = 0x0000007f, 15830 SC_PERF_SEL_RESERVED_128 = 0x00000080, 15831 SC_PERF_SEL_RESERVED_129 = 0x00000081, 15832 SC_PERF_SEL_RESERVED_130 = 0x00000082, 15833 SC_PERF_SEL_RESERVED_131 = 0x00000083, 15834 SC_PERF_SEL_RESERVED_132 = 0x00000084, 15835 SC_PERF_SEL_RESERVED_133 = 0x00000085, 15836 SC_PERF_SEL_RESERVED_134 = 0x00000086, 15837 SC_PERF_SEL_RESERVED_135 = 0x00000087, 15838 SC_PERF_SEL_RESERVED_136 = 0x00000088, 15839 SC_PERF_SEL_RESERVED_137 = 0x00000089, 15840 SC_PERF_SEL_RESERVED_138 = 0x0000008a, 15841 SC_PERF_SEL_RESERVED_139 = 0x0000008b, 15842 SC_PERF_SEL_RESERVED_140 = 0x0000008c, 15843 SC_PERF_SEL_RESERVED_141 = 0x0000008d, 15844 SC_PERF_SEL_RESERVED_142 = 0x0000008e, 15845 SC_PERF_SEL_RESERVED_143 = 0x0000008f, 15846 SC_PERF_SEL_RESERVED_144 = 0x00000090, 15847 SC_PERF_SEL_RESERVED_145 = 0x00000091, 15848 SC_PERF_SEL_RESERVED_146 = 0x00000092, 15849 SC_PERF_SEL_RESERVED_147 = 0x00000093, 15850 SC_PERF_SEL_RESERVED_148 = 0x00000094, 15851 SC_PERF_SEL_RESERVED_149 = 0x00000095, 15852 SC_PERF_SEL_RESERVED_150 = 0x00000096, 15853 SC_PERF_SEL_RESERVED_151 = 0x00000097, 15854 SC_PERF_SEL_RESERVED_152 = 0x00000098, 15855 SC_PERF_SEL_RESERVED_153 = 0x00000099, 15856 SC_PERF_SEL_RESERVED_154 = 0x0000009a, 15857 SC_PERF_SEL_RESERVED_155 = 0x0000009b, 15858 SC_PERF_SEL_RESERVED_156 = 0x0000009c, 15859 SC_PERF_SEL_RESERVED_157 = 0x0000009d, 15860 SC_PERF_SEL_RESERVED_158 = 0x0000009e, 15861 SC_QZ0_QUAD_COUNT = 0x0000009f, 15862 SC_PERF_SEL_RESERVED_160 = 0x000000a0, 15863 SC_PERF_SEL_RESERVED_161 = 0x000000a1, 15864 SC_PERF_SEL_RESERVED_162 = 0x000000a2, 15865 SC_P0_HIZ_TILE_COUNT = 0x000000a3, 15866 SC_PERF_SEL_RESERVED_164 = 0x000000a4, 15867 SC_PERF_SEL_RESERVED_165 = 0x000000a5, 15868 SC_PERF_SEL_RESERVED_166 = 0x000000a6, 15869 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, 15870 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, 15871 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, 15872 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, 15873 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, 15874 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, 15875 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, 15876 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, 15877 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, 15878 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, 15879 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, 15880 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, 15881 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, 15882 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, 15883 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, 15884 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, 15885 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, 15886 SC_PERF_SEL_RESERVED_184 = 0x000000b8, 15887 SC_PERF_SEL_RESERVED_185 = 0x000000b9, 15888 SC_PERF_SEL_RESERVED_186 = 0x000000ba, 15889 SC_PERF_SEL_RESERVED_187 = 0x000000bb, 15890 SC_PERF_SEL_RESERVED_188 = 0x000000bc, 15891 SC_PERF_SEL_RESERVED_189 = 0x000000bd, 15892 SC_PERF_SEL_RESERVED_190 = 0x000000be, 15893 SC_PERF_SEL_RESERVED_191 = 0x000000bf, 15894 SC_PERF_SEL_RESERVED_192 = 0x000000c0, 15895 SC_PERF_SEL_RESERVED_193 = 0x000000c1, 15896 SC_PERF_SEL_RESERVED_194 = 0x000000c2, 15897 SC_PERF_SEL_RESERVED_195 = 0x000000c3, 15898 SC_PERF_SEL_RESERVED_196 = 0x000000c4, 15899 SC_PERF_SEL_RESERVED_197 = 0x000000c5, 15900 SC_PERF_SEL_RESERVED_198 = 0x000000c6, 15901 SC_PERF_SEL_RESERVED_199 = 0x000000c7, 15902 SC_PERF_SEL_RESERVED_200 = 0x000000c8, 15903 SC_PERF_SEL_RESERVED_201 = 0x000000c9, 15904 SC_PERF_SEL_RESERVED_202 = 0x000000ca, 15905 SC_PERF_SEL_RESERVED_203 = 0x000000cb, 15906 SC_PERF_SEL_RESERVED_204 = 0x000000cc, 15907 SC_PERF_SEL_RESERVED_205 = 0x000000cd, 15908 SC_PERF_SEL_RESERVED_206 = 0x000000ce, 15909 SC_PERF_SEL_RESERVED_207 = 0x000000cf, 15910 SC_PERF_SEL_RESERVED_208 = 0x000000d0, 15911 SC_PERF_SEL_RESERVED_209 = 0x000000d1, 15912 SC_PERF_SEL_RESERVED_210 = 0x000000d2, 15913 SC_PERF_SEL_RESERVED_211 = 0x000000d3, 15914 SC_PERF_SEL_RESERVED_212 = 0x000000d4, 15915 SC_PERF_SEL_RESERVED_213 = 0x000000d5, 15916 SC_PERF_SEL_RESERVED_214 = 0x000000d6, 15917 SC_PERF_SEL_RESERVED_215 = 0x000000d7, 15918 SC_PERF_SEL_RESERVED_216 = 0x000000d8, 15919 SC_PERF_SEL_RESERVED_217 = 0x000000d9, 15920 SC_PERF_SEL_RESERVED_218 = 0x000000da, 15921 SC_PERF_SEL_RESERVED_219 = 0x000000db, 15922 SC_PERF_SEL_RESERVED_220 = 0x000000dc, 15923 SC_PERF_SEL_RESERVED_221 = 0x000000dd, 15924 SC_PERF_SEL_RESERVED_222 = 0x000000de, 15925 SC_PERF_SEL_RESERVED_223 = 0x000000df, 15926 SC_PERF_SEL_RESERVED_224 = 0x000000e0, 15927 SC_PERF_SEL_RESERVED_225 = 0x000000e1, 15928 SC_PERF_SEL_RESERVED_226 = 0x000000e2, 15929 SC_PERF_SEL_RESERVED_227 = 0x000000e3, 15930 SC_PERF_SEL_RESERVED_228 = 0x000000e4, 15931 SC_PERF_SEL_RESERVED_229 = 0x000000e5, 15932 SC_PERF_SEL_RESERVED_230 = 0x000000e6, 15933 SC_PERF_SEL_RESERVED_231 = 0x000000e7, 15934 SC_PERF_SEL_RESERVED_232 = 0x000000e8, 15935 SC_PERF_SEL_RESERVED_233 = 0x000000e9, 15936 SC_PERF_SEL_RESERVED_234 = 0x000000ea, 15937 SC_P0_HIZ_QUAD_COUNT = 0x000000eb, 15938 SC_PERF_SEL_RESERVED_236 = 0x000000ec, 15939 SC_PERF_SEL_RESERVED_237 = 0x000000ed, 15940 SC_PERF_SEL_RESERVED_238 = 0x000000ee, 15941 SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, 15942 SC_PERF_SEL_RESERVED_240 = 0x000000f0, 15943 SC_PERF_SEL_RESERVED_241 = 0x000000f1, 15944 SC_PERF_SEL_RESERVED_242 = 0x000000f2, 15945 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, 15946 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, 15947 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, 15948 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, 15949 SC_PERF_SEL_RESERVED_247 = 0x000000f7, 15950 SC_PERF_SEL_RESERVED_248 = 0x000000f8, 15951 SC_PERF_SEL_RESERVED_249 = 0x000000f9, 15952 SC_PERF_SEL_RESERVED_250 = 0x000000fa, 15953 SC_PERF_SEL_RESERVED_251 = 0x000000fb, 15954 SC_PERF_SEL_RESERVED_252 = 0x000000fc, 15955 SC_PERF_SEL_RESERVED_253 = 0x000000fd, 15956 SC_PERF_SEL_RESERVED_254 = 0x000000fe, 15957 SC_PERF_SEL_RESERVED_255 = 0x000000ff, 15958 SC_PERF_SEL_RESERVED_256 = 0x00000100, 15959 SC_PERF_SEL_RESERVED_257 = 0x00000101, 15960 SC_PERF_SEL_RESERVED_258 = 0x00000102, 15961 SC_EARLYZ_QUAD_COUNT = 0x00000103, 15962 SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, 15963 SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, 15964 SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, 15965 SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, 15966 SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, 15967 SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, 15968 SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, 15969 SC_PKR_4X2_FILL_QUAD = 0x0000010b, 15970 SC_PKR_END_OF_VECTOR = 0x0000010c, 15971 SC_PKR_CONTROL_XFER = 0x0000010d, 15972 SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, 15973 SC_REG_SCLK_BUSY = 0x0000010f, 15974 SC_GRP0_DYN_SCLK_BUSY = 0x00000110, 15975 SC_GRP1_DYN_SCLK_BUSY = 0x00000111, 15976 SC_GRP2_DYN_SCLK_BUSY = 0x00000112, 15977 SC_GRP3_DYN_SCLK_BUSY = 0x00000113, 15978 SC_GRP4_DYN_SCLK_BUSY = 0x00000114, 15979 SC_PA0_SC_DATA_FIFO_RD = 0x00000115, 15980 SC_PA0_SC_DATA_FIFO_WE = 0x00000116, 15981 SC_PERF_SEL_RESERVED_279 = 0x00000117, 15982 SC_PERF_SEL_RESERVED_280 = 0x00000118, 15983 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, 15984 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, 15985 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, 15986 SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, 15987 SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, 15988 SC_PS_ARB_SC_BUSY = 0x0000011e, 15989 SC_PS_ARB_PA_SC_BUSY = 0x0000011f, 15990 SC_PERF_SEL_RESERVED_288 = 0x00000120, 15991 SC_PERF_SEL_RESERVED_289 = 0x00000121, 15992 SC_PERF_SEL_RESERVED_290 = 0x00000122, 15993 SC_PERF_SEL_RESERVED_291 = 0x00000123, 15994 SC_PA_SC_DEALLOC_2_0_WE = 0x00000124, 15995 SC_PERF_SEL_RESERVED_293 = 0x00000125, 15996 SC_PERF_SEL_RESERVED_294 = 0x00000126, 15997 SC_PERF_SEL_RESERVED_295 = 0x00000127, 15998 SC_PERF_SEL_RESERVED_296 = 0x00000128, 15999 SC_PERF_SEL_RESERVED_297 = 0x00000129, 16000 SC_PERF_SEL_RESERVED_298 = 0x0000012a, 16001 SC_PERF_SEL_RESERVED_299 = 0x0000012b, 16002 SC_PA0_SC_EOP_WE = 0x0000012c, 16003 SC_PERF_SEL_RESERVED_301 = 0x0000012d, 16004 SC_PA0_SC_EVENT_WE = 0x0000012e, 16005 SC_PERF_SEL_RESERVED_303 = 0x0000012f, 16006 SC_PERF_SEL_RESERVED_304 = 0x00000130, 16007 SC_PERF_SEL_RESERVED_305 = 0x00000131, 16008 SC_PERF_SEL_RESERVED_306 = 0x00000132, 16009 SC_PERF_SEL_RESERVED_307 = 0x00000133, 16010 SC_PERF_SEL_RESERVED_308 = 0x00000134, 16011 SC_PERF_SEL_RESERVED_309 = 0x00000135, 16012 SC_PERF_SEL_RESERVED_310 = 0x00000136, 16013 SC_PERF_SEL_RESERVED_311 = 0x00000137, 16014 SC_PERF_SEL_RESERVED_312 = 0x00000138, 16015 SC_PERF_SEL_RESERVED_313 = 0x00000139, 16016 SC_PERF_SEL_RESERVED_314 = 0x0000013a, 16017 SC_PERF_SEL_RESERVED_315 = 0x0000013b, 16018 SC_PERF_SEL_RESERVED_316 = 0x0000013c, 16019 SC_PERF_SEL_RESERVED_317 = 0x0000013d, 16020 SC_PA_SC_FPOV_WE = 0x0000013e, 16021 SC_PERF_SEL_RESERVED_319 = 0x0000013f, 16022 SC_PERF_SEL_RESERVED_320 = 0x00000140, 16023 SC_PERF_SEL_RESERVED_321 = 0x00000141, 16024 SC_PERF_SEL_RESERVED_322 = 0x00000142, 16025 SC_PERF_SEL_RESERVED_323 = 0x00000143, 16026 SC_PERF_SEL_RESERVED_324 = 0x00000144, 16027 SC_PERF_SEL_RESERVED_325 = 0x00000145, 16028 SC_SPI_DEALLOC_4_0 = 0x00000146, 16029 SC_SPI_DEALLOC_7_5 = 0x00000147, 16030 SC_PERF_SEL_RESERVED_328 = 0x00000148, 16031 SC_PERF_SEL_RESERVED_329 = 0x00000149, 16032 SC_PERF_SEL_RESERVED_330 = 0x0000014a, 16033 SC_PERF_SEL_RESERVED_331 = 0x0000014b, 16034 SC_PERF_SEL_RESERVED_332 = 0x0000014c, 16035 SC_PERF_SEL_RESERVED_333 = 0x0000014d, 16036 SC_PERF_SEL_RESERVED_334 = 0x0000014e, 16037 SC_PERF_SEL_RESERVED_335 = 0x0000014f, 16038 SC_PERF_SEL_RESERVED_336 = 0x00000150, 16039 SC_PERF_SEL_RESERVED_337 = 0x00000151, 16040 SC_SPI_FPOV_4_0 = 0x00000152, 16041 SC_SPI_FPOV_7_5 = 0x00000153, 16042 SC_PERF_SEL_RESERVED_340 = 0x00000154, 16043 SC_PERF_SEL_RESERVED_341 = 0x00000155, 16044 SC_SPI_EVENT = 0x00000156, 16045 SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, 16046 SC_PS_TS_EVENT_FIFO_POP = 0x00000158, 16047 SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, 16048 SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, 16049 SC_PERF_SEL_RESERVED_347 = 0x0000015b, 16050 SC_PERF_SEL_RESERVED_348 = 0x0000015c, 16051 SC_PA0_SC_NULL_WE = 0x0000015d, 16052 SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, 16053 SC_PERF_SEL_RESERVED_351 = 0x0000015f, 16054 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, 16055 SC_PA0_SC_DEALLOC_2_0_RD = 0x00000161, 16056 SC_PERF_SEL_RESERVED_354 = 0x00000162, 16057 SC_PERF_SEL_RESERVED_355 = 0x00000163, 16058 SC_PERF_SEL_RESERVED_356 = 0x00000164, 16059 SC_PERF_SEL_RESERVED_357 = 0x00000165, 16060 SC_PERF_SEL_RESERVED_358 = 0x00000166, 16061 SC_PERF_SEL_RESERVED_359 = 0x00000167, 16062 SC_PERF_SEL_RESERVED_360 = 0x00000168, 16063 SC_PERF_SEL_RESERVED_361 = 0x00000169, 16064 SC_PERF_SEL_RESERVED_362 = 0x0000016a, 16065 SC_PERF_SEL_RESERVED_363 = 0x0000016b, 16066 SC_PERF_SEL_RESERVED_364 = 0x0000016c, 16067 SC_PERF_SEL_RESERVED_365 = 0x0000016d, 16068 SC_PERF_SEL_RESERVED_366 = 0x0000016e, 16069 SC_PERF_SEL_RESERVED_367 = 0x0000016f, 16070 SC_PERF_SEL_RESERVED_368 = 0x00000170, 16071 SC_PERF_SEL_RESERVED_369 = 0x00000171, 16072 SC_PERF_SEL_RESERVED_370 = 0x00000172, 16073 SC_PERF_SEL_RESERVED_371 = 0x00000173, 16074 SC_PERF_SEL_RESERVED_372 = 0x00000174, 16075 SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, 16076 SC_PS_PA0_SC_FIFO_FULL = 0x00000176, 16077 SC_PERF_SEL_RESERVED_375 = 0x00000177, 16078 SC_PERF_SEL_RESERVED_376 = 0x00000178, 16079 SC_PERF_SEL_RESERVED_377 = 0x00000179, 16080 SC_PERF_SEL_RESERVED_378 = 0x0000017a, 16081 SC_PERF_SEL_RESERVED_379 = 0x0000017b, 16082 SC_PERF_SEL_RESERVED_380 = 0x0000017c, 16083 SC_PERF_SEL_RESERVED_381 = 0x0000017d, 16084 SC_PERF_SEL_RESERVED_382 = 0x0000017e, 16085 SC_PERF_SEL_RESERVED_383 = 0x0000017f, 16086 SC_PERF_SEL_RESERVED_384 = 0x00000180, 16087 SC_PERF_SEL_RESERVED_385 = 0x00000181, 16088 SC_BUSY_CNT_NOT_ZERO = 0x00000182, 16089 SC_BM_BUSY = 0x00000183, 16090 SC_BACKEND_BUSY = 0x00000184, 16091 SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, 16092 SC_SCB_BUSY = 0x00000186, 16093 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, 16094 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, 16095 SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, 16096 SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, 16097 SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, 16098 SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, 16099 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, 16100 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, 16101 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, 16102 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, 16103 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, 16104 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, 16105 SC_PBB_BUSY = 0x00000193, 16106 SC_PBB_BUSY_AND_NO_SENDS = 0x00000194, 16107 SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, 16108 SC_PBB_NUM_BINS = 0x00000196, 16109 SC_PBB_END_OF_BIN = 0x00000197, 16110 SC_PBB_END_OF_BATCH = 0x00000198, 16111 SC_PBB_PRIMBIN_PROCESSED = 0x00000199, 16112 SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, 16113 SC_PBB_NONBINNED_PRIM = 0x0000019b, 16114 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, 16115 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, 16116 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, 16117 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, 16118 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, 16119 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, 16120 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, 16121 SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, 16122 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, 16123 SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, 16124 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, 16125 SC_PERF_SEL_RESERVED_423 = 0x000001a7, 16126 SC_PERF_SEL_RESERVED_424 = 0x000001a8, 16127 SC_PERF_SEL_RESERVED_425 = 0x000001a9, 16128 SC_PERF_SEL_RESERVED_426 = 0x000001aa, 16129 SC_PERF_SEL_RESERVED_427 = 0x000001ab, 16130 SC_PERF_SEL_RESERVED_428 = 0x000001ac, 16131 SC_PERF_SEL_RESERVED_429 = 0x000001ad, 16132 SC_PERF_SEL_RESERVED_430 = 0x000001ae, 16133 SC_PERF_SEL_RESERVED_431 = 0x000001af, 16134 SC_PERF_SEL_RESERVED_432 = 0x000001b0, 16135 SC_PERF_SEL_RESERVED_433 = 0x000001b1, 16136 SC_PERF_SEL_RESERVED_434 = 0x000001b2, 16137 SC_PERF_SEL_RESERVED_435 = 0x000001b3, 16138 SC_PERF_SEL_RESERVED_436 = 0x000001b4, 16139 SC_GRP5_DYN_SCLK_BUSY = 0x000001b5, 16140 SC_GRP6_DYN_SCLK_BUSY = 0x000001b6, 16141 SC_GRP7_DYN_SCLK_BUSY = 0x000001b7, 16142 SC_GRP8_DYN_SCLK_BUSY = 0x000001b8, 16143 SC_GRP9_DYN_SCLK_BUSY = 0x000001b9, 16144 SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba, 16145 SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb, 16146 SC_PK_BUSY = 0x000001bc, 16147 SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd, 16148 SC_PK_DEALLOC_WAVE_BREAK = 0x000001be, 16149 SC_SPI_SEND = 0x000001bf, 16150 SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0, 16151 SC_SPI_CREDIT_AT_MAX = 0x000001c1, 16152 SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2, 16153 SC_BCI_SEND = 0x000001c3, 16154 SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4, 16155 SC_BCI_CREDIT_AT_MAX = 0x000001c5, 16156 SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6, 16157 SC_SPIBC_FULL_FREEZE = 0x000001c7, 16158 SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8, 16159 SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9, 16160 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca, 16161 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb, 16162 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc, 16163 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd, 16164 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce, 16165 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf, 16166 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0, 16167 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1, 16168 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2, 16169 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3, 16170 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4, 16171 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5, 16172 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6, 16173 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7, 16174 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8, 16175 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9, 16176 SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da, 16177 SC_DB0_TILE_INTERFACE_BUSY = 0x000001db, 16178 SC_DB0_TILE_INTERFACE_SEND = 0x000001dc, 16179 SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd, 16180 SC_PERF_SEL_RESERVED_478 = 0x000001de, 16181 SC_PERF_SEL_RESERVED_479 = 0x000001df, 16182 SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0, 16183 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1, 16184 SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2, 16185 SC_PERF_SEL_RESERVED_483 = 0x000001e3, 16186 SC_PERF_SEL_RESERVED_484 = 0x000001e4, 16187 SC_PERF_SEL_RESERVED_485 = 0x000001e5, 16188 SC_PERF_SEL_RESERVED_486 = 0x000001e6, 16189 SC_PERF_SEL_RESERVED_487 = 0x000001e7, 16190 SC_PERF_SEL_RESERVED_488 = 0x000001e8, 16191 SC_PERF_SEL_RESERVED_489 = 0x000001e9, 16192 SC_PERF_SEL_RESERVED_490 = 0x000001ea, 16193 SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb, 16194 SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec, 16195 SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed, 16196 SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee, 16197 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef, 16198 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0, 16199 SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1, 16200 SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2, 16201 SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3, 16202 SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4, 16203 SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 0x000001f5, 16204 SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6, 16205 SC_STALLED_BY_DB0_TILEFIFO = 0x000001f7, 16206 SC_DB0_QUAD_INTF_SEND = 0x000001f8, 16207 SC_DB0_QUAD_INTF_BUSY = 0x000001f9, 16208 SC_DB0_QUAD_INTF_STALLED_BY_DB = 0x000001fa, 16209 SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 0x000001fb, 16210 SC_DB0_QUAD_INTF_IDLE = 0x000001fc, 16211 SC_PERF_SEL_RESERVED_509 = 0x000001fd, 16212 SC_PERF_SEL_RESERVED_510 = 0x000001fe, 16213 SC_PERF_SEL_RESERVED_511 = 0x000001ff, 16214 SC_PERF_SEL_RESERVED_512 = 0x00000200, 16215 SC_PERF_SEL_RESERVED_513 = 0x00000201, 16216 SC_PERF_SEL_RESERVED_514 = 0x00000202, 16217 SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 0x00000203, 16218 SC_PKR_WAVE_BREAK_FULL_TILE = 0x00000204, 16219 SC_RESERVED_60 = 0x00000205, 16220 SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206, 16221 SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207, 16222 SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 0x00000208, 16223 SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209, 16224 SC_DB0_TILE_MASK_FIFO_FULL = 0x0000020a, 16225 SC_PERF_SEL_RESERVED_523 = 0x0000020b, 16226 SC_PERF_SEL_RESERVED_524 = 0x0000020c, 16227 SC_PERF_SEL_RESERVED_525 = 0x0000020d, 16228 SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e, 16229 SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f, 16230 SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210, 16231 SC_PS_PM_PFF_PW_FULL = 0x00000211, 16232 SC_PS_PM_ZFF_PW_FULL = 0x00000212, 16233 SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 0x00000213, 16234 SC_PERF_SEL_RESERVED_532 = 0x00000214, 16235 SC_PERF_SEL_RESERVED_533 = 0x00000215, 16236 SC_PERF_SEL_RESERVED_534 = 0x00000216, 16237 SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 0x00000217, 16238 SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 0x00000218, 16239 SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 0x00000219, 16240 SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 0x0000021a, 16241 SC_PERF_SEL_RESERVED_539 = 0x0000021b, 16242 SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 0x0000021c, 16243 SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x0000021d, 16244 SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 0x0000021e, 16245 SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f, 16246 SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 0x00000220, 16247 SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 0x00000221, 16248 SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 0x00000222, 16249 SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H = 0x00000223, 16250 SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224, 16251 SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225, 16252 SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226, 16253 SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227, 16254 SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 0x00000228, 16255 SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 0x00000229, 16256 SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 0x0000022a, 16257 SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 0x0000022b, 16258 SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 0x0000022c, 16259 SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 0x0000022d, 16260 SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 0x0000022e, 16261 SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 0x0000022f, 16262 SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 0x00000230, 16263 SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 0x00000231, 16264 SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 0x00000232, 16265 SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 0x00000233, 16266 SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 0x00000234, 16267 SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 0x00000235, 16268 SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 0x00000236, 16269 SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 0x00000237, 16270 SC_PERF_SEL_RESERVED_568 = 0x00000238, 16271 SC_PBB_RESERVED = 0x00000239, 16272 SC_BM_BE0_STALLED = 0x0000023a, 16273 SC_BM_BE1_STALLED = 0x0000023b, 16274 SC_BM_BE2_STALLED = 0x0000023c, 16275 SC_BM_BE3_STALLED = 0x0000023d, 16276 SC_BM_MULTI_ACCUM_1_BE_STALLED = 0x0000023e, 16277 SC_BM_MULTI_ACCUM_2_BE_STALLED = 0x0000023f, 16278 SC_BM_MULTI_ACCUM_3_BE_STALLED = 0x00000240, 16279 SC_BM_MULTI_ACCUM_4_BE_STALLED = 0x00000241, 16280 SC_PBB_READ_PH0 = 0x00000242, 16281 SC_PBB_READ_DEALLOC_4_0 = 0x00000243, 16282 SC_PBB_READ_DEALLOC_7_5 = 0x00000244, 16283 SC_PBB_READ_FPOG_4_0 = 0x00000245, 16284 SC_PBB_READ_FPOG_7_5 = 0x00000246, 16285 SC_VRC_SECTOR_HIT = 0x00000247, 16286 SC_VRC_TAG_MISS = 0x00000248, 16287 SC_VRC_SECTOR_MISS = 0x00000249, 16288 SC_VRC_LRU_EVICT_STALL = 0x0000024a, 16289 SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL = 0x0000024b, 16290 SC_VRC_LRU_EVICT_PENDING_EVICT_STALL = 0x0000024c, 16291 SC_VRC_REEVICTION_STALL = 0x0000024d, 16292 SC_VRC_EVICT_NONZERO_INFLIGHT_STALL = 0x0000024e, 16293 SC_VRC_REPLACE_SCHEDULED_EVICT_STALL = 0x0000024f, 16294 SC_VRC_REPLACE_PENDING_EVICT_STALL = 0x00000250, 16295 SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL = 0x00000251, 16296 SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000252, 16297 SC_VRC_READ_OUTPUT_STALL = 0x00000253, 16298 SC_VRC_WRITE_OUTPUT_STALL = 0x00000254, 16299 SC_VRC_ACK_OUTPUT_STALL = 0x00000255, 16300 SC_VRC_FLUSH_EVICT_STALL = 0x00000256, 16301 SC_VRC_FLUSH_REFLUSH_STALL = 0x00000257, 16302 SC_VRC_FLUSH_FIP_HIT_STALL = 0x00000258, 16303 SC_VRC_FLUSH_WRREQ_DRAIN_STALL = 0x00000259, 16304 SC_VRC_FLUSH_DONE_STALL = 0x0000025a, 16305 SC_VRC_FLUSH_STALL = 0x0000025b, 16306 SC_VRC_STALL = 0x0000025c, 16307 SC_VRC_FLUSH = 0x0000025d, 16308 SC_VRC_SECTORS_FLUSHED = 0x0000025e, 16309 SC_VRC_DIRTY_SECTORS_FLUSHED = 0x0000025f, 16310 SC_VRC_TAGS_FLUSHED = 0x00000260, 16311 SC_VRC_HPF_REQ = 0x00000261, 16312 SC_VRC_HPF_EVENT = 0x00000262, 16313 SC_VRC_HPF_STALLED = 0x00000263, 16314 SC_VRC_PROBE_ACK_TILES = 0x00000264, 16315 SC_VRC_GL1X_RD_REQ = 0x00000265, 16316 SC_VRC_GL1X_WR_REQ = 0x00000266, 16317 SC_VRC_GL1X_SRC_XFR = 0x00000267, 16318 SC_VRC_GL1X_RD_RET = 0x00000268, 16319 SC_VRC_GL1X_WR_ACK = 0x00000269, 16320 SC_VRC_GL1X_RD_XNACK = 0x0000026a, 16321 SC_VRC_GL1X_WR_XNACK = 0x0000026b, 16322 SC_VRC_GL1X_REQ_STALLED = 0x0000026c, 16323 SC_VRC_GL1X_SRC_STALLED = 0x0000026d, 16324 SC_VRC_RATEMEM_WE_CNT = 0x0000026e, 16325 SC_VRC_RATEMEM_RE_CNT = 0x0000026f, 16326 SC_VRC_HINTMEM_WE_CNT = 0x00000270, 16327 SC_VRC_HINTMEM_RE_CNT = 0x00000271, 16328 SC_VRC_BUSY = 0x00000272, 16329 SC_GL1X_BUSY = 0x00000273, 16330 SC_BE_VRS_RD_REQ = 0x00000274, 16331 SC_BE_VRS_RD_REQ_STALLED = 0x00000275, 16332 SC_BE_VRS_RD_REQ_HIT = 0x00000276, 16333 SC_BE_VRS_RD_RET = 0x00000277, 16334 SC_BE_VRS_RD_RET_STALLED = 0x00000278, 16335 SC_BE_VRS_FB_RET = 0x00000279, 16336 SC_BE_VRS_FB_RET_STALLED = 0x0000027a, 16337 SC_BE_VRS_FB_RET_HIT = 0x0000027b, 16338 SC_VRS_BE_BUSY = 0x0000027c, 16339 SC_PWS_CS_EVENTS_PWS_ENABLE = 0x0000027d, 16340 SC_PWS_PS_EVENTS_PWS_ENABLE = 0x0000027e, 16341 SC_PWS_TS_EVENTS_PWS_ENABLE = 0x0000027f, 16342 SC_PWS_STALLED = 0x00000280, 16343 SC_PWS_P0_CS_SYNC_COMPLETE = 0x00000281, 16344 SC_PWS_P0_PS_SYNC_COMPLETE = 0x00000282, 16345 SC_PWS_P0_TS_SYNC_COMPLETE = 0x00000283, 16346 SC_PWS_P1_CS_SYNC_COMPLETE = 0x00000284, 16347 SC_PWS_P1_PS_SYNC_COMPLETE = 0x00000285, 16348 SC_PWS_P1_TS_SYNC_COMPLETE = 0x00000286, 16349 SC_PKR_PC_NO_CREDITS = 0x00000287, 16350 SC_PKR_PC_STALLED = 0x00000288, 16351 SC_PKR_PC_SEND = 0x00000289, 16352 SC_PKR_PC_SEND_PRIM_VALID_1 = 0x0000028a, 16353 SC_PKR_PC_SEND_PRIM_VALID_0 = 0x0000028b, 16354 SC_PKR_PC_SEND_TRUE_PRIM = 0x0000028c, 16355 SC_PKR_PC_SEND_EOV = 0x0000028d, 16356 SC_PKR_PC_SEND_EVENT = 0x0000028e, 16357 SC_PKR_DB_WAVE_STALL = 0x0000028f, 16358 SC_PKR_PSINVOC_SEDC_FIFO_FULL = 0x00000290, 16359 SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID = 0x00000291, 16360 SC_PKR_SPI_QUAD_COUNT = 0x00000292, 16361 SC_PKR_DB_OREO_WAVE_QUAD_COUNT = 0x00000293, 16362 SC_PKR_BCI_QUAD_NEW_PRIM = 0x00000294, 16363 SC_SPI_WAVE_STALLED_BY_SPI = 0x00000295, 16364 } SC_PERFCNT_SEL; 16365 16366 /* 16367 * ScMap enum 16368 */ 16369 16370 typedef enum ScMap { 16371 RASTER_CONFIG_SC_MAP_0 = 0x00000000, 16372 RASTER_CONFIG_SC_MAP_1 = 0x00000001, 16373 RASTER_CONFIG_SC_MAP_2 = 0x00000002, 16374 RASTER_CONFIG_SC_MAP_3 = 0x00000003, 16375 } ScMap; 16376 16377 /* 16378 * ScUncertaintyRegionMode enum 16379 */ 16380 16381 typedef enum ScUncertaintyRegionMode { 16382 SC_HALF_LSB = 0x00000000, 16383 SC_LSB_ONE_SIDED = 0x00000001, 16384 SC_LSB_TWO_SIDED = 0x00000002, 16385 } ScUncertaintyRegionMode; 16386 16387 /* 16388 * ScUncertaintyRegionMult enum 16389 */ 16390 16391 typedef enum ScUncertaintyRegionMult { 16392 SC_UR_1X = 0x00000000, 16393 SC_UR_2X = 0x00000001, 16394 SC_UR_4X = 0x00000002, 16395 SC_UR_8X = 0x00000003, 16396 } ScUncertaintyRegionMult; 16397 16398 /* 16399 * ScXsel enum 16400 */ 16401 16402 typedef enum ScXsel { 16403 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, 16404 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, 16405 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, 16406 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, 16407 } ScXsel; 16408 16409 /* 16410 * ScYsel enum 16411 */ 16412 16413 typedef enum ScYsel { 16414 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, 16415 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, 16416 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, 16417 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, 16418 } ScYsel; 16419 16420 /* 16421 * SeMap enum 16422 */ 16423 16424 typedef enum SeMap { 16425 RASTER_CONFIG_SE_MAP_0 = 0x00000000, 16426 RASTER_CONFIG_SE_MAP_1 = 0x00000001, 16427 RASTER_CONFIG_SE_MAP_2 = 0x00000002, 16428 RASTER_CONFIG_SE_MAP_3 = 0x00000003, 16429 } SeMap; 16430 16431 /* 16432 * SePairMap enum 16433 */ 16434 16435 typedef enum SePairMap { 16436 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, 16437 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, 16438 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, 16439 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, 16440 } SePairMap; 16441 16442 /* 16443 * SePairXsel enum 16444 */ 16445 16446 typedef enum SePairXsel { 16447 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, 16448 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, 16449 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, 16450 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, 16451 } SePairXsel; 16452 16453 /* 16454 * SePairYsel enum 16455 */ 16456 16457 typedef enum SePairYsel { 16458 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, 16459 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, 16460 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, 16461 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, 16462 } SePairYsel; 16463 16464 /* 16465 * SeXsel enum 16466 */ 16467 16468 typedef enum SeXsel { 16469 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, 16470 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, 16471 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, 16472 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, 16473 } SeXsel; 16474 16475 /* 16476 * SeYsel enum 16477 */ 16478 16479 typedef enum SeYsel { 16480 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, 16481 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, 16482 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, 16483 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, 16484 } SeYsel; 16485 16486 /* 16487 * VRSCombinerModeSC enum 16488 */ 16489 16490 typedef enum VRSCombinerModeSC { 16491 SC_VRS_COMB_MODE_PASSTHRU = 0x00000000, 16492 SC_VRS_COMB_MODE_OVERRIDE = 0x00000001, 16493 SC_VRS_COMB_MODE_MIN = 0x00000002, 16494 SC_VRS_COMB_MODE_MAX = 0x00000003, 16495 SC_VRS_COMB_MODE_SATURATE = 0x00000004, 16496 } VRSCombinerModeSC; 16497 16498 /* 16499 * VRSrate enum 16500 */ 16501 16502 typedef enum VRSrate { 16503 VRS_SHADING_RATE_1X1 = 0x00000000, 16504 VRS_SHADING_RATE_1X2 = 0x00000001, 16505 VRS_SHADING_RATE_UNDEFINED0 = 0x00000002, 16506 VRS_SHADING_RATE_UNDEFINED1 = 0x00000003, 16507 VRS_SHADING_RATE_2X1 = 0x00000004, 16508 VRS_SHADING_RATE_2X2 = 0x00000005, 16509 VRS_SHADING_RATE_2X4 = 0x00000006, 16510 VRS_SHADING_RATE_UNDEFINED2 = 0x00000007, 16511 VRS_SHADING_RATE_UNDEFINED3 = 0x00000008, 16512 VRS_SHADING_RATE_4X2 = 0x00000009, 16513 VRS_SHADING_RATE_4X4 = 0x0000000a, 16514 VRS_SHADING_RATE_UNDEFINED4 = 0x0000000b, 16515 VRS_SHADING_RATE_16X_SSAA = 0x0000000c, 16516 VRS_SHADING_RATE_8X_SSAA = 0x0000000d, 16517 VRS_SHADING_RATE_4X_SSAA = 0x0000000e, 16518 VRS_SHADING_RATE_2X_SSAA = 0x0000000f, 16519 } VRSrate; 16520 16521 /******************************************************* 16522 * TC Enums 16523 *******************************************************/ 16524 16525 /* 16526 * TC_EA_CID enum 16527 */ 16528 16529 typedef enum TC_EA_CID { 16530 TC_EA_CID_RT = 0x00000000, 16531 TC_EA_CID_FMASK = 0x00000001, 16532 TC_EA_CID_DCC = 0x00000002, 16533 TC_EA_CID_TCPMETA = 0x00000003, 16534 TC_EA_CID_Z = 0x00000004, 16535 TC_EA_CID_STENCIL = 0x00000005, 16536 TC_EA_CID_HTILE = 0x00000006, 16537 TC_EA_CID_MISC = 0x00000007, 16538 TC_EA_CID_TCP = 0x00000008, 16539 TC_EA_CID_SQC = 0x00000009, 16540 TC_EA_CID_CPF = 0x0000000a, 16541 TC_EA_CID_CPG = 0x0000000b, 16542 TC_EA_CID_IA = 0x0000000c, 16543 TC_EA_CID_WD = 0x0000000d, 16544 TC_EA_CID_PA = 0x0000000e, 16545 TC_EA_CID_UTCL2_TPI = 0x0000000f, 16546 } TC_EA_CID; 16547 16548 /* 16549 * TC_NACKS enum 16550 */ 16551 16552 typedef enum TC_NACKS { 16553 TC_NACK_NO_FAULT = 0x00000000, 16554 TC_NACK_PAGE_FAULT = 0x00000001, 16555 TC_NACK_PROTECTION_FAULT = 0x00000002, 16556 TC_NACK_DATA_ERROR = 0x00000003, 16557 } TC_NACKS; 16558 16559 /* 16560 * TC_OP enum 16561 */ 16562 16563 typedef enum TC_OP { 16564 TC_OP_READ = 0x00000000, 16565 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, 16566 TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, 16567 TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, 16568 TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, 16569 TC_OP_RESERVED_FADD_RTN_32 = 0x00000005, 16570 TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, 16571 TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, 16572 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, 16573 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, 16574 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, 16575 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, 16576 TC_OP_PROBE_FILTER = 0x0000000c, 16577 TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, 16578 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, 16579 TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, 16580 TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, 16581 TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, 16582 TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, 16583 TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, 16584 TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, 16585 TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, 16586 TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, 16587 TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, 16588 TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, 16589 TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, 16590 TC_OP_WBINVL1_VOL = 0x0000001a, 16591 TC_OP_WBINVL1_SD = 0x0000001b, 16592 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, 16593 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, 16594 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, 16595 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, 16596 TC_OP_WRITE = 0x00000020, 16597 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, 16598 TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, 16599 TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, 16600 TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, 16601 TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, 16602 TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, 16603 TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, 16604 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, 16605 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, 16606 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, 16607 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, 16608 TC_OP_WBINVL2_SD = 0x0000002c, 16609 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, 16610 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, 16611 TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, 16612 TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, 16613 TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, 16614 TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, 16615 TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, 16616 TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, 16617 TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, 16618 TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, 16619 TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, 16620 TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, 16621 TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, 16622 TC_OP_WBL2_NC = 0x0000003a, 16623 TC_OP_WBL2_WC = 0x0000003b, 16624 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, 16625 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, 16626 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, 16627 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, 16628 TC_OP_WBINVL1 = 0x00000040, 16629 TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, 16630 TC_OP_ATOMIC_FMIN_32 = 0x00000042, 16631 TC_OP_ATOMIC_FMAX_32 = 0x00000043, 16632 TC_OP_RESERVED_FOP_32_0 = 0x00000044, 16633 TC_OP_RESERVED_FADD_32 = 0x00000045, 16634 TC_OP_RESERVED_FOP_32_2 = 0x00000046, 16635 TC_OP_ATOMIC_SWAP_32 = 0x00000047, 16636 TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, 16637 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, 16638 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, 16639 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, 16640 TC_OP_INV_METADATA = 0x0000004c, 16641 TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, 16642 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, 16643 TC_OP_ATOMIC_ADD_32 = 0x0000004f, 16644 TC_OP_ATOMIC_SUB_32 = 0x00000050, 16645 TC_OP_ATOMIC_SMIN_32 = 0x00000051, 16646 TC_OP_ATOMIC_UMIN_32 = 0x00000052, 16647 TC_OP_ATOMIC_SMAX_32 = 0x00000053, 16648 TC_OP_ATOMIC_UMAX_32 = 0x00000054, 16649 TC_OP_ATOMIC_AND_32 = 0x00000055, 16650 TC_OP_ATOMIC_OR_32 = 0x00000056, 16651 TC_OP_ATOMIC_XOR_32 = 0x00000057, 16652 TC_OP_ATOMIC_INC_32 = 0x00000058, 16653 TC_OP_ATOMIC_DEC_32 = 0x00000059, 16654 TC_OP_INVL2_NC = 0x0000005a, 16655 TC_OP_NOP_RTN0 = 0x0000005b, 16656 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, 16657 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, 16658 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, 16659 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, 16660 TC_OP_WBINVL2 = 0x00000060, 16661 TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, 16662 TC_OP_ATOMIC_FMIN_64 = 0x00000062, 16663 TC_OP_ATOMIC_FMAX_64 = 0x00000063, 16664 TC_OP_RESERVED_FOP_64_0 = 0x00000064, 16665 TC_OP_RESERVED_FOP_64_1 = 0x00000065, 16666 TC_OP_RESERVED_FOP_64_2 = 0x00000066, 16667 TC_OP_ATOMIC_SWAP_64 = 0x00000067, 16668 TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, 16669 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, 16670 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, 16671 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, 16672 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, 16673 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, 16674 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, 16675 TC_OP_ATOMIC_ADD_64 = 0x0000006f, 16676 TC_OP_ATOMIC_SUB_64 = 0x00000070, 16677 TC_OP_ATOMIC_SMIN_64 = 0x00000071, 16678 TC_OP_ATOMIC_UMIN_64 = 0x00000072, 16679 TC_OP_ATOMIC_SMAX_64 = 0x00000073, 16680 TC_OP_ATOMIC_UMAX_64 = 0x00000074, 16681 TC_OP_ATOMIC_AND_64 = 0x00000075, 16682 TC_OP_ATOMIC_OR_64 = 0x00000076, 16683 TC_OP_ATOMIC_XOR_64 = 0x00000077, 16684 TC_OP_ATOMIC_INC_64 = 0x00000078, 16685 TC_OP_ATOMIC_DEC_64 = 0x00000079, 16686 TC_OP_WBINVL2_NC = 0x0000007a, 16687 TC_OP_NOP_ACK = 0x0000007b, 16688 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, 16689 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, 16690 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, 16691 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, 16692 } TC_OP; 16693 16694 /* 16695 * TC_OP_MASKS enum 16696 */ 16697 16698 typedef enum TC_OP_MASKS { 16699 TC_OP_MASK_FLUSH_DENROM = 0x00000008, 16700 TC_OP_MASK_64 = 0x00000020, 16701 TC_OP_MASK_NO_RTN = 0x00000040, 16702 } TC_OP_MASKS; 16703 16704 /******************************************************* 16705 * SPI Enums 16706 *******************************************************/ 16707 16708 /* 16709 * CLKGATE_BASE_MODE enum 16710 */ 16711 16712 typedef enum CLKGATE_BASE_MODE { 16713 MULT_8 = 0x00000000, 16714 MULT_16 = 0x00000001, 16715 } CLKGATE_BASE_MODE; 16716 16717 /* 16718 * CLKGATE_SM_MODE enum 16719 */ 16720 16721 typedef enum CLKGATE_SM_MODE { 16722 ON_SEQ = 0x00000000, 16723 OFF_SEQ = 0x00000001, 16724 PROG_SEQ = 0x00000002, 16725 READ_SEQ = 0x00000003, 16726 SM_MODE_RESERVED = 0x00000004, 16727 } CLKGATE_SM_MODE; 16728 16729 /* 16730 * CovToShaderSel enum 16731 */ 16732 16733 typedef enum CovToShaderSel { 16734 INPUT_COVERAGE = 0x00000000, 16735 INPUT_INNER_COVERAGE = 0x00000001, 16736 INPUT_DEPTH_COVERAGE = 0x00000002, 16737 RAW = 0x00000003, 16738 } CovToShaderSel; 16739 16740 /* 16741 * PC_PERFCNT_SEL enum 16742 */ 16743 16744 typedef enum PC_PERFCNT_SEL { 16745 PC_PERF_SC_PC_PTR_SEND0 = 0x00000000, 16746 PC_PERF_SC_PC_PTR_VALID0 = 0x00000001, 16747 PC_PERF_SC_FPOSG0 = 0x00000002, 16748 PC_PERF_SC_FPOSG_WAIT0 = 0x00000003, 16749 PC_PERF_SC_WAIT_SYNC0 = 0x00000004, 16750 PC_PERF_SC_PQ_FREEZE0 = 0x00000005, 16751 PC_PERF_PKR0_FPOSG_EQ1 = 0x00000006, 16752 PC_PERF_PKR0_FPOSG_GT1 = 0x00000007, 16753 PC_PERF_PKR0_FPOSG_GT16 = 0x00000008, 16754 PC_PERF_PKR0_FPOSG_GT64 = 0x00000009, 16755 PC_PERF_PKR0_FPOSG_GT128 = 0x0000000a, 16756 PC_PERF_PKR0_FPOSG_OUT_OF_WAVE = 0x0000000b, 16757 PC_PERF_PKR0_NUM_PROBES = 0x0000000c, 16758 PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1 = 0x0000000d, 16759 PC_PERF_PKR0_PRIMS_PER_PROBE_GT1 = 0x0000000e, 16760 PC_PERF_PKR0_PRIMS_PER_PROBE_GT2 = 0x0000000f, 16761 PC_PERF_PKR0_PRIMS_PER_PROBE_GT4 = 0x00000010, 16762 PC_PERF_PKR0_PRIMS_PER_PROBE_GT8 = 0x00000011, 16763 PC_PERF_PKR0_NUM_WAVES = 0x00000012, 16764 PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1 = 0x00000013, 16765 PC_PERF_PKR0_PRIMS_PER_WAVE_GT1 = 0x00000014, 16766 PC_PERF_PKR0_PRIMS_PER_WAVE_GT2 = 0x00000015, 16767 PC_PERF_PKR0_PRIMS_PER_WAVE_GT4 = 0x00000016, 16768 PC_PERF_PKR0_PRIMS_PER_WAVE_GT8 = 0x00000017, 16769 PC_PERF_PKR0_PROBES_PER_WAVE_EQ1 = 0x00000018, 16770 PC_PERF_PKR0_PROBES_PER_WAVE_GT1 = 0x00000019, 16771 PC_PERF_PKR0_PROBES_PER_WAVE_GT2 = 0x0000001a, 16772 PC_PERF_PKR0_PROBES_PER_WAVE_GT4 = 0x0000001b, 16773 PC_PERF_PKR0_PROBES_PER_WAVE_GT8 = 0x0000001c, 16774 PC_PERF_PKR0_PRIMS_REUSE = 0x0000001d, 16775 PC_PERF_SC_PC_PTR_SEND1 = 0x0000001e, 16776 PC_PERF_SC_PC_PTR_VALID1 = 0x0000001f, 16777 PC_PERF_SC_FPOSG1 = 0x00000020, 16778 PC_PERF_SC_FPOSG_WAIT1 = 0x00000021, 16779 PC_PERF_SC_WAIT_SYNC1 = 0x00000022, 16780 PC_PERF_SC_PQ_FREEZE1 = 0x00000023, 16781 PC_PERF_PKR1_FPOSG_EQ1 = 0x00000024, 16782 PC_PERF_PKR1_FPOSG_GT1 = 0x00000025, 16783 PC_PERF_PKR1_FPOSG_GT16 = 0x00000026, 16784 PC_PERF_PKR1_FPOSG_GT64 = 0x00000027, 16785 PC_PERF_PKR1_FPOSG_GT128 = 0x00000028, 16786 PC_PERF_PKR1_FPOSG_OUT_OF_WAVE = 0x00000029, 16787 PC_PERF_PKR1_NUM_PROBES = 0x0000002a, 16788 PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1 = 0x0000002b, 16789 PC_PERF_PKR1_PRIMS_PER_PROBE_GT1 = 0x0000002c, 16790 PC_PERF_PKR1_PRIMS_PER_PROBE_GT2 = 0x0000002d, 16791 PC_PERF_PKR1_PRIMS_PER_PROBE_GT4 = 0x0000002e, 16792 PC_PERF_PKR1_PRIMS_PER_PROBE_GT8 = 0x0000002f, 16793 PC_PERF_PKR1_NUM_WAVES = 0x00000030, 16794 PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1 = 0x00000031, 16795 PC_PERF_PKR1_PRIMS_PER_WAVE_GT1 = 0x00000032, 16796 PC_PERF_PKR1_PRIMS_PER_WAVE_GT2 = 0x00000033, 16797 PC_PERF_PKR1_PRIMS_PER_WAVE_GT4 = 0x00000034, 16798 PC_PERF_PKR1_PRIMS_PER_WAVE_GT8 = 0x00000035, 16799 PC_PERF_PKR1_PROBES_PER_WAVE_EQ1 = 0x00000036, 16800 PC_PERF_PKR1_PROBES_PER_WAVE_GT1 = 0x00000037, 16801 PC_PERF_PKR1_PROBES_PER_WAVE_GT2 = 0x00000038, 16802 PC_PERF_PKR1_PROBES_PER_WAVE_GT4 = 0x00000039, 16803 PC_PERF_PKR1_PROBES_PER_WAVE_GT8 = 0x0000003a, 16804 PC_PERF_PKR1_PRIMS_REUSE = 0x0000003b, 16805 PC_PERF_SC_PC_PTR_SEND2 = 0x0000003c, 16806 PC_PERF_SC_PC_PTR_VALID2 = 0x0000003d, 16807 PC_PERF_SC_FPOSG2 = 0x0000003e, 16808 PC_PERF_SC_FPOSG_WAIT2 = 0x0000003f, 16809 PC_PERF_SC_WAIT_SYNC2 = 0x00000040, 16810 PC_PERF_SC_PQ_FREEZE2 = 0x00000041, 16811 PC_PERF_PKR2_FPOSG_EQ1 = 0x00000042, 16812 PC_PERF_PKR2_FPOSG_GT1 = 0x00000043, 16813 PC_PERF_PKR2_FPOSG_GT16 = 0x00000044, 16814 PC_PERF_PKR2_FPOSG_GT64 = 0x00000045, 16815 PC_PERF_PKR2_FPOSG_GT128 = 0x00000046, 16816 PC_PERF_PKR2_FPOSG_OUT_OF_WAVE = 0x00000047, 16817 PC_PERF_PKR2_NUM_PROBES = 0x00000048, 16818 PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1 = 0x00000049, 16819 PC_PERF_PKR2_PRIMS_PER_PROBE_GT1 = 0x0000004a, 16820 PC_PERF_PKR2_PRIMS_PER_PROBE_GT2 = 0x0000004b, 16821 PC_PERF_PKR2_PRIMS_PER_PROBE_GT4 = 0x0000004c, 16822 PC_PERF_PKR2_PRIMS_PER_PROBE_GT8 = 0x0000004d, 16823 PC_PERF_PKR2_NUM_WAVES = 0x0000004e, 16824 PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1 = 0x0000004f, 16825 PC_PERF_PKR2_PRIMS_PER_WAVE_GT1 = 0x00000050, 16826 PC_PERF_PKR2_PRIMS_PER_WAVE_GT2 = 0x00000051, 16827 PC_PERF_PKR2_PRIMS_PER_WAVE_GT4 = 0x00000052, 16828 PC_PERF_PKR2_PRIMS_PER_WAVE_GT8 = 0x00000053, 16829 PC_PERF_PKR2_PROBES_PER_WAVE_EQ1 = 0x00000054, 16830 PC_PERF_PKR2_PROBES_PER_WAVE_GT1 = 0x00000055, 16831 PC_PERF_PKR2_PROBES_PER_WAVE_GT2 = 0x00000056, 16832 PC_PERF_PKR2_PROBES_PER_WAVE_GT4 = 0x00000057, 16833 PC_PERF_PKR2_PROBES_PER_WAVE_GT8 = 0x00000058, 16834 PC_PERF_PKR2_PRIMS_REUSE = 0x00000059, 16835 PC_PERF_SC_PC_PTR_SEND3 = 0x0000005a, 16836 PC_PERF_SC_PC_PTR_VALID3 = 0x0000005b, 16837 PC_PERF_SC_FPOSG3 = 0x0000005c, 16838 PC_PERF_SC_FPOSG_WAIT3 = 0x0000005d, 16839 PC_PERF_SC_WAIT_SYNC3 = 0x0000005e, 16840 PC_PERF_SC_PQ_FREEZE3 = 0x0000005f, 16841 PC_PERF_PKR3_FPOSG_EQ1 = 0x00000060, 16842 PC_PERF_PKR3_FPOSG_GT1 = 0x00000061, 16843 PC_PERF_PKR3_FPOSG_GT16 = 0x00000062, 16844 PC_PERF_PKR3_FPOSG_GT64 = 0x00000063, 16845 PC_PERF_PKR3_FPOSG_GT128 = 0x00000064, 16846 PC_PERF_PKR3_FPOSG_OUT_OF_WAVE = 0x00000065, 16847 PC_PERF_PKR3_NUM_PROBES = 0x00000066, 16848 PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1 = 0x00000067, 16849 PC_PERF_PKR3_PRIMS_PER_PROBE_GT1 = 0x00000068, 16850 PC_PERF_PKR3_PRIMS_PER_PROBE_GT2 = 0x00000069, 16851 PC_PERF_PKR3_PRIMS_PER_PROBE_GT4 = 0x0000006a, 16852 PC_PERF_PKR3_PRIMS_PER_PROBE_GT8 = 0x0000006b, 16853 PC_PERF_PKR3_NUM_WAVES = 0x0000006c, 16854 PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1 = 0x0000006d, 16855 PC_PERF_PKR3_PRIMS_PER_WAVE_GT1 = 0x0000006e, 16856 PC_PERF_PKR3_PRIMS_PER_WAVE_GT2 = 0x0000006f, 16857 PC_PERF_PKR3_PRIMS_PER_WAVE_GT4 = 0x00000070, 16858 PC_PERF_PKR3_PRIMS_PER_WAVE_GT8 = 0x00000071, 16859 PC_PERF_PKR3_PROBES_PER_WAVE_EQ1 = 0x00000072, 16860 PC_PERF_PKR3_PROBES_PER_WAVE_GT1 = 0x00000073, 16861 PC_PERF_PKR3_PROBES_PER_WAVE_GT2 = 0x00000074, 16862 PC_PERF_PKR3_PROBES_PER_WAVE_GT4 = 0x00000075, 16863 PC_PERF_PKR3_PROBES_PER_WAVE_GT8 = 0x00000076, 16864 PC_PERF_PKR3_PRIMS_REUSE = 0x00000077, 16865 PC_PERF_SC_MW_FREEZE = 0x00000078, 16866 PC_PERF_SC_NUM_PROBES = 0x00000079, 16867 PC_PERF_SC_NUM_WAVES = 0x0000007a, 16868 PC_PERF_SC_NUM_SPLIT_WAVES = 0x0000007b, 16869 PC_PERF_GE_GSDONE = 0x0000007c, 16870 PC_PERF_PKR0_GSDONE_WHILE_IDLE = 0x0000007d, 16871 PC_PERF_PKR1_GSDONE_WHILE_IDLE = 0x0000007e, 16872 PC_PERF_PKR2_GSDONE_WHILE_IDLE = 0x0000007f, 16873 PC_PERF_PKR3_GSDONE_WHILE_IDLE = 0x00000080, 16874 PC_PERF_PC_SPI_PROBE_FREEZE = 0x00000081, 16875 PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT = 0x00000082, 16876 PC_PERF_MW_RTN_ADDR_FREEZE = 0x00000083, 16877 PC_PERF_MW_PROBE_CNT_FREEZE = 0x00000084, 16878 PC_PERF_MW_GL1H_REQ_FREEZE = 0x00000085, 16879 PC_PERF_MW_GL1H_NUM_REQS = 0x00000086, 16880 PC_PERF_MW_DLINE_ALLOC = 0x00000087, 16881 PC_PERF_MW_DLINE_DEALLOC = 0x00000088, 16882 PC_PERF_MW_TAGLINE_ALLOC = 0x00000089, 16883 PC_PERF_MW_TAGLINE_DEALLOC = 0x0000008a, 16884 PC_PERF_MW_PHY_DLINE_FULL_STALL = 0x0000008b, 16885 PC_PERF_MW_CACHE_CNTL_FULL_STALL = 0x0000008c, 16886 PC_PERF_MW_STAMP_LIMIT_STALL = 0x0000008d, 16887 PC_PERF_MW_CACHE_MISS = 0x0000008e, 16888 PC_PERF_MW_CACHE_HIT = 0x0000008f, 16889 PC_PERF_MW_CACHE_REUSE = 0x00000090, 16890 PC_PERF_MW_DEALLOC_HIT = 0x00000091, 16891 PC_PERF_PC_MEM_BANK_CONF0 = 0x00000092, 16892 PC_PERF_PC_MEM_BANK_CONF1 = 0x00000093, 16893 PC_PERF_PC_LDS_VERTEX_REUSE0 = 0x00000094, 16894 PC_PERF_PC_LDS_CNTL_VALID0 = 0x00000095, 16895 PC_PERF_PC_LDS_VERTEX_REUSE1 = 0x00000096, 16896 PC_PERF_PC_LDS_CNTL_VALID1 = 0x00000097, 16897 PC_PERF_GRBM_BUSY = 0x00000098, 16898 PC_PERF_GL1_RTN_CNT_GTE1 = 0x00000099, 16899 PC_PERF_GL1_RTN_CNT_GT512 = 0x0000009a, 16900 PC_PERF_GL1_RTN_CNT_GT768 = 0x0000009b, 16901 PC_PERF_LWC0_PROBE_ORDER_STALL = 0x0000009c, 16902 PC_PERF_LWC0_PC_MEM_READ_STALL = 0x0000009d, 16903 PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING = 0x0000009e, 16904 PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING = 0x0000009f, 16905 PC_PERF_LWC1_PROBE_ORDER_STALL = 0x000000a0, 16906 PC_PERF_LWC1_PC_MEM_READ_STALL = 0x000000a1, 16907 PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING = 0x000000a2, 16908 PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING = 0x000000a3, 16909 PC_PERF_NUM_PSWAVE = 0x000000a4, 16910 } PC_PERFCNT_SEL; 16911 16912 /* 16913 * SPI_FOG_MODE enum 16914 */ 16915 16916 typedef enum SPI_FOG_MODE { 16917 SPI_FOG_NONE = 0x00000000, 16918 SPI_FOG_EXP = 0x00000001, 16919 SPI_FOG_EXP2 = 0x00000002, 16920 SPI_FOG_LINEAR = 0x00000003, 16921 } SPI_FOG_MODE; 16922 16923 /* 16924 * SPI_LB_WAVES_SELECT enum 16925 */ 16926 16927 typedef enum SPI_LB_WAVES_SELECT { 16928 HS_GS = 0x00000000, 16929 PS = 0x00000001, 16930 CS_NA = 0x00000002, 16931 SPI_LB_WAVES_RSVD = 0x00000003, 16932 } SPI_LB_WAVES_SELECT; 16933 16934 /* 16935 * SPI_PERFCNT_SEL enum 16936 */ 16937 16938 typedef enum SPI_PERFCNT_SEL { 16939 SPI_PERF_GS_WINDOW_VALID = 0x00000001, 16940 SPI_PERF_GS_BUSY = 0x00000002, 16941 SPI_PERF_GS_CRAWLER_STALL = 0x00000003, 16942 SPI_PERF_GS_EVENT_WAVE = 0x00000004, 16943 SPI_PERF_GS_WAVE = 0x00000005, 16944 SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000006, 16945 SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000007, 16946 SPI_PERF_GS_FIRST_SUBGRP = 0x00000008, 16947 SPI_PERF_GS_HS_DEALLOC = 0x00000009, 16948 SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000000a, 16949 SPI_PERF_GS_POS0_STALL = 0x0000000b, 16950 SPI_PERF_GS_POS1_STALL = 0x0000000c, 16951 SPI_PERF_GS_INDX0_STALL = 0x0000000d, 16952 SPI_PERF_GS_INDX1_STALL = 0x0000000e, 16953 SPI_PERF_GS_PWS_STALL = 0x0000000f, 16954 SPI_PERF_GS_GRP_LIFETIME = 0x00000010, 16955 SPI_PERF_GS_WAVE_IN_FLIGHT = 0x00000011, 16956 SPI_PERF_GS_GRP_LIFETIME_SAMPLE = 0x00000012, 16957 SPI_PERF_HS_WINDOW_VALID = 0x00000015, 16958 SPI_PERF_HS_BUSY = 0x00000016, 16959 SPI_PERF_HS_CRAWLER_STALL = 0x00000017, 16960 SPI_PERF_HS_FIRST_WAVE = 0x00000018, 16961 SPI_PERF_HS_EVENT_WAVE = 0x0000001a, 16962 SPI_PERF_HS_WAVE = 0x0000001b, 16963 SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000001c, 16964 SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000001d, 16965 SPI_PERF_HS_PWS_STALL = 0x0000001e, 16966 SPI_PERF_HS_WAVE_IN_FLIGHT = 0x0000001f, 16967 SPI_PERF_CSGN_WINDOW_VALID = 0x00000025, 16968 SPI_PERF_CSGN_BUSY = 0x00000026, 16969 SPI_PERF_CSGN_NUM_THREADGROUPS = 0x00000027, 16970 SPI_PERF_CSGN_CRAWLER_STALL = 0x00000028, 16971 SPI_PERF_CSGN_EVENT_WAVE = 0x00000029, 16972 SPI_PERF_CSGN_WAVE = 0x0000002a, 16973 SPI_PERF_CSGN_PWS_STALL = 0x0000002b, 16974 SPI_PERF_CSGN_WAVE_IN_FLIGHT = 0x0000002c, 16975 SPI_PERF_CSN_WINDOW_VALID = 0x0000002d, 16976 SPI_PERF_CSN_BUSY = 0x0000002e, 16977 SPI_PERF_CSN_NUM_THREADGROUPS = 0x0000002f, 16978 SPI_PERF_CSN_CRAWLER_STALL = 0x00000030, 16979 SPI_PERF_CSN_EVENT_WAVE = 0x00000031, 16980 SPI_PERF_CSN_WAVE = 0x00000032, 16981 SPI_PERF_CSN_WAVE_IN_FLIGHT = 0x00000033, 16982 SPI_PERF_PS0_WINDOW_VALID = 0x00000035, 16983 SPI_PERF_PS1_WINDOW_VALID = 0x00000036, 16984 SPI_PERF_PS2_WINDOW_VALID = 0x00000037, 16985 SPI_PERF_PS3_WINDOW_VALID = 0x00000038, 16986 SPI_PERF_PS0_BUSY = 0x00000039, 16987 SPI_PERF_PS1_BUSY = 0x0000003a, 16988 SPI_PERF_PS2_BUSY = 0x0000003b, 16989 SPI_PERF_PS3_BUSY = 0x0000003c, 16990 SPI_PERF_PS0_ACTIVE = 0x0000003d, 16991 SPI_PERF_PS1_ACTIVE = 0x0000003e, 16992 SPI_PERF_PS2_ACTIVE = 0x0000003f, 16993 SPI_PERF_PS3_ACTIVE = 0x00000040, 16994 SPI_PERF_PS0_DEALLOC = 0x00000041, 16995 SPI_PERF_PS1_DEALLOC = 0x00000042, 16996 SPI_PERF_PS2_DEALLOC = 0x00000043, 16997 SPI_PERF_PS3_DEALLOC = 0x00000044, 16998 SPI_PERF_PS0_EVENT_WAVE = 0x00000045, 16999 SPI_PERF_PS1_EVENT_WAVE = 0x00000046, 17000 SPI_PERF_PS2_EVENT_WAVE = 0x00000047, 17001 SPI_PERF_PS3_EVENT_WAVE = 0x00000048, 17002 SPI_PERF_PS0_WAVE = 0x00000049, 17003 SPI_PERF_PS1_WAVE = 0x0000004a, 17004 SPI_PERF_PS2_WAVE = 0x0000004b, 17005 SPI_PERF_PS3_WAVE = 0x0000004c, 17006 SPI_PERF_PS0_OPT_WAVE = 0x0000004d, 17007 SPI_PERF_PS1_OPT_WAVE = 0x0000004e, 17008 SPI_PERF_PS2_OPT_WAVE = 0x0000004f, 17009 SPI_PERF_PS3_OPT_WAVE = 0x00000050, 17010 SPI_PERF_PS0_PRIM_BIN0 = 0x00000051, 17011 SPI_PERF_PS1_PRIM_BIN0 = 0x00000052, 17012 SPI_PERF_PS2_PRIM_BIN0 = 0x00000053, 17013 SPI_PERF_PS3_PRIM_BIN0 = 0x00000054, 17014 SPI_PERF_PS0_PRIM_BIN1 = 0x00000055, 17015 SPI_PERF_PS1_PRIM_BIN1 = 0x00000056, 17016 SPI_PERF_PS2_PRIM_BIN1 = 0x00000057, 17017 SPI_PERF_PS3_PRIM_BIN1 = 0x00000058, 17018 SPI_PERF_PS0_CRAWLER_STALL = 0x00000059, 17019 SPI_PERF_PS1_CRAWLER_STALL = 0x0000005a, 17020 SPI_PERF_PS2_CRAWLER_STALL = 0x0000005b, 17021 SPI_PERF_PS3_CRAWLER_STALL = 0x0000005c, 17022 SPI_PERF_PS_PERS_UPD_FULL0 = 0x0000005d, 17023 SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000005e, 17024 SPI_PERF_PS0_2_WAVE_GROUPS = 0x0000005f, 17025 SPI_PERF_PS1_2_WAVE_GROUPS = 0x00000060, 17026 SPI_PERF_PS2_2_WAVE_GROUPS = 0x00000061, 17027 SPI_PERF_PS3_2_WAVE_GROUPS = 0x00000062, 17028 SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 0x00000063, 17029 SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 0x00000064, 17030 SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 0x00000065, 17031 SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 0x00000066, 17032 SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 0x00000067, 17033 SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 0x00000068, 17034 SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 0x00000069, 17035 SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 0x0000006a, 17036 SPI_PERF_PS_PWS_STALL = 0x0000006b, 17037 SPI_PERF_PS0_LDS_DONE_FULL = 0x0000006c, 17038 SPI_PERF_PS1_LDS_DONE_FULL = 0x0000006d, 17039 SPI_PERF_PS2_LDS_DONE_FULL = 0x0000006e, 17040 SPI_PERF_PS3_LDS_DONE_FULL = 0x0000006f, 17041 SPI_PERF_PS0_DEALLOC_FULL = 0x00000070, 17042 SPI_PERF_PS1_DEALLOC_FULL = 0x00000071, 17043 SPI_PERF_PS2_DEALLOC_FULL = 0x00000072, 17044 SPI_PERF_PS3_DEALLOC_FULL = 0x00000073, 17045 SPI_PERF_PS0_WAVE_IN_FLIGHT = 0x00000074, 17046 SPI_PERF_PS1_WAVE_IN_FLIGHT = 0x00000075, 17047 SPI_PERF_PS2_WAVE_IN_FLIGHT = 0x00000076, 17048 SPI_PERF_PS3_WAVE_IN_FLIGHT = 0x00000077, 17049 SPI_PERF_RA_GS_LDS_OCCUPANCY = 0x00000085, 17050 SPI_PERF_RA_GS_VGPR_OCCUPANCY = 0x00000086, 17051 SPI_PERF_RA_PS_LDS_OCCUPANCY = 0x00000087, 17052 SPI_PERF_RA_PS_VGPR_OCCUPANCY = 0x00000088, 17053 SPI_PERF_RA_SPI_THROTTLE = 0x00000089, 17054 SPI_PERF_RA_PH_THROTTLE = 0x0000008a, 17055 SPI_PERF_RA_PC_PROBE_STALL_PS = 0x0000008b, 17056 SPI_PERF_RA_PC_PSWAVE_STALL_PS = 0x0000008c, 17057 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000008d, 17058 SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000008e, 17059 SPI_PERF_RA_WR_CTL_FULL = 0x0000008f, 17060 SPI_PERF_RA_REQ_NO_ALLOC = 0x00000090, 17061 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000091, 17062 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000092, 17063 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000093, 17064 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000094, 17065 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000095, 17066 SPI_PERF_RA_RES_STALL_PS = 0x00000096, 17067 SPI_PERF_RA_RES_STALL_GS = 0x00000097, 17068 SPI_PERF_RA_RES_STALL_HS = 0x00000098, 17069 SPI_PERF_RA_RES_STALL_CSG = 0x00000099, 17070 SPI_PERF_RA_RES_STALL_CSN = 0x0000009a, 17071 SPI_PERF_RA_TMP_STALL_PS = 0x0000009b, 17072 SPI_PERF_RA_TMP_STALL_GS = 0x0000009c, 17073 SPI_PERF_RA_TMP_STALL_HS = 0x0000009d, 17074 SPI_PERF_RA_TMP_STALL_CSG = 0x0000009e, 17075 SPI_PERF_RA_TMP_STALL_CSN = 0x0000009f, 17076 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x000000a0, 17077 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x000000a1, 17078 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x000000a2, 17079 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x000000a3, 17080 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a4, 17081 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a5, 17082 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a6, 17083 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a7, 17084 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a8, 17085 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a9, 17086 SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000aa, 17087 SPI_PERF_RA_LDS_CU_FULL_HS = 0x000000ab, 17088 SPI_PERF_RA_LDS_CU_FULL_GS = 0x000000ac, 17089 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000ad, 17090 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000ae, 17091 SPI_PERF_RA_BAR_CU_FULL_PS = 0x000000af, 17092 SPI_PERF_RA_BAR_CU_FULL_GS = 0x000000b0, 17093 SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000b1, 17094 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b2, 17095 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b3, 17096 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b4, 17097 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b5, 17098 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b6, 17099 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b7, 17100 SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b8, 17101 SPI_PERF_RA_WVLIM_STALL_GS = 0x000000b9, 17102 SPI_PERF_RA_WVLIM_STALL_HS = 0x000000ba, 17103 SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000bb, 17104 SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000bc, 17105 SPI_PERF_RA_GS_LOCK = 0x000000bd, 17106 SPI_PERF_RA_HS_LOCK = 0x000000be, 17107 SPI_PERF_RA_CSG_LOCK = 0x000000bf, 17108 SPI_PERF_RA_CSN_LOCK = 0x000000c0, 17109 SPI_PERF_RA_RSV_UPD = 0x000000c1, 17110 SPI_PERF_RA_PRE_ALLOC_STALL = 0x000000c2, 17111 SPI_PERF_RA_GFX_UNDER_TUNNEL = 0x000000c3, 17112 SPI_PERF_RA_CSC_UNDER_TUNNEL = 0x000000c4, 17113 SPI_PERF_RA_WVALLOC_STALL = 0x000000c5, 17114 SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 0x000000c6, 17115 SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 0x000000c7, 17116 SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 0x000000c8, 17117 SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 0x000000c9, 17118 SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 0x000000ca, 17119 SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 0x000000cb, 17120 SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 0x000000cc, 17121 SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 0x000000cd, 17122 SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 0x000000ce, 17123 SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 0x000000cf, 17124 SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 0x000000d0, 17125 SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 0x000000d1, 17126 SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 0x000000d2, 17127 SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 0x000000d3, 17128 SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 0x000000d4, 17129 SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 0x000000d5, 17130 SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 0x000000d6, 17131 SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 0x000000d7, 17132 SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 0x000000d8, 17133 SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 0x000000d9, 17134 SPI_PERF_EXP_ARB_COL_CNT = 0x000000da, 17135 SPI_PERF_EXP_ARB_POS_CNT = 0x000000db, 17136 SPI_PERF_EXP_ARB_GDS_CNT = 0x000000dc, 17137 SPI_PERF_EXP_ARB_IDX_CNT = 0x000000dd, 17138 SPI_PERF_EXP_WITH_CONFLICT = 0x000000de, 17139 SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 0x000000df, 17140 SPI_PERF_GS_EXP_DONE = 0x000000e0, 17141 SPI_PERF_PS_EXP_DONE = 0x000000e1, 17142 SPI_PERF_PS_EXP_ARB_CONFLICT = 0x000000e2, 17143 SPI_PERF_GS_SCBD_IDX_CLEANUP = 0x000000e3, 17144 SPI_PERF_GS_SCBD_POS_CLEANUP = 0x000000e4, 17145 SPI_PERF_PS_EXP_ALLOC = 0x000000e5, 17146 SPI_PERF_PS0_WAVEID_STARVED = 0x000000e6, 17147 SPI_PERF_PS1_WAVEID_STARVED = 0x000000e7, 17148 SPI_PERF_PS2_WAVEID_STARVED = 0x000000e8, 17149 SPI_PERF_PS3_WAVEID_STARVED = 0x000000e9, 17150 SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 0x000000ea, 17151 SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 0x000000eb, 17152 SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 0x000000ec, 17153 SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 0x000000ed, 17154 SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 0x000000ee, 17155 SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 0x000000ef, 17156 SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 0x000000f0, 17157 SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 0x000000f1, 17158 SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 0x000000f2, 17159 SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 0x000000f3, 17160 SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 0x000000f4, 17161 SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 0x000000f5, 17162 SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 0x000000f6, 17163 SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 0x000000f7, 17164 SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 0x000000f8, 17165 SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 0x000000f9, 17166 SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000fa, 17167 SPI_PERF_GS_ALLOC_IDX = 0x000000fb, 17168 SPI_PERF_GS_ALLOC_POS = 0x000000fc, 17169 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000fd, 17170 SPI_PERF_EXPORT_SCB0_STALL = 0x000000fe, 17171 SPI_PERF_EXPORT_SCB1_STALL = 0x000000ff, 17172 SPI_PERF_EXPORT_SCB2_STALL = 0x00000100, 17173 SPI_PERF_EXPORT_SCB3_STALL = 0x00000101, 17174 SPI_PERF_EXPORT_DB0_STALL = 0x00000102, 17175 SPI_PERF_EXPORT_DB1_STALL = 0x00000103, 17176 SPI_PERF_EXPORT_DB2_STALL = 0x00000104, 17177 SPI_PERF_EXPORT_DB3_STALL = 0x00000105, 17178 SPI_PERF_EXPORT_DB4_STALL = 0x00000106, 17179 SPI_PERF_EXPORT_DB5_STALL = 0x00000107, 17180 SPI_PERF_EXPORT_DB6_STALL = 0x00000108, 17181 SPI_PERF_EXPORT_DB7_STALL = 0x00000109, 17182 SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x0000010a, 17183 SPI_PERF_GS_NGG_STALL_MSG_VAL = 0x0000010b, 17184 SPI_PERF_SWC_PS_WR = 0x0000010c, 17185 SPI_PERF_SWC_GS_WR = 0x0000010d, 17186 SPI_PERF_SWC_HS_WR = 0x0000010e, 17187 SPI_PERF_SWC_CSGN_WR = 0x0000010f, 17188 SPI_PERF_SWC_CSN_WR = 0x00000110, 17189 SPI_PERF_VWC_PS_WR = 0x00000111, 17190 SPI_PERF_VWC_ES_WR = 0x00000112, 17191 SPI_PERF_VWC_GS_WR = 0x00000113, 17192 SPI_PERF_VWC_LS_WR = 0x00000114, 17193 SPI_PERF_VWC_HS_WR = 0x00000115, 17194 SPI_PERF_VWC_CSGN_WR = 0x00000116, 17195 SPI_PERF_VWC_CSN_WR = 0x00000117, 17196 SPI_PERF_EXP_THROT_UPSTEP = 0x00000118, 17197 SPI_PERF_EXP_THROT_DOWNSTEP = 0x00000119, 17198 SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 0x0000011a, 17199 SPI_PERF_BUSY = 0x0000011b, 17200 SPI_PERF_ALL_PS_WAVE = 0x0000011c, 17201 SPI_PERF_ALL_PS_WAVE_IN_FLIGHT = 0x0000011d, 17202 SPI_PERF_ALL_WAVE = 0x0000011e, 17203 SPI_PERF_ALL_WAVE_IN_FLIGHT = 0x0000011f, 17204 SPI_PERF_RA_REQ_ALLOC = 0x00000120, 17205 SPI_PERF_VGPR_INIT = 0x00000121, 17206 SPI_PERF_SGPR_INIT = 0x00000122, 17207 SPI_PERF_VGPR_ALLOC_LEVEL = 0x00000123, 17208 SPI_PERF_LDS_ALLOC_LEVEL = 0x00000124, 17209 SPI_PERF_GFX_TEMP_ALLOC_LEVEL = 0x00000125, 17210 SPI_PERF_CSG_TEMP_ALLOC_LEVEL = 0x00000126, 17211 SPI_PERF_CSN_TEMP_ALLOC_LEVEL = 0x00000127, 17212 SPI_PERF_ALL_WAVE_RESTORED = 0x00000128, 17213 SPI_PERF_ALL_WAVE_SAVED = 0x00000129, 17214 SPI_PERF_ALL_WAVE_W32 = 0x0000012a, 17215 SPI_PERF_ALL_WAVE_W64 = 0x0000012b, 17216 SPI_PERF_ALL_WAVE_ITEMS = 0x0000012c, 17217 SPI_PERF_ALL_WAVE_ITEMS_W32 = 0x0000012d, 17218 SPI_PERF_ALL_WAVE_ITEMS_W64 = 0x0000012e, 17219 SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL = 0x0000012f, 17220 SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL = 0x00000130, 17221 SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL = 0x00000131, 17222 SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL = 0x00000132, 17223 } SPI_PERFCNT_SEL; 17224 17225 /* 17226 * SPI_PNT_SPRITE_OVERRIDE enum 17227 */ 17228 17229 typedef enum SPI_PNT_SPRITE_OVERRIDE { 17230 SPI_PNT_SPRITE_SEL_0 = 0x00000000, 17231 SPI_PNT_SPRITE_SEL_1 = 0x00000001, 17232 SPI_PNT_SPRITE_SEL_S = 0x00000002, 17233 SPI_PNT_SPRITE_SEL_T = 0x00000003, 17234 SPI_PNT_SPRITE_SEL_NONE = 0x00000004, 17235 } SPI_PNT_SPRITE_OVERRIDE; 17236 17237 /* 17238 * SPI_PS_LDS_GROUP_SIZE enum 17239 */ 17240 17241 typedef enum SPI_PS_LDS_GROUP_SIZE { 17242 SPI_PS_LDS_GROUP_1 = 0x00000000, 17243 SPI_PS_LDS_GROUP_2 = 0x00000001, 17244 SPI_PS_LDS_GROUP_4 = 0x00000002, 17245 } SPI_PS_LDS_GROUP_SIZE; 17246 17247 /* 17248 * SPI_SAMPLE_CNTL enum 17249 */ 17250 17251 typedef enum SPI_SAMPLE_CNTL { 17252 CENTROIDS_ONLY = 0x00000000, 17253 CENTERS_ONLY = 0x00000001, 17254 CENTROIDS_AND_CENTERS = 0x00000002, 17255 UNDEF = 0x00000003, 17256 } SPI_SAMPLE_CNTL; 17257 17258 /* 17259 * SPI_SHADER_EX_FORMAT enum 17260 */ 17261 17262 typedef enum SPI_SHADER_EX_FORMAT { 17263 SPI_SHADER_ZERO = 0x00000000, 17264 SPI_SHADER_32_R = 0x00000001, 17265 SPI_SHADER_32_GR = 0x00000002, 17266 SPI_SHADER_32_AR = 0x00000003, 17267 SPI_SHADER_FP16_ABGR = 0x00000004, 17268 SPI_SHADER_UNORM16_ABGR = 0x00000005, 17269 SPI_SHADER_SNORM16_ABGR = 0x00000006, 17270 SPI_SHADER_UINT16_ABGR = 0x00000007, 17271 SPI_SHADER_SINT16_ABGR = 0x00000008, 17272 SPI_SHADER_32_ABGR = 0x00000009, 17273 } SPI_SHADER_EX_FORMAT; 17274 17275 /* 17276 * SPI_SHADER_FORMAT enum 17277 */ 17278 17279 typedef enum SPI_SHADER_FORMAT { 17280 SPI_SHADER_NONE = 0x00000000, 17281 SPI_SHADER_1COMP = 0x00000001, 17282 SPI_SHADER_2COMP = 0x00000002, 17283 SPI_SHADER_4COMPRESS = 0x00000003, 17284 SPI_SHADER_4COMP = 0x00000004, 17285 } SPI_SHADER_FORMAT; 17286 17287 /******************************************************* 17288 * SQ Enums 17289 *******************************************************/ 17290 17291 /* 17292 * SH_MEM_ADDRESS_MODE enum 17293 */ 17294 17295 typedef enum SH_MEM_ADDRESS_MODE { 17296 SH_MEM_ADDRESS_MODE_64 = 0x00000000, 17297 SH_MEM_ADDRESS_MODE_32 = 0x00000001, 17298 } SH_MEM_ADDRESS_MODE; 17299 17300 /* 17301 * SH_MEM_ALIGNMENT_MODE enum 17302 */ 17303 17304 typedef enum SH_MEM_ALIGNMENT_MODE { 17305 SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, 17306 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, 17307 SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, 17308 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, 17309 } SH_MEM_ALIGNMENT_MODE; 17310 17311 /* 17312 * SQG_PERF_SEL enum 17313 */ 17314 17315 typedef enum SQG_PERF_SEL { 17316 SQG_PERF_SEL_NONE = 0x00000000, 17317 SQG_PERF_SEL_MSG_BUS_BUSY = 0x00000001, 17318 SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000002, 17319 SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000003, 17320 SQG_PERF_SEL_EXP_BUS0_BUSY = 0x00000004, 17321 SQG_PERF_SEL_EXP_BUS1_BUSY = 0x00000005, 17322 SQG_PERF_SEL_TTRACE_WRITE_DATA = 0x00000006, 17323 SQG_PERF_SEL_TTRACE_STALL = 0x00000007, 17324 SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000008, 17325 SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000009, 17326 SQG_PERF_SEL_EVENTS = 0x0000000a, 17327 SQG_PERF_SEL_WAVES_RESTORED = 0x0000000b, 17328 SQG_PERF_SEL_WAVES_SAVED = 0x0000000c, 17329 SQG_PERF_SEL_ACCUM_PREV = 0x0000000d, 17330 SQG_PERF_SEL_CYCLES = 0x0000000e, 17331 SQG_PERF_SEL_BUSY_CYCLES = 0x0000000f, 17332 SQG_PERF_SEL_WAVE_CYCLES = 0x00000010, 17333 SQG_PERF_SEL_MSG = 0x00000011, 17334 SQG_PERF_SEL_MSG_INTERRUPT = 0x00000012, 17335 SQG_PERF_SEL_WAVES = 0x00000013, 17336 SQG_PERF_SEL_WAVES_32 = 0x00000014, 17337 SQG_PERF_SEL_WAVES_64 = 0x00000015, 17338 SQG_PERF_SEL_LEVEL_WAVES = 0x00000016, 17339 SQG_PERF_SEL_ITEMS = 0x00000017, 17340 SQG_PERF_SEL_WAVE32_ITEMS = 0x00000018, 17341 SQG_PERF_SEL_WAVE64_ITEMS = 0x00000019, 17342 SQG_PERF_SEL_PS_QUADS = 0x0000001a, 17343 SQG_PERF_SEL_WAVES_EQ_64 = 0x0000001b, 17344 SQG_PERF_SEL_WAVES_EQ_32 = 0x0000001c, 17345 SQG_PERF_SEL_WAVES_LT_64 = 0x0000001d, 17346 SQG_PERF_SEL_WAVES_LT_48 = 0x0000001e, 17347 SQG_PERF_SEL_WAVES_LT_32 = 0x0000001f, 17348 SQG_PERF_SEL_WAVES_LT_16 = 0x00000020, 17349 SQG_PERF_SEL_REFCLKS = 0x00000021, 17350 SQG_PERF_SEL_WAVES_WGP_TAKEOVER = 0x00000022, 17351 SQG_PERF_SEL_WAVES_DYN_VGPR = 0x00000023, 17352 SQG_PERF_SEL_ITEMS_PS = 0x00000024, 17353 SQG_PERF_SEL_ITEMS_GS = 0x00000025, 17354 SQG_PERF_SEL_ITEMS_HS = 0x00000026, 17355 SQG_PERF_SEL_ITEMS_CS = 0x00000027, 17356 SQG_PERF_SEL_WAVES_VEC32 = 0x00000028, 17357 SQG_PERF_SEL_WAVES_PS_VEC32 = 0x00000029, 17358 SQG_PERF_SEL_WAVES_GS_VEC32 = 0x0000002a, 17359 SQG_PERF_SEL_WAVES_HS_VEC32 = 0x0000002b, 17360 SQG_PERF_SEL_WAVES_CS_VEC32 = 0x0000002c, 17361 SQG_PERF_SEL_LEVEL_WGP_ACTIVE = 0x0000002d, 17362 SQG_PERF_SEL_DUMMY_LAST = 0x0000002e, 17363 } SQG_PERF_SEL; 17364 17365 /* 17366 * SQ_CAC_POWER_SEL enum 17367 */ 17368 17369 typedef enum SQ_CAC_POWER_SEL { 17370 SQ_CAC_POWER_VALU = 0x00000000, 17371 SQ_CAC_POWER_VALU0 = 0x00000001, 17372 SQ_CAC_POWER_VALU1 = 0x00000002, 17373 SQ_CAC_POWER_VALU2 = 0x00000003, 17374 SQ_CAC_POWER_GPR_RD = 0x00000004, 17375 SQ_CAC_POWER_GPR_WR = 0x00000005, 17376 SQ_CAC_POWER_LDS_BUSY = 0x00000006, 17377 SQ_CAC_POWER_ALU_BUSY = 0x00000007, 17378 SQ_CAC_POWER_TEX_BUSY = 0x00000008, 17379 } SQ_CAC_POWER_SEL; 17380 17381 /* 17382 * SQ_EDC_INFO_SOURCE enum 17383 */ 17384 17385 typedef enum SQ_EDC_INFO_SOURCE { 17386 SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, 17387 SQ_EDC_INFO_SOURCE_INST = 0x00000001, 17388 SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, 17389 SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, 17390 SQ_EDC_INFO_SOURCE_LDS = 0x00000004, 17391 SQ_EDC_INFO_SOURCE_GDS = 0x00000005, 17392 SQ_EDC_INFO_SOURCE_TA = 0x00000006, 17393 } SQ_EDC_INFO_SOURCE; 17394 17395 /* 17396 * SQ_IBUF_ST enum 17397 */ 17398 17399 typedef enum SQ_IBUF_ST { 17400 SQ_IBUF_IB_IDLE = 0x00000000, 17401 SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, 17402 SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, 17403 SQ_IBUF_IB_LE_4DW = 0x00000003, 17404 SQ_IBUF_IB_WAIT_DRET = 0x00000004, 17405 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, 17406 SQ_IBUF_IB_DRET = 0x00000006, 17407 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, 17408 } SQ_IBUF_ST; 17409 17410 /* 17411 * SQ_IMG_FILTER_TYPE enum 17412 */ 17413 17414 typedef enum SQ_IMG_FILTER_TYPE { 17415 SQ_IMG_FILTER_MODE_BLEND = 0x00000000, 17416 SQ_IMG_FILTER_MODE_MIN = 0x00000001, 17417 SQ_IMG_FILTER_MODE_MAX = 0x00000002, 17418 } SQ_IMG_FILTER_TYPE; 17419 17420 /* 17421 * SQ_IND_CMD_CMD enum 17422 */ 17423 17424 typedef enum SQ_IND_CMD_CMD { 17425 SQ_IND_CMD_CMD_NULL = 0x00000000, 17426 SQ_IND_CMD_CMD_SETHALT = 0x00000001, 17427 SQ_IND_CMD_CMD_SAVECTX = 0x00000002, 17428 SQ_IND_CMD_CMD_KILL = 0x00000003, 17429 SQ_IND_CMD_CMD_TRAP_AFTER_INST = 0x00000004, 17430 SQ_IND_CMD_CMD_TRAP = 0x00000005, 17431 SQ_IND_CMD_CMD_SET_SYS_PRIO = 0x00000006, 17432 SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, 17433 SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008, 17434 } SQ_IND_CMD_CMD; 17435 17436 /* 17437 * SQ_IND_CMD_MODE enum 17438 */ 17439 17440 typedef enum SQ_IND_CMD_MODE { 17441 SQ_IND_CMD_MODE_SINGLE = 0x00000000, 17442 SQ_IND_CMD_MODE_BROADCAST = 0x00000001, 17443 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, 17444 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, 17445 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, 17446 } SQ_IND_CMD_MODE; 17447 17448 /* 17449 * SQ_INST_STR_ST enum 17450 */ 17451 17452 typedef enum SQ_INST_STR_ST { 17453 SQ_INST_STR_IB_WAVE_NORML = 0x00000000, 17454 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, 17455 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, 17456 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, 17457 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000004, 17458 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005, 17459 } SQ_INST_STR_ST; 17460 17461 /* 17462 * SQ_INST_TYPE enum 17463 */ 17464 17465 typedef enum SQ_INST_TYPE { 17466 SQ_INST_TYPE_VALU = 0x00000000, 17467 SQ_INST_TYPE_SCALAR = 0x00000001, 17468 SQ_INST_TYPE_TEX = 0x00000002, 17469 SQ_INST_TYPE_LDS = 0x00000003, 17470 SQ_INST_TYPE_LDS_DIRECT = 0x00000004, 17471 SQ_INST_TYPE_EXP = 0x00000005, 17472 SQ_INST_TYPE_MSG = 0x00000006, 17473 SQ_INST_TYPE_BARRIER = 0x00000007, 17474 SQ_INST_TYPE_BRANCH_NOT_TAKEN = 0x00000008, 17475 SQ_INST_TYPE_BRANCH_TAKEN = 0x00000009, 17476 SQ_INST_TYPE_JUMP = 0x0000000a, 17477 SQ_INST_TYPE_OTHER = 0x0000000b, 17478 SQ_INST_TYPE_NONE = 0x0000000c, 17479 SQ_INST_TYPE_DUAL_VALU = 0x0000000d, 17480 SQ_INST_TYPE_FLAT = 0x0000000e, 17481 SQ_INST_TYPE_VALU_MATRIX = 0x0000000f, 17482 } SQ_INST_TYPE; 17483 17484 /* 17485 * SQ_LLC_CTL enum 17486 */ 17487 17488 typedef enum SQ_LLC_CTL { 17489 SQ_LLC_0 = 0x00000000, 17490 SQ_LLC_1 = 0x00000001, 17491 SQ_LLC_RSVD_2 = 0x00000002, 17492 SQ_LLC_BYPASS = 0x00000003, 17493 } SQ_LLC_CTL; 17494 17495 /* 17496 * SQ_NO_INST_ISSUE enum 17497 */ 17498 17499 typedef enum SQ_NO_INST_ISSUE { 17500 SQ_NO_INST_ISSUE_NO_INSTS = 0x00000000, 17501 SQ_NO_INST_ISSUE_ALU_DEP = 0x00000001, 17502 SQ_NO_INST_ISSUE_S_WAITCNT = 0x00000002, 17503 SQ_NO_INST_ISSUE_NO_ARB_WIN = 0x00000003, 17504 SQ_NO_INST_ISSUE_SLEEP_WAIT = 0x00000004, 17505 SQ_NO_INST_ISSUE_BARRIER_WAIT = 0x00000005, 17506 SQ_NO_INST_ISSUE_OTHER = 0x00000006, 17507 SQ_NO_INST_ISSUE_INTERNAL = 0x00000007, 17508 } SQ_NO_INST_ISSUE; 17509 17510 /* 17511 * SQ_OOB_SELECT enum 17512 */ 17513 17514 typedef enum SQ_OOB_SELECT { 17515 SQ_OOB_INDEX_AND_OFFSET = 0x00000000, 17516 SQ_OOB_INDEX_ONLY = 0x00000001, 17517 SQ_OOB_NUM_RECORDS_0 = 0x00000002, 17518 SQ_OOB_COMPLETE = 0x00000003, 17519 } SQ_OOB_SELECT; 17520 17521 /* 17522 * SQ_PERF_SEL enum 17523 */ 17524 17525 typedef enum SQ_PERF_SEL { 17526 SQ_PERF_SEL_NONE = 0x00000000, 17527 SQ_PERF_SEL_ACCUM_PREV = 0x00000001, 17528 SQ_PERF_SEL_CYCLES = 0x00000002, 17529 SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, 17530 SQ_PERF_SEL_WAVES = 0x00000004, 17531 SQ_PERF_SEL_WAVES_32 = 0x00000005, 17532 SQ_PERF_SEL_WAVES_64 = 0x00000006, 17533 SQ_PERF_SEL_LEVEL_WAVES = 0x00000007, 17534 SQ_PERF_SEL_ITEMS = 0x00000008, 17535 SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009, 17536 SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a, 17537 SQ_PERF_SEL_PS_QUADS = 0x0000000b, 17538 SQ_PERF_SEL_EVENTS = 0x0000000c, 17539 SQ_PERF_SEL_WAVES_EQ_32 = 0x0000000d, 17540 SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000e, 17541 SQ_PERF_SEL_WAVES_LT_64 = 0x0000000f, 17542 SQ_PERF_SEL_WAVES_LT_48 = 0x00000010, 17543 SQ_PERF_SEL_WAVES_LT_32 = 0x00000011, 17544 SQ_PERF_SEL_WAVES_LT_16 = 0x00000012, 17545 SQ_PERF_SEL_WAVES_RESTORED = 0x00000013, 17546 SQ_PERF_SEL_WAVES_SAVED = 0x00000014, 17547 SQ_PERF_SEL_MSG = 0x00000015, 17548 SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016, 17549 SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000017, 17550 SQ_PERF_SEL_WAVE_CYCLES = 0x00000018, 17551 SQ_PERF_SEL_WAVE_READY = 0x00000019, 17552 SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001a, 17553 SQ_PERF_SEL_WAIT_ANY = 0x0000001b, 17554 SQ_PERF_SEL_WAIT_CNT_ANY = 0x0000001c, 17555 SQ_PERF_SEL_WAIT_CNT_LOAD = 0x0000001d, 17556 SQ_PERF_SEL_WAIT_CNT_STORE = 0x0000001e, 17557 SQ_PERF_SEL_WAIT_TTRACE = 0x0000001f, 17558 SQ_PERF_SEL_WAIT_IFETCH = 0x00000020, 17559 SQ_PERF_SEL_WAIT_BARRIER = 0x00000021, 17560 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000022, 17561 SQ_PERF_SEL_WAIT_SLEEP = 0x00000023, 17562 SQ_PERF_SEL_WAIT_DELAY_ALU = 0x00000024, 17563 SQ_PERF_SEL_WAIT_DEPCTR = 0x00000025, 17564 SQ_PERF_SEL_WAIT_OTHER = 0x00000026, 17565 SQ_PERF_SEL_INSTS_ALL = 0x00000027, 17566 SQ_PERF_SEL_INSTS_BRANCH = 0x00000028, 17567 SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000029, 17568 SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x0000002a, 17569 SQ_PERF_SEL_INSTS_EXP = 0x0000002b, 17570 SQ_PERF_SEL_INSTS_FLAT = 0x0000002c, 17571 SQ_PERF_SEL_INSTS_LDS = 0x0000002d, 17572 SQ_PERF_SEL_INSTS_SALU = 0x0000002e, 17573 SQ_PERF_SEL_INSTS_SMEM = 0x0000002f, 17574 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x00000030, 17575 SQ_PERF_SEL_INSTS_SENDMSG = 0x00000031, 17576 SQ_PERF_SEL_INSTS_VALU = 0x00000032, 17577 SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x00000033, 17578 SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000034, 17579 SQ_PERF_SEL_INSTS_TEX = 0x00000035, 17580 SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000036, 17581 SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000037, 17582 SQ_PERF_SEL_INSTS_DELAY_ALU = 0x00000038, 17583 SQ_PERF_SEL_INSTS_INTERNAL = 0x00000039, 17584 SQ_PERF_SEL_INSTS_VEC32 = 0x0000003a, 17585 SQ_PERF_SEL_INSTS_VEC32_FLAT = 0x0000003b, 17586 SQ_PERF_SEL_INSTS_VEC32_LDS = 0x0000003c, 17587 SQ_PERF_SEL_INSTS_VEC32_VALU = 0x0000003d, 17588 SQ_PERF_SEL_VEC32_INSTS_EXP = 0x0000003e, 17589 SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32 = 0x0000003f, 17590 SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC = 0x00000040, 17591 SQ_PERF_SEL_INSTS_VEC32_TEX = 0x00000041, 17592 SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD = 0x00000042, 17593 SQ_PERF_SEL_INSTS_VEC32_TEX_STORE = 0x00000043, 17594 SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000044, 17595 SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000045, 17596 SQ_PERF_SEL_WAVE32_INSTS = 0x00000046, 17597 SQ_PERF_SEL_WAVE64_INSTS = 0x00000047, 17598 SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000048, 17599 SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000049, 17600 SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000004a, 17601 SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000004b, 17602 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000004c, 17603 SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x0000004d, 17604 SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x0000004e, 17605 SQ_PERF_SEL_IFETCH_REQS = 0x0000004f, 17606 SQ_PERF_SEL_IFETCH_LEVEL = 0x00000050, 17607 SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x00000051, 17608 SQ_PERF_SEL_VALU_SGATHER_STALL = 0x00000052, 17609 SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x00000053, 17610 SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000054, 17611 SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000055, 17612 SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000056, 17613 SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000057, 17614 SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000058, 17615 SQ_PERF_SEL_INST_ISSUE_SMEM_STALL = 0x00000059, 17616 SQ_PERF_SEL_INST_ISSUE_ALL_STALL = 0x0000005a, 17617 SQ_PERF_SEL_INST_ISSUE_VALU_STALL = 0x0000005b, 17618 SQ_PERF_SEL_INST_ISSUE_SALU_STALL = 0x0000005c, 17619 SQ_PERF_SEL_INST_ISSUE_TEX_STALL = 0x0000005d, 17620 SQ_PERF_SEL_INST_ISSUE_LDS_STALL = 0x0000005e, 17621 SQ_PERF_SEL_INST_ISSUE_EXP_STALL = 0x00000060, 17622 SQ_PERF_SEL_INST_WAITCNT_STALL = 0x00000061, 17623 SQ_PERF_SEL_INST_BARRIER_STALL = 0x00000062, 17624 SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000063, 17625 SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000064, 17626 SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000065, 17627 SQ_PERF_SEL_INST_CYCLES_VMEM = 0x00000066, 17628 SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x00000067, 17629 SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x00000068, 17630 SQ_PERF_SEL_INST_CYCLES_LDS = 0x00000069, 17631 SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000006a, 17632 SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000006b, 17633 SQ_PERF_SEL_INST_CYCLES_EXP = 0x0000006c, 17634 SQ_PERF_SEL_VALU_STARVE = 0x0000006d, 17635 SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x0000006e, 17636 SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x0000006f, 17637 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000070, 17638 SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000071, 17639 SQ_PERF_SEL_VMEM_BUS_STALL = 0x00000072, 17640 SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000073, 17641 SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x00000074, 17642 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x00000075, 17643 SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x00000076, 17644 SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x00000077, 17645 SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x00000078, 17646 SQ_PERF_SEL_SALU_PIPE_STALL = 0x00000079, 17647 SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x0000007a, 17648 SQ_PERF_SEL_MSG_BUS_BUSY = 0x0000007b, 17649 SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x0000007c, 17650 SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x0000007d, 17651 SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x0000007e, 17652 SQ_PERF_SEL_EXP_BUS0_BUSY = 0x0000007f, 17653 SQ_PERF_SEL_EXP_BUS1_BUSY = 0x00000080, 17654 SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x00000081, 17655 SQ_PERF_SEL_USER0 = 0x00000082, 17656 SQ_PERF_SEL_USER1 = 0x00000083, 17657 SQ_PERF_SEL_USER2 = 0x00000084, 17658 SQ_PERF_SEL_USER3 = 0x00000085, 17659 SQ_PERF_SEL_USER4 = 0x00000086, 17660 SQ_PERF_SEL_USER5 = 0x00000087, 17661 SQ_PERF_SEL_USER6 = 0x00000088, 17662 SQ_PERF_SEL_USER7 = 0x00000089, 17663 SQ_PERF_SEL_USER8 = 0x0000008a, 17664 SQ_PERF_SEL_USER9 = 0x0000008b, 17665 SQ_PERF_SEL_USER10 = 0x0000008c, 17666 SQ_PERF_SEL_USER11 = 0x0000008d, 17667 SQ_PERF_SEL_USER12 = 0x0000008e, 17668 SQ_PERF_SEL_USER13 = 0x0000008f, 17669 SQ_PERF_SEL_USER14 = 0x00000090, 17670 SQ_PERF_SEL_USER15 = 0x00000091, 17671 SQ_PERF_SEL_USER_LEVEL0 = 0x00000092, 17672 SQ_PERF_SEL_USER_LEVEL1 = 0x00000093, 17673 SQ_PERF_SEL_USER_LEVEL2 = 0x00000094, 17674 SQ_PERF_SEL_USER_LEVEL3 = 0x00000095, 17675 SQ_PERF_SEL_USER_LEVEL4 = 0x00000096, 17676 SQ_PERF_SEL_USER_LEVEL5 = 0x00000097, 17677 SQ_PERF_SEL_USER_LEVEL6 = 0x00000098, 17678 SQ_PERF_SEL_USER_LEVEL7 = 0x00000099, 17679 SQ_PERF_SEL_USER_LEVEL8 = 0x0000009a, 17680 SQ_PERF_SEL_USER_LEVEL9 = 0x0000009b, 17681 SQ_PERF_SEL_USER_LEVEL10 = 0x0000009c, 17682 SQ_PERF_SEL_USER_LEVEL11 = 0x0000009d, 17683 SQ_PERF_SEL_USER_LEVEL12 = 0x0000009e, 17684 SQ_PERF_SEL_USER_LEVEL13 = 0x0000009f, 17685 SQ_PERF_SEL_USER_LEVEL14 = 0x000000a0, 17686 SQ_PERF_SEL_USER_LEVEL15 = 0x000000a1, 17687 SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000a2, 17688 SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a3, 17689 SQ_PERF_SEL_INSTS_VALU_TRANS = 0x000000a4, 17690 SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 0x000000a5, 17691 SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 0x000000a6, 17692 SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD = 0x000000a7, 17693 SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 0x000000a8, 17694 SQ_PERF_SEL_INSTS_VALU_VINTERP = 0x000000a9, 17695 SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP = 0x000000aa, 17696 SQ_PERF_SEL_OVERFLOW_PREV = 0x000000ab, 17697 SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 0x000000ac, 17698 SQ_PERF_SEL_INSTS_VALU_1_PASS = 0x000000ad, 17699 SQ_PERF_SEL_INSTS_VALU_2_PASS = 0x000000ae, 17700 SQ_PERF_SEL_INSTS_VALU_4_PASS = 0x000000af, 17701 SQ_PERF_SEL_INSTS_VALU_DP = 0x000000b0, 17702 SQ_PERF_SEL_SP_CONST_CYCLES = 0x000000b1, 17703 SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 0x000000b2, 17704 SQ_PERF_SEL_ITEMS_VALU = 0x000000b3, 17705 SQ_PERF_SEL_ITEMS_MAX_VALU = 0x000000b4, 17706 SQ_PERF_SEL_ITEM_CYCLES_VMEM = 0x000000b5, 17707 SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE = 0x000000b6, 17708 SQ_PERF_SEL_INSTS_FLAT_LOAD = 0x000000b7, 17709 SQ_PERF_SEL_INSTS_FLAT_STORE = 0x000000b8, 17710 SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT = 0x000000b9, 17711 SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT = 0x000000ba, 17712 SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED = 0x000000bb, 17713 SQ_PERF_SEL_INSTS_BARRIER_LOCK = 0x000000bc, 17714 SQ_PERF_SEL_INSTS_WAKEUP = 0x000000bd, 17715 SQ_PERF_SEL_IS_CACHE_REQ = 0x000000be, 17716 SQ_PERF_SEL_INSTS_SALU_PS = 0x000000bf, 17717 SQ_PERF_SEL_INSTS_SALU_GS = 0x000000c0, 17718 SQ_PERF_SEL_INSTS_SALU_HS = 0x000000c1, 17719 SQ_PERF_SEL_INSTS_SALU_CS = 0x000000c2, 17720 SQ_PERF_SEL_INSTS_SMEM_PS = 0x000000c3, 17721 SQ_PERF_SEL_INSTS_SMEM_GS = 0x000000c4, 17722 SQ_PERF_SEL_INSTS_SMEM_HS = 0x000000c5, 17723 SQ_PERF_SEL_INSTS_SMEM_CS = 0x000000c6, 17724 SQ_PERF_SEL_INSTS_VEC32_TEX_PS = 0x000000c7, 17725 SQ_PERF_SEL_INSTS_VEC32_TEX_GS = 0x000000c8, 17726 SQ_PERF_SEL_INSTS_VEC32_TEX_HS = 0x000000c9, 17727 SQ_PERF_SEL_INSTS_VEC32_TEX_CS = 0x000000ca, 17728 SQ_PERF_SEL_INSTS_VEC32_VALU_PS = 0x000000cb, 17729 SQ_PERF_SEL_INSTS_VEC32_VALU_GS = 0x000000cc, 17730 SQ_PERF_SEL_INSTS_VEC32_VALU_HS = 0x000000cd, 17731 SQ_PERF_SEL_INSTS_VEC32_VALU_CS = 0x000000ce, 17732 SQ_PERF_SEL_WAIT_CNT_SAMPLE = 0x000000cf, 17733 SQ_PERF_SEL_WAIT_CNT_KM = 0x000000d1, 17734 SQ_PERF_SEL_WAIT_CNT_DS = 0x000000d2, 17735 SQ_PERF_SEL_WAIT_CNT_EXP = 0x000000d3, 17736 SQ_PERF_SEL_INSTS_SALU_FLOAT = 0x000000d4, 17737 SQ_PERF_SEL_INSTS_VGPR_ALLOC = 0x000000d5, 17738 SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL = 0x000000d6, 17739 SQ_PERF_SEL_INSTS_LOCK = 0x000000d7, 17740 SQ_PERF_SEL_INSTS_VALU_COISSUE = 0x000000d8, 17741 SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD = 0x000000d9, 17742 SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE = 0x000000da, 17743 SQ_PERF_SEL_IS_CACHE_MISS = 0x000000db, 17744 SQ_PERF_SEL_IS_CACHE_DUP_MISS = 0x000000dc, 17745 SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC = 0x000000dd, 17746 SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD = 0x000000de, 17747 SQ_PERF_SEL_INSTS_TEX_SAMPLE = 0x000000e0, 17748 SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN = 0x000000e1, 17749 SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE = 0x000000e2, 17750 SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN = 0x000000e3, 17751 SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH = 0x000000e4, 17752 SQ_PERF_SEL_INSTS_WMMA_LOAD = 0x000000e5, 17753 SQ_PERF_SEL_INSTS_FLAT_ATOMIC = 0x000000e6, 17754 SQ_PERF_SEL_INSTS_EXP_MRT = 0x000000e7, 17755 SQ_PERF_SEL_INSTS_EXP_Z = 0x000000e8, 17756 SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA = 0x000000e9, 17757 SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD = 0x000000ea, 17758 SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN = 0x000000eb, 17759 SQ_PERF_SEL_INSTS_VEC32_LDS_STORE = 0x000000ec, 17760 SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN = 0x000000ed, 17761 SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER = 0x000000ef, 17762 SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE = 0x000000f1, 17763 SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC = 0x000000f2, 17764 SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD = 0x000000f3, 17765 SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE = 0x000000f4, 17766 SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC = 0x000000f5, 17767 SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH = 0x000000f6, 17768 SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD = 0x000000f7, 17769 SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE = 0x000000f8, 17770 SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC = 0x000000f9, 17771 SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS = 0x000000fa, 17772 SQ_PERF_SEL_DUMMY_END = 0x000000fb, 17773 SQ_PERF_SEL_DUMMY_LAST = 0x0000011f, 17774 SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x00000120, 17775 SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x00000121, 17776 SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x00000122, 17777 SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000123, 17778 SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000124, 17779 SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000125, 17780 SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000126, 17781 SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000127, 17782 SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000128, 17783 SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000129, 17784 SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000012a, 17785 SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000012b, 17786 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000012c, 17787 SQC_PERF_SEL_ICACHE_REQ = 0x0000012d, 17788 SQC_PERF_SEL_ICACHE_HITS = 0x0000012e, 17789 SQC_PERF_SEL_ICACHE_MISSES = 0x0000012f, 17790 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000130, 17791 SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000131, 17792 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000132, 17793 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000133, 17794 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000134, 17795 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000135, 17796 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000136, 17797 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000137, 17798 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000138, 17799 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000139, 17800 SQC_PERF_SEL_TC_REQ = 0x0000013a, 17801 SQC_PERF_SEL_TC_INST_REQ = 0x0000013b, 17802 SQC_PERF_SEL_TC_DATA_READ_REQ = 0x0000013c, 17803 SQC_PERF_SEL_TC_STALL = 0x0000013d, 17804 SQC_PERF_SEL_TC_STARVE = 0x0000013e, 17805 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000013f, 17806 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000140, 17807 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000141, 17808 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000142, 17809 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000143, 17810 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000144, 17811 SQC_PERF_SEL_DCACHE_REQ = 0x00000145, 17812 SQC_PERF_SEL_DCACHE_HITS = 0x00000146, 17813 SQC_PERF_SEL_DCACHE_MISSES = 0x00000147, 17814 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000148, 17815 SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000149, 17816 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000014a, 17817 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x0000014b, 17818 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000014c, 17819 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000014d, 17820 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000014e, 17821 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000014f, 17822 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000150, 17823 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000151, 17824 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000152, 17825 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000153, 17826 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000154, 17827 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000155, 17828 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000156, 17829 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000157, 17830 SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000158, 17831 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000159, 17832 SQC_PERF_SEL_TD_VGPR_BUSY = 0x0000015a, 17833 SQC_PERF_SEL_LDS_VGPR_BUSY = 0x0000015b, 17834 SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 0x0000015c, 17835 SQC_PERF_SEL_ICACHE_GCR = 0x0000015d, 17836 SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000015e, 17837 SQC_PERF_SEL_DCACHE_GCR = 0x0000015f, 17838 SQC_PERF_SEL_DCACHE_GCR_HITS = 0x00000160, 17839 SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x00000161, 17840 SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x00000162, 17841 SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 0x00000163, 17842 SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES = 0x00000164, 17843 SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES = 0x00000165, 17844 SQC_PERF_SEL_ICACHE_PREFETCH_MISSES = 0x00000166, 17845 SQC_PERF_SEL_DCACHE_PREFETCH_MISSES = 0x00000167, 17846 SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT = 0x00000168, 17847 SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT = 0x00000169, 17848 SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT = 0x0000016a, 17849 SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT = 0x0000016b, 17850 SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT = 0x0000016c, 17851 SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT = 0x0000016d, 17852 SQC_PERF_SEL_LDS_STORE_DWORDS = 0x0000016e, 17853 SQC_PERF_SEL_LDS_LOAD_DWORDS = 0x0000016f, 17854 SQC_PERF_SEL_LDS_ATOMIC_DWORDS = 0x00000170, 17855 SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL = 0x00000171, 17856 SQC_PERF_SEL_DUMMY_LAST = 0x00000172, 17857 SP_PERF_SEL_DST_BUF_ALLOC_STALL = 0x000001c0, 17858 SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 0x000001c1, 17859 SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 0x000001c2, 17860 SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 0x000001c3, 17861 SP_PERF_SEL_DST_BUF_ODD_DIRTY = 0x000001c4, 17862 SP_PERF_SEL_SRC_CACHE_HIT_B0 = 0x000001c5, 17863 SP_PERF_SEL_SRC_CACHE_HIT_B1 = 0x000001c6, 17864 SP_PERF_SEL_SRC_CACHE_HIT_B2 = 0x000001c7, 17865 SP_PERF_SEL_SRC_CACHE_HIT_B3 = 0x000001c8, 17866 SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 0x000001c9, 17867 SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 0x000001ca, 17868 SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 0x000001cb, 17869 SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 0x000001cc, 17870 SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 0x000001cd, 17871 SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 0x000001ce, 17872 SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 0x000001cf, 17873 SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 0x000001d0, 17874 SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 0x000001d1, 17875 SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 0x000001d2, 17876 SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 0x000001d3, 17877 SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 0x000001d4, 17878 SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 0x000001d5, 17879 SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 0x000001d6, 17880 SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 0x000001d7, 17881 SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 0x000001d8, 17882 SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 0x000001d9, 17883 SP_PERF_SEL_VALU_OPERAND = 0x000001da, 17884 SP_PERF_SEL_VALU_VGPR_OPERAND = 0x000001db, 17885 SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 0x000001dc, 17886 SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 0x000001dd, 17887 SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 0x000001de, 17888 SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 0x000001df, 17889 SP_PERF_SEL_VALU_STALL = 0x000001e0, 17890 SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 0x000001e1, 17891 SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 0x000001e2, 17892 SP_PERF_SEL_VALU_STALL_VDST_FWD = 0x000001e3, 17893 SP_PERF_SEL_VALU_STALL_SDST_FWD = 0x000001e4, 17894 SP_PERF_SEL_VALU_STALL_DST_STALL = 0x000001e5, 17895 SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6, 17896 SP_PERF_SEL_VGPR_VMEM_RD = 0x000001e7, 17897 SP_PERF_SEL_VGPR_EXP_RD = 0x000001e8, 17898 SP_PERF_SEL_VGPR_SPI_WR = 0x000001e9, 17899 SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 0x000001ea, 17900 SP_PERF_SEL_VGPR_WR = 0x000001eb, 17901 SP_PERF_SEL_VGPR_RD = 0x000001ec, 17902 SP_PERF_SEL_VGPR_WR_KILL = 0x000001ed, 17903 SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP = 0x000001ee, 17904 SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS = 0x000001ef, 17905 SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX = 0x000001f0, 17906 SP_PERF_SEL_DUMMY_LAST = 0x000001f1, 17907 SQ_PERF_SEL_NONE2 = 0x000001ff, 17908 } SQ_PERF_SEL; 17909 17910 /* 17911 * SQ_ROUND_MODE enum 17912 */ 17913 17914 typedef enum SQ_ROUND_MODE { 17915 SQ_ROUND_NEAREST_EVEN = 0x00000000, 17916 SQ_ROUND_PLUS_INFINITY = 0x00000001, 17917 SQ_ROUND_MINUS_INFINITY = 0x00000002, 17918 SQ_ROUND_TO_ZERO = 0x00000003, 17919 } SQ_ROUND_MODE; 17920 17921 /* 17922 * SQ_RSRC_BUF_TYPE enum 17923 */ 17924 17925 typedef enum SQ_RSRC_BUF_TYPE { 17926 SQ_RSRC_BUF = 0x00000000, 17927 SQ_RSRC_BUF_RSVD_1 = 0x00000001, 17928 SQ_RSRC_BUF_RSVD_2 = 0x00000002, 17929 SQ_RSRC_BUF_RSVD_3 = 0x00000003, 17930 } SQ_RSRC_BUF_TYPE; 17931 17932 /* 17933 * SQ_RSRC_FLAT_TYPE enum 17934 */ 17935 17936 typedef enum SQ_RSRC_FLAT_TYPE { 17937 SQ_RSRC_FLAT_RSVD_0 = 0x00000000, 17938 SQ_RSRC_FLAT = 0x00000001, 17939 SQ_RSRC_FLAT_RSVD_2 = 0x00000002, 17940 SQ_RSRC_FLAT_RSVD_3 = 0x00000003, 17941 } SQ_RSRC_FLAT_TYPE; 17942 17943 /* 17944 * SQ_RSRC_IMG_TYPE enum 17945 */ 17946 17947 typedef enum SQ_RSRC_IMG_TYPE { 17948 SQ_RSRC_IMG_RSVD_0 = 0x00000000, 17949 SQ_RSRC_IMG_RSVD_1 = 0x00000001, 17950 SQ_RSRC_IMG_RSVD_2 = 0x00000002, 17951 SQ_RSRC_IMG_RSVD_3 = 0x00000003, 17952 SQ_RSRC_IMG_RSVD_4 = 0x00000004, 17953 SQ_RSRC_IMG_RSVD_5 = 0x00000005, 17954 SQ_RSRC_IMG_RSVD_6 = 0x00000006, 17955 SQ_RSRC_IMG_RSVD_7 = 0x00000007, 17956 SQ_RSRC_IMG_1D = 0x00000008, 17957 SQ_RSRC_IMG_2D = 0x00000009, 17958 SQ_RSRC_IMG_3D = 0x0000000a, 17959 SQ_RSRC_IMG_CUBE = 0x0000000b, 17960 SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, 17961 SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, 17962 SQ_RSRC_IMG_2D_MSAA = 0x0000000e, 17963 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, 17964 } SQ_RSRC_IMG_TYPE; 17965 17966 /* 17967 * SQ_SEL_XYZW01 enum 17968 */ 17969 17970 typedef enum SQ_SEL_XYZW01 { 17971 SQ_SEL_0 = 0x00000000, 17972 SQ_SEL_1 = 0x00000001, 17973 SQ_SEL_N_BC_1 = 0x00000002, 17974 SQ_SEL_RESERVED_1 = 0x00000003, 17975 SQ_SEL_X = 0x00000004, 17976 SQ_SEL_Y = 0x00000005, 17977 SQ_SEL_Z = 0x00000006, 17978 SQ_SEL_W = 0x00000007, 17979 } SQ_SEL_XYZW01; 17980 17981 /* 17982 * SQ_TEX_ANISO_RATIO enum 17983 */ 17984 17985 typedef enum SQ_TEX_ANISO_RATIO { 17986 SQ_TEX_ANISO_RATIO_1 = 0x00000000, 17987 SQ_TEX_ANISO_RATIO_2 = 0x00000001, 17988 SQ_TEX_ANISO_RATIO_4 = 0x00000002, 17989 SQ_TEX_ANISO_RATIO_8 = 0x00000003, 17990 SQ_TEX_ANISO_RATIO_16 = 0x00000004, 17991 } SQ_TEX_ANISO_RATIO; 17992 17993 /* 17994 * SQ_TEX_BORDER_COLOR enum 17995 */ 17996 17997 typedef enum SQ_TEX_BORDER_COLOR { 17998 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, 17999 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, 18000 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, 18001 SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, 18002 } SQ_TEX_BORDER_COLOR; 18003 18004 /* 18005 * SQ_TEX_CLAMP enum 18006 */ 18007 18008 typedef enum SQ_TEX_CLAMP { 18009 SQ_TEX_WRAP = 0x00000000, 18010 SQ_TEX_MIRROR = 0x00000001, 18011 SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, 18012 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, 18013 SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, 18014 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, 18015 SQ_TEX_CLAMP_BORDER = 0x00000006, 18016 SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, 18017 } SQ_TEX_CLAMP; 18018 18019 /* 18020 * SQ_TEX_DEPTH_COMPARE enum 18021 */ 18022 18023 typedef enum SQ_TEX_DEPTH_COMPARE { 18024 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, 18025 SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, 18026 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, 18027 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, 18028 SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, 18029 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, 18030 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, 18031 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, 18032 } SQ_TEX_DEPTH_COMPARE; 18033 18034 /* 18035 * SQ_TEX_MIP_FILTER enum 18036 */ 18037 18038 typedef enum SQ_TEX_MIP_FILTER { 18039 SQ_TEX_MIP_FILTER_NONE = 0x00000000, 18040 SQ_TEX_MIP_FILTER_POINT = 0x00000001, 18041 SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, 18042 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, 18043 } SQ_TEX_MIP_FILTER; 18044 18045 /* 18046 * SQ_TEX_XY_FILTER enum 18047 */ 18048 18049 typedef enum SQ_TEX_XY_FILTER { 18050 SQ_TEX_XY_FILTER_POINT = 0x00000000, 18051 SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, 18052 SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, 18053 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, 18054 } SQ_TEX_XY_FILTER; 18055 18056 /* 18057 * SQ_TEX_Z_FILTER enum 18058 */ 18059 18060 typedef enum SQ_TEX_Z_FILTER { 18061 SQ_TEX_Z_FILTER_NONE = 0x00000000, 18062 SQ_TEX_Z_FILTER_POINT = 0x00000001, 18063 SQ_TEX_Z_FILTER_LINEAR = 0x00000002, 18064 } SQ_TEX_Z_FILTER; 18065 18066 /* 18067 * SQ_WATCH_MODES enum 18068 */ 18069 18070 typedef enum SQ_WATCH_MODES { 18071 SQ_WATCH_MODE_READ = 0x00000000, 18072 SQ_WATCH_MODE_NONREAD = 0x00000001, 18073 SQ_WATCH_MODE_ATOMIC = 0x00000002, 18074 SQ_WATCH_MODE_ALL = 0x00000003, 18075 } SQ_WATCH_MODES; 18076 18077 /* 18078 * SQ_WAVE_FWD_PROG_INTERVAL enum 18079 */ 18080 18081 typedef enum SQ_WAVE_FWD_PROG_INTERVAL { 18082 SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0x00000000, 18083 SQ_WAVE_FWD_PROG_INTERVAL_256 = 0x00000001, 18084 SQ_WAVE_FWD_PROG_INTERVAL_1024 = 0x00000002, 18085 SQ_WAVE_FWD_PROG_INTERVAL_4096 = 0x00000003, 18086 } SQ_WAVE_FWD_PROG_INTERVAL; 18087 18088 /* 18089 * SQ_WAVE_SCHED_MODES enum 18090 */ 18091 18092 typedef enum SQ_WAVE_SCHED_MODES { 18093 SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000, 18094 SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001, 18095 SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC = 0x00000002, 18096 } SQ_WAVE_SCHED_MODES; 18097 18098 /* 18099 * SQ_WAVE_TYPE enum 18100 */ 18101 18102 typedef enum SQ_WAVE_TYPE { 18103 SQ_WAVE_TYPE_PS = 0x00000000, 18104 SQ_WAVE_TYPE_RSVD0 = 0x00000001, 18105 SQ_WAVE_TYPE_GS = 0x00000002, 18106 SQ_WAVE_TYPE_RSVD1 = 0x00000003, 18107 SQ_WAVE_TYPE_HS = 0x00000004, 18108 SQ_WAVE_TYPE_RSVD2 = 0x00000005, 18109 SQ_WAVE_TYPE_CS = 0x00000006, 18110 SQ_WAVE_TYPE_PS1 = 0x00000007, 18111 SQ_WAVE_TYPE_PS2 = 0x00000008, 18112 SQ_WAVE_TYPE_PS3 = 0x00000009, 18113 } SQ_WAVE_TYPE; 18114 18115 /* 18116 * SQ_WAVE_TYPE value 18117 */ 18118 18119 #define SQ_WAVE_TYPE_PS0 0x00000000 18120 18121 /* 18122 * SQ_SEG value 18123 */ 18124 18125 #define SQ_FLAT 0x00000000 18126 #define SQ_SCRATCH 0x00000001 18127 #define SQ_GLOBAL 0x00000002 18128 18129 /* 18130 * SQIND_PARTITIONS value 18131 */ 18132 18133 #define SQIND_GLOBAL_REGS_OFFSET 0x00000000 18134 #define SQIND_GLOBAL_REGS_SIZE 0x00000008 18135 #define SQIND_LOCAL_REGS_OFFSET 0x00000008 18136 #define SQIND_LOCAL_REGS_SIZE 0x00000008 18137 #define SQIND_WAVE_HW_REGS_OFFSET 0x00000100 18138 #define SQIND_WAVE_HW_REGS_SIZE 0x00000040 18139 #define SQIND_WAVE_HOST_REGS_OFFSET 0x00000140 18140 #define SQIND_WAVE_HOST_REGS_SIZE 0x000000c0 18141 #define SQIND_WAVE_SGPRS_OFFSET 0x00000200 18142 #define SQIND_WAVE_SGPRS_SIZE 0x00000200 18143 #define SQIND_WAVE_VGPRS_OFFSET 0x00000400 18144 #define SQIND_WAVE_VGPRS_SIZE 0x00000400 18145 18146 /* 18147 * SQ_GFXDEC value 18148 */ 18149 18150 #define SQ_GFXDEC_BEGIN 0x0000a000 18151 #define SQ_GFXDEC_END 0x0000c000 18152 #define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a 18153 18154 /* 18155 * SQDEC value 18156 */ 18157 18158 #define SQDEC_BEGIN 0x00002300 18159 #define SQDEC_END 0x000023ff 18160 18161 /* 18162 * PFVF_SQDEC value 18163 */ 18164 18165 #define PFVF_SQDEC_BEGIN 0x0000a9e0 18166 #define PFVF_SQDEC_END 0x0000a9ff 18167 18168 /* 18169 * SQPERFSDEC value 18170 */ 18171 18172 #define SQPERFSDEC_BEGIN 0x0000d9c0 18173 #define SQPERFSDEC_END 0x0000da40 18174 18175 /* 18176 * SQPERFDDEC value 18177 */ 18178 18179 #define SQPERFDDEC_BEGIN 0x0000d1c0 18180 #define SQPERFDDEC_END 0x0000d240 18181 18182 /* 18183 * SQGFXUDEC value 18184 */ 18185 18186 #define SQGFXUDEC_BEGIN 0x0000c330 18187 #define SQGFXUDEC_END 0x0000c380 18188 18189 /* 18190 * SQPWRDEC value 18191 */ 18192 18193 #define SQPWRDEC_BEGIN 0x0000f08c 18194 #define SQPWRDEC_END 0x0000f094 18195 18196 /* 18197 * SQ_DISPATCHER value 18198 */ 18199 18200 #define SQ_DISPATCHER_GFX_MIN 0x00000010 18201 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 18202 18203 /* 18204 * SQ_MAX value 18205 */ 18206 18207 #define SQ_MAX_PGM_SGPRS 0x00000068 18208 #define SQ_MAX_PGM_VGPRS 0x00000100 18209 18210 /* 18211 * SQ_EXCP_BITS value 18212 */ 18213 18214 #define SQ_EX_EXCP_VALU_BASE 0x00000000 18215 #define SQ_EX_EXCP_VALU_SIZE 0x00000007 18216 #define SQ_EX_EXCP_ALU_INVALID 0x00000000 18217 #define SQ_EX_EXCP_ALU_INPUT_DENORM 0x00000001 18218 #define SQ_EX_EXCP_ALU_FLOAT_DIV0 0x00000002 18219 #define SQ_EX_EXCP_ALU_OVERFLOW 0x00000003 18220 #define SQ_EX_EXCP_ALU_UNDERFLOW 0x00000004 18221 #define SQ_EX_EXCP_ALU_INEXACT 0x00000005 18222 #define SQ_EX_EXCP_ALU_INT_DIV0 0x00000006 18223 #define SQ_EX_EXCP_ADDR_WATCH 0x00000007 18224 18225 /* 18226 * HW_INSERTED_INST_ID value 18227 */ 18228 18229 #define INST_ID_PRIV_START 0x80000000 18230 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 18231 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 18232 #define INST_ID_HW_TRAP 0xfffffff2 18233 #define INST_ID_KILL_SEQ 0xfffffff3 18234 #define INST_ID_SPI_WREXEC 0xfffffff4 18235 #define INST_ID_HW_TRAP_GET_TBA 0xfffffff5 18236 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe 18237 18238 /* 18239 * SIMM16_WAITCNT_PARTITIONS value 18240 */ 18241 18242 #define SIMM16_WAITCNT_EXP_CNT_START 0x00000000 18243 #define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 18244 #define SIMM16_WAITCNT_LGKM_CNT_START 0x00000004 18245 #define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000006 18246 #define SIMM16_WAITCNT_VM_CNT_START 0x0000000a 18247 #define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000006 18248 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000 18249 #define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001 18250 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001 18251 #define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001 18252 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002 18253 #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003 18254 #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000007 18255 #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001 18256 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000008 18257 #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001 18258 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000009 18259 #define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003 18260 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000c 18261 #define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000004 18262 18263 /* 18264 * SIMM16_WAIT_EVENT_PARTITIONS value 18265 */ 18266 18267 #define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000 18268 #define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001 18269 18270 /* 18271 * SQ_WAVE_IB_DEP_COUNTER_SIZES value 18272 */ 18273 18274 #define SQ_WAVE_IB_DEP_SA_SDST_SIZE 0x00000004 18275 #define SQ_WAVE_IB_DEP_SA_EXEC_SIZE 0x00000002 18276 #define SQ_WAVE_IB_DEP_SA_M0_SIZE 0x00000001 18277 #define SQ_WAVE_IB_DEP_VM_VSRC_SIZE 0x00000004 18278 #define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE 0x00000001 18279 #define SQ_WAVE_IB_DEP_VA_SSRC_SIZE 0x00000003 18280 #define SQ_WAVE_IB_DEP_VA_SDST_SIZE 0x00000004 18281 #define SQ_WAVE_IB_DEP_VA_VCC_SIZE 0x00000003 18282 #define SQ_WAVE_IB_DEP_VA_EXEC_SIZE 0x00000002 18283 #define SQ_WAVE_IB_DEP_VA_VDST_SIZE 0x00000005 18284 #define SQ_WAVE_IB_DEP_LDS_DIR_SIZE 0x00000003 18285 18286 /* 18287 * SQ_ARB_STATE value 18288 */ 18289 18290 #define SQ_ARB_STATE_ISSUED_BRMSG 0x00000000 18291 #define SQ_ARB_STATE_ISSUED_EXPORT 0x00000001 18292 #define SQ_ARB_STATE_ISSUED_LDS_DIRECT 0x00000002 18293 #define SQ_ARB_STATE_ISSUED_LDS 0x00000003 18294 #define SQ_ARB_STATE_ISSUED_TEX 0x00000004 18295 #define SQ_ARB_STATE_ISSUED_SCALAR 0x00000005 18296 #define SQ_ARB_STATE_ISSUED_VALU 0x00000006 18297 #define SQ_ARB_STATE_STALLED_BRMSG 0x00000008 18298 #define SQ_ARB_STATE_STALLED_EXPORT 0x00000009 18299 #define SQ_ARB_STATE_STALLED_LDS_DIRECT 0x0000000a 18300 #define SQ_ARB_STATE_STALLED_LDS 0x0000000b 18301 #define SQ_ARB_STATE_STALLED_TEX 0x0000000c 18302 #define SQ_ARB_STATE_STALLED_SCALAR 0x0000000d 18303 #define SQ_ARB_STATE_STALLED_VALU 0x0000000e 18304 18305 /******************************************************* 18306 * GL1 Enums 18307 *******************************************************/ 18308 18309 /* 18310 * GL1A_PERF_SEL enum 18311 */ 18312 18313 typedef enum GL1A_PERF_SEL { 18314 GL1A_PERF_SEL_BUSY = 0x00000000, 18315 GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001, 18316 GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002, 18317 GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003, 18318 GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004, 18319 GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000005, 18320 GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000006, 18321 GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000007, 18322 GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000008, 18323 GL1A_PERF_SEL_WDS_32B_GL1C0 = 0x00000009, 18324 GL1A_PERF_SEL_WDS_32B_GL1C1 = 0x0000000a, 18325 GL1A_PERF_SEL_WDS_32B_GL1C2 = 0x0000000b, 18326 GL1A_PERF_SEL_WDS_32B_GL1C3 = 0x0000000c, 18327 GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 0x0000000d, 18328 GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 0x0000000e, 18329 GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 0x0000000f, 18330 GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 0x00000010, 18331 GL1A_PERF_SEL_ARB_REQUESTS = 0x00000011, 18332 GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012, 18333 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000013, 18334 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000014, 18335 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000015, 18336 GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000016, 18337 GL1A_PERF_SEL_CYCLE = 0x00000017, 18338 } GL1A_PERF_SEL; 18339 18340 /* 18341 * GL1C_PERF_SEL enum 18342 */ 18343 18344 typedef enum GL1C_PERF_SEL { 18345 GL1C_PERF_SEL_CYCLE = 0x00000000, 18346 GL1C_PERF_SEL_BUSY = 0x00000001, 18347 GL1C_PERF_SEL_STARVE = 0x00000002, 18348 GL1C_PERF_SEL_ARB_RET_LEVEL = 0x00000003, 18349 GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, 18350 GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, 18351 GL1C_PERF_SEL_REQ = 0x00000006, 18352 GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, 18353 GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, 18354 GL1C_PERF_SEL_REQ_NOP_ACK = 0x00000009, 18355 GL1C_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, 18356 GL1C_PERF_SEL_REQ_READ = 0x0000000b, 18357 GL1C_PERF_SEL_REQ_READ_128B = 0x0000000c, 18358 GL1C_PERF_SEL_REQ_READ_32B = 0x0000000d, 18359 GL1C_PERF_SEL_REQ_READ_64B = 0x0000000e, 18360 GL1C_PERF_SEL_REQ_WRITE = 0x0000000f, 18361 GL1C_PERF_SEL_REQ_WRITE_32B = 0x00000010, 18362 GL1C_PERF_SEL_REQ_WRITE_64B = 0x00000011, 18363 GL1C_PERF_SEL_STALL_GL2_GL1 = 0x00000012, 18364 GL1C_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, 18365 GL1C_PERF_SEL_STALL_VM = 0x00000014, 18366 GL1C_PERF_SEL_REQ_CLIENT0 = 0x00000015, 18367 GL1C_PERF_SEL_REQ_CLIENT1 = 0x00000016, 18368 GL1C_PERF_SEL_REQ_CLIENT2 = 0x00000017, 18369 GL1C_PERF_SEL_REQ_CLIENT3 = 0x00000018, 18370 GL1C_PERF_SEL_REQ_CLIENT4 = 0x00000019, 18371 GL1C_PERF_SEL_REQ_CLIENT5 = 0x0000001a, 18372 GL1C_PERF_SEL_REQ_CLIENT6 = 0x0000001b, 18373 GL1C_PERF_SEL_REQ_CLIENT7 = 0x0000001c, 18374 GL1C_PERF_SEL_REQ_CLIENT8 = 0x0000001d, 18375 GL1C_PERF_SEL_REQ_CLIENT9 = 0x0000001e, 18376 GL1C_PERF_SEL_REQ_CLIENT10 = 0x0000001f, 18377 GL1C_PERF_SEL_REQ_CLIENT11 = 0x00000020, 18378 GL1C_PERF_SEL_REQ_CLIENT12 = 0x00000021, 18379 GL1C_PERF_SEL_REQ_CLIENT13 = 0x00000022, 18380 GL1C_PERF_SEL_REQ_CLIENT14 = 0x00000023, 18381 GL1C_PERF_SEL_REQ_CLIENT15 = 0x00000024, 18382 GL1C_PERF_SEL_REQ_CLIENT16 = 0x00000025, 18383 GL1C_PERF_SEL_REQ_CLIENT17 = 0x00000026, 18384 GL1C_PERF_SEL_REQ_CLIENT18 = 0x00000027, 18385 GL1C_PERF_SEL_REQ_CLIENT19 = 0x00000028, 18386 GL1C_PERF_SEL_REQ_CLIENT20 = 0x00000029, 18387 GL1C_PERF_SEL_REQ_CLIENT21 = 0x0000002a, 18388 GL1C_PERF_SEL_REQ_CLIENT22 = 0x0000002b, 18389 GL1C_PERF_SEL_REQ_CLIENT23 = 0x0000002c, 18390 GL1C_PERF_SEL_REQ_CLIENT24 = 0x0000002d, 18391 GL1C_PERF_SEL_REQ_CLIENT25 = 0x0000002e, 18392 GL1C_PERF_SEL_REQ_CLIENT26 = 0x0000002f, 18393 GL1C_PERF_SEL_REQ_CLIENT27 = 0x00000030, 18394 GL1C_PERF_SEL_UTCL0_REQUEST = 0x00000031, 18395 GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000032, 18396 GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000033, 18397 GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000034, 18398 GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000035, 18399 GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000036, 18400 GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000037, 18401 GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000038, 18402 GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000039, 18403 GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000003a, 18404 GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000003b, 18405 GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000003c, 18406 GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000003d, 18407 GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000003e, 18408 GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000003f, 18409 GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000040, 18410 GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000041, 18411 GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000042, 18412 GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000043, 18413 GL1C_PERF_SEL_UTCL0_GPA3_REQUEST = 0x00000044, 18414 } GL1C_PERF_SEL; 18415 18416 /* 18417 * GL1XA_PERF_SEL enum 18418 */ 18419 18420 typedef enum GL1XA_PERF_SEL { 18421 GL1XA_PERF_SEL_BUSY = 0x00000000, 18422 GL1XA_PERF_SEL_STALL_GL1XC0 = 0x00000001, 18423 GL1XA_PERF_SEL_STALL_GL1XC1 = 0x00000002, 18424 GL1XA_PERF_SEL_STALL_GL1XC2 = 0x00000003, 18425 GL1XA_PERF_SEL_STALL_GL1XC3 = 0x00000004, 18426 GL1XA_PERF_SEL_REQUEST_GL1XC0 = 0x00000005, 18427 GL1XA_PERF_SEL_REQUEST_GL1XC1 = 0x00000006, 18428 GL1XA_PERF_SEL_REQUEST_GL1XC2 = 0x00000007, 18429 GL1XA_PERF_SEL_REQUEST_GL1XC3 = 0x00000008, 18430 GL1XA_PERF_SEL_WDS_32B_GL1XC0 = 0x00000009, 18431 GL1XA_PERF_SEL_WDS_32B_GL1XC1 = 0x0000000a, 18432 GL1XA_PERF_SEL_WDS_32B_GL1XC2 = 0x0000000b, 18433 GL1XA_PERF_SEL_WDS_32B_GL1XC3 = 0x0000000c, 18434 GL1XA_PERF_SEL_BURST_COUNT_GL1XC0 = 0x0000000d, 18435 GL1XA_PERF_SEL_BURST_COUNT_GL1XC1 = 0x0000000e, 18436 GL1XA_PERF_SEL_BURST_COUNT_GL1XC2 = 0x0000000f, 18437 GL1XA_PERF_SEL_BURST_COUNT_GL1XC3 = 0x00000010, 18438 GL1XA_PERF_SEL_ARB_REQUESTS = 0x00000011, 18439 GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012, 18440 GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0 = 0x00000013, 18441 GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1 = 0x00000014, 18442 GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2 = 0x00000015, 18443 GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3 = 0x00000016, 18444 GL1XA_PERF_SEL_CYCLE = 0x00000017, 18445 } GL1XA_PERF_SEL; 18446 18447 /* 18448 * GL1XC_PERF_SEL enum 18449 */ 18450 18451 typedef enum GL1XC_PERF_SEL { 18452 GL1XC_PERF_SEL_CYCLE = 0x00000000, 18453 GL1XC_PERF_SEL_BUSY = 0x00000001, 18454 GL1XC_PERF_SEL_STARVE = 0x00000002, 18455 GL1XC_PERF_SEL_ARB_RET_LEVEL = 0x00000003, 18456 GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, 18457 GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, 18458 GL1XC_PERF_SEL_REQ = 0x00000006, 18459 GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, 18460 GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, 18461 GL1XC_PERF_SEL_REQ_NOP_ACK = 0x00000009, 18462 GL1XC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, 18463 GL1XC_PERF_SEL_REQ_READ = 0x0000000b, 18464 GL1XC_PERF_SEL_REQ_READ_128B = 0x0000000c, 18465 GL1XC_PERF_SEL_REQ_READ_32B = 0x0000000d, 18466 GL1XC_PERF_SEL_REQ_READ_64B = 0x0000000e, 18467 GL1XC_PERF_SEL_REQ_WRITE = 0x0000000f, 18468 GL1XC_PERF_SEL_REQ_WRITE_32B = 0x00000010, 18469 GL1XC_PERF_SEL_REQ_WRITE_64B = 0x00000011, 18470 GL1XC_PERF_SEL_STALL_GL2_GL1 = 0x00000012, 18471 GL1XC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, 18472 GL1XC_PERF_SEL_STALL_VM = 0x00000014, 18473 GL1XC_PERF_SEL_REQ_CLIENT0 = 0x00000015, 18474 GL1XC_PERF_SEL_REQ_CLIENT1 = 0x00000016, 18475 GL1XC_PERF_SEL_REQ_CLIENT2 = 0x00000017, 18476 GL1XC_PERF_SEL_REQ_CLIENT3 = 0x00000018, 18477 GL1XC_PERF_SEL_REQ_CLIENT4 = 0x00000019, 18478 GL1XC_PERF_SEL_REQ_CLIENT5 = 0x0000001a, 18479 GL1XC_PERF_SEL_REQ_CLIENT6 = 0x0000001b, 18480 GL1XC_PERF_SEL_REQ_CLIENT7 = 0x0000001c, 18481 GL1XC_PERF_SEL_REQ_CLIENT8 = 0x0000001d, 18482 GL1XC_PERF_SEL_REQ_CLIENT9 = 0x0000001e, 18483 GL1XC_PERF_SEL_REQ_CLIENT10 = 0x0000001f, 18484 GL1XC_PERF_SEL_REQ_CLIENT11 = 0x00000020, 18485 GL1XC_PERF_SEL_REQ_CLIENT12 = 0x00000021, 18486 GL1XC_PERF_SEL_REQ_CLIENT13 = 0x00000022, 18487 GL1XC_PERF_SEL_REQ_CLIENT14 = 0x00000023, 18488 GL1XC_PERF_SEL_REQ_CLIENT15 = 0x00000024, 18489 GL1XC_PERF_SEL_REQ_CLIENT16 = 0x00000025, 18490 GL1XC_PERF_SEL_REQ_CLIENT17 = 0x00000026, 18491 GL1XC_PERF_SEL_REQ_CLIENT18 = 0x00000027, 18492 GL1XC_PERF_SEL_REQ_CLIENT19 = 0x00000028, 18493 GL1XC_PERF_SEL_REQ_CLIENT20 = 0x00000029, 18494 GL1XC_PERF_SEL_REQ_CLIENT21 = 0x0000002a, 18495 GL1XC_PERF_SEL_REQ_CLIENT22 = 0x0000002b, 18496 GL1XC_PERF_SEL_REQ_CLIENT23 = 0x0000002c, 18497 GL1XC_PERF_SEL_REQ_CLIENT24 = 0x0000002d, 18498 GL1XC_PERF_SEL_REQ_CLIENT25 = 0x0000002e, 18499 GL1XC_PERF_SEL_REQ_CLIENT26 = 0x0000002f, 18500 GL1XC_PERF_SEL_REQ_CLIENT27 = 0x00000030, 18501 GL1XC_PERF_SEL_UTCL0_REQUEST = 0x00000031, 18502 GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000032, 18503 GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000033, 18504 GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000034, 18505 GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000035, 18506 GL1XC_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000036, 18507 GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000037, 18508 GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000038, 18509 GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000039, 18510 GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000003a, 18511 GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000003b, 18512 GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000003c, 18513 GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000003d, 18514 GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000003e, 18515 GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000003f, 18516 GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000040, 18517 GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000041, 18518 GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000042, 18519 GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000043, 18520 GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST = 0x00000044, 18521 } GL1XC_PERF_SEL; 18522 18523 /******************************************************* 18524 * GRBMH Enums 18525 *******************************************************/ 18526 18527 /* 18528 * GRBMH_PERF_SEL enum 18529 */ 18530 18531 typedef enum GRBMH_PERF_SEL { 18532 GRBMH_PERF_SEL_COUNT = 0x00000000, 18533 GRBMH_PERF_SEL_USER_DEFINED = 0x00000001, 18534 GRBMH_PERF_SEL_CB_BUSY = 0x00000002, 18535 GRBMH_PERF_SEL_CB_CLEAN = 0x00000003, 18536 GRBMH_PERF_SEL_DB_BUSY = 0x00000004, 18537 GRBMH_PERF_SEL_DB_CLEAN = 0x00000005, 18538 GRBMH_PERF_SEL_SC_BUSY = 0x00000006, 18539 GRBMH_PERF_SEL_SC_CLEAN = 0x00000007, 18540 GRBMH_PERF_SEL_SPI_BUSY = 0x00000009, 18541 GRBMH_PERF_SEL_SX_BUSY = 0x0000000a, 18542 GRBMH_PERF_SEL_TA_BUSY = 0x0000000b, 18543 GRBMH_PERF_SEL_EA_BUSY = 0x0000000c, 18544 GRBMH_PERF_SEL_EA_LINK_BUSY = 0x0000000d, 18545 GRBMH_PERF_SEL_PA_BUSY = 0x0000000e, 18546 GRBMH_PERF_SEL_BCI_BUSY = 0x0000000f, 18547 GRBMH_PERF_SEL_GL2A_BUSY = 0x00000010, 18548 GRBMH_PERF_SEL_GL2C_BUSY = 0x00000011, 18549 GRBMH_PERF_SEL_UTCL1_BUSY = 0x00000012, 18550 GRBMH_PERF_SEL_TCP_BUSY = 0x00000013, 18551 GRBMH_PERF_SEL_GL1A_BUSY = 0x00000014, 18552 GRBMH_PERF_SEL_GL1CC_BUSY = 0x00000015, 18553 GRBMH_PERF_SEL_GL1XCC_BUSY = 0x00000016, 18554 GRBMH_PERF_SEL_PC_BUSY = 0x00000017, 18555 GRBMH_PERF_SEL_GE_BUSY = 0x00000018, 18556 GRBMH_PERF_SEL_RLC_BUSY = 0x00000019, 18557 } GRBMH_PERF_SEL; 18558 18559 /******************************************************* 18560 * TA Enums 18561 *******************************************************/ 18562 18563 /* 18564 * TA_PERFCOUNT_SEL enum 18565 */ 18566 18567 typedef enum TA_PERFCOUNT_SEL { 18568 TA_PERF_SEL_NULL = 0x00000000, 18569 TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001, 18570 TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002, 18571 TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003, 18572 TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004, 18573 TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005, 18574 TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006, 18575 TA_PERF_SEL_gradient_busy = 0x00000007, 18576 TA_PERF_SEL_gradient_fifo_busy = 0x00000008, 18577 TA_PERF_SEL_lod_busy = 0x00000009, 18578 TA_PERF_SEL_lod_fifo_busy = 0x0000000a, 18579 TA_PERF_SEL_addresser_busy = 0x0000000b, 18580 TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, 18581 TA_PERF_SEL_aligner_busy = 0x0000000d, 18582 TA_PERF_SEL_write_path_busy = 0x0000000e, 18583 TA_PERF_SEL_ta_busy = 0x0000000f, 18584 TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010, 18585 TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011, 18586 TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012, 18587 TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013, 18588 TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014, 18589 TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015, 18590 TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016, 18591 TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017, 18592 TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018, 18593 TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019, 18594 TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a, 18595 TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b, 18596 TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c, 18597 TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d, 18598 TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e, 18599 TA_PERF_SEL_total_wavefronts = 0x00000020, 18600 TA_PERF_SEL_gradient_cycles = 0x00000021, 18601 TA_PERF_SEL_walker_cycles = 0x00000022, 18602 TA_PERF_SEL_aligner_cycles = 0x00000023, 18603 TA_PERF_SEL_image_wavefronts = 0x00000024, 18604 TA_PERF_SEL_image_read_wavefronts = 0x00000025, 18605 TA_PERF_SEL_image_store_wavefronts = 0x00000026, 18606 TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, 18607 TA_PERF_SEL_image_sampler_total_cycles = 0x00000028, 18608 TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029, 18609 TA_PERF_SEL_flat_total_cycles = 0x0000002a, 18610 TA_PERF_SEL_buffer_wavefronts = 0x0000002c, 18611 TA_PERF_SEL_buffer_load_wavefronts = 0x0000002d, 18612 TA_PERF_SEL_buffer_store_wavefronts = 0x0000002e, 18613 TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, 18614 TA_PERF_SEL_buffer_total_cycles = 0x00000031, 18615 TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032, 18616 TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033, 18617 TA_PERF_SEL_buffer_has_index_instructions = 0x00000034, 18618 TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035, 18619 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, 18620 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, 18621 TA_PERF_SEL_image_sampler_wavefronts = 0x00000038, 18622 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, 18623 TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, 18624 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, 18625 TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, 18626 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, 18627 TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, 18628 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, 18629 TA_PERF_SEL_color_1_cycle_quads = 0x00000040, 18630 TA_PERF_SEL_color_2_cycle_quads = 0x00000041, 18631 TA_PERF_SEL_color_3_cycle_quads = 0x00000042, 18632 TA_PERF_SEL_mip_1_cycle_quads = 0x00000044, 18633 TA_PERF_SEL_mip_2_cycle_quads = 0x00000045, 18634 TA_PERF_SEL_vol_1_cycle_quads = 0x00000046, 18635 TA_PERF_SEL_vol_2_cycle_quads = 0x00000047, 18636 TA_PERF_SEL_sampler_op_quads = 0x00000048, 18637 TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, 18638 TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, 18639 TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, 18640 TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, 18641 TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, 18642 TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, 18643 TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, 18644 TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, 18645 TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, 18646 TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, 18647 TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, 18648 TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, 18649 TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, 18650 TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, 18651 TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, 18652 TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, 18653 TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, 18654 TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, 18655 TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, 18656 TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, 18657 TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, 18658 TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, 18659 TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, 18660 TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, 18661 TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, 18662 TA_PERF_SEL_store_write_data_input_cycles = 0x00000062, 18663 TA_PERF_SEL_store_write_data_output_cycles = 0x00000063, 18664 TA_PERF_SEL_flat_wavefronts = 0x00000064, 18665 TA_PERF_SEL_flat_load_wavefronts = 0x00000065, 18666 TA_PERF_SEL_flat_store_wavefronts = 0x00000066, 18667 TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, 18668 TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068, 18669 TA_PERF_SEL_register_clk_valid_cycles = 0x00000069, 18670 TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a, 18671 TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b, 18672 TA_PERF_SEL_flat_2_address_input_vgpr_instructions = 0x0000006c, 18673 TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d, 18674 TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e, 18675 TA_PERF_SEL_mipmap_lod_15_samples = 0x00000070, 18676 TA_PERF_SEL_mipmap_lod_16_samples = 0x00000071, 18677 TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072, 18678 TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073, 18679 TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074, 18680 TA_PERF_SEL_store_has_x_instructions = 0x00000075, 18681 TA_PERF_SEL_store_has_y_instructions = 0x00000076, 18682 TA_PERF_SEL_store_has_z_instructions = 0x00000077, 18683 TA_PERF_SEL_store_has_w_instructions = 0x00000078, 18684 TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079, 18685 TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a, 18686 TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b, 18687 TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c, 18688 TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d, 18689 TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e, 18690 TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f, 18691 TA_PERF_SEL_in_busy = 0x00000080, 18692 TA_PERF_SEL_in_fifos_busy = 0x00000081, 18693 TA_PERF_SEL_in_cfifo_busy = 0x00000082, 18694 TA_PERF_SEL_in_qfifo_busy = 0x00000083, 18695 TA_PERF_SEL_in_wfifo_busy = 0x00000084, 18696 TA_PERF_SEL_in_rfifo_busy = 0x00000085, 18697 TA_PERF_SEL_bf_busy = 0x00000086, 18698 TA_PERF_SEL_ns_busy = 0x00000087, 18699 TA_PERF_SEL_smp_busy_ns_idle = 0x00000088, 18700 TA_PERF_SEL_smp_idle_ns_busy = 0x00000089, 18701 TA_PERF_SEL_vmemcmd_cycles = 0x00000090, 18702 TA_PERF_SEL_vmemreq_cycles = 0x00000091, 18703 TA_PERF_SEL_in_waiting_on_req_cycles = 0x00000092, 18704 TA_PERF_SEL_in_addr_cycles = 0x00000096, 18705 TA_PERF_SEL_in_data_cycles = 0x00000097, 18706 TA_PERF_SEL_point_sampled_quads = 0x000000a0, 18707 TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2, 18708 TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3, 18709 TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4, 18710 TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5, 18711 TA_PERF_SEL_num_unlit_nodes_ta_opt = 0x000000ad, 18712 TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae, 18713 TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af, 18714 TA_PERF_SEL_image_sampler_1_op_burst = 0x000000c0, 18715 TA_PERF_SEL_image_sampler_2to3_op_burst = 0x000000c1, 18716 TA_PERF_SEL_image_sampler_4to7_op_burst = 0x000000c2, 18717 TA_PERF_SEL_image_sampler_ge8_op_burst = 0x000000c3, 18718 TA_PERF_SEL_image_linked_1_op_burst = 0x000000c4, 18719 TA_PERF_SEL_image_linked_2to3_op_burst = 0x000000c5, 18720 TA_PERF_SEL_image_linked_4to7_op_burst = 0x000000c6, 18721 TA_PERF_SEL_image_linked_ge8_op_burst = 0x000000c7, 18722 TA_PERF_SEL_image_nosampler_1_op_burst = 0x000000cc, 18723 TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd, 18724 TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce, 18725 TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf, 18726 TA_PERF_SEL_buffer_flat_1_op_burst = 0x000000d0, 18727 TA_PERF_SEL_buffer_flat_2to3_op_burst = 0x000000d1, 18728 TA_PERF_SEL_buffer_flat_4to31_op_burst = 0x000000d2, 18729 TA_PERF_SEL_buffer_flat_ge32_op_burst = 0x000000d3, 18730 TA_PERF_SEL_write_1_op_burst = 0x000000d4, 18731 TA_PERF_SEL_write_2to3_op_burst = 0x000000d5, 18732 TA_PERF_SEL_write_4to31_op_burst = 0x000000d6, 18733 TA_PERF_SEL_write_ge32_op_burst = 0x000000d7, 18734 TA_PERF_SEL_ibubble_1_cycle_burst = 0x000000d8, 18735 TA_PERF_SEL_ibubble_2to3_cycle_burst = 0x000000d9, 18736 TA_PERF_SEL_ibubble_4to15_cycle_burst = 0x000000da, 18737 TA_PERF_SEL_ibubble_16to31_cycle_burst = 0x000000db, 18738 TA_PERF_SEL_ibubble_32to63_cycle_burst = 0x000000dc, 18739 TA_PERF_SEL_ibubble_ge64_cycle_burst = 0x000000dd, 18740 TA_PERF_SEL_sampler_clk_valid_cycles = 0x000000e0, 18741 TA_PERF_SEL_nonsampler_clk_valid_cycles = 0x000000e1, 18742 TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2, 18743 TA_PERF_SEL_write_data_clk_valid_cycles = 0x000000e3, 18744 TA_PERF_SEL_gradient_clk_valid_cycles = 0x000000e4, 18745 TA_PERF_SEL_lod_aniso_clk_valid_cycles = 0x000000e5, 18746 TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6, 18747 TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7, 18748 TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8, 18749 TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9, 18750 TA_PERF_SEL_aligner_clk_valid_cycles = 0x000000ea, 18751 TA_PERF_SEL_tcreq_clk_valid_cycles = 0x000000eb, 18752 } TA_PERFCOUNT_SEL; 18753 18754 /* 18755 * TEX_BC_SWIZZLE enum 18756 */ 18757 18758 typedef enum TEX_BC_SWIZZLE { 18759 TEX_BC_Swizzle_XYZW = 0x00000000, 18760 TEX_BC_Swizzle_XWYZ = 0x00000001, 18761 TEX_BC_Swizzle_WZYX = 0x00000002, 18762 TEX_BC_Swizzle_WXYZ = 0x00000003, 18763 TEX_BC_Swizzle_ZYXW = 0x00000004, 18764 TEX_BC_Swizzle_YXWZ = 0x00000005, 18765 } TEX_BC_SWIZZLE; 18766 18767 /* 18768 * TEX_BORDER_COLOR_TYPE enum 18769 */ 18770 18771 typedef enum TEX_BORDER_COLOR_TYPE { 18772 TEX_BorderColor_TransparentBlack = 0x00000000, 18773 TEX_BorderColor_OpaqueBlack = 0x00000001, 18774 TEX_BorderColor_OpaqueWhite = 0x00000002, 18775 TEX_BorderColor_Register = 0x00000003, 18776 } TEX_BORDER_COLOR_TYPE; 18777 18778 /* 18779 * TEX_CHROMA_KEY enum 18780 */ 18781 18782 typedef enum TEX_CHROMA_KEY { 18783 TEX_ChromaKey_Disabled = 0x00000000, 18784 TEX_ChromaKey_Kill = 0x00000001, 18785 TEX_ChromaKey_Blend = 0x00000002, 18786 TEX_ChromaKey_RESERVED_3 = 0x00000003, 18787 } TEX_CHROMA_KEY; 18788 18789 /* 18790 * TEX_CLAMP enum 18791 */ 18792 18793 typedef enum TEX_CLAMP { 18794 TEX_Clamp_Repeat = 0x00000000, 18795 TEX_Clamp_Mirror = 0x00000001, 18796 TEX_Clamp_ClampToLast = 0x00000002, 18797 TEX_Clamp_MirrorOnceToLast = 0x00000003, 18798 TEX_Clamp_ClampHalfToBorder = 0x00000004, 18799 TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, 18800 TEX_Clamp_ClampToBorder = 0x00000006, 18801 TEX_Clamp_MirrorOnceToBorder = 0x00000007, 18802 } TEX_CLAMP; 18803 18804 /* 18805 * TEX_COORD_TYPE enum 18806 */ 18807 18808 typedef enum TEX_COORD_TYPE { 18809 TEX_CoordType_Unnormalized = 0x00000000, 18810 TEX_CoordType_Normalized = 0x00000001, 18811 } TEX_COORD_TYPE; 18812 18813 /* 18814 * TEX_DEPTH_COMPARE_FUNCTION enum 18815 */ 18816 18817 typedef enum TEX_DEPTH_COMPARE_FUNCTION { 18818 TEX_DepthCompareFunction_Never = 0x00000000, 18819 TEX_DepthCompareFunction_Less = 0x00000001, 18820 TEX_DepthCompareFunction_Equal = 0x00000002, 18821 TEX_DepthCompareFunction_LessEqual = 0x00000003, 18822 TEX_DepthCompareFunction_Greater = 0x00000004, 18823 TEX_DepthCompareFunction_NotEqual = 0x00000005, 18824 TEX_DepthCompareFunction_GreaterEqual = 0x00000006, 18825 TEX_DepthCompareFunction_Always = 0x00000007, 18826 } TEX_DEPTH_COMPARE_FUNCTION; 18827 18828 /* 18829 * TEX_FORMAT_COMP enum 18830 */ 18831 18832 typedef enum TEX_FORMAT_COMP { 18833 TEX_FormatComp_Unsigned = 0x00000000, 18834 TEX_FormatComp_Signed = 0x00000001, 18835 TEX_FormatComp_UnsignedBiased = 0x00000002, 18836 TEX_FormatComp_RESERVED_3 = 0x00000003, 18837 } TEX_FORMAT_COMP; 18838 18839 /* 18840 * TEX_MAX_ANISO_RATIO enum 18841 */ 18842 18843 typedef enum TEX_MAX_ANISO_RATIO { 18844 TEX_MaxAnisoRatio_1to1 = 0x00000000, 18845 TEX_MaxAnisoRatio_2to1 = 0x00000001, 18846 TEX_MaxAnisoRatio_4to1 = 0x00000002, 18847 TEX_MaxAnisoRatio_8to1 = 0x00000003, 18848 TEX_MaxAnisoRatio_16to1 = 0x00000004, 18849 TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, 18850 TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, 18851 TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, 18852 } TEX_MAX_ANISO_RATIO; 18853 18854 /* 18855 * TEX_MIP_FILTER enum 18856 */ 18857 18858 typedef enum TEX_MIP_FILTER { 18859 TEX_MipFilter_None = 0x00000000, 18860 TEX_MipFilter_Point = 0x00000001, 18861 TEX_MipFilter_Linear = 0x00000002, 18862 TEX_MipFilter_Point_Aniso_Adj = 0x00000003, 18863 } TEX_MIP_FILTER; 18864 18865 /* 18866 * TEX_REQUEST_SIZE enum 18867 */ 18868 18869 typedef enum TEX_REQUEST_SIZE { 18870 TEX_RequestSize_32B = 0x00000000, 18871 TEX_RequestSize_64B = 0x00000001, 18872 TEX_RequestSize_128B = 0x00000002, 18873 TEX_RequestSize_2X64B = 0x00000003, 18874 } TEX_REQUEST_SIZE; 18875 18876 /* 18877 * TEX_SAMPLER_TYPE enum 18878 */ 18879 18880 typedef enum TEX_SAMPLER_TYPE { 18881 TEX_SamplerType_Invalid = 0x00000000, 18882 TEX_SamplerType_Valid = 0x00000001, 18883 } TEX_SAMPLER_TYPE; 18884 18885 /* 18886 * TEX_XY_FILTER enum 18887 */ 18888 18889 typedef enum TEX_XY_FILTER { 18890 TEX_XYFilter_Point = 0x00000000, 18891 TEX_XYFilter_Linear = 0x00000001, 18892 TEX_XYFilter_AnisoPoint = 0x00000002, 18893 TEX_XYFilter_AnisoLinear = 0x00000003, 18894 } TEX_XY_FILTER; 18895 18896 /* 18897 * TEX_Z_FILTER enum 18898 */ 18899 18900 typedef enum TEX_Z_FILTER { 18901 TEX_ZFilter_None = 0x00000000, 18902 TEX_ZFilter_Point = 0x00000001, 18903 TEX_ZFilter_Linear = 0x00000002, 18904 TEX_ZFilter_RESERVED_3 = 0x00000003, 18905 } TEX_Z_FILTER; 18906 18907 /* 18908 * TVX_TYPE enum 18909 */ 18910 18911 typedef enum TVX_TYPE { 18912 TVX_Type_InvalidTextureResource = 0x00000000, 18913 TVX_Type_InvalidVertexBuffer = 0x00000001, 18914 TVX_Type_ValidTextureResource = 0x00000002, 18915 TVX_Type_ValidVertexBuffer = 0x00000003, 18916 } TVX_TYPE; 18917 18918 /* 18919 * TA_TC_ADDR_MODES enum 18920 */ 18921 18922 typedef enum TA_TC_ADDR_MODES { 18923 TA_TC_ADDR_MODE_DEFAULT = 0x00000000, 18924 TA_TC_ADDR_MODE_COMP0 = 0x00000001, 18925 TA_TC_ADDR_MODE_COMP1 = 0x00000002, 18926 TA_TC_ADDR_MODE_COMP2 = 0x00000003, 18927 TA_TC_ADDR_MODE_COMP3 = 0x00000004, 18928 TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, 18929 TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, 18930 } TA_TC_ADDR_MODES; 18931 18932 /* 18933 * TA_TC_REQ_MODES enum 18934 */ 18935 18936 typedef enum TA_TC_REQ_MODES { 18937 TA_TC_REQ_MODE_BORDER = 0x00000000, 18938 TA_TC_REQ_MODE_TEX2 = 0x00000001, 18939 TA_TC_REQ_MODE_TEX1 = 0x00000002, 18940 TA_TC_REQ_MODE_TEX0 = 0x00000003, 18941 TA_TC_REQ_MODE_NORMAL = 0x00000004, 18942 TA_TC_REQ_MODE_DWORD = 0x00000005, 18943 TA_TC_REQ_MODE_BYTE = 0x00000006, 18944 TA_TC_REQ_MODE_BYTE_NV = 0x00000007, 18945 } TA_TC_REQ_MODES; 18946 18947 /* 18948 * TCP_CACHE_POLICIES enum 18949 */ 18950 18951 typedef enum TCP_CACHE_POLICIES { 18952 TCP_CACHE_POLICY_MISS_LRU = 0x00000000, 18953 TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, 18954 TCP_CACHE_POLICY_HIT_LRU = 0x00000002, 18955 TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, 18956 } TCP_CACHE_POLICIES; 18957 18958 /* 18959 * TCP_CACHE_STORE_POLICIES enum 18960 */ 18961 18962 typedef enum TCP_CACHE_STORE_POLICIES { 18963 TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, 18964 TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, 18965 } TCP_CACHE_STORE_POLICIES; 18966 18967 /* 18968 * TCP_COMPRESSION_BYPASS enum 18969 */ 18970 18971 typedef enum TCP_COMPRESSION_BYPASS { 18972 TCP_COMPRESSION_BYPASS_DIS = 0x00000000, 18973 TCP_COMPRESSION_BYPASS_EN = 0x00000001, 18974 } TCP_COMPRESSION_BYPASS; 18975 18976 /* 18977 * TCP_COMPRESSION_OVERRIDE enum 18978 */ 18979 18980 typedef enum TCP_COMPRESSION_OVERRIDE { 18981 TCP_COMPRESSION_OVERRIDE_DIS = 0x00000000, 18982 TCP_COMPRESSION_OVERRIDE_EN = 0x00000001, 18983 } TCP_COMPRESSION_OVERRIDE; 18984 18985 /* 18986 * TCP_OPCODE_TYPE enum 18987 */ 18988 18989 typedef enum TCP_OPCODE_TYPE { 18990 TCP_OPCODE_READ = 0x00000000, 18991 TCP_OPCODE_WRITE = 0x00000001, 18992 TCP_OPCODE_ATOMIC = 0x00000002, 18993 TCP_OPCODE_INV = 0x00000003, 18994 TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004, 18995 TCP_OPCODE_SAMPLER = 0x00000005, 18996 TCP_OPCODE_LOAD = 0x00000006, 18997 TCP_OPCODE_GATHERH = 0x00000007, 18998 } TCP_OPCODE_TYPE; 18999 19000 /* 19001 * TCP_PERFCOUNT_SELECT enum 19002 */ 19003 19004 typedef enum TCP_PERFCOUNT_SELECT { 19005 TCP_PERF_SEL_GATE_EN1 = 0x00000000, 19006 TCP_PERF_SEL_GATE_EN2 = 0x00000001, 19007 TCP_PERF_SEL_TA_REQ = 0x00000002, 19008 TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000003, 19009 TCP_PERF_SEL_TA_REQ_READ = 0x00000004, 19010 TCP_PERF_SEL_TA_REQ_WRITE = 0x00000005, 19011 TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x00000006, 19012 TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x00000007, 19013 TCP_PERF_SEL_TA_REQ_GL0_INV = 0x00000008, 19014 TCP_PERF_SEL_REQ = 0x00000009, 19015 TCP_PERF_SEL_REQ_READ = 0x0000000a, 19016 TCP_PERF_SEL_REQ_READ_HIT_LRU = 0x0000000c, 19017 TCP_PERF_SEL_REQ_READ_MISS_EVICT = 0x0000000d, 19018 TCP_PERF_SEL_REQ_WRITE = 0x0000000e, 19019 TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 0x0000000f, 19020 TCP_PERF_SEL_REQ_NON_READ = 0x00000010, 19021 TCP_PERF_SEL_REQ_MISS = 0x00000011, 19022 TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 0x00000012, 19023 TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 0x00000013, 19024 TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 0x00000014, 19025 TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 0x00000015, 19026 TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 0x00000016, 19027 TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 0x00000017, 19028 TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 0x00000018, 19029 TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 0x00000019, 19030 TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 0x0000001a, 19031 TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 0x0000001b, 19032 TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 0x0000001c, 19033 TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 0x0000001d, 19034 TCP_PERF_SEL_GL1_REQ_READ = 0x0000001e, 19035 TCP_PERF_SEL_GL1_REQ_READ_128B = 0x0000001f, 19036 TCP_PERF_SEL_GL1_REQ_READ_64B = 0x00000020, 19037 TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000021, 19038 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000022, 19039 TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000023, 19040 TCP_PERF_SEL_GL1_READ_LATENCY = 0x00000024, 19041 TCP_PERF_SEL_GL1_WRITE_LATENCY = 0x00000025, 19042 TCP_PERF_SEL_TCP_LATENCY = 0x00000026, 19043 TCP_PERF_SEL_TCP_TA_REQ_STALL = 0x00000027, 19044 TCP_PERF_SEL_TA_TCP_REQ_STARVE = 0x00000028, 19045 TCP_PERF_SEL_DATA_FIFO_STALL = 0x00000029, 19046 TCP_PERF_SEL_LOD_STALL = 0x0000002a, 19047 TCP_PERF_SEL_POWER_STALL = 0x0000002b, 19048 TCP_PERF_SEL_ALLOC_STALL = 0x0000002c, 19049 TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 0x0000002e, 19050 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 0x0000002f, 19051 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 0x00000030, 19052 TCP_PERF_SEL_LFIFO_STALL = 0x00000031, 19053 TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 0x00000032, 19054 TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 0x00000033, 19055 TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 0x00000034, 19056 TCP_PERF_SEL_GL1_GRANT_READ_STALL = 0x00000035, 19057 TCP_PERF_SEL_GL1_PENDING_STALL = 0x00000036, 19058 TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 0x00000037, 19059 TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 0x00000038, 19060 TCP_PERF_SEL_READ_DATACONFLICT_STALL = 0x00000039, 19061 TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 0x0000003a, 19062 TCP_PERF_SEL_TD_TCP_STALL = 0x0000003b, 19063 TCP_PERF_SEL_TA_REQ_BUFFERNOP = 0x0000003c, 19064 TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE = 0x0000003d, 19065 TCP_PERF_SEL_TAGFAKE_EOW = 0x0000003e, 19066 TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID = 0x0000003f, 19067 TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0 = 0x00000040, 19068 TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2 = 0x00000041, 19069 TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4 = 0x00000042, 19070 TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8 = 0x00000043, 19071 TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16 = 0x00000044, 19072 TCP_PERF_SEL_BURST_BIN_READHIT_0 = 0x00000046, 19073 TCP_PERF_SEL_BURST_BIN_READHIT_1 = 0x00000047, 19074 TCP_PERF_SEL_BURST_BIN_READHIT_2to4 = 0x00000048, 19075 TCP_PERF_SEL_BURST_BIN_READHIT_5to8 = 0x00000049, 19076 TCP_PERF_SEL_BURST_BIN_READHIT_9to16 = 0x0000004a, 19077 TCP_PERF_SEL_BURST_BIN_READHIT_gt16 = 0x0000004b, 19078 TCP_PERF_SEL_TA_TC_REQ_EN_SUM = 0x0000004c, 19079 TCP_PERF_SEL_GL1_REQ_LU = 0x0000004d, 19080 TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE = 0x0000004e, 19081 } TCP_PERFCOUNT_SELECT; 19082 19083 /* 19084 * TCP_WATCH_MODES enum 19085 */ 19086 19087 typedef enum TCP_WATCH_MODES { 19088 TCP_WATCH_MODE_READ = 0x00000000, 19089 TCP_WATCH_MODE_NONREAD = 0x00000001, 19090 TCP_WATCH_MODE_ATOMIC = 0x00000002, 19091 TCP_WATCH_MODE_ALL = 0x00000003, 19092 } TCP_WATCH_MODES; 19093 19094 /* 19095 * TCP_WRITE_COMPRESSION_DISABLE enum 19096 */ 19097 19098 typedef enum TCP_WRITE_COMPRESSION_DISABLE { 19099 TCP_WRITE_COMPRESSION_DISABLE_DIS = 0x00000000, 19100 TCP_WRITE_COMPRESSION_DISABLE_EN = 0x00000001, 19101 } TCP_WRITE_COMPRESSION_DISABLE; 19102 19103 /******************************************************* 19104 * TD Enums 19105 *******************************************************/ 19106 19107 /* 19108 * TD_PERFCOUNT_SEL enum 19109 */ 19110 19111 typedef enum TD_PERFCOUNT_SEL { 19112 TD_PERF_SEL_none = 0x00000000, 19113 TD_PERF_SEL_td_busy = 0x00000001, 19114 TD_PERF_SEL_input_busy = 0x00000002, 19115 TD_PERF_SEL_sampler_lerp_busy = 0x00000003, 19116 TD_PERF_SEL_sampler_out_busy = 0x00000004, 19117 TD_PERF_SEL_nofilter_busy = 0x00000005, 19118 TD_PERF_SEL_sampler_core_sclk_en = 0x00000007, 19119 TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008, 19120 TD_PERF_SEL_sampler_bilerp_sclk_en = 0x00000009, 19121 TD_PERF_SEL_sampler_bypass_sclk_en = 0x0000000a, 19122 TD_PERF_SEL_sampler_minmax_sclk_en = 0x0000000b, 19123 TD_PERF_SEL_sampler_accum_sclk_en = 0x0000000c, 19124 TD_PERF_SEL_sampler_format_flt_sclk_en = 0x0000000d, 19125 TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e, 19126 TD_PERF_SEL_sampler_out_sclk_en = 0x0000000f, 19127 TD_PERF_SEL_nofilter_sclk_en = 0x00000010, 19128 TD_PERF_SEL_nofilter_d32_sclk_en = 0x00000011, 19129 TD_PERF_SEL_nofilter_d16_sclk_en = 0x00000012, 19130 TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a, 19131 TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b, 19132 TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c, 19133 TD_PERF_SEL_core_state_ram_max_cnt = 0x00000020, 19134 TD_PERF_SEL_core_state_rams_read = 0x00000021, 19135 TD_PERF_SEL_weight_data_rams_read = 0x00000022, 19136 TD_PERF_SEL_reference_data_rams_read = 0x00000023, 19137 TD_PERF_SEL_tc_td_ram_fifo_full = 0x00000024, 19138 TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 0x00000025, 19139 TD_PERF_SEL_tc_td_data_fifo_full = 0x00000026, 19140 TD_PERF_SEL_input_state_fifo_full = 0x00000027, 19141 TD_PERF_SEL_ta_data_stall = 0x00000028, 19142 TD_PERF_SEL_tc_data_stall = 0x00000029, 19143 TD_PERF_SEL_tc_ram_stall = 0x0000002a, 19144 TD_PERF_SEL_lds_stall = 0x0000002b, 19145 TD_PERF_SEL_sampler_pkr_full = 0x0000002c, 19146 TD_PERF_SEL_sampler_pkr_full_due_to_arb = 0x0000002d, 19147 TD_PERF_SEL_nofilter_pkr_full = 0x0000002e, 19148 TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f, 19149 TD_PERF_SEL_gather4_instr = 0x00000032, 19150 TD_PERF_SEL_gather4h_instr = 0x00000033, 19151 TD_PERF_SEL_getlod_instr = 0x00000034, 19152 TD_PERF_SEL_sample_instr = 0x00000036, 19153 TD_PERF_SEL_sample_c_instr = 0x00000037, 19154 TD_PERF_SEL_load_instr = 0x00000038, 19155 TD_PERF_SEL_ps_load_instr = 0x00000039, 19156 TD_PERF_SEL_write_ack_instr = 0x0000003a, 19157 TD_PERF_SEL_d16_en_instr = 0x0000003b, 19158 TD_PERF_SEL_bypassLerp_instr = 0x0000003c, 19159 TD_PERF_SEL_min_max_filter_instr = 0x0000003d, 19160 TD_PERF_SEL_one_comp_return_instr = 0x0000003e, 19161 TD_PERF_SEL_two_comp_return_instr = 0x0000003f, 19162 TD_PERF_SEL_three_comp_return_instr = 0x00000040, 19163 TD_PERF_SEL_four_comp_return_instr = 0x00000041, 19164 TD_PERF_SEL_user_defined_border = 0x00000042, 19165 TD_PERF_SEL_white_border = 0x00000043, 19166 TD_PERF_SEL_opaque_black_border = 0x00000044, 19167 TD_PERF_SEL_lod_warn_from_ta = 0x00000045, 19168 TD_PERF_SEL_instruction_dest_is_lds = 0x00000046, 19169 TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047, 19170 TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048, 19171 TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049, 19172 TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a, 19173 TD_PERF_SEL_out_of_order_instr = 0x0000004b, 19174 TD_PERF_SEL_total_num_instr = 0x0000004c, 19175 TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d, 19176 TD_PERF_SEL_total_num_sampler_instr = 0x0000004e, 19177 TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f, 19178 TD_PERF_SEL_total_num_nofilter_instr = 0x00000050, 19179 TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051, 19180 TD_PERF_SEL_mixmode_instr = 0x00000054, 19181 TD_PERF_SEL_mixmode_resource = 0x00000055, 19182 TD_PERF_SEL_status_packet = 0x00000056, 19183 TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059, 19184 TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a, 19185 TD_PERF_SEL_done_scoreboard_not_empty = 0x0000005b, 19186 TD_PERF_SEL_done_scoreboard_is_full = 0x0000005c, 19187 TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d, 19188 TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e, 19189 TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f, 19190 TD_PERF_SEL_nofilter_insert_extra_comps = 0x00000060, 19191 TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061, 19192 TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062, 19193 TD_PERF_SEL_msaa_load_instr = 0x00000063, 19194 TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064, 19195 TD_PERF_SEL_resmap_instr = 0x00000066, 19196 TD_PERF_SEL_prt_ack_instr = 0x00000067, 19197 TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068, 19198 TD_PERF_SEL_resmap_with_aniso_filtering = 0x00000069, 19199 TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a, 19200 TD_PERF_SEL_resmap_with_cubemap_corner = 0x0000006b, 19201 TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083, 19202 TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084, 19203 TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085, 19204 TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086, 19205 TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087, 19206 TD_PERF_SEL_burst_bin_sampler_1 = 0x00000088, 19207 TD_PERF_SEL_burst_bin_sampler_2to8 = 0x00000089, 19208 TD_PERF_SEL_burst_bin_sampler_9to16 = 0x0000008a, 19209 TD_PERF_SEL_burst_bin_sampler_gt16 = 0x0000008b, 19210 TD_PERF_SEL_burst_bin_gather_1 = 0x0000008c, 19211 TD_PERF_SEL_burst_bin_gather_2to8 = 0x0000008d, 19212 TD_PERF_SEL_burst_bin_gather_9to16 = 0x0000008e, 19213 TD_PERF_SEL_burst_bin_gather_gt16 = 0x0000008f, 19214 TD_PERF_SEL_burst_bin_nofilter_1 = 0x00000090, 19215 TD_PERF_SEL_burst_bin_nofilter_2to4 = 0x00000091, 19216 TD_PERF_SEL_burst_bin_nofilter_5to7 = 0x00000092, 19217 TD_PERF_SEL_burst_bin_nofilter_8to16 = 0x00000093, 19218 TD_PERF_SEL_burst_bin_nofilter_gt16 = 0x00000094, 19219 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa, 19220 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab, 19221 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac, 19222 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad, 19223 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae, 19224 TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af, 19225 TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 0x000000b0, 19226 TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 0x000000b1, 19227 TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 0x000000b2, 19228 TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 0x000000b3, 19229 TD_PERF_SEL_preempting_nofilter_max_cnt = 0x000000b4, 19230 TD_PERF_SEL_sampler_lerp0_active = 0x000000b5, 19231 TD_PERF_SEL_sampler_lerp1_active = 0x000000b6, 19232 TD_PERF_SEL_sampler_lerp2_active = 0x000000b7, 19233 TD_PERF_SEL_sampler_lerp3_active = 0x000000b8, 19234 TD_PERF_SEL_sampler_lerp4_active = 0x000000b9, 19235 TD_PERF_SEL_sampler_lerp5_active = 0x000000ba, 19236 TD_PERF_SEL_sampler_lerp6_active = 0x000000bb, 19237 TD_PERF_SEL_sampler_lerp7_active = 0x000000bc, 19238 TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000bd, 19239 TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000be, 19240 TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bf, 19241 TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000c0, 19242 TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000c1, 19243 TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000c2, 19244 TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000c3, 19245 TD_PERF_SEL_store_preempts_a_load = 0x000000c8, 19246 TD_PERF_SEL_sample_2x_instr = 0x000000c9, 19247 TD_PERF_SEL_gather4_2x_instr = 0x000000ca, 19248 TD_PERF_SEL_gather4h_2x_instr = 0x000000cb, 19249 TD_PERF_SEL_getlod_2x_instr = 0x000000cc, 19250 TD_PERF_SEL_resmap_2x_instr = 0x000000cd, 19251 TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad = 0x000000ce, 19252 TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit = 0x000000cf, 19253 TD_PERF_SEL_tri_proc_node_override_slot0 = 0x000000d0, 19254 TD_PERF_SEL_tri_run_intersect_ahs_slot0 = 0x000000d1, 19255 TD_PERF_SEL_tri_run_ahs_slot0 = 0x000000d2, 19256 TD_PERF_SEL_tri_proc_node_override_slot1 = 0x000000e7, 19257 TD_PERF_SEL_tri_run_intersect_ahs_slot1 = 0x000000e8, 19258 TD_PERF_SEL_tri_run_ahs_slot1 = 0x000000e9, 19259 TD_PERF_SEL_instance_mask_culled = 0x000000f1, 19260 TD_PERF_SEL_box_opaque_culled = 0x000000f2, 19261 TD_PERF_SEL_box_non_opaque_culled = 0x000000f3, 19262 TD_PERF_SEL_box_with_triangle_children_only_culled = 0x000000f4, 19263 TD_PERF_SEL_box_with_procedural_children_only_culled = 0x000000f5, 19264 TD_PERF_SEL_triangle_opaque_culled = 0x000000f6, 19265 TD_PERF_SEL_triangle_non_opaque_culled = 0x000000f7, 19266 TD_PERF_SEL_triangle_front_facing_culled = 0x000000f8, 19267 TD_PERF_SEL_triangle_back_facing_culled = 0x000000f9, 19268 } TD_PERFCOUNT_SEL; 19269 19270 /* 19271 * GL2A_PERF_SEL enum 19272 */ 19273 19274 typedef enum GL2A_PERF_SEL { 19275 GL2A_PERF_SEL_NONE = 0x00000000, 19276 GL2A_PERF_SEL_CYCLE = 0x00000001, 19277 GL2A_PERF_SEL_BUSY = 0x00000002, 19278 GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003, 19279 GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004, 19280 GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005, 19281 GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006, 19282 GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007, 19283 GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008, 19284 GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009, 19285 GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a, 19286 GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013, 19287 GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014, 19288 GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015, 19289 GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016, 19290 GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017, 19291 GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018, 19292 GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019, 19293 GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a, 19294 GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b, 19295 GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c, 19296 GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d, 19297 GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e, 19298 GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f, 19299 GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020, 19300 GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021, 19301 GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022, 19302 GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023, 19303 GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024, 19304 GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025, 19305 GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026, 19306 GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027, 19307 GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028, 19308 GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029, 19309 GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a, 19310 GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b, 19311 GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c, 19312 GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d, 19313 GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e, 19314 GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f, 19315 GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030, 19316 GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031, 19317 GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032, 19318 GL2A_PERF_SEL_RTN_CLIENT8 = 0x00000033, 19319 GL2A_PERF_SEL_RTN_CLIENT9 = 0x00000034, 19320 GL2A_PERF_SEL_RTN_CLIENT10 = 0x00000035, 19321 GL2A_PERF_SEL_RTN_CLIENT11 = 0x00000036, 19322 GL2A_PERF_SEL_RTN_CLIENT12 = 0x00000037, 19323 GL2A_PERF_SEL_RTN_CLIENT13 = 0x00000038, 19324 GL2A_PERF_SEL_RTN_CLIENT14 = 0x00000039, 19325 GL2A_PERF_SEL_RTN_CLIENT15 = 0x0000003a, 19326 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x0000003b, 19327 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x0000003c, 19328 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x0000003d, 19329 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x0000003e, 19330 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x0000003f, 19331 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000040, 19332 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000041, 19333 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x00000042, 19334 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 0x00000043, 19335 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 0x00000044, 19336 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045, 19337 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046, 19338 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047, 19339 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048, 19340 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049, 19341 GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a, 19342 GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 0x0000004b, 19343 GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 0x0000004c, 19344 GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 0x0000004d, 19345 GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 0x0000004e, 19346 GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 0x0000004f, 19347 GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 0x00000050, 19348 GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 0x00000051, 19349 GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 0x00000052, 19350 GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 0x00000053, 19351 GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 0x00000054, 19352 GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 0x00000055, 19353 GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 0x00000056, 19354 GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 0x00000057, 19355 GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 0x00000058, 19356 GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 0x00000059, 19357 GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 0x0000005a, 19358 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 0x0000005b, 19359 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 0x0000005c, 19360 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 0x0000005d, 19361 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 0x0000005e, 19362 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 0x0000005f, 19363 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 0x00000060, 19364 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 0x00000061, 19365 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 0x00000062, 19366 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 0x00000063, 19367 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 0x00000064, 19368 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 0x00000065, 19369 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 0x00000067, 19370 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 0x00000068, 19371 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 0x00000069, 19372 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 0x0000006a, 19373 GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 0x0000006b, 19374 } GL2A_PERF_SEL; 19375 19376 /* 19377 * GL2C_PERF_SEL enum 19378 */ 19379 19380 typedef enum GL2C_PERF_SEL { 19381 GL2C_PERF_SEL_NONE = 0x00000000, 19382 GL2C_PERF_SEL_CYCLE = 0x00000001, 19383 GL2C_PERF_SEL_BUSY = 0x00000002, 19384 GL2C_PERF_SEL_REQ = 0x00000003, 19385 GL2C_PERF_SEL_VOL_REQ = 0x00000004, 19386 GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005, 19387 GL2C_PERF_SEL_READ = 0x00000006, 19388 GL2C_PERF_SEL_WRITE = 0x00000007, 19389 GL2C_PERF_SEL_ATOMIC = 0x00000008, 19390 GL2C_PERF_SEL_NOP_ACK = 0x00000009, 19391 GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a, 19392 GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000b, 19393 GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000c, 19394 GL2C_PERF_SEL_CLIENT0_REQ = 0x0000000d, 19395 GL2C_PERF_SEL_CLIENT1_REQ = 0x0000000e, 19396 GL2C_PERF_SEL_CLIENT2_REQ = 0x0000000f, 19397 GL2C_PERF_SEL_CLIENT3_REQ = 0x00000010, 19398 GL2C_PERF_SEL_CLIENT4_REQ = 0x00000011, 19399 GL2C_PERF_SEL_CLIENT5_REQ = 0x00000012, 19400 GL2C_PERF_SEL_CLIENT6_REQ = 0x00000013, 19401 GL2C_PERF_SEL_CLIENT7_REQ = 0x00000014, 19402 GL2C_PERF_SEL_CLIENT8_REQ = 0x00000015, 19403 GL2C_PERF_SEL_CLIENT9_REQ = 0x00000016, 19404 GL2C_PERF_SEL_CLIENT10_REQ = 0x00000017, 19405 GL2C_PERF_SEL_CLIENT11_REQ = 0x00000018, 19406 GL2C_PERF_SEL_CLIENT12_REQ = 0x00000019, 19407 GL2C_PERF_SEL_CLIENT13_REQ = 0x0000001a, 19408 GL2C_PERF_SEL_CLIENT14_REQ = 0x0000001b, 19409 GL2C_PERF_SEL_CLIENT15_REQ = 0x0000001c, 19410 GL2C_PERF_SEL_C_RW_S_REQ = 0x0000001d, 19411 GL2C_PERF_SEL_C_RW_US_REQ = 0x0000001e, 19412 GL2C_PERF_SEL_C_RO_S_REQ = 0x0000001f, 19413 GL2C_PERF_SEL_C_RO_US_REQ = 0x00000020, 19414 GL2C_PERF_SEL_UC_REQ = 0x00000021, 19415 GL2C_PERF_SEL_LRU_REQ = 0x00000022, 19416 GL2C_PERF_SEL_STREAM_REQ = 0x00000023, 19417 GL2C_PERF_SEL_BYPASS_REQ = 0x00000024, 19418 GL2C_PERF_SEL_NOA_REQ = 0x00000025, 19419 GL2C_PERF_SEL_SHARED_REQ = 0x00000026, 19420 GL2C_PERF_SEL_HIT = 0x00000027, 19421 GL2C_PERF_SEL_MISS = 0x00000028, 19422 GL2C_PERF_SEL_FULL_HIT = 0x00000029, 19423 GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x0000002a, 19424 GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x0000002b, 19425 GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x0000002c, 19426 GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x0000002d, 19427 GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x0000002e, 19428 GL2C_PERF_SEL_UNCACHED_WRITE = 0x0000002f, 19429 GL2C_PERF_SEL_WRITEBACK = 0x00000030, 19430 GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x00000031, 19431 GL2C_PERF_SEL_EVICT = 0x00000032, 19432 GL2C_PERF_SEL_NORMAL_EVICT = 0x00000033, 19433 GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000034, 19434 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000035, 19435 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x00000036, 19436 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x00000037, 19437 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x00000038, 19438 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x00000039, 19439 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x0000003a, 19440 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x0000003b, 19441 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x0000003c, 19442 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 0x0000003d, 19443 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 0x0000003e, 19444 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 0x0000003f, 19445 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 0x00000040, 19446 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 0x00000041, 19447 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 0x00000042, 19448 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 0x00000043, 19449 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 0x00000044, 19450 GL2C_PERF_SEL_READ_32_REQ = 0x00000045, 19451 GL2C_PERF_SEL_READ_64_REQ = 0x00000046, 19452 GL2C_PERF_SEL_READ_128_REQ = 0x00000047, 19453 GL2C_PERF_SEL_WRITE_32_REQ = 0x00000048, 19454 GL2C_PERF_SEL_WRITE_64_REQ = 0x00000049, 19455 GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x0000004a, 19456 GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x0000004b, 19457 GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x0000004c, 19458 GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x0000004d, 19459 GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x0000004e, 19460 GL2C_PERF_SEL_MC_WRREQ = 0x0000004f, 19461 GL2C_PERF_SEL_EA_WRREQ_SNOOP = 0x00000050, 19462 GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000051, 19463 GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000052, 19464 GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000053, 19465 GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000054, 19466 GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x00000055, 19467 GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x00000056, 19468 GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000057, 19469 GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x00000058, 19470 GL2C_PERF_SEL_EA_ATOMIC = 0x00000059, 19471 GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x0000005a, 19472 GL2C_PERF_SEL_MC_RDREQ = 0x0000005b, 19473 GL2C_PERF_SEL_EA_RDREQ_SNOOP = 0x0000005c, 19474 GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x0000005d, 19475 GL2C_PERF_SEL_EA_RDREQ_32B = 0x0000005e, 19476 GL2C_PERF_SEL_EA_RDREQ_64B = 0x0000005f, 19477 GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000060, 19478 GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000061, 19479 GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000062, 19480 GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000063, 19481 GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x00000064, 19482 GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x00000065, 19483 GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x00000066, 19484 GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x00000067, 19485 GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x00000068, 19486 GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x00000069, 19487 GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x0000006a, 19488 GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x0000006b, 19489 GL2C_PERF_SEL_ONION_READ = 0x0000006c, 19490 GL2C_PERF_SEL_ONION_WRITE = 0x0000006d, 19491 GL2C_PERF_SEL_IO_READ = 0x0000006e, 19492 GL2C_PERF_SEL_IO_WRITE = 0x0000006f, 19493 GL2C_PERF_SEL_GARLIC_READ = 0x00000070, 19494 GL2C_PERF_SEL_GARLIC_WRITE = 0x00000071, 19495 GL2C_PERF_SEL_EA_OUTSTANDING = 0x00000072, 19496 GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000073, 19497 GL2C_PERF_SEL_SRC_FIFO_FULL = 0x00000074, 19498 GL2C_PERF_SEL_TAG_STALL = 0x00000075, 19499 GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x00000076, 19500 GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x00000077, 19501 GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x00000078, 19502 GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x00000079, 19503 GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x0000007a, 19504 GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x0000007b, 19505 GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x0000007c, 19506 GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x0000007d, 19507 GL2C_PERF_SEL_BUBBLE = 0x0000007e, 19508 GL2C_PERF_SEL_IB_REQ = 0x0000007f, 19509 GL2C_PERF_SEL_IB_STALL = 0x00000080, 19510 GL2C_PERF_SEL_IB_TAG_STALL = 0x00000081, 19511 GL2C_PERF_SEL_RETURN_ACK = 0x00000082, 19512 GL2C_PERF_SEL_RETURN_DATA = 0x00000083, 19513 GL2C_PERF_SEL_EA_RDRET_NACK = 0x00000084, 19514 GL2C_PERF_SEL_EA_WRRET_NACK = 0x00000085, 19515 GL2C_PERF_SEL_GL2A_LEVEL = 0x00000086, 19516 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000087, 19517 GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000088, 19518 GL2C_PERF_SEL_GCR_INV = 0x00000089, 19519 GL2C_PERF_SEL_GCR_WB = 0x0000008a, 19520 GL2C_PERF_SEL_GCR_DISCARD = 0x0000008b, 19521 GL2C_PERF_SEL_GCR_RANGE = 0x0000008c, 19522 GL2C_PERF_SEL_GCR_ALL = 0x0000008d, 19523 GL2C_PERF_SEL_GCR_VOL = 0x0000008e, 19524 GL2C_PERF_SEL_GCR_UNSHARED = 0x0000008f, 19525 GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x00000090, 19526 GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x00000091, 19527 GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x00000092, 19528 GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x00000093, 19529 GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x00000094, 19530 GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x00000095, 19531 GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x00000096, 19532 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x00000097, 19533 GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x00000098, 19534 GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x00000099, 19535 GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x0000009a, 19536 GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x0000009b, 19537 GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x0000009c, 19538 GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x0000009d, 19539 GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x0000009e, 19540 GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x0000009f, 19541 GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x000000a0, 19542 GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000a1, 19543 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 0x000000a2, 19544 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 0x000000a3, 19545 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 0x000000a4, 19546 GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 0x000000a5, 19547 } GL2C_PERF_SEL; 19548 19549 /* 19550 * SX_BLEND_OPT enum 19551 */ 19552 19553 typedef enum SX_BLEND_OPT { 19554 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, 19555 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, 19556 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, 19557 BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, 19558 BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, 19559 BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, 19560 BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, 19561 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, 19562 } SX_BLEND_OPT; 19563 19564 /* 19565 * SX_DOWNCONVERT_FORMAT enum 19566 */ 19567 19568 typedef enum SX_DOWNCONVERT_FORMAT { 19569 SX_RT_EXPORT_NO_CONVERSION = 0x00000000, 19570 SX_RT_EXPORT_32_R = 0x00000001, 19571 SX_RT_EXPORT_32_A = 0x00000002, 19572 SX_RT_EXPORT_10_11_11 = 0x00000003, 19573 SX_RT_EXPORT_2_10_10_10 = 0x00000004, 19574 SX_RT_EXPORT_8_8_8_8 = 0x00000005, 19575 SX_RT_EXPORT_5_6_5 = 0x00000006, 19576 SX_RT_EXPORT_1_5_5_5 = 0x00000007, 19577 SX_RT_EXPORT_4_4_4_4 = 0x00000008, 19578 SX_RT_EXPORT_16_16_GR = 0x00000009, 19579 SX_RT_EXPORT_16_16_AR = 0x0000000a, 19580 SX_RT_EXPORT_9_9_9_E5 = 0x0000000b, 19581 SX_RT_EXPORT_2_10_10_10_7E3 = 0x0000000c, 19582 SX_RT_EXPORT_2_10_10_10_6E4 = 0x0000000d, 19583 } SX_DOWNCONVERT_FORMAT; 19584 19585 /* 19586 * SX_OPT_COMB_FCN enum 19587 */ 19588 19589 typedef enum SX_OPT_COMB_FCN { 19590 OPT_COMB_NONE = 0x00000000, 19591 OPT_COMB_ADD = 0x00000001, 19592 OPT_COMB_SUBTRACT = 0x00000002, 19593 OPT_COMB_MIN = 0x00000003, 19594 OPT_COMB_MAX = 0x00000004, 19595 OPT_COMB_REVSUBTRACT = 0x00000005, 19596 OPT_COMB_BLEND_DISABLED = 0x00000006, 19597 OPT_COMB_SAFE_ADD = 0x00000007, 19598 } SX_OPT_COMB_FCN; 19599 19600 /* 19601 * SX_PERFCOUNTER_VALS enum 19602 */ 19603 19604 typedef enum SX_PERFCOUNTER_VALS { 19605 SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, 19606 SX_PERF_SEL_PA_REQ = 0x00000001, 19607 SX_PERF_SEL_PA_POS = 0x00000002, 19608 SX_PERF_SEL_CLOCK = 0x00000003, 19609 SX_PERF_SEL_GATE_EN1 = 0x00000004, 19610 SX_PERF_SEL_GATE_EN2 = 0x00000005, 19611 SX_PERF_SEL_GATE_EN3 = 0x00000006, 19612 SX_PERF_SEL_GATE_EN4 = 0x00000007, 19613 SX_PERF_SEL_SH_POS_STARVE = 0x00000008, 19614 SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, 19615 SX_PERF_SEL_SH_POS_STALL = 0x0000000a, 19616 SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, 19617 SX_PERF_SEL_DB0_PIXELS = 0x0000000c, 19618 SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, 19619 SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, 19620 SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, 19621 SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, 19622 SX_PERF_SEL_DB1_PIXELS = 0x00000011, 19623 SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, 19624 SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, 19625 SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, 19626 SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, 19627 SX_PERF_SEL_DB2_PIXELS = 0x00000016, 19628 SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, 19629 SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, 19630 SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, 19631 SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, 19632 SX_PERF_SEL_DB3_PIXELS = 0x0000001b, 19633 SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, 19634 SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, 19635 SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, 19636 SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, 19637 SX_PERF_SEL_COL_BUSY = 0x00000020, 19638 SX_PERF_SEL_POS_BUSY = 0x00000021, 19639 SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 0x00000022, 19640 SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 0x00000023, 19641 SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 0x00000024, 19642 SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 0x00000025, 19643 SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 0x00000026, 19644 SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 0x00000027, 19645 SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 0x00000028, 19646 SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 0x00000029, 19647 SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 0x0000002a, 19648 SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 0x0000002b, 19649 SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 0x0000002c, 19650 SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 0x0000002d, 19651 SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 0x0000002e, 19652 SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 0x0000002f, 19653 SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 0x00000030, 19654 SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 0x00000031, 19655 SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 0x00000032, 19656 SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 0x00000033, 19657 SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 0x00000034, 19658 SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 0x00000035, 19659 SX_PERF_SEL_PA_REQ_LATENCY = 0x00000036, 19660 SX_PERF_SEL_POS_SCBD_STALL = 0x00000037, 19661 SX_PERF_SEL_CLOCK_DROP_STALL = 0x00000038, 19662 SX_PERF_SEL_GATE_EN5 = 0x00000039, 19663 SX_PERF_SEL_GATE_EN6 = 0x0000003a, 19664 SX_PERF_SEL_DB0_SIZE = 0x0000003b, 19665 SX_PERF_SEL_DB1_SIZE = 0x0000003c, 19666 SX_PERF_SEL_DB2_SIZE = 0x0000003d, 19667 SX_PERF_SEL_DB3_SIZE = 0x0000003e, 19668 SX_PERF_SEL_IDX_STALL_CYCLES = 0x0000003f, 19669 SX_PERF_SEL_IDX_IDLE_CYCLES = 0x00000040, 19670 SX_PERF_SEL_IDX_REQ = 0x00000041, 19671 SX_PERF_SEL_IDX_RET = 0x00000042, 19672 SX_PERF_SEL_IDX_REQ_LATENCY = 0x00000043, 19673 SX_PERF_SEL_IDX_SCBD_STALL = 0x00000044, 19674 SX_PERF_SEL_GATE_EN7 = 0x00000045, 19675 SX_PERF_SEL_GATE_EN8 = 0x00000046, 19676 SX_PERF_SEL_SH_IDX_STARVE = 0x00000047, 19677 SX_PERF_SEL_IDX_BUSY = 0x00000048, 19678 SX_PERF_SEL_PA_POS_BANK_CONF = 0x00000049, 19679 SX_PERF_SEL_DB0_END_OF_WAVE = 0x0000004a, 19680 SX_PERF_SEL_DB0_4X2_DISCARD = 0x0000004b, 19681 SX_PERF_SEL_DB1_END_OF_WAVE = 0x0000004c, 19682 SX_PERF_SEL_DB1_4X2_DISCARD = 0x0000004d, 19683 SX_PERF_SEL_DB2_END_OF_WAVE = 0x0000004e, 19684 SX_PERF_SEL_DB2_4X2_DISCARD = 0x0000004f, 19685 SX_PERF_SEL_DB3_END_OF_WAVE = 0x00000050, 19686 SX_PERF_SEL_DB3_4X2_DISCARD = 0x00000051, 19687 } SX_PERFCOUNTER_VALS; 19688 19689 /* 19690 * CompareFrag enum 19691 */ 19692 19693 typedef enum CompareFrag { 19694 FRAG_NEVER = 0x00000000, 19695 FRAG_LESS = 0x00000001, 19696 FRAG_EQUAL = 0x00000002, 19697 FRAG_LEQUAL = 0x00000003, 19698 FRAG_GREATER = 0x00000004, 19699 FRAG_NOTEQUAL = 0x00000005, 19700 FRAG_GEQUAL = 0x00000006, 19701 FRAG_ALWAYS = 0x00000007, 19702 } CompareFrag; 19703 19704 /* 19705 * ConservativeZExport enum 19706 */ 19707 19708 typedef enum ConservativeZExport { 19709 EXPORT_ANY_Z = 0x00000000, 19710 EXPORT_LESS_THAN_Z = 0x00000001, 19711 EXPORT_GREATER_THAN_Z = 0x00000002, 19712 EXPORT_RESERVED = 0x00000003, 19713 } ConservativeZExport; 19714 19715 /* 19716 * DbMemArbWatermarks enum 19717 */ 19718 19719 typedef enum DbMemArbWatermarks { 19720 TRANSFERRED_64_BYTES = 0x00000000, 19721 TRANSFERRED_128_BYTES = 0x00000001, 19722 TRANSFERRED_256_BYTES = 0x00000002, 19723 TRANSFERRED_512_BYTES = 0x00000003, 19724 TRANSFERRED_1024_BYTES = 0x00000004, 19725 TRANSFERRED_2048_BYTES = 0x00000005, 19726 TRANSFERRED_4096_BYTES = 0x00000006, 19727 TRANSFERRED_8192_BYTES = 0x00000007, 19728 } DbMemArbWatermarks; 19729 19730 /* 19731 * DbPRTFaultBehavior enum 19732 */ 19733 19734 typedef enum DbPRTFaultBehavior { 19735 FAULT_ZERO = 0x00000000, 19736 FAULT_ONE = 0x00000001, 19737 FAULT_FAIL = 0x00000002, 19738 FAULT_PASS = 0x00000003, 19739 } DbPRTFaultBehavior; 19740 19741 /* 19742 * DbPSLControl enum 19743 */ 19744 19745 typedef enum DbPSLControl { 19746 PSLC_AUTO = 0x00000000, 19747 PSLC_ON_HANG_ONLY = 0x00000001, 19748 PSLC_ASAP = 0x00000002, 19749 PSLC_COUNTDOWN = 0x00000003, 19750 } DbPSLControl; 19751 19752 /* 19753 * ForceControl enum 19754 */ 19755 19756 typedef enum ForceControl { 19757 FORCE_OFF = 0x00000000, 19758 FORCE_ENABLE = 0x00000001, 19759 FORCE_DISABLE = 0x00000002, 19760 FORCE_RESERVED = 0x00000003, 19761 } ForceControl; 19762 19763 /* 19764 * GLCompressionMode enum 19765 */ 19766 19767 typedef enum GLCompressionMode { 19768 DB_DEFAULT = 0x00000000, 19769 DB_BYPASS = 0x00000001, 19770 DB_COMP_WR_DISABLE = 0x00000002, 19771 DB_BYPASS_WR_DISABLE = 0x00000003, 19772 } GLCompressionMode; 19773 19774 /* 19775 * OreoMode enum 19776 */ 19777 19778 typedef enum OreoMode { 19779 OMODE_BLEND = 0x00000000, 19780 OMODE_O_THEN_B = 0x00000001, 19781 OMODE_P_THEN_O_THEN_B = 0x00000002, 19782 OMODE_RESERVED_3 = 0x00000003, 19783 } OreoMode; 19784 19785 /* 19786 * PerfCounter_Vals enum 19787 */ 19788 19789 typedef enum PerfCounter_Vals { 19790 DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, 19791 DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, 19792 DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, 19793 DB_PERF_SEL_SC_DB_tile_events = 0x00000003, 19794 DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, 19795 DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, 19796 DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, 19797 DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, 19798 DB_PERF_SEL_hiz_tile_culled = 0x00000008, 19799 DB_PERF_SEL_his_tile_culled = 0x00000009, 19800 DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, 19801 DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, 19802 DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, 19803 DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, 19804 DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, 19805 DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, 19806 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, 19807 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, 19808 DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, 19809 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, 19810 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, 19811 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, 19812 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, 19813 DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, 19814 DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, 19815 DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, 19816 DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, 19817 DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, 19818 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, 19819 DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, 19820 DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, 19821 DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, 19822 DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, 19823 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, 19824 DB_PERF_SEL_DB_CB_export_events = 0x00000022, 19825 DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, 19826 DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, 19827 DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, 19828 DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, 19829 DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, 19830 DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, 19831 DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, 19832 DB_PERF_SEL_DB_CB_export_sends = 0x0000002c, 19833 DB_PERF_SEL_DB_CB_export_busy = 0x0000002d, 19834 DB_PERF_SEL_DB_CB_export_stalls = 0x0000002e, 19835 DB_PERF_SEL_DB_CB_export_quads = 0x0000002f, 19836 DB_PERF_SEL_tile_rd_sends = 0x00000030, 19837 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, 19838 DB_PERF_SEL_quad_rd_sends = 0x00000032, 19839 DB_PERF_SEL_quad_rd_busy = 0x00000033, 19840 DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, 19841 DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, 19842 DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, 19843 DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, 19844 DB_PERF_SEL_quad_rd_panic = 0x00000038, 19845 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, 19846 DB_PERF_SEL_quad_rdret_sends = 0x0000003a, 19847 DB_PERF_SEL_quad_rdret_busy = 0x0000003b, 19848 DB_PERF_SEL_tile_wr_sends = 0x0000003c, 19849 DB_PERF_SEL_tile_wr_acks = 0x0000003d, 19850 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, 19851 DB_PERF_SEL_quad_wr_sends = 0x0000003f, 19852 DB_PERF_SEL_quad_wr_busy = 0x00000040, 19853 DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, 19854 DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, 19855 DB_PERF_SEL_quad_wr_acks = 0x00000043, 19856 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, 19857 DB_PERF_SEL_Tile_Cache_misses = 0x00000045, 19858 DB_PERF_SEL_Tile_Cache_hits = 0x00000046, 19859 DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, 19860 DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, 19861 DB_PERF_SEL_Tile_Cache_starves = 0x00000049, 19862 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, 19863 DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, 19864 DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, 19865 DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, 19866 DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, 19867 DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, 19868 DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, 19869 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, 19870 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, 19871 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, 19872 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, 19873 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, 19874 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, 19875 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, 19876 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, 19877 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, 19878 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, 19879 DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, 19880 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, 19881 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, 19882 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, 19883 DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, 19884 DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, 19885 DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, 19886 DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, 19887 DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, 19888 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, 19889 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, 19890 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, 19891 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, 19892 DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, 19893 DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, 19894 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, 19895 DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, 19896 DB_PERF_SEL_Z_Cache_frees = 0x0000006c, 19897 DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, 19898 DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, 19899 DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, 19900 DB_PERF_SEL_Plane_Cache_starves = 0x00000070, 19901 DB_PERF_SEL_Plane_Cache_frees = 0x00000071, 19902 DB_PERF_SEL_flush_expanded_stencil = 0x00000072, 19903 DB_PERF_SEL_flush_compressed_stencil = 0x00000073, 19904 DB_PERF_SEL_flush_single_stencil = 0x00000074, 19905 DB_PERF_SEL_planes_flushed = 0x00000075, 19906 DB_PERF_SEL_flush_1plane = 0x00000076, 19907 DB_PERF_SEL_flush_2plane = 0x00000077, 19908 DB_PERF_SEL_flush_3plane = 0x00000078, 19909 DB_PERF_SEL_flush_4plane = 0x00000079, 19910 DB_PERF_SEL_flush_5plane = 0x0000007a, 19911 DB_PERF_SEL_flush_6plane = 0x0000007b, 19912 DB_PERF_SEL_flush_7plane = 0x0000007c, 19913 DB_PERF_SEL_flush_8plane = 0x0000007d, 19914 DB_PERF_SEL_flush_9plane = 0x0000007e, 19915 DB_PERF_SEL_flush_10plane = 0x0000007f, 19916 DB_PERF_SEL_flush_11plane = 0x00000080, 19917 DB_PERF_SEL_flush_12plane = 0x00000081, 19918 DB_PERF_SEL_flush_13plane = 0x00000082, 19919 DB_PERF_SEL_flush_14plane = 0x00000083, 19920 DB_PERF_SEL_flush_15plane = 0x00000084, 19921 DB_PERF_SEL_flush_16plane = 0x00000085, 19922 DB_PERF_SEL_flush_expanded_z = 0x00000086, 19923 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, 19924 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, 19925 DB_PERF_SEL_dk_tile_sends = 0x00000089, 19926 DB_PERF_SEL_dk_tile_busy = 0x0000008a, 19927 DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, 19928 DB_PERF_SEL_dk_tile_stalls = 0x0000008c, 19929 DB_PERF_SEL_dk_squad_sends = 0x0000008d, 19930 DB_PERF_SEL_dk_squad_busy = 0x0000008e, 19931 DB_PERF_SEL_dk_squad_stalls = 0x0000008f, 19932 DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, 19933 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, 19934 DB_PERF_SEL_qc_busy = 0x00000092, 19935 DB_PERF_SEL_qc_xfc = 0x00000093, 19936 DB_PERF_SEL_qc_conflicts = 0x00000094, 19937 DB_PERF_SEL_qc_full_stall = 0x00000095, 19938 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, 19939 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, 19940 DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, 19941 DB_PERF_SEL_tl_busy = 0x00000099, 19942 DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, 19943 DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, 19944 DB_PERF_SEL_tl_stencil_stall = 0x0000009c, 19945 DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, 19946 DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, 19947 DB_PERF_SEL_tl_events = 0x0000009f, 19948 DB_PERF_SEL_tl_summarize_squads = 0x000000a0, 19949 DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, 19950 DB_PERF_SEL_tl_expand_squads = 0x000000a2, 19951 DB_PERF_SEL_tl_preZ_squads = 0x000000a3, 19952 DB_PERF_SEL_tl_postZ_squads = 0x000000a4, 19953 DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, 19954 DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, 19955 DB_PERF_SEL_tl_tile_ops = 0x000000a7, 19956 DB_PERF_SEL_tl_in_xfc = 0x000000a8, 19957 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, 19958 DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, 19959 DB_PERF_SEL_tl_out_xfc = 0x000000ab, 19960 DB_PERF_SEL_tl_out_squads = 0x000000ac, 19961 DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, 19962 DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, 19963 DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, 19964 DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, 19965 DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, 19966 DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, 19967 DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, 19968 DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, 19969 DB_PERF_SEL_sc_kick_start = 0x000000b5, 19970 DB_PERF_SEL_sc_kick_end = 0x000000b6, 19971 DB_PERF_SEL_clock_reg_active = 0x000000b7, 19972 DB_PERF_SEL_clock_main_active = 0x000000b8, 19973 DB_PERF_SEL_clock_mem_export_active = 0x000000b9, 19974 DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, 19975 DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, 19976 DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, 19977 DB_PERF_SEL_etr_out_send = 0x000000bd, 19978 DB_PERF_SEL_etr_out_busy = 0x000000be, 19979 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, 19980 DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, 19981 DB_PERF_SEL_esr_ps_vic_busy = 0x000000c2, 19982 DB_PERF_SEL_esr_ps_vic_stall = 0x000000c3, 19983 DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, 19984 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, 19985 DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, 19986 DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, 19987 DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, 19988 DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, 19989 DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, 19990 DB_PERF_SEL_postzl_se_busy = 0x000000cb, 19991 DB_PERF_SEL_postzl_se_stall = 0x000000cc, 19992 DB_PERF_SEL_postzl_partial_launch = 0x000000cd, 19993 DB_PERF_SEL_postzl_full_launch = 0x000000ce, 19994 DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, 19995 DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, 19996 DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, 19997 DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2, 19998 DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, 19999 DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, 20000 DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, 20001 DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, 20002 DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, 20003 DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, 20004 DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, 20005 DB_PERF_SEL_mi_wrreq_stall = 0x000000da, 20006 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, 20007 DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, 20008 DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, 20009 DB_PERF_SEL_prezl_src_in_stall = 0x000000de, 20010 DB_PERF_SEL_prezl_src_in_squads = 0x000000df, 20011 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, 20012 DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, 20013 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, 20014 DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, 20015 DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, 20016 DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, 20017 DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, 20018 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, 20019 DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, 20020 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, 20021 DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, 20022 DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, 20023 DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, 20024 DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, 20025 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, 20026 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, 20027 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, 20028 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, 20029 DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, 20030 DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3, 20031 DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, 20032 DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, 20033 DB_PERF_SEL_flush_compressed = 0x000000f6, 20034 DB_PERF_SEL_flush_plane_le4 = 0x000000f7, 20035 DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, 20036 DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, 20037 DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, 20038 DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, 20039 DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, 20040 DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, 20041 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, 20042 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, 20043 DB_PERF_SEL_di_dt_stall = 0x00000100, 20044 DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102, 20045 DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103, 20046 DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104, 20047 DB_PERF_SEL_DB_CB_export_export_quads = 0x00000105, 20048 DB_PERF_SEL_DB_CB_export_double_format = 0x00000106, 20049 DB_PERF_SEL_DB_CB_export_fast_format = 0x00000107, 20050 DB_PERF_SEL_DB_CB_export_slow_format = 0x00000108, 20051 DB_PERF_SEL_CB_DB_rdreq_sends = 0x00000109, 20052 DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010a, 20053 DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010b, 20054 DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010c, 20055 DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010d, 20056 DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010e, 20057 DB_PERF_SEL_DB_CB_wrret_ack = 0x0000010f, 20058 DB_PERF_SEL_DB_CB_wrret_nack = 0x00000110, 20059 DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111, 20060 DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112, 20061 DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113, 20062 DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114, 20063 DB_PERF_SEL_unmapped_z_tile_culled = 0x00000115, 20064 DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116, 20065 DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117, 20066 DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS = 0x00000118, 20067 DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event = 0x00000119, 20068 DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix = 0x0000011a, 20069 DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix = 0x0000011b, 20070 DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix = 0x0000011c, 20071 DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix = 0x0000011d, 20072 DB_PERF_SEL_DB_CB_export_num_pixels_need_blending = 0x0000011e, 20073 DB_PERF_SEL_DB_CB_context_dones = 0x0000011f, 20074 DB_PERF_SEL_DB_CB_eop_dones = 0x00000120, 20075 DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121, 20076 DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122, 20077 DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123, 20078 DB_PERF_SEL_SC_DB_tile_backface = 0x00000124, 20079 DB_PERF_SEL_SC_DB_quad_quads = 0x00000125, 20080 DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126, 20081 DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127, 20082 DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128, 20083 DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129, 20084 DB_PERF_SEL_DB_SC_quad_double_quad = 0x0000012a, 20085 DB_PERF_SEL_SX_DB_quad_export_quads = 0x0000012b, 20086 DB_PERF_SEL_SX_DB_quad_double_format = 0x0000012c, 20087 DB_PERF_SEL_SX_DB_quad_fast_format = 0x0000012d, 20088 DB_PERF_SEL_SX_DB_quad_slow_format = 0x0000012e, 20089 DB_PERF_SEL_quad_rd_sends_unc = 0x0000012f, 20090 DB_PERF_SEL_quad_rd_mi_stall_unc = 0x00000130, 20091 DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 0x00000131, 20092 DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 0x00000132, 20093 DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 0x00000133, 20094 DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 0x00000134, 20095 DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135, 20096 DB_PERF_SEL_noz_waiting_for_postz_done = 0x00000136, 20097 DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1 = 0x00000137, 20098 DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1 = 0x00000138, 20099 DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2 = 0x00000139, 20100 DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2 = 0x0000013a, 20101 DB_PERF_SEL_RMI_rd_tile_32byte_req = 0x0000013b, 20102 DB_PERF_SEL_RMI_rd_z_32byte_req = 0x0000013c, 20103 DB_PERF_SEL_RMI_rd_s_32byte_req = 0x0000013d, 20104 DB_PERF_SEL_RMI_wr_tile_32byte_req = 0x0000013e, 20105 DB_PERF_SEL_RMI_wr_z_32byte_req = 0x0000013f, 20106 DB_PERF_SEL_RMI_wr_s_32byte_req = 0x00000140, 20107 DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 0x00000141, 20108 DB_PERF_SEL_RMI_rd_tile_32byte_ret = 0x00000142, 20109 DB_PERF_SEL_RMI_rd_z_32byte_ret = 0x00000143, 20110 DB_PERF_SEL_RMI_rd_s_32byte_ret = 0x00000144, 20111 DB_PERF_SEL_RMI_wr_tile_32byte_ack = 0x00000145, 20112 DB_PERF_SEL_RMI_wr_z_32byte_ack = 0x00000146, 20113 DB_PERF_SEL_RMI_wr_s_32byte_ack = 0x00000147, 20114 DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 0x00000148, 20115 DB_PERF_SEL_esr_vic_sqq_busy = 0x00000149, 20116 DB_PERF_SEL_esr_vic_sqq_stall = 0x0000014a, 20117 DB_PERF_SEL_esr_psi_vic_tile_rate = 0x0000014b, 20118 DB_PERF_SEL_esr_vic_footprint_match_2x2 = 0x0000014c, 20119 DB_PERF_SEL_esr_vic_footprint_match_2x1 = 0x0000014d, 20120 DB_PERF_SEL_esr_vic_footprint_match_1x2 = 0x0000014e, 20121 DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f, 20122 DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150, 20123 DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151, 20124 DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152, 20125 DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153, 20126 DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154, 20127 DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155, 20128 DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 0x00000156, 20129 DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 0x00000157, 20130 DB_PERF_SEL_ts_events_pws_enable = 0x00000158, 20131 DB_PERF_SEL_ps_events_pws_enable = 0x00000159, 20132 DB_PERF_SEL_cs_events_pws_enable = 0x0000015a, 20133 DB_PERF_SEL_DB_SC_quad_noz_tiles = 0x0000015b, 20134 DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 0x0000015c, 20135 DB_PERF_SEL_DB_SC_quad_conflicts = 0x0000015d, 20136 DB_PERF_SEL_SC_DB_quad_vrs_1x1 = 0x0000015e, 20137 DB_PERF_SEL_SC_DB_quad_vrs_1x2 = 0x0000015f, 20138 DB_PERF_SEL_SC_DB_quad_vrs_2x1 = 0x00000160, 20139 DB_PERF_SEL_SC_DB_quad_vrs_2x2 = 0x00000161, 20140 DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa = 0x00000162, 20141 DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa = 0x00000163, 20142 DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa = 0x00000164, 20143 DB_PERF_SEL_SC_DB_wave_sends = 0x00000165, 20144 DB_PERF_SEL_SC_DB_wave_busy = 0x00000166, 20145 DB_PERF_SEL_SC_DB_wave_quads = 0x00000167, 20146 DB_PERF_SEL_SC_DB_wave_id_wrapped = 0x00000168, 20147 DB_PERF_SEL_DB_SC_wave_sends = 0x00000169, 20148 DB_PERF_SEL_DB_SC_wave_busy = 0x0000016a, 20149 DB_PERF_SEL_DB_SC_wave_stalls = 0x0000016b, 20150 DB_PERF_SEL_DB_SC_wave_conflict = 0x0000016c, 20151 DB_PERF_SEL_DB_SC_wave_hard_conflict = 0x0000016d, 20152 DB_PERF_SEL_DB_SC_wave_id_wrapped = 0x0000016e, 20153 DB_PERF_SEL_SX_DB_quad_waves = 0x0000016f, 20154 DB_PERF_SEL_pws_stall = 0x00000170, 20155 DB_PERF_SEL_pws_liveness_stall_dtt_tag = 0x00000171, 20156 DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr = 0x00000172, 20157 DB_PERF_SEL_OREO_TT_load = 0x00000173, 20158 DB_PERF_SEL_OREO_TT_read = 0x00000174, 20159 DB_PERF_SEL_OREO_TT_stalls = 0x00000175, 20160 DB_PERF_SEL_OREO_ST_load = 0x00000176, 20161 DB_PERF_SEL_OREO_ST_read = 0x00000177, 20162 DB_PERF_SEL_OREO_ST_stalls = 0x00000178, 20163 DB_PERF_SEL_OREO_WT_load = 0x00000179, 20164 DB_PERF_SEL_OREO_WT_read = 0x0000017a, 20165 DB_PERF_SEL_OREO_SB_misses = 0x0000017b, 20166 DB_PERF_SEL_OREO_SB_hits = 0x0000017c, 20167 DB_PERF_SEL_OREO_SB_evicts = 0x0000017d, 20168 DB_PERF_SEL_OREO_SB_stalls = 0x0000017e, 20169 DB_PERF_SEL_OREO_Events_load = 0x0000017f, 20170 DB_PERF_SEL_OREO_Events_transition = 0x00000180, 20171 DB_PERF_SEL_OREO_Events_non_transition = 0x00000181, 20172 DB_PERF_SEL_OREO_Events_delayed = 0x00000182, 20173 DB_PERF_SEL_OREO_Events_stalls = 0x00000183, 20174 } PerfCounter_Vals; 20175 20176 /* 20177 * PixelPipeCounterId enum 20178 */ 20179 20180 typedef enum PixelPipeCounterId { 20181 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, 20182 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, 20183 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, 20184 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, 20185 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, 20186 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, 20187 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, 20188 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, 20189 } PixelPipeCounterId; 20190 20191 /* 20192 * PixelPipeStride enum 20193 */ 20194 20195 typedef enum PixelPipeStride { 20196 PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, 20197 PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, 20198 PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, 20199 PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, 20200 } PixelPipeStride; 20201 20202 /* 20203 * RingCounterControl enum 20204 */ 20205 20206 typedef enum RingCounterControl { 20207 COUNTER_RING_SPLIT = 0x00000000, 20208 COUNTER_RING_0 = 0x00000001, 20209 COUNTER_RING_1 = 0x00000002, 20210 } RingCounterControl; 20211 20212 /* 20213 * StencilOp enum 20214 */ 20215 20216 typedef enum StencilOp { 20217 STENCIL_KEEP = 0x00000000, 20218 STENCIL_ZERO = 0x00000001, 20219 STENCIL_ONES = 0x00000002, 20220 STENCIL_REPLACE_TEST = 0x00000003, 20221 STENCIL_REPLACE_OP = 0x00000004, 20222 STENCIL_ADD_CLAMP = 0x00000005, 20223 STENCIL_SUB_CLAMP = 0x00000006, 20224 STENCIL_INVERT = 0x00000007, 20225 STENCIL_ADD_WRAP = 0x00000008, 20226 STENCIL_SUB_WRAP = 0x00000009, 20227 STENCIL_AND = 0x0000000a, 20228 STENCIL_OR = 0x0000000b, 20229 STENCIL_XOR = 0x0000000c, 20230 STENCIL_NAND = 0x0000000d, 20231 STENCIL_NOR = 0x0000000e, 20232 STENCIL_XNOR = 0x0000000f, 20233 } StencilOp; 20234 20235 /* 20236 * ZLimitSumm enum 20237 */ 20238 20239 typedef enum ZLimitSumm { 20240 FORCE_SUMM_OFF = 0x00000000, 20241 FORCE_SUMM_MINZ = 0x00000001, 20242 FORCE_SUMM_MAXZ = 0x00000002, 20243 FORCE_SUMM_BOTH = 0x00000003, 20244 } ZLimitSumm; 20245 20246 /* 20247 * ZModeForce enum 20248 */ 20249 20250 typedef enum ZModeForce { 20251 NO_FORCE = 0x00000000, 20252 FORCE_EARLY_Z = 0x00000001, 20253 FORCE_LATE_Z = 0x00000002, 20254 FORCE_RE_Z = 0x00000003, 20255 } ZModeForce; 20256 20257 /* 20258 * ZOrder enum 20259 */ 20260 20261 typedef enum ZOrder { 20262 LATE_Z = 0x00000000, 20263 EARLY_Z_THEN_LATE_Z = 0x00000001, 20264 RE_Z = 0x00000002, 20265 EARLY_Z_THEN_RE_Z = 0x00000003, 20266 } ZOrder; 20267 20268 /* 20269 * ZSamplePosition enum 20270 */ 20271 20272 typedef enum ZSamplePosition { 20273 Z_SAMPLE_CENTER = 0x00000000, 20274 Z_SAMPLE_CENTROID = 0x00000001, 20275 } ZSamplePosition; 20276 20277 /* 20278 * SU_PERFCNT_SEL enum 20279 */ 20280 20281 typedef enum SU_PERFCNT_SEL { 20282 PERF_PAPC_PASX_REQ = 0x00000000, 20283 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, 20284 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, 20285 PERF_CLPR_INPUT_PRIM = 0x00000008, 20286 PERF_CLPR_INPUT_NULL_PRIM = 0x00000009, 20287 PERF_CLPR_INPUT_EVENT = 0x0000000a, 20288 PERF_CLPR_INPUT_FIRST_OF_SUBGROUP = 0x0000000b, 20289 PERF_CLPR_INPUT_END_OF_PACKET = 0x0000000c, 20290 PERF_CLPR_INPUT_EXTENDED_EVENT = 0x0000000d, 20291 PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, 20292 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, 20293 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, 20294 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, 20295 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, 20296 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, 20297 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, 20298 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, 20299 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, 20300 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, 20301 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, 20302 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, 20303 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, 20304 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, 20305 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, 20306 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, 20307 PERF_CLPR_CLIP_PLANE_CNT_9_PLUS = 0x0000001e, 20308 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, 20309 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, 20310 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, 20311 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, 20312 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, 20313 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, 20314 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, 20315 PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, 20316 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, 20317 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, 20318 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, 20319 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, 20320 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, 20321 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, 20322 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, 20323 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS = 0x0000002f, 20324 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, 20325 PERF_PAPC_SU_INPUT_PRIM = 0x00000031, 20326 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, 20327 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, 20328 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, 20329 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, 20330 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, 20331 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, 20332 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, 20333 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, 20334 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, 20335 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, 20336 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, 20337 PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, 20338 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, 20339 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, 20340 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, 20341 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, 20342 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, 20343 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, 20344 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, 20345 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, 20346 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, 20347 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, 20348 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, 20349 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, 20350 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, 20351 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, 20352 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, 20353 PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, 20354 PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, 20355 PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, 20356 PERF_PAPC_PASX_REC_IDLE = 0x00000050, 20357 PERF_PAPC_PASX_REC_BUSY = 0x00000051, 20358 PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, 20359 PERF_PAPC_PASX_REC_STALLED = 0x00000053, 20360 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, 20361 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, 20362 PERF_PAPC_CCGSM_IDLE = 0x00000056, 20363 PERF_PAPC_CCGSM_BUSY = 0x00000057, 20364 PERF_PAPC_CCGSM_STALLED = 0x00000058, 20365 PERF_PAPC_CLPRIM_IDLE = 0x00000059, 20366 PERF_PAPC_CLPRIM_BUSY = 0x0000005a, 20367 PERF_PAPC_CLPRIM_STALLED = 0x0000005b, 20368 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, 20369 PERF_PAPC_CLIPSM_IDLE = 0x0000005d, 20370 PERF_PAPC_CLIPSM_BUSY = 0x0000005e, 20371 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, 20372 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, 20373 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, 20374 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, 20375 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, 20376 PERF_PAPC_CLIPGA_IDLE = 0x00000064, 20377 PERF_PAPC_CLIPGA_BUSY = 0x00000065, 20378 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, 20379 PERF_PAPC_CLIPGA_STALLED = 0x00000067, 20380 PERF_PAPC_CLIP_IDLE = 0x00000068, 20381 PERF_PAPC_CLIP_BUSY = 0x00000069, 20382 PERF_PAPC_SU_IDLE = 0x0000006a, 20383 PERF_PAPC_SU_BUSY = 0x0000006b, 20384 PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, 20385 PERF_PAPC_SU_STALLED_SC = 0x0000006d, 20386 PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, 20387 PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, 20388 PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, 20389 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, 20390 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, 20391 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, 20392 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, 20393 PERF_PAPC_SU_ALL_OUTPUT_PRIM = 0x0000007d, 20394 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, 20395 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, 20396 PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM = 0x00000080, 20397 PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, 20398 PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, 20399 PERF_PAPC_SU_ALL_STALLED_SC = 0x00000085, 20400 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, 20401 PERF_PAPC_SU_CULLED_PRIM = 0x00000087, 20402 PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, 20403 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, 20404 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, 20405 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, 20406 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, 20407 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, 20408 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, 20409 PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, 20410 PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, 20411 PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099, 20412 PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a, 20413 PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b, 20414 PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c, 20415 PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d, 20416 PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e, 20417 PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f, 20418 PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0, 20419 PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1, 20420 PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2, 20421 PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3, 20422 PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4, 20423 PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5, 20424 PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000a9, 20425 PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000aa, 20426 PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ab, 20427 PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ac, 20428 PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ad, 20429 PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ae, 20430 PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000af, 20431 PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b0, 20432 PERF_PA_VERTEX_FIFO_FULL = 0x000000b1, 20433 PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x000000b2, 20434 PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x000000b3, 20435 PERF_ENGG_CSB_MACHINE_IS_STARVED = 0x000000b7, 20436 PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000b8, 20437 PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x000000b9, 20438 PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 0x000000ba, 20439 PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 0x000000bc, 20440 PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 0x000000bd, 20441 PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 0x000000be, 20442 PERF_ENGG_CSB_NULL_SUBGROUP = 0x000000bf, 20443 PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 0x000000c0, 20444 PERF_ENGG_CSB_GE_MEMORY_FULL = 0x000000c1, 20445 PERF_ENGG_CSB_GE_MEMORY_EMPTY = 0x000000c2, 20446 PERF_ENGG_CSB_SPI_MEMORY_FULL = 0x000000c3, 20447 PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 0x000000c4, 20448 PERF_ENGG_INDEX_REQ_NULL_REQUEST = 0x000000e0, 20449 PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM = 0x000000e1, 20450 PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM = 0x000000e2, 20451 PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM = 0x000000e3, 20452 PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM = 0x000000e4, 20453 PERF_ENGG_INDEX_REQ_STARVED = 0x000000e5, 20454 PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000e6, 20455 PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000e7, 20456 PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000e8, 20457 PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x000000e9, 20458 PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x000000ea, 20459 PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000eb, 20460 PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x000000ec, 20461 PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000ed, 20462 PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000ee, 20463 PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000ef, 20464 PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 0x000000f0, 20465 PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f1, 20466 PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f2, 20467 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f3, 20468 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f4, 20469 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000f5, 20470 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000f6, 20471 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000f7, 20472 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000f8, 20473 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000f9, 20474 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000fa, 20475 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x000000fb, 20476 PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x000000fc, 20477 PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000102, 20478 PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000103, 20479 PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000104, 20480 PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x00000105, 20481 PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x00000106, 20482 PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x00000107, 20483 PERF_ENGG_POS_REQ_STARVED = 0x00000108, 20484 PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x00000109, 20485 PERF_ENGG_BUSY = 0x0000010a, 20486 PERF_CLIPSM_CULL_PRIMS_CNT = 0x0000010b, 20487 PERF_PH_SEND_1_SC = 0x0000010c, 20488 PERF_PH_SEND_2_SC = 0x0000010d, 20489 PERF_PH_SEND_3_SC = 0x0000010e, 20490 PERF_PH_SEND_4_SC = 0x0000010f, 20491 PERF_OUTPUT_PRIM_1_SC = 0x00000110, 20492 PERF_OUTPUT_PRIM_2_SC = 0x00000111, 20493 PERF_OUTPUT_PRIM_3_SC = 0x00000112, 20494 PERF_OUTPUT_PRIM_4_SC = 0x00000113, 20495 PERF_PASX_POS_VECTOR = 0x00000114, 20496 PERF_PASX_MISC_VECTOR = 0x00000115, 20497 PERF_PASX_CCDIST0_VECTOR = 0x00000116, 20498 PERF_PASX_CCDIST1_VECTOR = 0x00000117, 20499 PERF_PASX_STEREO_POS_VECTOR = 0x00000118, 20500 PERF_CLPR_INPUT_SEND = 0x00000119, 20501 PERF_SU_INPUT_SEND = 0x0000011a, 20502 PERF_SU_OUTPUT_SEND = 0x0000011b, 20503 PERF_PAPC_SU_SE4_PRIM_FILTER_CULL = 0x0000011c, 20504 PERF_PAPC_SU_SE5_PRIM_FILTER_CULL = 0x0000011d, 20505 PERF_PAPC_SU_SE4_OUTPUT_PRIM = 0x0000011e, 20506 PERF_PAPC_SU_SE5_OUTPUT_PRIM = 0x0000011f, 20507 PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM = 0x00000120, 20508 PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM = 0x00000121, 20509 PERF_PAPC_SU_SE4_STALLED_SC = 0x00000122, 20510 PERF_PAPC_SU_SE5_STALLED_SC = 0x00000123, 20511 PERF_ENGG_INDEX_RET0_NEW_VERTS = 0x00000124, 20512 PERF_ENGG_INDEX_RET1_NEW_VERTS = 0x00000125, 20513 PERF_ENGG_INDEX_RET2_NEW_VERTS = 0x00000126, 20514 PERF_ENGG_INDEX_RET3_NEW_VERTS = 0x00000127, 20515 PERF_ENGG_INDEX_RET4_NEW_VERTS = 0x00000128, 20516 PERF_ENGG_INDEX_RET5_NEW_VERTS = 0x00000129, 20517 PERF_ENGG_INDEX_RET6_NEW_VERTS = 0x0000012a, 20518 PERF_ENGG_INDEX_RET7_NEW_VERTS = 0x0000012b, 20519 PERF_ENGG_INDEX_RET8_NEW_VERTS = 0x0000012c, 20520 PERF_ENGG_INDEX_RET9_NEW_VERTS = 0x0000012d, 20521 PERF_ENGG_INDEX_RET10_NEW_VERTS = 0x0000012e, 20522 PERF_ENGG_INDEX_RET11_NEW_VERTS = 0x0000012f, 20523 PERF_ENGG_INDEX_RET12_NEW_VERTS = 0x00000130, 20524 PERF_PH_SEND_5_SC = 0x00000131, 20525 PERF_PH_SEND_6_SC = 0x00000132, 20526 PERF_OUTPUT_PRIM_5_SC = 0x00000133, 20527 PERF_OUTPUT_PRIM_6_SC = 0x00000134, 20528 PERF_CLPR_BACK_PRIM = 0x00000135, 20529 PERF_PA_BUSY = 0x00000136, 20530 } SU_PERFCNT_SEL; 20531 20532 /* 20533 * RMIPerfSel enum 20534 */ 20535 20536 typedef enum RMIPerfSel { 20537 RMI_PERF_SEL_NONE = 0x00000000, 20538 RMI_PERF_SEL_BUSY = 0x00000001, 20539 RMI_PERF_SEL_REG_CLK_VLD = 0x00000002, 20540 RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003, 20541 RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004, 20542 RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005, 20543 RMI_PERF_SEL_PERF_WINDOW = 0x00000006, 20544 RMI_PERF_SEL_EVENT_SEND = 0x00000007, 20545 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000008, 20546 RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 0x00000009, 20547 RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x0000000a, 20548 RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x0000000b, 20549 RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x0000000c, 20550 RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000000d, 20551 RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000000e, 20552 RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000000f, 20553 RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x00000010, 20554 RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x00000011, 20555 RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 0x00000012, 20556 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000013, 20557 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000014, 20558 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000015, 20559 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000016, 20560 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000017, 20561 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000018, 20562 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000019, 20563 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x0000001a, 20564 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x0000001b, 20565 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x0000001c, 20566 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000001d, 20567 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000001e, 20568 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000001f, 20569 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x00000020, 20570 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x00000021, 20571 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x00000022, 20572 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000023, 20573 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000024, 20574 RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 0x00000025, 20575 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000026, 20576 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000027, 20577 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000028, 20578 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000029, 20579 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x0000002a, 20580 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x0000002b, 20581 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x0000002c, 20582 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000002d, 20583 RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000002e, 20584 RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000002f, 20585 RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x00000030, 20586 RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x00000031, 20587 RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x00000032, 20588 RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000033, 20589 RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000034, 20590 RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000035, 20591 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000036, 20592 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000037, 20593 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000038, 20594 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000039, 20595 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x0000003a, 20596 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x0000003b, 20597 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x0000003c, 20598 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000003d, 20599 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000003e, 20600 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000003f, 20601 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x00000040, 20602 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x00000041, 20603 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x00000042, 20604 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000043, 20605 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000044, 20606 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000045, 20607 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000046, 20608 RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 0x00000047, 20609 RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 0x00000048, 20610 RMI_PERF_SEL_RB_RMI_WR_IDLE = 0x00000049, 20611 RMI_PERF_SEL_RB_RMI_WR_STARVE = 0x0000004a, 20612 RMI_PERF_SEL_RB_RMI_WR_STALL = 0x0000004b, 20613 RMI_PERF_SEL_RB_RMI_WR_BUSY = 0x0000004c, 20614 RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 0x0000004d, 20615 RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 0x0000004e, 20616 RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 0x0000004f, 20617 RMI_PERF_SEL_RB_RMI_RD_IDLE = 0x00000050, 20618 RMI_PERF_SEL_RB_RMI_RD_STARVE = 0x00000051, 20619 RMI_PERF_SEL_RB_RMI_RD_STALL = 0x00000052, 20620 RMI_PERF_SEL_RB_RMI_RD_BUSY = 0x00000053, 20621 RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 0x00000054, 20622 RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 0x00000055, 20623 RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 0x00000056, 20624 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000057, 20625 RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000058, 20626 RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000059, 20627 RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x0000005a, 20628 RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x0000005b, 20629 RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x0000005c, 20630 RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000005d, 20631 RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000005e, 20632 RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000005f, 20633 RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x00000060, 20634 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x00000061, 20635 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x00000062, 20636 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000063, 20637 RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000064, 20638 RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000065, 20639 RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000066, 20640 RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000067, 20641 RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000068, 20642 RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000069, 20643 RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x0000006a, 20644 RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x0000006b, 20645 RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 0x0000006c, 20646 RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 0x0000006d, 20647 RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 0x0000006e, 20648 RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 0x0000006f, 20649 RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 0x00000070, 20650 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000071, 20651 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x00000072, 20652 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x00000073, 20653 RMI_PERF_SEL_TCIW_REQ = 0x00000074, 20654 RMI_PERF_SEL_TCIW_BUSY = 0x00000075, 20655 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x00000076, 20656 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x00000077, 20657 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x00000078, 20658 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x00000079, 20659 RMI_PERF_SEL_REORDER_FIFO_REQ = 0x0000007a, 20660 RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x0000007b, 20661 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x0000007c, 20662 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x0000007d, 20663 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x0000007e, 20664 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x0000007f, 20665 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x00000080, 20666 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x00000081, 20667 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x00000082, 20668 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x00000083, 20669 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x00000084, 20670 RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR = 0x00000085, 20671 RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR = 0x00000086, 20672 RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR = 0x00000087, 20673 RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR = 0x00000088, 20674 RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR = 0x00000089, 20675 RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR = 0x0000008a, 20676 } RMIPerfSel; 20677 20678 /* 20679 * UTCL1PerfSel enum 20680 */ 20681 20682 typedef enum UTCL1PerfSel { 20683 UTCL1_PERF_SEL_NONE = 0x00000000, 20684 UTCL1_PERF_SEL_REQS = 0x00000001, 20685 UTCL1_PERF_SEL_HITS = 0x00000002, 20686 UTCL1_PERF_SEL_MISSES = 0x00000003, 20687 UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 0x00000004, 20688 UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 0x00000005, 20689 UTCL1_PERF_SEL_UTCL2_REQS = 0x00000006, 20690 UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 0x00000007, 20691 UTCL1_PERF_SEL_UTCL2_RET_FAULT = 0x00000008, 20692 UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 0x00000009, 20693 UTCL1_PERF_SEL_STALL_MH_FULL = 0x0000000a, 20694 UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b, 20695 UTCL1_PERF_SEL_UTCL2_RET_CNT = 0x0000000c, 20696 UTCL1_PERF_SEL_RTNS = 0x0000000d, 20697 UTCL1_PERF_SEL_XLAT_REQ_BUSY = 0x0000000e, 20698 UTCL1_PERF_SEL_RANGE_INVREQS = 0x0000000f, 20699 UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 0x00000010, 20700 UTCL1_PERF_SEL_BYPASS_REQS = 0x00000011, 20701 UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000012, 20702 UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 0x00000013, 20703 UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 0x00000014, 20704 UTCL1_PERF_SEL_CP_INVREQS = 0x00000015, 20705 UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 0x00000016, 20706 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K = 0x00000017, 20707 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K = 0x00000018, 20708 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K = 0x00000019, 20709 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M = 0x0000001a, 20710 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M = 0x0000001b, 20711 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M = 0x0000001c, 20712 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M = 0x0000001d, 20713 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M = 0x0000001e, 20714 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M = 0x0000001f, 20715 UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF = 0x00000020, 20716 UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM = 0x00000021, 20717 UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0 = 0x00000022, 20718 UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1 = 0x00000023, 20719 UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2 = 0x00000024, 20720 UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3 = 0x00000025, 20721 UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0 = 0x00000026, 20722 UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1 = 0x00000027, 20723 UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2 = 0x00000028, 20724 UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3 = 0x00000029, 20725 UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS = 0x0000002a, 20726 UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS = 0x0000002b, 20727 UTCL1_PERF_SEL_HITS_PG_SIZE_1 = 0x0000002c, 20728 UTCL1_PERF_SEL_HITS_PG_SIZE_2 = 0x0000002d, 20729 UTCL1_PERF_SEL_HITS_PG_SIZE_3 = 0x0000002e, 20730 UTCL1_PERF_SEL_HITS_PG_SIZE_4 = 0x0000002f, 20731 UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0 = 0x00000030, 20732 UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1 = 0x00000031, 20733 UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2 = 0x00000032, 20734 UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3 = 0x00000033, 20735 UTCL1_PERF_SEL_AVG_INV_LATENCY = 0x00000034, 20736 UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0 = 0x00000035, 20737 UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1 = 0x00000036, 20738 UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2 = 0x00000037, 20739 UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3 = 0x00000038, 20740 UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0 = 0x00000039, 20741 UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1 = 0x0000003a, 20742 UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2 = 0x0000003b, 20743 UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3 = 0x0000003c, 20744 UTCL1_PERF_SEL_EVICTIONS_NUM_CC0 = 0x0000003d, 20745 UTCL1_PERF_SEL_EVICTIONS_NUM_CC1 = 0x0000003e, 20746 UTCL1_PERF_SEL_EVICTIONS_NUM_CC2 = 0x0000003f, 20747 UTCL1_PERF_SEL_EVICTIONS_NUM_CC3 = 0x00000040, 20748 UTCL1_PERF_SEL_ALOG_INTERRUPT = 0x00000041, 20749 UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED = 0x00000042, 20750 UTCL1_PERF_SEL_ALOG_CACHE_REQ = 0x00000043, 20751 UTCL1_PERF_SEL_ALOG_CACHE_HIT = 0x00000044, 20752 UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS = 0x00000045, 20753 } UTCL1PerfSel; 20754 20755 /* 20756 * GC_EA_SE_PERFCOUNT_SEL enum 20757 */ 20758 20759 typedef enum GC_EA_SE_PERFCOUNT_SEL { 20760 GC_EA_SE_PERF_SEL_ALWAYS_COUNT = 0x00000000, 20761 GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD = 0x00000001, 20762 GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 0x00000002, 20763 GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 0x00000003, 20764 GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0 = 0x00000004, 20765 GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0 = 0x00000005, 20766 GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1 = 0x00000006, 20767 GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1 = 0x00000007, 20768 GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD = 0x00000008, 20769 GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 0x00000009, 20770 GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 0x0000000a, 20771 GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0 = 0x0000000b, 20772 GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0 = 0x0000000c, 20773 GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1 = 0x0000000d, 20774 GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1 = 0x0000000e, 20775 GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD = 0x0000000f, 20776 GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP = 0x00000010, 20777 GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 0x00000011, 20778 GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0 = 0x00000012, 20779 GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0 = 0x00000013, 20780 GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1 = 0x00000014, 20781 GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1 = 0x00000015, 20782 GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD = 0x00000016, 20783 GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP = 0x00000017, 20784 GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 0x00000018, 20785 GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0 = 0x00000019, 20786 GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0 = 0x0000001a, 20787 GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1 = 0x0000001b, 20788 GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1 = 0x0000001c, 20789 GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP = 0x0000001d, 20790 GC_EA_SE_PERF_SEL_RIO_SIZE_REQ = 0x0000001e, 20791 GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ = 0x0000001f, 20792 GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ = 0x00000020, 20793 GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ = 0x00000021, 20794 GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ = 0x00000022, 20795 GC_EA_SE_PERF_SEL_RIO_LATENCY_START0 = 0x00000023, 20796 GC_EA_SE_PERF_SEL_RIO_LATENCY_END0 = 0x00000024, 20797 GC_EA_SE_PERF_SEL_RIO_LATENCY_START1 = 0x00000025, 20798 GC_EA_SE_PERF_SEL_RIO_LATENCY_END1 = 0x00000026, 20799 GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP = 0x00000027, 20800 GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 0x00000028, 20801 GC_EA_SE_PERF_SEL_WIO_SIZE_REQ = 0x00000029, 20802 GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ = 0x0000002a, 20803 GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ = 0x0000002b, 20804 GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ = 0x0000002c, 20805 GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ = 0x0000002d, 20806 GC_EA_SE_PERF_SEL_WIO_LATENCY_START0 = 0x0000002e, 20807 GC_EA_SE_PERF_SEL_WIO_LATENCY_END0 = 0x0000002f, 20808 GC_EA_SE_PERF_SEL_WIO_LATENCY_START1 = 0x00000030, 20809 GC_EA_SE_PERF_SEL_WIO_LATENCY_END1 = 0x00000031, 20810 GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC = 0x00000032, 20811 GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC = 0x00000033, 20812 GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC = 0x00000034, 20813 GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC = 0x00000035, 20814 GC_EA_SE_PERF_SEL_SARB_SIZE_REQ = 0x00000036, 20815 GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ = 0x00000037, 20816 GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ = 0x00000038, 20817 GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ = 0x00000039, 20818 GC_EA_SE_PERF_SEL_SARB_LATENCY_START0 = 0x0000003a, 20819 GC_EA_SE_PERF_SEL_SARB_LATENCY_END0 = 0x0000003b, 20820 GC_EA_SE_PERF_SEL_SARB_LATENCY_START1 = 0x0000003c, 20821 GC_EA_SE_PERF_SEL_SARB_LATENCY_END1 = 0x0000003d, 20822 GC_EA_SE_PERF_SEL_SARB_BUSY = 0x0000003e, 20823 GC_EA_SE_PERF_SEL_SARB_STALLED = 0x0000003f, 20824 GC_EA_SE_PERF_SEL_SARB_STARVING = 0x00000040, 20825 GC_EA_SE_PERF_SEL_SARB_IDLE = 0x00000041, 20826 GC_EA_SE_PERF_SEL_RRET_VLD = 0x00000042, 20827 GC_EA_SE_PERF_SEL_WRET_VLD = 0x00000043, 20828 GC_EA_SE_PERF_SEL_PRB_REQ = 0x00000044, 20829 GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT = 0x00000045, 20830 GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD = 0x00000046, 20831 GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT = 0x00000047, 20832 GC_EA_SE_PERF_SEL_MAM_NUM_DQRY = 0x00000048, 20833 GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT = 0x00000049, 20834 GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 0x0000004a, 20835 GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED = 0x0000004b, 20836 GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING = 0x0000004c, 20837 GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ = 0x0000004d, 20838 GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ = 0x0000004e, 20839 GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ = 0x0000004f, 20840 GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ = 0x00000050, 20841 GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 0x00000051, 20842 GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 0x00000052, 20843 GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000053, 20844 GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000054, 20845 GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000055, 20846 GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000056, 20847 GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT = 0x00000057, 20848 GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD = 0x00000058, 20849 GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ = 0x00000059, 20850 GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 0x0000005a, 20851 GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 0x0000005b, 20852 GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ = 0x0000005c, 20853 GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP = 0x0000005d, 20854 GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 0x0000005e, 20855 GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 0x0000005f, 20856 GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING = 0x00000060, 20857 GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT = 0x00000061, 20858 } GC_EA_SE_PERFCOUNT_SEL; 20859 20860 /* 20861 * LSDMA_PERF_SEL enum 20862 */ 20863 20864 typedef enum LSDMA_PERF_SEL { 20865 LSDMA_PERF_SEL_CYCLE = 0x00000000, 20866 LSDMA_PERF_SEL_IDLE = 0x00000001, 20867 LSDMA_PERF_SEL_REG_IDLE = 0x00000002, 20868 LSDMA_PERF_SEL_RB_EMPTY = 0x00000003, 20869 LSDMA_PERF_SEL_RB_FULL = 0x00000004, 20870 LSDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, 20871 LSDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, 20872 LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, 20873 LSDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, 20874 LSDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, 20875 LSDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, 20876 LSDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, 20877 LSDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, 20878 LSDMA_PERF_SEL_EX_IDLE = 0x0000000d, 20879 LSDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, 20880 LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, 20881 LSDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, 20882 LSDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, 20883 LSDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, 20884 LSDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, 20885 LSDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, 20886 LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, 20887 LSDMA_PERF_SEL_SEM_IDLE = 0x00000018, 20888 LSDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, 20889 LSDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, 20890 LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, 20891 LSDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, 20892 LSDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, 20893 LSDMA_PERF_SEL_INT_IDLE = 0x0000001e, 20894 LSDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, 20895 LSDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, 20896 LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, 20897 LSDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, 20898 LSDMA_PERF_SEL_NUM_PACKET = 0x00000023, 20899 LSDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, 20900 LSDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, 20901 LSDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, 20902 LSDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, 20903 LSDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, 20904 LSDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, 20905 LSDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, 20906 LSDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, 20907 LSDMA_PERF_SEL_DUMMY_0 = 0x0000002f, 20908 LSDMA_PERF_SEL_DUMMY_1 = 0x00000030, 20909 LSDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, 20910 LSDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, 20911 LSDMA_PERF_SEL_CE_RD_STALL = 0x00000033, 20912 LSDMA_PERF_SEL_CE_WR_STALL = 0x00000034, 20913 LSDMA_PERF_SEL_GFX_SELECT = 0x00000035, 20914 LSDMA_PERF_SEL_RLC0_SELECT = 0x00000036, 20915 LSDMA_PERF_SEL_RLC1_SELECT = 0x00000037, 20916 LSDMA_PERF_SEL_PAGE_SELECT = 0x00000038, 20917 LSDMA_PERF_SEL_CTX_CHANGE = 0x00000039, 20918 LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, 20919 LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, 20920 LSDMA_PERF_SEL_DOORBELL = 0x0000003c, 20921 LSDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, 20922 LSDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, 20923 LSDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, 20924 LSDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, 20925 LSDMA_PERF_SEL_CE_L1_STALL = 0x00000041, 20926 LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, 20927 LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, 20928 LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, 20929 LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, 20930 LSDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, 20931 LSDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, 20932 LSDMA_PERF_SEL_ATCL2_FREE = 0x00000048, 20933 LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, 20934 LSDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, 20935 LSDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, 20936 LSDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, 20937 LSDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, 20938 LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, 20939 LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, 20940 LSDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, 20941 LSDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, 20942 LSDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, 20943 LSDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, 20944 LSDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, 20945 LSDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, 20946 LSDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, 20947 LSDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, 20948 LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, 20949 LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, 20950 LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, 20951 LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, 20952 LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, 20953 LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, 20954 LSDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, 20955 LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 0x0000005f, 20956 LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 0x00000060, 20957 LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 0x00000061, 20958 LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 0x00000062, 20959 LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 0x00000063, 20960 LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 0x00000064, 20961 LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 0x00000065, 20962 LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 0x00000066, 20963 LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 0x00000067, 20964 LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 0x00000068, 20965 LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 0x00000069, 20966 LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 0x0000006a, 20967 LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000006b, 20968 LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x0000006c, 20969 LSDMA_PERF_SEL_CMD_OP_MATCH = 0x0000006d, 20970 LSDMA_PERF_SEL_CMD_OP_START = 0x0000006e, 20971 LSDMA_PERF_SEL_CMD_OP_END = 0x0000006f, 20972 LSDMA_PERF_SEL_CE_BUSY = 0x00000070, 20973 LSDMA_PERF_SEL_CE_BUSY_START = 0x00000071, 20974 LSDMA_PERF_SEL_CE_BUSY_END = 0x00000072, 20975 LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000073, 20976 LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074, 20977 LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x00000075, 20978 LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 0x00000076, 20979 LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 0x00000077, 20980 LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 0x00000078, 20981 LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 0x00000079, 20982 LSDMA_PERF_SEL_DRAM_ECC = 0x0000007a, 20983 LSDMA_PERF_SEL_NACK_GEN_ERR = 0x0000007b, 20984 } LSDMA_PERF_SEL; 20985 20986 /* 20987 * ROM_SIGNATURE value 20988 */ 20989 20990 #define ROM_SIGNATURE 0x0000aa55 20991 20992 /* 20993 * EFC_SURFACE_PIXEL_FORMAT enum 20994 */ 20995 20996 typedef enum EFC_SURFACE_PIXEL_FORMAT { 20997 EFC_ARGB1555 = 0x00000001, 20998 EFC_RGBA5551 = 0x00000002, 20999 EFC_RGB565 = 0x00000003, 21000 EFC_BGR565 = 0x00000004, 21001 EFC_ARGB4444 = 0x00000005, 21002 EFC_RGBA4444 = 0x00000006, 21003 EFC_ARGB8888 = 0x00000008, 21004 EFC_RGBA8888 = 0x00000009, 21005 EFC_ARGB2101010 = 0x0000000a, 21006 EFC_RGBA1010102 = 0x0000000b, 21007 EFC_AYCrCb8888 = 0x0000000c, 21008 EFC_YCrCbA8888 = 0x0000000d, 21009 EFC_ACrYCb8888 = 0x0000000e, 21010 EFC_CrYCbA8888 = 0x0000000f, 21011 EFC_ARGB16161616_10MSB = 0x00000010, 21012 EFC_RGBA16161616_10MSB = 0x00000011, 21013 EFC_ARGB16161616_10LSB = 0x00000012, 21014 EFC_RGBA16161616_10LSB = 0x00000013, 21015 EFC_ARGB16161616_12MSB = 0x00000014, 21016 EFC_RGBA16161616_12MSB = 0x00000015, 21017 EFC_ARGB16161616_12LSB = 0x00000016, 21018 EFC_RGBA16161616_12LSB = 0x00000017, 21019 EFC_ARGB16161616_FLOAT = 0x00000018, 21020 EFC_RGBA16161616_FLOAT = 0x00000019, 21021 EFC_ARGB16161616_UNORM = 0x0000001a, 21022 EFC_RGBA16161616_UNORM = 0x0000001b, 21023 EFC_ARGB16161616_SNORM = 0x0000001c, 21024 EFC_RGBA16161616_SNORM = 0x0000001d, 21025 EFC_AYCrCb16161616_10MSB = 0x00000020, 21026 EFC_AYCrCb16161616_10LSB = 0x00000021, 21027 EFC_YCrCbA16161616_10MSB = 0x00000022, 21028 EFC_YCrCbA16161616_10LSB = 0x00000023, 21029 EFC_ACrYCb16161616_10MSB = 0x00000024, 21030 EFC_ACrYCb16161616_10LSB = 0x00000025, 21031 EFC_CrYCbA16161616_10MSB = 0x00000026, 21032 EFC_CrYCbA16161616_10LSB = 0x00000027, 21033 EFC_AYCrCb16161616_12MSB = 0x00000028, 21034 EFC_AYCrCb16161616_12LSB = 0x00000029, 21035 EFC_YCrCbA16161616_12MSB = 0x0000002a, 21036 EFC_YCrCbA16161616_12LSB = 0x0000002b, 21037 EFC_ACrYCb16161616_12MSB = 0x0000002c, 21038 EFC_ACrYCb16161616_12LSB = 0x0000002d, 21039 EFC_CrYCbA16161616_12MSB = 0x0000002e, 21040 EFC_CrYCbA16161616_12LSB = 0x0000002f, 21041 EFC_Y8_CrCb88_420_PLANAR = 0x00000040, 21042 EFC_Y8_CbCr88_420_PLANAR = 0x00000041, 21043 EFC_Y10_CrCb1010_420_PLANAR = 0x00000042, 21044 EFC_Y10_CbCr1010_420_PLANAR = 0x00000043, 21045 EFC_Y12_CrCb1212_420_PLANAR = 0x00000044, 21046 EFC_Y12_CbCr1212_420_PLANAR = 0x00000045, 21047 EFC_YCrYCb8888_422_PACKED = 0x00000048, 21048 EFC_YCbYCr8888_422_PACKED = 0x00000049, 21049 EFC_CrYCbY8888_422_PACKED = 0x0000004a, 21050 EFC_CbYCrY8888_422_PACKED = 0x0000004b, 21051 EFC_YCrYCb10101010_422_PACKED = 0x0000004c, 21052 EFC_YCbYCr10101010_422_PACKED = 0x0000004d, 21053 EFC_CrYCbY10101010_422_PACKED = 0x0000004e, 21054 EFC_CbYCrY10101010_422_PACKED = 0x0000004f, 21055 EFC_YCrYCb12121212_422_PACKED = 0x00000050, 21056 EFC_YCbYCr12121212_422_PACKED = 0x00000051, 21057 EFC_CrYCbY12121212_422_PACKED = 0x00000052, 21058 EFC_CbYCrY12121212_422_PACKED = 0x00000053, 21059 EFC_RGB111110_FIX = 0x00000070, 21060 EFC_BGR101111_FIX = 0x00000071, 21061 EFC_ACrYCb2101010 = 0x00000072, 21062 EFC_CrYCbA1010102 = 0x00000073, 21063 EFC_RGB111110_FLOAT = 0x00000076, 21064 EFC_BGR101111_FLOAT = 0x00000077, 21065 EFC_MONO_8 = 0x00000078, 21066 EFC_MONO_10MSB = 0x00000079, 21067 EFC_MONO_10LSB = 0x0000007a, 21068 EFC_MONO_12MSB = 0x0000007b, 21069 EFC_MONO_12LSB = 0x0000007c, 21070 EFC_MONO_16 = 0x0000007d, 21071 } EFC_SURFACE_PIXEL_FORMAT; 21072 21073 #endif /*_soc24_ENUM_HEADER*/ 21074