Searched refs:GATE_CLK_DDR23_DIV1 (Results 1 – 2 of 2) sorted by relevance
96 #define GATE_CLK_DDR23_DIV1 80 macro
447 SG2042_GATE_FW(GATE_CLK_DDR23_DIV1, "clk_gate_ddr23_div1", "fpll",931 case GATE_CLK_DDR23_DIV1: in sg2042_clk_register_gates_fw()