Searched refs:GATE_CLK_DDR23_DIV0 (Results 1 – 2 of 2) sorted by relevance
99 #define GATE_CLK_DDR23_DIV0 82 macro
444 SG2042_GATE_FW(GATE_CLK_DDR23_DIV0, "clk_gate_ddr23_div0", "dpll1",928 case GATE_CLK_DDR23_DIV0: in sg2042_clk_register_gates_fw()