1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef CIK_H 25 #define CIK_H 26 27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 33 #define MC_SEQ_MISC0__MT__HBM 0x60000000 34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 35 36 #define CP_ME_TABLE_SIZE 96 37 38 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 41 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 42 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 43 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45 46 /* hpd instance offsets */ 47 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 48 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 49 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 50 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 51 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 52 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 53 54 /* audio endpt instance offsets */ 55 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 56 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 57 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 58 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 59 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 60 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 61 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 62 63 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 64 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 65 66 #define PIPEID(x) ((x) << 0) 67 #define MEID(x) ((x) << 2) 68 #define VMID(x) ((x) << 4) 69 #define QUEUEID(x) ((x) << 8) 70 71 #define mmCC_DRM_ID_STRAPS 0x1559 72 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 73 74 #define mmCHUB_CONTROL 0x619 75 #define BYPASS_VM (1 << 0) 76 77 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 78 79 #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 80 #define LUT_10BIT_BYPASS_EN (1 << 8) 81 82 # define CURSOR_MONO 0 83 # define CURSOR_24_1 1 84 # define CURSOR_24_8_PRE_MULT 2 85 # define CURSOR_24_8_UNPRE_MULT 3 86 # define CURSOR_URGENT_ALWAYS 0 87 # define CURSOR_URGENT_1_8 1 88 # define CURSOR_URGENT_1_4 2 89 # define CURSOR_URGENT_3_8 3 90 # define CURSOR_URGENT_1_2 4 91 92 # define GRPH_DEPTH_8BPP 0 93 # define GRPH_DEPTH_16BPP 1 94 # define GRPH_DEPTH_32BPP 2 95 /* 8 BPP */ 96 # define GRPH_FORMAT_INDEXED 0 97 /* 16 BPP */ 98 # define GRPH_FORMAT_ARGB1555 0 99 # define GRPH_FORMAT_ARGB565 1 100 # define GRPH_FORMAT_ARGB4444 2 101 # define GRPH_FORMAT_AI88 3 102 # define GRPH_FORMAT_MONO16 4 103 # define GRPH_FORMAT_BGRA5551 5 104 /* 32 BPP */ 105 # define GRPH_FORMAT_ARGB8888 0 106 # define GRPH_FORMAT_ARGB2101010 1 107 # define GRPH_FORMAT_32BPP_DIG 2 108 # define GRPH_FORMAT_8B_ARGB2101010 3 109 # define GRPH_FORMAT_BGRA1010102 4 110 # define GRPH_FORMAT_8B_BGRA1010102 5 111 # define GRPH_FORMAT_RGB111110 6 112 # define GRPH_FORMAT_BGR101111 7 113 # define ADDR_SURF_MACRO_TILE_ASPECT_1 0 114 # define ADDR_SURF_MACRO_TILE_ASPECT_2 1 115 # define ADDR_SURF_MACRO_TILE_ASPECT_4 2 116 # define ADDR_SURF_MACRO_TILE_ASPECT_8 3 117 # define GRPH_ARRAY_LINEAR_GENERAL 0 118 # define GRPH_ARRAY_LINEAR_ALIGNED 1 119 # define GRPH_ARRAY_1D_TILED_THIN1 2 120 # define GRPH_ARRAY_2D_TILED_THIN1 4 121 # define DISPLAY_MICRO_TILING 0 122 # define THIN_MICRO_TILING 1 123 # define DEPTH_MICRO_TILING 2 124 # define ROTATED_MICRO_TILING 4 125 # define GRPH_ENDIAN_NONE 0 126 # define GRPH_ENDIAN_8IN16 1 127 # define GRPH_ENDIAN_8IN32 2 128 # define GRPH_ENDIAN_8IN64 3 129 # define GRPH_RED_SEL_R 0 130 # define GRPH_RED_SEL_G 1 131 # define GRPH_RED_SEL_B 2 132 # define GRPH_RED_SEL_A 3 133 # define GRPH_GREEN_SEL_G 0 134 # define GRPH_GREEN_SEL_B 1 135 # define GRPH_GREEN_SEL_A 2 136 # define GRPH_GREEN_SEL_R 3 137 # define GRPH_BLUE_SEL_B 0 138 # define GRPH_BLUE_SEL_A 1 139 # define GRPH_BLUE_SEL_R 2 140 # define GRPH_BLUE_SEL_G 3 141 # define GRPH_ALPHA_SEL_A 0 142 # define GRPH_ALPHA_SEL_R 1 143 # define GRPH_ALPHA_SEL_G 2 144 # define GRPH_ALPHA_SEL_B 3 145 # define INPUT_GAMMA_USE_LUT 0 146 # define INPUT_GAMMA_BYPASS 1 147 # define INPUT_GAMMA_SRGB_24 2 148 # define INPUT_GAMMA_XVYCC_222 3 149 150 # define INPUT_CSC_BYPASS 0 151 # define INPUT_CSC_PROG_COEFF 1 152 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 153 154 # define OUTPUT_CSC_BYPASS 0 155 # define OUTPUT_CSC_TV_RGB 1 156 # define OUTPUT_CSC_YCBCR_601 2 157 # define OUTPUT_CSC_YCBCR_709 3 158 # define OUTPUT_CSC_PROG_COEFF 4 159 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 160 161 # define DEGAMMA_BYPASS 0 162 # define DEGAMMA_SRGB_24 1 163 # define DEGAMMA_XVYCC_222 2 164 # define GAMUT_REMAP_BYPASS 0 165 # define GAMUT_REMAP_PROG_COEFF 1 166 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 167 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 168 169 # define REGAMMA_BYPASS 0 170 # define REGAMMA_SRGB_24 1 171 # define REGAMMA_XVYCC_222 2 172 # define REGAMMA_PROG_A 3 173 # define REGAMMA_PROG_B 4 174 175 # define FMT_CLAMP_6BPC 0 176 # define FMT_CLAMP_8BPC 1 177 # define FMT_CLAMP_10BPC 2 178 179 # define HDMI_24BIT_DEEP_COLOR 0 180 # define HDMI_30BIT_DEEP_COLOR 1 181 # define HDMI_36BIT_DEEP_COLOR 2 182 # define HDMI_ACR_HW 0 183 # define HDMI_ACR_32 1 184 # define HDMI_ACR_44 2 185 # define HDMI_ACR_48 3 186 # define HDMI_ACR_X1 1 187 # define HDMI_ACR_X2 2 188 # define HDMI_ACR_X4 4 189 # define AFMT_AVI_INFO_Y_RGB 0 190 # define AFMT_AVI_INFO_Y_YCBCR422 1 191 # define AFMT_AVI_INFO_Y_YCBCR444 2 192 193 #define NO_AUTO 0 194 #define ES_AUTO 1 195 #define GS_AUTO 2 196 #define ES_AND_GS_AUTO 3 197 198 # define ARRAY_MODE(x) ((x) << 2) 199 # define PIPE_CONFIG(x) ((x) << 6) 200 # define TILE_SPLIT(x) ((x) << 11) 201 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 202 # define SAMPLE_SPLIT(x) ((x) << 25) 203 # define BANK_WIDTH(x) ((x) << 0) 204 # define BANK_HEIGHT(x) ((x) << 2) 205 # define MACRO_TILE_ASPECT(x) ((x) << 4) 206 # define NUM_BANKS(x) ((x) << 6) 207 208 #define MSG_ENTER_RLC_SAFE_MODE 1 209 #define MSG_EXIT_RLC_SAFE_MODE 0 210 211 /* 212 * PM4 213 */ 214 #define PACKET_TYPE0 0 215 #define PACKET_TYPE1 1 216 #define PACKET_TYPE2 2 217 #define PACKET_TYPE3 3 218 219 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 220 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 221 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 222 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 223 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 224 ((reg) & 0xFFFF) | \ 225 ((n) & 0x3FFF) << 16) 226 #define CP_PACKET2 0x80000000 227 #define PACKET2_PAD_SHIFT 0 228 #define PACKET2_PAD_MASK (0x3fffffff << 0) 229 230 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 231 232 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 233 (((op) & 0xFF) << 8) | \ 234 ((n) & 0x3FFF) << 16) 235 236 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 237 238 /* Packet 3 types */ 239 #define PACKET3_NOP 0x10 240 #define PACKET3_SET_BASE 0x11 241 #define PACKET3_BASE_INDEX(x) ((x) << 0) 242 #define CE_PARTITION_BASE 3 243 #define PACKET3_CLEAR_STATE 0x12 244 #define PACKET3_INDEX_BUFFER_SIZE 0x13 245 #define PACKET3_DISPATCH_DIRECT 0x15 246 #define PACKET3_DISPATCH_INDIRECT 0x16 247 #define PACKET3_ATOMIC_GDS 0x1D 248 #define PACKET3_ATOMIC_MEM 0x1E 249 #define PACKET3_OCCLUSION_QUERY 0x1F 250 #define PACKET3_SET_PREDICATION 0x20 251 #define PACKET3_REG_RMW 0x21 252 #define PACKET3_COND_EXEC 0x22 253 #define PACKET3_PRED_EXEC 0x23 254 #define PACKET3_DRAW_INDIRECT 0x24 255 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 256 #define PACKET3_INDEX_BASE 0x26 257 #define PACKET3_DRAW_INDEX_2 0x27 258 #define PACKET3_CONTEXT_CONTROL 0x28 259 #define PACKET3_INDEX_TYPE 0x2A 260 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 261 #define PACKET3_DRAW_INDEX_AUTO 0x2D 262 #define PACKET3_NUM_INSTANCES 0x2F 263 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 264 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 265 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 266 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 267 #define PACKET3_DRAW_PREAMBLE 0x36 268 #define PACKET3_WRITE_DATA 0x37 269 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 270 /* 0 - register 271 * 1 - memory (sync - via GRBM) 272 * 2 - gl2 273 * 3 - gds 274 * 4 - reserved 275 * 5 - memory (async - direct) 276 */ 277 #define WR_ONE_ADDR (1 << 16) 278 #define WR_CONFIRM (1 << 20) 279 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 280 /* 0 - LRU 281 * 1 - Stream 282 */ 283 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 284 /* 0 - me 285 * 1 - pfp 286 * 2 - ce 287 */ 288 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 289 #define PACKET3_MEM_SEMAPHORE 0x39 290 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 291 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 292 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 293 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 294 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 295 #define PACKET3_COPY_DW 0x3B 296 #define PACKET3_WAIT_REG_MEM 0x3C 297 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 298 /* 0 - always 299 * 1 - < 300 * 2 - <= 301 * 3 - == 302 * 4 - != 303 * 5 - >= 304 * 6 - > 305 */ 306 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 307 /* 0 - reg 308 * 1 - mem 309 */ 310 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 311 /* 0 - wait_reg_mem 312 * 1 - wr_wait_wr_reg 313 */ 314 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 315 /* 0 - me 316 * 1 - pfp 317 */ 318 #define PACKET3_INDIRECT_BUFFER 0x3F 319 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 320 #define INDIRECT_BUFFER_VALID (1 << 23) 321 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 322 /* 0 - LRU 323 * 1 - Stream 324 * 2 - Bypass 325 */ 326 #define PACKET3_COPY_DATA 0x40 327 #define PACKET3_PFP_SYNC_ME 0x42 328 #define PACKET3_SURFACE_SYNC 0x43 329 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 330 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 331 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 332 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 333 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 334 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 335 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 336 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 337 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 338 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 339 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 340 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 341 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 342 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 343 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 344 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 345 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 346 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 347 # define PACKET3_CB_ACTION_ENA (1 << 25) 348 # define PACKET3_DB_ACTION_ENA (1 << 26) 349 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 350 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 351 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 352 #define PACKET3_COND_WRITE 0x45 353 #define PACKET3_EVENT_WRITE 0x46 354 #define EVENT_TYPE(x) ((x) << 0) 355 #define EVENT_INDEX(x) ((x) << 8) 356 /* 0 - any non-TS event 357 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 358 * 2 - SAMPLE_PIPELINESTAT 359 * 3 - SAMPLE_STREAMOUTSTAT* 360 * 4 - *S_PARTIAL_FLUSH 361 * 5 - EOP events 362 * 6 - EOS events 363 */ 364 #define PACKET3_EVENT_WRITE_EOP 0x47 365 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 366 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 367 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 368 #define EOP_TCL1_ACTION_EN (1 << 16) 369 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 370 #define EOP_TCL2_VOLATILE (1 << 24) 371 #define EOP_CACHE_POLICY(x) ((x) << 25) 372 /* 0 - LRU 373 * 1 - Stream 374 * 2 - Bypass 375 */ 376 #define EOP_EXEC (1 << 28) /* For Trailing Fence */ 377 #define DATA_SEL(x) ((x) << 29) 378 /* 0 - discard 379 * 1 - send low 32bit data 380 * 2 - send 64bit data 381 * 3 - send 64bit GPU counter value 382 * 4 - send 64bit sys counter value 383 */ 384 #define INT_SEL(x) ((x) << 24) 385 /* 0 - none 386 * 1 - interrupt only (DATA_SEL = 0) 387 * 2 - interrupt when data write is confirmed 388 */ 389 #define DST_SEL(x) ((x) << 16) 390 /* 0 - MC 391 * 1 - TC/L2 392 */ 393 #define PACKET3_EVENT_WRITE_EOS 0x48 394 #define PACKET3_RELEASE_MEM 0x49 395 #define PACKET3_PREAMBLE_CNTL 0x4A 396 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 397 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 398 #define PACKET3_DMA_DATA 0x50 399 /* 1. header 400 * 2. CONTROL 401 * 3. SRC_ADDR_LO or DATA [31:0] 402 * 4. SRC_ADDR_HI [31:0] 403 * 5. DST_ADDR_LO [31:0] 404 * 6. DST_ADDR_HI [7:0] 405 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 406 */ 407 /* CONTROL */ 408 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 409 /* 0 - ME 410 * 1 - PFP 411 */ 412 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 413 /* 0 - LRU 414 * 1 - Stream 415 * 2 - Bypass 416 */ 417 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 418 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 419 /* 0 - DST_ADDR using DAS 420 * 1 - GDS 421 * 3 - DST_ADDR using L2 422 */ 423 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 424 /* 0 - LRU 425 * 1 - Stream 426 * 2 - Bypass 427 */ 428 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 429 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 430 /* 0 - SRC_ADDR using SAS 431 * 1 - GDS 432 * 2 - DATA 433 * 3 - SRC_ADDR using L2 434 */ 435 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 436 /* COMMAND */ 437 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 438 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 439 /* 0 - none 440 * 1 - 8 in 16 441 * 2 - 8 in 32 442 * 3 - 8 in 64 443 */ 444 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 445 /* 0 - none 446 * 1 - 8 in 16 447 * 2 - 8 in 32 448 * 3 - 8 in 64 449 */ 450 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 451 /* 0 - memory 452 * 1 - register 453 */ 454 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 455 /* 0 - memory 456 * 1 - register 457 */ 458 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 459 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 460 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 461 #define PACKET3_ACQUIRE_MEM 0x58 462 #define PACKET3_REWIND 0x59 463 #define PACKET3_LOAD_UCONFIG_REG 0x5E 464 #define PACKET3_LOAD_SH_REG 0x5F 465 #define PACKET3_LOAD_CONFIG_REG 0x60 466 #define PACKET3_LOAD_CONTEXT_REG 0x61 467 #define PACKET3_SET_CONFIG_REG 0x68 468 #define PACKET3_SET_CONFIG_REG_START 0x00002000 469 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 470 #define PACKET3_SET_CONTEXT_REG 0x69 471 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 472 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 473 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 474 #define PACKET3_SET_SH_REG 0x76 475 #define PACKET3_SET_SH_REG_START 0x00002c00 476 #define PACKET3_SET_SH_REG_END 0x00003000 477 #define PACKET3_SET_SH_REG_OFFSET 0x77 478 #define PACKET3_SET_QUEUE_REG 0x78 479 #define PACKET3_SET_UCONFIG_REG 0x79 480 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 481 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 482 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 483 #define PACKET3_SCRATCH_RAM_READ 0x7E 484 #define PACKET3_LOAD_CONST_RAM 0x80 485 #define PACKET3_WRITE_CONST_RAM 0x81 486 #define PACKET3_DUMP_CONST_RAM 0x83 487 #define PACKET3_INCREMENT_CE_COUNTER 0x84 488 #define PACKET3_INCREMENT_DE_COUNTER 0x85 489 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 490 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 491 #define PACKET3_SWITCH_BUFFER 0x8B 492 493 /* SDMA - first instance at 0xd000, second at 0xd800 */ 494 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 495 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 496 #define SDMA_MAX_INSTANCE 2 497 498 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 499 (((sub_op) & 0xFF) << 8) | \ 500 (((op) & 0xFF) << 0)) 501 /* sDMA opcodes */ 502 #define SDMA_OPCODE_NOP 0 503 # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 504 #define SDMA_OPCODE_COPY 1 505 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 506 # define SDMA_COPY_SUB_OPCODE_TILED 1 507 # define SDMA_COPY_SUB_OPCODE_SOA 3 508 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 509 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 510 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 511 #define SDMA_OPCODE_WRITE 2 512 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 513 # define SDMA_WRITE_SUB_OPCODE_TILED 1 514 #define SDMA_OPCODE_INDIRECT_BUFFER 4 515 #define SDMA_OPCODE_FENCE 5 516 #define SDMA_OPCODE_TRAP 6 517 #define SDMA_OPCODE_SEMAPHORE 7 518 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 519 /* 0 - increment 520 * 1 - write 1 521 */ 522 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 523 /* 0 - wait 524 * 1 - signal 525 */ 526 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 527 /* mailbox */ 528 #define SDMA_OPCODE_POLL_REG_MEM 8 529 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 530 /* 0 - wait_reg_mem 531 * 1 - wr_wait_wr_reg 532 */ 533 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 534 /* 0 - always 535 * 1 - < 536 * 2 - <= 537 * 3 - == 538 * 4 - != 539 * 5 - >= 540 * 6 - > 541 */ 542 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 543 /* 0 = register 544 * 1 = memory 545 */ 546 #define SDMA_OPCODE_COND_EXEC 9 547 #define SDMA_OPCODE_CONSTANT_FILL 11 548 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 549 /* 0 = byte fill 550 * 2 = DW fill 551 */ 552 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 553 #define SDMA_OPCODE_TIMESTAMP 13 554 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 555 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 556 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 557 #define SDMA_OPCODE_SRBM_WRITE 14 558 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 559 /* byte mask */ 560 561 #define VCE_CMD_NO_OP 0x00000000 562 #define VCE_CMD_END 0x00000001 563 #define VCE_CMD_IB 0x00000002 564 #define VCE_CMD_FENCE 0x00000003 565 #define VCE_CMD_TRAP 0x00000004 566 #define VCE_CMD_IB_AUTO 0x00000005 567 #define VCE_CMD_SEMAPHORE 0x00000006 568 569 /* if PTR32, these are the bases for scratch and lds */ 570 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 571 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 572 573 #define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) 574 575 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 576 enum { 577 MTYPE_CACHED = 0, 578 MTYPE_NONCACHED = 3 579 }; 580 581 /* mmPA_SC_RASTER_CONFIG mask */ 582 #define RB_MAP_PKR0(x) ((x) << 0) 583 #define RB_MAP_PKR0_MASK (0x3 << 0) 584 #define RB_MAP_PKR1(x) ((x) << 2) 585 #define RB_MAP_PKR1_MASK (0x3 << 2) 586 #define RB_XSEL2(x) ((x) << 4) 587 #define RB_XSEL2_MASK (0x3 << 4) 588 #define RB_XSEL (1 << 6) 589 #define RB_YSEL (1 << 7) 590 #define PKR_MAP(x) ((x) << 8) 591 #define PKR_MAP_MASK (0x3 << 8) 592 #define PKR_XSEL(x) ((x) << 10) 593 #define PKR_XSEL_MASK (0x3 << 10) 594 #define PKR_YSEL(x) ((x) << 12) 595 #define PKR_YSEL_MASK (0x3 << 12) 596 #define SC_MAP(x) ((x) << 16) 597 #define SC_MAP_MASK (0x3 << 16) 598 #define SC_XSEL(x) ((x) << 18) 599 #define SC_XSEL_MASK (0x3 << 18) 600 #define SC_YSEL(x) ((x) << 20) 601 #define SC_YSEL_MASK (0x3 << 20) 602 #define SE_MAP(x) ((x) << 24) 603 #define SE_MAP_MASK (0x3 << 24) 604 #define SE_XSEL(x) ((x) << 26) 605 #define SE_XSEL_MASK (0x3 << 26) 606 #define SE_YSEL(x) ((x) << 28) 607 #define SE_YSEL_MASK (0x3 << 28) 608 609 /* mmPA_SC_RASTER_CONFIG_1 mask */ 610 #define SE_PAIR_MAP(x) ((x) << 0) 611 #define SE_PAIR_MAP_MASK (0x3 << 0) 612 #define SE_PAIR_XSEL(x) ((x) << 2) 613 #define SE_PAIR_XSEL_MASK (0x3 << 2) 614 #define SE_PAIR_YSEL(x) ((x) << 4) 615 #define SE_PAIR_YSEL_MASK (0x3 << 4) 616 617 #endif 618