| /linux/Documentation/driver-api/fpga/ |
| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
32 FPGA Bridge
35 FPGA Bridges prevent spurious signals from going out of an FPGA or a
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| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
22 The struct fpga_image_info specifies what FPGA image to program. It is
26 How to program an FPGA using a region
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-fpga-manager | 13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
26 * power up = FPGA reports power is up
27 * reset = FPGA held in reset state
30 * write init = preparing FPGA for programming
31 * write init error = Error while preparing FPGA for programming
32 * write = FPGA ready to receive image data
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| H A D | sysfs-bus-mcb | 11 Description: The FPGA's revision number
17 Description: The FPGA's minor number
23 Description: The FPGA's model number
29 Description: The FPGA's name
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| H A D | sysfs-class-fpga-region | 5 Description: FPGA region id for compatibility check, e.g. compatibility
6 of the FPGA reconfiguration hardware and image. This value
8 FPGA region. This interface returns the compat_id value or
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| H A D | sysfs-class-ocxl | 44 Control whether the FPGA is reloaded on a link reset. Enabled
45 through a vendor-specific logic block on the FPGA.
48 0 Do not reload FPGA image from flash
49 1 Reload FPGA image from flash
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| H A D | sysfs-platform-dfl-fme | 5 Description: Read-only. One DFL FPGA device may have more than 1
7 number of ports on the FPGA device when read it.
13 Description: Read-only. It returns Bitstream (static FPGA region)
15 and other information of this static FPGA region.
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
23 information of this static FPGA region.
29 Description: Read-only. It returns cache size of this FPGA device.
35 Description: Read-only. It returns fabric version of this FPGA device.
44 this FPGA belongs to, only valid for integrated solution.
126 Description: Read-Only. It returns FPGA device temperature in millidegrees
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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| H A D | men-chameleon-bus.rst | 63 called Chameleon FPGA device found on some hardware produced my MEN Mikro
65 single FPGA and usually attached via some sort of PCI or PCIe link. Each
66 FPGA contains a header section describing the content of the FPGA. The
68 BAR, size in the FPGA, interrupt number and some other properties currently
75 Chameleon FPGA is attached to. Some IP Core drivers may need to interact with
125 device ids which identify the IP Core inside the FPGA. The driver structure
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| /linux/Documentation/fpga/ |
| H A D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
56 FPGA Interface Unit (FIU) represents a standalone functional unit for the
57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
75 and can be implemented in register regions of any FPGA device.
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| /linux/drivers/char/xillybus/ |
| H A D | Kconfig | 10 tristate "Xillybus generic FPGA interface"
16 programmable logic (FPGA). The driver probes the hardware for
28 with the FPGA. The module will be called xillybus_pcie.
43 tristate "XillyUSB: Xillybus generic FPGA interface for USB"
49 with the FPGA.
52 the FPGA. The module will be called xillyusb.
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| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
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| H A D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
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| H A D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
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| /linux/drivers/misc/altera-stapl/ |
| H A D | Kconfig | 2 comment "Altera FPGA firmware download module (requires I2C)"
6 tristate "Altera FPGA firmware download module"
9 An Altera FPGA module. Say Y when you want to support this tool.
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| /linux/drivers/fpga/tests/ |
| H A D | Kconfig | 2 tristate "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS
3 depends on FPGA && FPGA_REGION && FPGA_BRIDGE && KUNIT=y
6 This builds unit tests for the FPGA subsystem
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| /linux/Documentation/translations/zh_CN/arch/openrisc/ |
| H A D | openrisc_port.rst | 52 3) 在FPGA上运行（可选)
54 OpenRISC社区通常使用FuseSoC来管理构建和编程SoC到FPGA中。 下面是用
56 FPGA RTL是从FuseSoC IP核库中下载的代码，并使用FPGA供应商工具构建。
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| /linux/Documentation/translations/zh_TW/arch/openrisc/ |
| H A D | openrisc_port.rst | 52 3) 在FPGA上運行（可選)
54 OpenRISC社區通常使用FuseSoC來管理構建和編程SoC到FPGA中。 下面是用
56 FPGA RTL是從FuseSoC IP核庫中下載的代碼，並使用FPGA供應商工具構建。
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| /linux/drivers/net/can/ctucanfd/ |
| H A D | Kconfig | 9 Implementation on Intel FPGA-based PCI Express board is available
20 The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
25 tristate "CTU CAN-FD IP core platform (FPGA, SoC) driver"
32 company. FPGA design https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top.
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| /linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-misc-cp500 | 5 Description: Version of the FPGA configuration bitstream as printable string.
13 Description: Flag which signals if FPGA shall keep or reload configuration
14 bitstream on reset. Normal FPGA behavior and default is to keep
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| /linux/Documentation/devicetree/bindings/powerpc/4xx/ |
| H A D | akebono.txt | 34 1.c) The FPGA node
37 number in an FPGA which is represented by this node.
42 - reg : should contain the FPGA registers location and length.
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| /linux/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | ts4800-ts.txt | 8 describes the FPGA's syscon registers.
9 - phandle to FPGA's syscon
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | ts4800-wdt.txt | 6 describes the FPGA's syscon registers.
7 - phandle to FPGA's syscon
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | gef_sbc610.dts | 35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
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