1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * UCSI driver for Cypress CCGx Type-C controller
4 *
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
7 *
8 * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
9 */
10 #include <linux/acpi.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/hex.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/usb/typec_dp.h>
21
22 #include <linux/unaligned.h>
23 #include "ucsi.h"
24
25 enum enum_fw_mode {
26 BOOT, /* bootloader */
27 FW1, /* FW partition-1 (contains secondary fw) */
28 FW2, /* FW partition-2 (contains primary fw) */
29 FW_INVALID,
30 };
31
32 #define CCGX_RAB_DEVICE_MODE 0x0000
33 #define CCGX_RAB_INTR_REG 0x0006
34 #define DEV_INT BIT(0)
35 #define PORT0_INT BIT(1)
36 #define PORT1_INT BIT(2)
37 #define UCSI_READ_INT BIT(7)
38 #define CCGX_RAB_JUMP_TO_BOOT 0x0007
39 #define TO_BOOT 'J'
40 #define TO_ALT_FW 'A'
41 #define CCGX_RAB_RESET_REQ 0x0008
42 #define RESET_SIG 'R'
43 #define CMD_RESET_I2C 0x0
44 #define CMD_RESET_DEV 0x1
45 #define CCGX_RAB_ENTER_FLASHING 0x000A
46 #define FLASH_ENTER_SIG 'P'
47 #define CCGX_RAB_VALIDATE_FW 0x000B
48 #define CCGX_RAB_FLASH_ROW_RW 0x000C
49 #define FLASH_SIG 'F'
50 #define FLASH_RD_CMD 0x0
51 #define FLASH_WR_CMD 0x1
52 #define FLASH_FWCT1_WR_CMD 0x2
53 #define FLASH_FWCT2_WR_CMD 0x3
54 #define FLASH_FWCT_SIG_WR_CMD 0x4
55 #define CCGX_RAB_READ_ALL_VER 0x0010
56 #define CCGX_RAB_READ_FW2_VER 0x0020
57 #define CCGX_RAB_UCSI_CONTROL 0x0039
58 #define CCGX_RAB_UCSI_CONTROL_START BIT(0)
59 #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
60 #define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
61 #define REG_FLASH_RW_MEM 0x0200
62 #define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
63 #define CCGX_RAB_PDPORT_ENABLE 0x002C
64 #define PDPORT_1 BIT(0)
65 #define PDPORT_2 BIT(1)
66 #define CCGX_RAB_RESPONSE 0x007E
67 #define ASYNC_EVENT BIT(7)
68
69 /* CCGx events & async msg codes */
70 #define RESET_COMPLETE 0x80
71 #define EVENT_INDEX RESET_COMPLETE
72 #define PORT_CONNECT_DET 0x84
73 #define PORT_DISCONNECT_DET 0x85
74 #define ROLE_SWAP_COMPELETE 0x87
75
76 /* ccg firmware */
77 #define CYACD_LINE_SIZE 527
78 #define CCG4_ROW_SIZE 256
79 #define FW1_METADATA_ROW 0x1FF
80 #define FW2_METADATA_ROW 0x1FE
81 #define FW_CFG_TABLE_SIG_SIZE 256
82
83 static int secondary_fw_min_ver = 41;
84
85 enum enum_flash_mode {
86 SECONDARY_BL, /* update secondary using bootloader */
87 PRIMARY, /* update primary using secondary */
88 SECONDARY, /* update secondary using primary */
89 FLASH_NOT_NEEDED, /* update not required */
90 FLASH_INVALID,
91 };
92
93 static const char * const ccg_fw_names[] = {
94 "ccg_boot.cyacd",
95 "ccg_primary.cyacd",
96 "ccg_secondary.cyacd"
97 };
98
99 struct ccg_dev_info {
100 #define CCG_DEVINFO_FWMODE_SHIFT (0)
101 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
102 #define CCG_DEVINFO_PDPORTS_SHIFT (2)
103 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
104 u8 mode;
105 u8 bl_mode;
106 __le16 silicon_id;
107 __le16 bl_last_row;
108 } __packed;
109
110 struct version_format {
111 __le16 build;
112 u8 patch;
113 u8 ver;
114 #define CCG_VERSION_PATCH(x) ((x) << 16)
115 #define CCG_VERSION(x) ((x) << 24)
116 #define CCG_VERSION_MIN_SHIFT (0)
117 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
118 #define CCG_VERSION_MAJ_SHIFT (4)
119 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
120 } __packed;
121
122 /*
123 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
124 * of missing interrupt when a device is connected for runtime resume
125 */
126 #define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
127 #define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
128
129 /* Firmware for Tegra doesn't support UCSI ALT command, built
130 * for NVIDIA has known issue of reporting wrong capability info
131 */
132 #define CCG_FW_BUILD_NVIDIA_TEGRA (('g' << 8) | 'n')
133
134 /* Altmode offset for NVIDIA Function Test Board (FTB) */
135 #define NVIDIA_FTB_DP_OFFSET (2)
136 #define NVIDIA_FTB_DBG_OFFSET (3)
137
138 struct version_info {
139 struct version_format base;
140 struct version_format app;
141 };
142
143 struct fw_config_table {
144 u32 identity;
145 u16 table_size;
146 u8 fwct_version;
147 u8 is_key_change;
148 u8 guid[16];
149 struct version_format base;
150 struct version_format app;
151 u8 primary_fw_digest[32];
152 u32 key_exp_length;
153 u8 key_modulus[256];
154 u8 key_exp[4];
155 };
156
157 /* CCGx response codes */
158 enum ccg_resp_code {
159 CMD_NO_RESP = 0x00,
160 CMD_SUCCESS = 0x02,
161 FLASH_DATA_AVAILABLE = 0x03,
162 CMD_INVALID = 0x05,
163 FLASH_UPDATE_FAIL = 0x07,
164 INVALID_FW = 0x08,
165 INVALID_ARG = 0x09,
166 CMD_NOT_SUPPORT = 0x0A,
167 TRANSACTION_FAIL = 0x0C,
168 PD_CMD_FAIL = 0x0D,
169 UNDEF_ERROR = 0x0F,
170 INVALID_RESP = 0x10,
171 };
172
173 #define CCG_EVENT_MAX (EVENT_INDEX + 43)
174
175 struct ccg_cmd {
176 u16 reg;
177 u32 data;
178 int len;
179 u32 delay; /* ms delay for cmd timeout */
180 };
181
182 struct ccg_resp {
183 u8 code;
184 u8 length;
185 };
186
187 struct ucsi_ccg_altmode {
188 u16 svid;
189 u32 mid;
190 u8 linked_idx;
191 u8 active_idx;
192 #define UCSI_MULTI_DP_INDEX (0xff)
193 bool checked;
194 } __packed;
195
196 #define CCGX_MESSAGE_IN_MAX 4
197 struct op_region {
198 __le32 cci;
199 __le32 message_in[CCGX_MESSAGE_IN_MAX];
200 };
201
202 struct ucsi_ccg {
203 struct device *dev;
204 struct ucsi *ucsi;
205 struct i2c_client *client;
206
207 struct ccg_dev_info info;
208 /* version info for boot, primary and secondary */
209 struct version_info version[FW2 + 1];
210 u32 fw_version;
211 /* CCG HPI communication flags */
212 unsigned long flags;
213 #define RESET_PENDING 0
214 #define DEV_CMD_PENDING 1
215 struct ccg_resp dev_resp;
216 u8 cmd_resp;
217 int port_num;
218 int irq;
219 struct work_struct work;
220 struct mutex lock; /* to sync between user and driver thread */
221
222 /* fw build with vendor information */
223 u16 fw_build;
224 struct work_struct pm_work;
225
226 bool has_multiple_dp;
227 struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES];
228 struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES];
229
230 /*
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
232 * will be updated in ISR
233 */
234 spinlock_t op_lock;
235 struct op_region op_data;
236 };
237
ccg_read(struct ucsi_ccg * uc,u16 rab,u8 * data,u32 len)238 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
239 {
240 struct i2c_client *client = uc->client;
241 const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
242 unsigned char buf[2];
243 struct i2c_msg msgs[] = {
244 {
245 .addr = client->addr,
246 .flags = 0x0,
247 .len = sizeof(buf),
248 .buf = buf,
249 },
250 {
251 .addr = client->addr,
252 .flags = I2C_M_RD,
253 .buf = data,
254 },
255 };
256 u32 rlen, rem_len = len, max_read_len = len;
257 int status;
258
259 /* check any max_read_len limitation on i2c adapter */
260 if (quirks && quirks->max_read_len)
261 max_read_len = quirks->max_read_len;
262
263 pm_runtime_get_sync(uc->dev);
264 while (rem_len > 0) {
265 msgs[1].buf = &data[len - rem_len];
266 rlen = min_t(u16, rem_len, max_read_len);
267 msgs[1].len = rlen;
268 put_unaligned_le16(rab, buf);
269 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
270 if (status < 0) {
271 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
272 pm_runtime_put_sync(uc->dev);
273 return status;
274 }
275 rab += rlen;
276 rem_len -= rlen;
277 }
278
279 pm_runtime_put_sync(uc->dev);
280 return 0;
281 }
282
ccg_write(struct ucsi_ccg * uc,u16 rab,const u8 * data,u32 len)283 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
284 {
285 struct i2c_client *client = uc->client;
286 unsigned char *buf;
287 struct i2c_msg msgs[] = {
288 {
289 .addr = client->addr,
290 .flags = 0x0,
291 }
292 };
293 int status;
294
295 buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
296 if (!buf)
297 return -ENOMEM;
298
299 put_unaligned_le16(rab, buf);
300 memcpy(buf + sizeof(rab), data, len);
301
302 msgs[0].len = len + sizeof(rab);
303 msgs[0].buf = buf;
304
305 pm_runtime_get_sync(uc->dev);
306 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
307 if (status < 0) {
308 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
309 pm_runtime_put_sync(uc->dev);
310 kfree(buf);
311 return status;
312 }
313
314 pm_runtime_put_sync(uc->dev);
315 kfree(buf);
316 return 0;
317 }
318
ccg_op_region_update(struct ucsi_ccg * uc,u32 cci)319 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci)
320 {
321 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_MESSAGE_IN);
322 struct op_region *data = &uc->op_data;
323 unsigned char *buf;
324 size_t size = sizeof(data->message_in);
325
326 buf = kzalloc(size, GFP_ATOMIC);
327 if (!buf)
328 return -ENOMEM;
329 if (UCSI_CCI_LENGTH(cci)) {
330 int ret = ccg_read(uc, reg, (void *)buf, size);
331
332 if (ret) {
333 kfree(buf);
334 return ret;
335 }
336 }
337
338 spin_lock(&uc->op_lock);
339 data->cci = cpu_to_le32(cci);
340 if (UCSI_CCI_LENGTH(cci))
341 memcpy(&data->message_in, buf, size);
342 spin_unlock(&uc->op_lock);
343 kfree(buf);
344 return 0;
345 }
346
ucsi_ccg_init(struct ucsi_ccg * uc)347 static int ucsi_ccg_init(struct ucsi_ccg *uc)
348 {
349 unsigned int count = 10;
350 u8 data;
351 int status;
352
353 spin_lock_init(&uc->op_lock);
354
355 data = CCGX_RAB_UCSI_CONTROL_STOP;
356 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
357 if (status < 0)
358 return status;
359
360 data = CCGX_RAB_UCSI_CONTROL_START;
361 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
362 if (status < 0)
363 return status;
364
365 /*
366 * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
367 * register write will push response which must be cleared.
368 */
369 do {
370 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
371 if (status < 0)
372 return status;
373
374 if (!(data & DEV_INT))
375 return 0;
376
377 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
378 if (status < 0)
379 return status;
380
381 usleep_range(10000, 11000);
382 } while (--count);
383
384 return -ETIMEDOUT;
385 }
386
ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg * uc,u8 * data)387 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
388 {
389 u8 cam, new_cam;
390
391 cam = data[0];
392 new_cam = uc->orig[cam].linked_idx;
393 uc->updated[new_cam].active_idx = cam;
394 data[0] = new_cam;
395 }
396
ucsi_ccg_update_altmodes(struct ucsi * ucsi,u8 recipient,struct ucsi_altmode * orig,struct ucsi_altmode * updated)397 static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi,
398 u8 recipient,
399 struct ucsi_altmode *orig,
400 struct ucsi_altmode *updated)
401 {
402 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
403 struct ucsi_ccg_altmode *alt, *new_alt;
404 int i, j, k = 0;
405 bool found = false;
406
407 if (recipient != UCSI_RECIPIENT_CON)
408 return false;
409
410 alt = uc->orig;
411 new_alt = uc->updated;
412 memset(uc->updated, 0, sizeof(uc->updated));
413
414 /*
415 * Copy original connector altmodes to new structure.
416 * We need this before second loop since second loop
417 * checks for duplicate altmodes.
418 */
419 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
420 alt[i].svid = orig[i].svid;
421 alt[i].mid = orig[i].mid;
422 if (!alt[i].svid)
423 break;
424 }
425
426 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
427 if (!alt[i].svid)
428 break;
429
430 /* already checked and considered */
431 if (alt[i].checked)
432 continue;
433
434 if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) {
435 /* Found Non DP altmode */
436 new_alt[k].svid = alt[i].svid;
437 new_alt[k].mid |= alt[i].mid;
438 new_alt[k].linked_idx = i;
439 alt[i].linked_idx = k;
440 updated[k].svid = new_alt[k].svid;
441 updated[k].mid = new_alt[k].mid;
442 k++;
443 continue;
444 }
445
446 for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) {
447 if (alt[i].svid != alt[j].svid ||
448 !DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) {
449 continue;
450 } else {
451 /* Found duplicate DP mode */
452 new_alt[k].svid = alt[i].svid;
453 new_alt[k].mid |= alt[i].mid | alt[j].mid;
454 new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
455 alt[i].linked_idx = k;
456 alt[j].linked_idx = k;
457 alt[j].checked = true;
458 found = true;
459 }
460 }
461 if (found) {
462 uc->has_multiple_dp = true;
463 } else {
464 /* Didn't find any duplicate DP altmode */
465 new_alt[k].svid = alt[i].svid;
466 new_alt[k].mid |= alt[i].mid;
467 new_alt[k].linked_idx = i;
468 alt[i].linked_idx = k;
469 }
470 updated[k].svid = new_alt[k].svid;
471 updated[k].mid = new_alt[k].mid;
472 k++;
473 }
474 return found;
475 }
476
ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg * uc,struct ucsi_connector * con,u64 * cmd)477 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
478 struct ucsi_connector *con,
479 u64 *cmd)
480 {
481 struct ucsi_ccg_altmode *new_port, *port;
482 struct typec_altmode *alt = NULL;
483 u8 new_cam, cam, pin;
484 bool enter_new_mode;
485 int i, j, k = 0xff;
486
487 port = uc->orig;
488 new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd);
489 if (new_cam >= ARRAY_SIZE(uc->updated))
490 return;
491 new_port = &uc->updated[new_cam];
492 cam = new_port->linked_idx;
493 enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd);
494
495 /*
496 * If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode
497 * with multiple DP mode. Find out CAM for best pin assignment
498 * among all DP mode. Priorite pin E->D->C after making sure
499 * the partner supports that pin.
500 */
501 if (cam == UCSI_MULTI_DP_INDEX) {
502 if (enter_new_mode) {
503 for (i = 0; con->partner_altmode[i]; i++) {
504 alt = con->partner_altmode[i];
505 if (alt->svid == new_port->svid)
506 break;
507 }
508 /*
509 * alt will always be non NULL since this is
510 * UCSI_SET_NEW_CAM command and so there will be
511 * at least one con->partner_altmode[i] with svid
512 * matching with new_port->svid.
513 */
514 for (j = 0; port[j].svid; j++) {
515 pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid);
516 if (alt && port[j].svid == alt->svid &&
517 (pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) {
518 /* prioritize pin E->D->C */
519 if (k == 0xff || (k != 0xff && pin >
520 DP_CONF_GET_PIN_ASSIGN(port[k].mid))
521 ) {
522 k = j;
523 }
524 }
525 }
526 cam = k;
527 new_port->active_idx = cam;
528 } else {
529 cam = new_port->active_idx;
530 }
531 }
532 *cmd &= ~UCSI_SET_NEW_CAM_AM_MASK;
533 *cmd |= UCSI_SET_NEW_CAM_SET_AM(cam);
534 }
535
536 /*
537 * Change the order of vdo values of NVIDIA test device FTB
538 * (Function Test Board) which reports altmode list with vdo=0x3
539 * first and then vdo=0x. Current logic to assign mode value is
540 * based on order in altmode list and it causes a mismatch of CON
541 * and SOP altmodes since NVIDIA GPU connector has order of vdo=0x1
542 * first and then vdo=0x3
543 */
ucsi_ccg_nvidia_altmode(struct ucsi_ccg * uc,struct ucsi_altmode * alt,u64 command)544 static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc,
545 struct ucsi_altmode *alt,
546 u64 command)
547 {
548 switch (UCSI_ALTMODE_OFFSET(command)) {
549 case NVIDIA_FTB_DP_OFFSET:
550 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DBG_VDO)
551 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DP_VDO |
552 DP_CAP_DP_SIGNALLING(0) | DP_CAP_USB |
553 DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_E));
554 break;
555 case NVIDIA_FTB_DBG_OFFSET:
556 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DP_VDO)
557 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DBG_VDO;
558 break;
559 default:
560 break;
561 }
562 }
563
ucsi_ccg_read_version(struct ucsi * ucsi,u16 * version)564 static int ucsi_ccg_read_version(struct ucsi *ucsi, u16 *version)
565 {
566 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
567 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_VERSION);
568
569 return ccg_read(uc, reg, (u8 *)version, sizeof(*version));
570 }
571
ucsi_ccg_read_cci(struct ucsi * ucsi,u32 * cci)572 static int ucsi_ccg_read_cci(struct ucsi *ucsi, u32 *cci)
573 {
574 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
575
576 spin_lock(&uc->op_lock);
577 *cci = uc->op_data.cci;
578 spin_unlock(&uc->op_lock);
579
580 return 0;
581 }
582
ucsi_ccg_read_message_in(struct ucsi * ucsi,void * val,size_t val_len)583 static int ucsi_ccg_read_message_in(struct ucsi *ucsi, void *val, size_t val_len)
584 {
585 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
586
587 spin_lock(&uc->op_lock);
588 memcpy(val, uc->op_data.message_in, val_len);
589 spin_unlock(&uc->op_lock);
590
591 return 0;
592 }
593
ucsi_ccg_async_control(struct ucsi * ucsi,u64 command)594 static int ucsi_ccg_async_control(struct ucsi *ucsi, u64 command)
595 {
596 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
597 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CONTROL);
598
599 /*
600 * UCSI may read CCI instantly after async_control,
601 * clear CCI to avoid caller getting wrong data before we get CCI from ISR
602 */
603 spin_lock(&uc->op_lock);
604 uc->op_data.cci = 0;
605 spin_unlock(&uc->op_lock);
606
607 return ccg_write(uc, reg, (u8 *)&command, sizeof(command));
608 }
609
ucsi_ccg_sync_control(struct ucsi * ucsi,u64 command,u32 * cci,void * data,size_t size,void * msg_out,size_t msg_out_size)610 static int ucsi_ccg_sync_control(struct ucsi *ucsi, u64 command, u32 *cci,
611 void *data, size_t size, void *msg_out,
612 size_t msg_out_size)
613 {
614 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
615 struct ucsi_connector *con;
616 int con_index;
617 int ret;
618
619 mutex_lock(&uc->lock);
620 pm_runtime_get_sync(uc->dev);
621
622 if (UCSI_COMMAND(command) == UCSI_SET_NEW_CAM &&
623 uc->has_multiple_dp) {
624 con_index = (command >> 16) &
625 UCSI_CMD_CONNECTOR_MASK;
626 if (con_index == 0) {
627 ret = -EINVAL;
628 goto err_put;
629 }
630 con = &uc->ucsi->connector[con_index - 1];
631 ucsi_ccg_update_set_new_cam_cmd(uc, con, &command);
632 }
633
634 ret = ucsi_sync_control_common(ucsi, command, cci, data, size,
635 msg_out, msg_out_size);
636
637 switch (UCSI_COMMAND(command)) {
638 case UCSI_GET_CURRENT_CAM:
639 if (uc->has_multiple_dp)
640 ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)data);
641 break;
642 case UCSI_GET_ALTERNATE_MODES:
643 if (UCSI_ALTMODE_RECIPIENT(command) == UCSI_RECIPIENT_SOP) {
644 struct ucsi_altmode *alt = data;
645
646 if (alt[0].svid == USB_TYPEC_NVIDIA_VLINK_SID)
647 ucsi_ccg_nvidia_altmode(uc, alt, command);
648 }
649 break;
650 case UCSI_GET_CAPABILITY:
651 if (uc->fw_build == CCG_FW_BUILD_NVIDIA_TEGRA) {
652 struct ucsi_capability *cap = data;
653
654 cap->features &= ~UCSI_CAP_ALT_MODE_DETAILS;
655 }
656 break;
657 default:
658 break;
659 }
660
661 err_put:
662 pm_runtime_put_sync(uc->dev);
663 mutex_unlock(&uc->lock);
664
665 return ret;
666 }
667
668 static const struct ucsi_operations ucsi_ccg_ops = {
669 .read_version = ucsi_ccg_read_version,
670 .read_cci = ucsi_ccg_read_cci,
671 .poll_cci = ucsi_ccg_read_cci,
672 .read_message_in = ucsi_ccg_read_message_in,
673 .sync_control = ucsi_ccg_sync_control,
674 .async_control = ucsi_ccg_async_control,
675 .update_altmodes = ucsi_ccg_update_altmodes
676 };
677
ccg_irq_handler(int irq,void * data)678 static irqreturn_t ccg_irq_handler(int irq, void *data)
679 {
680 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
681 struct ucsi_ccg *uc = data;
682 u8 intr_reg;
683 u32 cci = 0;
684 int ret = 0;
685
686 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
687 if (ret)
688 return ret;
689
690 if (!intr_reg)
691 return IRQ_HANDLED;
692 else if (!(intr_reg & UCSI_READ_INT))
693 goto err_clear_irq;
694
695 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
696 if (ret)
697 goto err_clear_irq;
698
699 /*
700 * As per CCGx UCSI interface guide, copy CCI and MESSAGE_IN
701 * to the OpRegion before clear the UCSI interrupt
702 */
703 ret = ccg_op_region_update(uc, cci);
704 if (ret)
705 goto err_clear_irq;
706
707 err_clear_irq:
708 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
709
710 if (!ret)
711 ucsi_notify_common(uc->ucsi, cci);
712
713 return IRQ_HANDLED;
714 }
715
ccg_request_irq(struct ucsi_ccg * uc)716 static int ccg_request_irq(struct ucsi_ccg *uc)
717 {
718 unsigned long flags = IRQF_ONESHOT;
719
720 if (!dev_fwnode(uc->dev))
721 flags |= IRQF_TRIGGER_HIGH;
722
723 return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc);
724 }
725
ccg_pm_workaround_work(struct work_struct * pm_work)726 static void ccg_pm_workaround_work(struct work_struct *pm_work)
727 {
728 ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
729 }
730
get_fw_info(struct ucsi_ccg * uc)731 static int get_fw_info(struct ucsi_ccg *uc)
732 {
733 int err;
734
735 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
736 sizeof(uc->version));
737 if (err < 0)
738 return err;
739
740 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
741 CCG_VERSION_PATCH(uc->version[FW2].app.patch);
742
743 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
744 sizeof(uc->info));
745 if (err < 0)
746 return err;
747
748 return 0;
749 }
750
invalid_async_evt(int code)751 static inline bool invalid_async_evt(int code)
752 {
753 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
754 }
755
ccg_process_response(struct ucsi_ccg * uc)756 static void ccg_process_response(struct ucsi_ccg *uc)
757 {
758 struct device *dev = uc->dev;
759
760 if (uc->dev_resp.code & ASYNC_EVENT) {
761 if (uc->dev_resp.code == RESET_COMPLETE) {
762 if (test_bit(RESET_PENDING, &uc->flags))
763 uc->cmd_resp = uc->dev_resp.code;
764 get_fw_info(uc);
765 }
766 if (invalid_async_evt(uc->dev_resp.code))
767 dev_err(dev, "invalid async evt %d\n",
768 uc->dev_resp.code);
769 } else {
770 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
771 uc->cmd_resp = uc->dev_resp.code;
772 clear_bit(DEV_CMD_PENDING, &uc->flags);
773 } else {
774 dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
775 uc->dev_resp.code);
776 }
777 }
778 }
779
ccg_read_response(struct ucsi_ccg * uc)780 static int ccg_read_response(struct ucsi_ccg *uc)
781 {
782 unsigned long target = jiffies + msecs_to_jiffies(1000);
783 struct device *dev = uc->dev;
784 u8 intval;
785 int status;
786
787 /* wait for interrupt status to get updated */
788 do {
789 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
790 sizeof(intval));
791 if (status < 0)
792 return status;
793
794 if (intval & DEV_INT)
795 break;
796 usleep_range(500, 600);
797 } while (time_is_after_jiffies(target));
798
799 if (time_is_before_jiffies(target)) {
800 dev_err(dev, "response timeout error\n");
801 return -ETIME;
802 }
803
804 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
805 sizeof(uc->dev_resp));
806 if (status < 0)
807 return status;
808
809 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
810 if (status < 0)
811 return status;
812
813 return 0;
814 }
815
816 /* Caller must hold uc->lock */
ccg_send_command(struct ucsi_ccg * uc,struct ccg_cmd * cmd)817 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
818 {
819 struct device *dev = uc->dev;
820 int ret;
821
822 switch (cmd->reg & 0xF000) {
823 case DEV_REG_IDX:
824 set_bit(DEV_CMD_PENDING, &uc->flags);
825 break;
826 default:
827 dev_err(dev, "invalid cmd register\n");
828 break;
829 }
830
831 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
832 if (ret < 0)
833 return ret;
834
835 msleep(cmd->delay);
836
837 ret = ccg_read_response(uc);
838 if (ret < 0) {
839 dev_err(dev, "response read error\n");
840 switch (cmd->reg & 0xF000) {
841 case DEV_REG_IDX:
842 clear_bit(DEV_CMD_PENDING, &uc->flags);
843 break;
844 default:
845 dev_err(dev, "invalid cmd register\n");
846 break;
847 }
848 return -EIO;
849 }
850 ccg_process_response(uc);
851
852 return uc->cmd_resp;
853 }
854
ccg_cmd_enter_flashing(struct ucsi_ccg * uc)855 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
856 {
857 struct ccg_cmd cmd;
858 int ret;
859
860 cmd.reg = CCGX_RAB_ENTER_FLASHING;
861 cmd.data = FLASH_ENTER_SIG;
862 cmd.len = 1;
863 cmd.delay = 50;
864
865 mutex_lock(&uc->lock);
866
867 ret = ccg_send_command(uc, &cmd);
868
869 mutex_unlock(&uc->lock);
870
871 if (ret != CMD_SUCCESS) {
872 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
873 return ret;
874 }
875
876 return 0;
877 }
878
ccg_cmd_reset(struct ucsi_ccg * uc)879 static int ccg_cmd_reset(struct ucsi_ccg *uc)
880 {
881 struct ccg_cmd cmd;
882 u8 *p;
883 int ret;
884
885 p = (u8 *)&cmd.data;
886 cmd.reg = CCGX_RAB_RESET_REQ;
887 p[0] = RESET_SIG;
888 p[1] = CMD_RESET_DEV;
889 cmd.len = 2;
890 cmd.delay = 5000;
891
892 mutex_lock(&uc->lock);
893
894 set_bit(RESET_PENDING, &uc->flags);
895
896 ret = ccg_send_command(uc, &cmd);
897 if (ret != RESET_COMPLETE)
898 goto err_clear_flag;
899
900 ret = 0;
901
902 err_clear_flag:
903 clear_bit(RESET_PENDING, &uc->flags);
904
905 mutex_unlock(&uc->lock);
906
907 return ret;
908 }
909
ccg_cmd_port_control(struct ucsi_ccg * uc,bool enable)910 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
911 {
912 struct ccg_cmd cmd;
913 int ret;
914
915 cmd.reg = CCGX_RAB_PDPORT_ENABLE;
916 if (enable)
917 cmd.data = (uc->port_num == 1) ?
918 PDPORT_1 : (PDPORT_1 | PDPORT_2);
919 else
920 cmd.data = 0x0;
921 cmd.len = 1;
922 cmd.delay = 10;
923
924 mutex_lock(&uc->lock);
925
926 ret = ccg_send_command(uc, &cmd);
927
928 mutex_unlock(&uc->lock);
929
930 if (ret != CMD_SUCCESS) {
931 dev_err(uc->dev, "port control failed ret=%d\n", ret);
932 return ret;
933 }
934 return 0;
935 }
936
ccg_cmd_jump_boot_mode(struct ucsi_ccg * uc,int bl_mode)937 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
938 {
939 struct ccg_cmd cmd;
940 int ret;
941
942 cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
943
944 if (bl_mode)
945 cmd.data = TO_BOOT;
946 else
947 cmd.data = TO_ALT_FW;
948
949 cmd.len = 1;
950 cmd.delay = 100;
951
952 mutex_lock(&uc->lock);
953
954 set_bit(RESET_PENDING, &uc->flags);
955
956 ret = ccg_send_command(uc, &cmd);
957 if (ret != RESET_COMPLETE)
958 goto err_clear_flag;
959
960 ret = 0;
961
962 err_clear_flag:
963 clear_bit(RESET_PENDING, &uc->flags);
964
965 mutex_unlock(&uc->lock);
966
967 return ret;
968 }
969
970 static int
ccg_cmd_write_flash_row(struct ucsi_ccg * uc,u16 row,const void * data,u8 fcmd)971 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
972 const void *data, u8 fcmd)
973 {
974 struct i2c_client *client = uc->client;
975 struct ccg_cmd cmd;
976 u8 buf[CCG4_ROW_SIZE + 2];
977 u8 *p;
978 int ret;
979
980 /* Copy the data into the flash read/write memory. */
981 put_unaligned_le16(REG_FLASH_RW_MEM, buf);
982
983 memcpy(buf + 2, data, CCG4_ROW_SIZE);
984
985 mutex_lock(&uc->lock);
986
987 ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
988 if (ret != CCG4_ROW_SIZE + 2) {
989 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
990 mutex_unlock(&uc->lock);
991 return ret < 0 ? ret : -EIO;
992 }
993
994 /* Use the FLASH_ROW_READ_WRITE register to trigger */
995 /* writing of data to the desired flash row */
996 p = (u8 *)&cmd.data;
997 cmd.reg = CCGX_RAB_FLASH_ROW_RW;
998 p[0] = FLASH_SIG;
999 p[1] = fcmd;
1000 put_unaligned_le16(row, &p[2]);
1001 cmd.len = 4;
1002 cmd.delay = 50;
1003 if (fcmd == FLASH_FWCT_SIG_WR_CMD)
1004 cmd.delay += 400;
1005 if (row == 510)
1006 cmd.delay += 220;
1007 ret = ccg_send_command(uc, &cmd);
1008
1009 mutex_unlock(&uc->lock);
1010
1011 if (ret != CMD_SUCCESS) {
1012 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
1013 return ret;
1014 }
1015
1016 return 0;
1017 }
1018
ccg_cmd_validate_fw(struct ucsi_ccg * uc,unsigned int fwid)1019 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
1020 {
1021 struct ccg_cmd cmd;
1022 int ret;
1023
1024 cmd.reg = CCGX_RAB_VALIDATE_FW;
1025 cmd.data = fwid;
1026 cmd.len = 1;
1027 cmd.delay = 500;
1028
1029 mutex_lock(&uc->lock);
1030
1031 ret = ccg_send_command(uc, &cmd);
1032
1033 mutex_unlock(&uc->lock);
1034
1035 if (ret != CMD_SUCCESS)
1036 return ret;
1037
1038 return 0;
1039 }
1040
ccg_check_vendor_version(struct ucsi_ccg * uc,struct version_format * app,struct fw_config_table * fw_cfg)1041 static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
1042 struct version_format *app,
1043 struct fw_config_table *fw_cfg)
1044 {
1045 struct device *dev = uc->dev;
1046
1047 /* Check if the fw build is for supported vendors */
1048 if (le16_to_cpu(app->build) != uc->fw_build) {
1049 dev_info(dev, "current fw is not from supported vendor\n");
1050 return false;
1051 }
1052
1053 /* Check if the new fw build is for supported vendors */
1054 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
1055 dev_info(dev, "new fw is not from supported vendor\n");
1056 return false;
1057 }
1058 return true;
1059 }
1060
ccg_check_fw_version(struct ucsi_ccg * uc,const char * fw_name,struct version_format * app)1061 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
1062 struct version_format *app)
1063 {
1064 const struct firmware *fw = NULL;
1065 struct device *dev = uc->dev;
1066 struct fw_config_table fw_cfg;
1067 u32 cur_version, new_version;
1068 bool is_later = false;
1069
1070 if (request_firmware(&fw, fw_name, dev) != 0) {
1071 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
1072 return false;
1073 }
1074
1075 /*
1076 * check if signed fw
1077 * last part of fw image is fw cfg table and signature
1078 */
1079 if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
1080 goto out_release_firmware;
1081
1082 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1083 sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
1084
1085 if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
1086 dev_info(dev, "not a signed image\n");
1087 goto out_release_firmware;
1088 }
1089
1090 /* compare input version with FWCT version */
1091 cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
1092 CCG_VERSION(app->ver);
1093
1094 new_version = le16_to_cpu(fw_cfg.app.build) |
1095 CCG_VERSION_PATCH(fw_cfg.app.patch) |
1096 CCG_VERSION(fw_cfg.app.ver);
1097
1098 if (!ccg_check_vendor_version(uc, app, &fw_cfg))
1099 goto out_release_firmware;
1100
1101 if (new_version > cur_version)
1102 is_later = true;
1103
1104 out_release_firmware:
1105 release_firmware(fw);
1106 return is_later;
1107 }
1108
ccg_fw_update_needed(struct ucsi_ccg * uc,enum enum_flash_mode * mode)1109 static int ccg_fw_update_needed(struct ucsi_ccg *uc,
1110 enum enum_flash_mode *mode)
1111 {
1112 struct device *dev = uc->dev;
1113 int err;
1114 struct version_info version[3];
1115
1116 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
1117 sizeof(uc->info));
1118 if (err) {
1119 dev_err(dev, "read device mode failed\n");
1120 return err;
1121 }
1122
1123 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
1124 sizeof(version));
1125 if (err) {
1126 dev_err(dev, "read device mode failed\n");
1127 return err;
1128 }
1129
1130 if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
1131 sizeof(struct version_info)) == 0) {
1132 dev_info(dev, "secondary fw is not flashed\n");
1133 *mode = SECONDARY_BL;
1134 } else if (le16_to_cpu(version[FW1].base.build) <
1135 secondary_fw_min_ver) {
1136 dev_info(dev, "secondary fw version is too low (< %d)\n",
1137 secondary_fw_min_ver);
1138 *mode = SECONDARY;
1139 } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
1140 sizeof(struct version_info)) == 0) {
1141 dev_info(dev, "primary fw is not flashed\n");
1142 *mode = PRIMARY;
1143 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
1144 &version[FW2].app)) {
1145 dev_info(dev, "found primary fw with later version\n");
1146 *mode = PRIMARY;
1147 } else {
1148 dev_info(dev, "secondary and primary fw are the latest\n");
1149 *mode = FLASH_NOT_NEEDED;
1150 }
1151 return 0;
1152 }
1153
do_flash(struct ucsi_ccg * uc,enum enum_flash_mode mode)1154 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
1155 {
1156 struct device *dev = uc->dev;
1157 const struct firmware *fw = NULL;
1158 const char *p, *s;
1159 const char *eof;
1160 int err, row, len, line_sz, line_cnt = 0;
1161 unsigned long start_time = jiffies;
1162 struct fw_config_table fw_cfg;
1163 u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
1164 u8 *wr_buf;
1165
1166 err = request_firmware(&fw, ccg_fw_names[mode], dev);
1167 if (err) {
1168 dev_err(dev, "request %s failed err=%d\n",
1169 ccg_fw_names[mode], err);
1170 return err;
1171 }
1172
1173 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
1174 CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
1175 err = ccg_cmd_port_control(uc, false);
1176 if (err < 0)
1177 goto release_fw;
1178 err = ccg_cmd_jump_boot_mode(uc, 0);
1179 if (err < 0)
1180 goto release_fw;
1181 }
1182
1183 eof = fw->data + fw->size;
1184
1185 /*
1186 * check if signed fw
1187 * last part of fw image is fw cfg table and signature
1188 */
1189 if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
1190 goto not_signed_fw;
1191
1192 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1193 sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
1194
1195 if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
1196 dev_info(dev, "not a signed image\n");
1197 goto not_signed_fw;
1198 }
1199 eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
1200
1201 memcpy((uint8_t *)&fw_cfg_sig,
1202 fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
1203
1204 /* flash fw config table and signature first */
1205 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
1206 FLASH_FWCT1_WR_CMD);
1207 if (err)
1208 goto release_fw;
1209
1210 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
1211 FLASH_FWCT2_WR_CMD);
1212 if (err)
1213 goto release_fw;
1214
1215 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
1216 FLASH_FWCT_SIG_WR_CMD);
1217 if (err)
1218 goto release_fw;
1219
1220 not_signed_fw:
1221 wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
1222 if (!wr_buf) {
1223 err = -ENOMEM;
1224 goto release_fw;
1225 }
1226
1227 err = ccg_cmd_enter_flashing(uc);
1228 if (err)
1229 goto release_mem;
1230
1231 /*****************************************************************
1232 * CCG firmware image (.cyacd) file line format
1233 *
1234 * :00rrrrllll[dd....]cc/r/n
1235 *
1236 * :00 header
1237 * rrrr is row number to flash (4 char)
1238 * llll is data len to flash (4 char)
1239 * dd is a data field represents one byte of data (512 char)
1240 * cc is checksum (2 char)
1241 * \r\n newline
1242 *
1243 * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
1244 *
1245 *****************************************************************/
1246
1247 p = strnchr(fw->data, fw->size, ':');
1248 if (!p) {
1249 dev_err(dev, "Bad FW format: no ':' record header found\n");
1250 err = -EINVAL;
1251 goto release_mem;
1252 }
1253 while (p < eof) {
1254 s = strnchr(p + 1, eof - p - 1, ':');
1255
1256 if (!s)
1257 s = eof;
1258
1259 line_sz = s - p;
1260
1261 if (line_sz != CYACD_LINE_SIZE) {
1262 dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
1263 err = -EINVAL;
1264 goto release_mem;
1265 }
1266
1267 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
1268 err = -EINVAL;
1269 goto release_mem;
1270 }
1271
1272 row = get_unaligned_be16(wr_buf);
1273 len = get_unaligned_be16(&wr_buf[2]);
1274
1275 if (len != CCG4_ROW_SIZE) {
1276 err = -EINVAL;
1277 goto release_mem;
1278 }
1279
1280 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
1281 FLASH_WR_CMD);
1282 if (err)
1283 goto release_mem;
1284
1285 line_cnt++;
1286 p = s;
1287 }
1288
1289 dev_info(dev, "total %d row flashed. time: %dms\n",
1290 line_cnt, jiffies_to_msecs(jiffies - start_time));
1291
1292 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
1293 if (err)
1294 dev_err(dev, "%s validation failed err=%d\n",
1295 (mode == PRIMARY) ? "FW2" : "FW1", err);
1296 else
1297 dev_info(dev, "%s validated\n",
1298 (mode == PRIMARY) ? "FW2" : "FW1");
1299
1300 err = ccg_cmd_port_control(uc, false);
1301 if (err < 0)
1302 goto release_mem;
1303
1304 err = ccg_cmd_reset(uc);
1305 if (err < 0)
1306 goto release_mem;
1307
1308 err = ccg_cmd_port_control(uc, true);
1309 if (err < 0)
1310 goto release_mem;
1311
1312 release_mem:
1313 kfree(wr_buf);
1314
1315 release_fw:
1316 release_firmware(fw);
1317 return err;
1318 }
1319
1320 /*******************************************************************************
1321 * CCG4 has two copies of the firmware in addition to the bootloader.
1322 * If the device is running FW1, FW2 can be updated with the new version.
1323 * Dual firmware mode allows the CCG device to stay in a PD contract and support
1324 * USB PD and Type-C functionality while a firmware update is in progress.
1325 ******************************************************************************/
ccg_fw_update(struct ucsi_ccg * uc,enum enum_flash_mode flash_mode)1326 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
1327 {
1328 int err = 0;
1329
1330 while (flash_mode != FLASH_NOT_NEEDED) {
1331 err = do_flash(uc, flash_mode);
1332 if (err < 0)
1333 return err;
1334 err = ccg_fw_update_needed(uc, &flash_mode);
1335 if (err < 0)
1336 return err;
1337 }
1338 dev_info(uc->dev, "CCG FW update successful\n");
1339
1340 return err;
1341 }
1342
ccg_restart(struct ucsi_ccg * uc)1343 static int ccg_restart(struct ucsi_ccg *uc)
1344 {
1345 struct device *dev = uc->dev;
1346 int status;
1347
1348 status = ucsi_ccg_init(uc);
1349 if (status < 0) {
1350 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
1351 return status;
1352 }
1353
1354 status = ccg_request_irq(uc);
1355 if (status < 0) {
1356 dev_err(dev, "request_threaded_irq failed - %d\n", status);
1357 return status;
1358 }
1359
1360 status = ucsi_register(uc->ucsi);
1361 if (status) {
1362 dev_err(uc->dev, "failed to register the interface\n");
1363 return status;
1364 }
1365
1366 pm_runtime_enable(uc->dev);
1367 return 0;
1368 }
1369
ccg_update_firmware(struct work_struct * work)1370 static void ccg_update_firmware(struct work_struct *work)
1371 {
1372 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1373 enum enum_flash_mode flash_mode;
1374 int status;
1375
1376 status = ccg_fw_update_needed(uc, &flash_mode);
1377 if (status < 0)
1378 return;
1379
1380 if (flash_mode != FLASH_NOT_NEEDED) {
1381 ucsi_unregister(uc->ucsi);
1382 pm_runtime_disable(uc->dev);
1383 free_irq(uc->irq, uc);
1384
1385 ccg_fw_update(uc, flash_mode);
1386 ccg_restart(uc);
1387 }
1388 }
1389
do_flash_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1390 static ssize_t do_flash_store(struct device *dev,
1391 struct device_attribute *attr,
1392 const char *buf, size_t n)
1393 {
1394 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1395 bool flash;
1396
1397 if (kstrtobool(buf, &flash))
1398 return -EINVAL;
1399
1400 if (!flash)
1401 return n;
1402
1403 schedule_work(&uc->work);
1404 return n;
1405 }
1406
ucsi_ccg_attrs_is_visible(struct kobject * kobj,struct attribute * attr,int idx)1407 static umode_t ucsi_ccg_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1408 {
1409 struct device *dev = kobj_to_dev(kobj);
1410 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1411
1412 if (!uc->fw_build)
1413 return 0;
1414
1415 return attr->mode;
1416 }
1417
1418 static DEVICE_ATTR_WO(do_flash);
1419
1420 static struct attribute *ucsi_ccg_attrs[] = {
1421 &dev_attr_do_flash.attr,
1422 NULL,
1423 };
1424 static struct attribute_group ucsi_ccg_attr_group = {
1425 .attrs = ucsi_ccg_attrs,
1426 .is_visible = ucsi_ccg_attrs_is_visible,
1427 };
1428 static const struct attribute_group *ucsi_ccg_groups[] = {
1429 &ucsi_ccg_attr_group,
1430 NULL,
1431 };
1432
ucsi_ccg_probe(struct i2c_client * client)1433 static int ucsi_ccg_probe(struct i2c_client *client)
1434 {
1435 struct device *dev = &client->dev;
1436 struct ucsi_ccg *uc;
1437 const char *fw_name;
1438 int status;
1439
1440 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1441 if (!uc)
1442 return -ENOMEM;
1443
1444 uc->dev = dev;
1445 uc->client = client;
1446 uc->irq = client->irq;
1447 mutex_init(&uc->lock);
1448 INIT_WORK(&uc->work, ccg_update_firmware);
1449 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1450
1451 /* Only fail FW flashing when FW build information is not provided */
1452 status = device_property_read_string(dev, "firmware-name", &fw_name);
1453 if (!status) {
1454 if (!strcmp(fw_name, "nvidia,jetson-agx-xavier"))
1455 uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA;
1456 else if (!strcmp(fw_name, "nvidia,gpu"))
1457 uc->fw_build = CCG_FW_BUILD_NVIDIA;
1458 if (!uc->fw_build)
1459 dev_err(uc->dev, "failed to get FW build information\n");
1460 }
1461
1462 /* reset ccg device and initialize ucsi */
1463 status = ucsi_ccg_init(uc);
1464 if (status < 0) {
1465 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1466 return status;
1467 }
1468
1469 status = get_fw_info(uc);
1470 if (status < 0) {
1471 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1472 return status;
1473 }
1474
1475 uc->port_num = 1;
1476
1477 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1478 uc->port_num++;
1479
1480 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1481 if (IS_ERR(uc->ucsi))
1482 return PTR_ERR(uc->ucsi);
1483
1484 ucsi_set_drvdata(uc->ucsi, uc);
1485
1486 status = ccg_request_irq(uc);
1487 if (status < 0) {
1488 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1489 goto out_ucsi_destroy;
1490 }
1491
1492 status = ucsi_register(uc->ucsi);
1493 if (status)
1494 goto out_free_irq;
1495
1496 i2c_set_clientdata(client, uc);
1497
1498 device_disable_async_suspend(uc->dev);
1499
1500 pm_runtime_set_active(uc->dev);
1501 pm_runtime_enable(uc->dev);
1502 pm_runtime_use_autosuspend(uc->dev);
1503 pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1504 pm_runtime_idle(uc->dev);
1505
1506 return 0;
1507
1508 out_free_irq:
1509 free_irq(uc->irq, uc);
1510 out_ucsi_destroy:
1511 ucsi_destroy(uc->ucsi);
1512
1513 return status;
1514 }
1515
ucsi_ccg_remove(struct i2c_client * client)1516 static void ucsi_ccg_remove(struct i2c_client *client)
1517 {
1518 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1519
1520 cancel_work_sync(&uc->pm_work);
1521 cancel_work_sync(&uc->work);
1522 pm_runtime_disable(uc->dev);
1523 ucsi_unregister(uc->ucsi);
1524 free_irq(uc->irq, uc);
1525 ucsi_destroy(uc->ucsi);
1526 }
1527
1528 static const struct of_device_id ucsi_ccg_of_match_table[] = {
1529 { .compatible = "cypress,cypd4226", },
1530 { /* sentinel */ }
1531 };
1532 MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table);
1533
1534 static const struct i2c_device_id ucsi_ccg_device_id[] = {
1535 { .name = "ccgx-ucsi" },
1536 { }
1537 };
1538 MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
1539
1540 static const struct acpi_device_id amd_i2c_ucsi_match[] = {
1541 {"AMDI0042"},
1542 {}
1543 };
1544 MODULE_DEVICE_TABLE(acpi, amd_i2c_ucsi_match);
1545
ucsi_ccg_resume(struct device * dev)1546 static int ucsi_ccg_resume(struct device *dev)
1547 {
1548 struct i2c_client *client = to_i2c_client(dev);
1549 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1550
1551 return ucsi_resume(uc->ucsi);
1552 }
1553
ucsi_ccg_runtime_suspend(struct device * dev)1554 static int ucsi_ccg_runtime_suspend(struct device *dev)
1555 {
1556 return 0;
1557 }
1558
ucsi_ccg_runtime_resume(struct device * dev)1559 static int ucsi_ccg_runtime_resume(struct device *dev)
1560 {
1561 struct i2c_client *client = to_i2c_client(dev);
1562 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1563
1564 /*
1565 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
1566 * of missing interrupt when a device is connected for runtime resume.
1567 * Schedule a work to call ISR as a workaround.
1568 */
1569 if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1570 uc->fw_version <= CCG_OLD_FW_VERSION)
1571 schedule_work(&uc->pm_work);
1572
1573 return 0;
1574 }
1575
1576 static const struct dev_pm_ops ucsi_ccg_pm = {
1577 .resume = ucsi_ccg_resume,
1578 .runtime_suspend = ucsi_ccg_runtime_suspend,
1579 .runtime_resume = ucsi_ccg_runtime_resume,
1580 };
1581
1582 static struct i2c_driver ucsi_ccg_driver = {
1583 .driver = {
1584 .name = "ucsi_ccg",
1585 .pm = &ucsi_ccg_pm,
1586 .dev_groups = ucsi_ccg_groups,
1587 .acpi_match_table = amd_i2c_ucsi_match,
1588 .of_match_table = ucsi_ccg_of_match_table,
1589 },
1590 .probe = ucsi_ccg_probe,
1591 .remove = ucsi_ccg_remove,
1592 .id_table = ucsi_ccg_device_id,
1593 };
1594
1595 module_i2c_driver(ucsi_ccg_driver);
1596
1597 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1598 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1599 MODULE_LICENSE("GPL v2");
1600