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Searched refs:FIELD_PREP_CONST (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/net/wan/framer/pef2256/
H A Dpef2256-regs.h31 #define PEF2256_FMR0_XC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
32 #define PEF2256_FMR0_XC_CMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
33 #define PEF2256_FMR0_XC_AMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
34 #define PEF2256_FMR0_XC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
36 #define PEF2256_FMR0_RC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
37 #define PEF2256_FMR0_RC_CMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
38 #define PEF2256_FMR0_RC_AMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
39 #define PEF2256_FMR0_RC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
47 #define PEF2256_FMR1_SSD_2048 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
48 #define PEF2256_FMR1_SSD_4096 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
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/linux/drivers/pinctrl/
H A Dpinctrl-pef2256.c27 #define PEF2256_12_PC_RPC_SYPR FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x0)
28 #define PEF2256_12_PC_RPC_RFM FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x1)
29 #define PEF2256_12_PC_RPC_RFMB FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x2)
30 #define PEF2256_12_PC_RPC_RSIGM FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x3)
31 #define PEF2256_12_PC_RPC_RSIG FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x4)
32 #define PEF2256_12_PC_RPC_DLR FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x5)
33 #define PEF2256_12_PC_RPC_FREEZE FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x6)
34 #define PEF2256_12_PC_RPC_RFSP FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x7)
36 #define PEF2256_12_PC_XPC_SYPX FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x0)
37 #define PEF2256_12_PC_XPC_XFMS FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x1)
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/linux/include/linux/amba/
H A Dserial.h138 #define ST_UART011_DMAWM_RX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 0)
139 #define ST_UART011_DMAWM_RX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 1)
140 #define ST_UART011_DMAWM_RX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 2)
141 #define ST_UART011_DMAWM_RX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 3)
142 #define ST_UART011_DMAWM_RX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 4)
143 #define ST_UART011_DMAWM_RX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 5)
144 #define ST_UART011_DMAWM_RX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 6)
146 #define ST_UART011_DMAWM_TX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 0)
147 #define ST_UART011_DMAWM_TX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 1)
148 #define ST_UART011_DMAWM_TX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 2)
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/linux/drivers/soc/fsl/qe/
H A Dtsa.c29 #define TSA_CPM1_SIRAM_ENTRY_CSEL_NU FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x0)
30 #define TSA_CPM1_SIRAM_ENTRY_CSEL_SCC2 FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x2)
31 #define TSA_CPM1_SIRAM_ENTRY_CSEL_SCC3 FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x3)
32 #define TSA_CPM1_SIRAM_ENTRY_CSEL_SCC4 FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x4)
33 #define TSA_CPM1_SIRAM_ENTRY_CSEL_SMC1 FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x5)
34 #define TSA_CPM1_SIRAM_ENTRY_CSEL_SMC2 FIELD_PREP_CONST(TSA_CPM1_SIRAM_ENTRY_CSEL_MASK, 0x6)
42 #define TSA_QE_SIRAM_ENTRY_CSEL_NU FIELD_PREP_CONST(TSA_QE_SIRAM_ENTRY_CSEL_MASK, 0x0)
43 #define TSA_QE_SIRAM_ENTRY_CSEL_UCC5 FIELD_PREP_CONST(TSA_QE_SIRAM_ENTRY_CSEL_MASK, 0x1)
44 #define TSA_QE_SIRAM_ENTRY_CSEL_UCC1 FIELD_PREP_CONST(TSA_QE_SIRAM_ENTRY_CSEL_MASK, 0x9)
45 #define TSA_QE_SIRAM_ENTRY_CSEL_UCC2 FIELD_PREP_CONST(TSA_QE_SIRAM_ENTRY_CSEL_MASK, 0xa)
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_guc_relay_test.c54 FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
55 FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |
56 FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_ACTION, TEST_ACTION) |
57 FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_DATA0, TEST_DATA(0)),
99 FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC) |
100 FIELD_PREP_CONST(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |
101 FIELD_PREP_CONST(GUC_HXG_EVENT_MSG_0_ACTION, XE_GUC_ACTION_GUC2PF_RELAY_FROM_VF),
102 FIELD_PREP_CONST(GUC2PF_RELAY_FROM_VF_EVENT_MSG_1_VFID, TEST_VFID),
103 FIELD_PREP_CONST(GUC2PF_RELAY_FROM_VF_EVENT_MSG_2_RELAY_ID, TEST_RID),
105 FIELD_PREP_CONST(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
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/linux/drivers/net/mdio/
H A Dmdio-airoha.c25 #define AN7583_MII_CMD_CL22_WRITE FIELD_PREP_CONST(AN7583_MII_CMD, 0x1)
26 #define AN7583_MII_CMD_CL22_READ FIELD_PREP_CONST(AN7583_MII_CMD, 0x2)
27 #define AN7583_MII_CMD_CL45_ADDR FIELD_PREP_CONST(AN7583_MII_CMD, 0x0)
28 #define AN7583_MII_CMD_CL45_WRITE FIELD_PREP_CONST(AN7583_MII_CMD, 0x1)
29 #define AN7583_MII_CMD_CL45_POSTREAD_INCADDR FIELD_PREP_CONST(AN7583_MII_CMD, 0x2)
30 #define AN7583_MII_CMD_CL45_READ FIELD_PREP_CONST(AN7583_MII_CMD, 0x3)
32 #define AN7583_MII_ST_CL45 FIELD_PREP_CONST(AN7583_MII_ST, 0x0)
33 #define AN7583_MII_ST_CL22 FIELD_PREP_CONST(AN7583_MII_ST, 0x1)
/linux/drivers/net/phy/qcom/
H A Dqcom.h76 #define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
77 #define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
78 #define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
79 #define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
82 #define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
83 #define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
84 #define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1908 (FIELD_PREP_CONST(PHYPARAM0_TXVREFTUNE, 14) |
1909 FIELD_PREP_CONST(PHYPARAM0_TXRISETUNE, 1) |
1910 FIELD_PREP_CONST(PHYPARAM0_TXRESTUNE, 3) |
1911 FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) |
1912 FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) |
1913 FIELD_PREP_CONST(PHYPARAM0_TXFSLSTUNE, 3) |
1914 FIELD_PREP_CONST(PHYPARAM0_SQRXTUNE, 6) |
1915 FIELD_PREP_CONST(PHYPARAM0_OTGTUNE, 2) |
1916 FIELD_PREP_CONST(PHYPARAM0_COMPDISTUNE, 3))),
2033 (FIELD_PREP_CONST(HSPPARACON_TXVREF, 7) |
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/linux/drivers/gpu/drm/xe/
H A Dxe_guc_klv_helpers.h38 (FIELD_PREP_CONST(GUC_KLV_0_KEY, (key)) | \
39 FIELD_PREP_CONST(GUC_KLV_0_LEN, (len)))
/linux/sound/soc/codecs/
H A Dwsa884x.c1387 { WSA884X_BOP2_PROG, FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_VTH_MASK, 0x6) |
1388 FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_HYST_MASK, 0x6) },
1390 FIELD_PREP_CONST(WSA884X_REF_CTRL_BG_RDY_SEL_MASK, 0x1) },
1396 FIELD_PREP_CONST(WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK, 0xd) },
1398 FIELD_PREP_CONST(WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 0x9) },
1400 FIELD_PREP_CONST(WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK, 0x3) },
1402 FIELD_PREP_CONST(WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK, 0x3) },
1403 { WSA884X_CKWD_CTL_1, FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK, 0x0) |
1404 FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK, 0x13) },
1406 FIELD_PREP_CONST(WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK, 0x4) }, /* == 0xfe */
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/linux/drivers/dpll/zl3073x/
H A Dregs.h50 FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \
51 FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \
52 FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \
/linux/drivers/clk/renesas/
H A Dr9a09g077-cpg.c36 (FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \
37 FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \
38 FIELD_PREP_CONST(WIDTH_MASK, (width)))
H A Drzv2h-cpg.h161 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
162 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
/linux/drivers/pinctrl/spacemit/
H A Dpinctrl-k1.h29 FIELD_PREP_CONST(K1_PIN_IO_TYPE, type)
/linux/include/linux/
H A Dbitfield.h154 #define FIELD_PREP_CONST(_mask, _val) \ macro
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzg2l.c96 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
98 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
121 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
/linux/drivers/phy/renesas/
H A Dphy-rcar-gen3-usb2.c84 #define USB2_VBCTRL_VBLVL(m) FIELD_PREP_CONST(USB2_VBCTRL_VBLVL_MASK, (m))
476 FIELD_PREP_CONST(USB2_VBCTRL_VBSTA_MASK, USB2_VBCTRL_VBSTA_DEFAULT)) in rcar_gen3_configure_vblvl_ctrl()
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-airoha.c115 #define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
118 #define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
121 #define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
124 #define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
127 #define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
/linux/drivers/leds/
H A Dleds-sun50i-a100.c162 FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2); in sun50i_a100_ledc_start_xfer()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c107 FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
108 FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
/linux/drivers/cpufreq/
H A Dintel_pstate.c3702 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3703 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3704 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3705 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8703b.c624 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | in rtw8703b_phy_set_param()
625 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); in rtw8703b_phy_set_param()
/linux/drivers/net/wireless/intel/iwlwifi/mld/
H A Dmac80211.c92 #define IWL_MLD_CAPA_OPS (FIELD_PREP_CONST( \
/linux/drivers/net/wireless/virtual/
H A Dmac80211_hwsim.c5366 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_TID_TO_LINK_MAP_NEG_SUPP, \
5368 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, \